SCAS647B − OCTOBER 2000 − REVISED DECEMBER 2002
D Phase-Lock Loop Clock Driver for Double
D
D
D
D
D
D
D
D
D
Data-Rate Synchronous DRAM
Applications
Spread Spectrum Clock Compatible
Operating Frequency: 60 to 140 MHz
Low Jitter (cyc−cyc): ±75 ps
Distributes One Differential Clock Input to
Ten Differential Outputs
Two-Line Serial Interface Provides Output
Enable and Functional Control
Outputs Are Put Into a High-Impedance
State When the Input Differential Clocks
Are <20 MHz
48-Pin TSSOP Package
Consumes <250-µA Quiescent Current
External Feedback Pins (FBIN, FBIN) Are
Used to Synchronize the Outputs to the
Input Clocks
description
DGG PACKAGE
(TOP VIEW)
GND
Y0
Y0
VDDQ
Y1
Y1
GND
GND
Y2
Y2
VDDQ
SCLK
CLK
CLK
VDDI
AVDD
AGND
GND
Y3
Y3
VDDQ
Y4
Y4
GND
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
GND
Y5
Y5
VDDQ
Y6
Y6
GND
GND
Y7
Y7
VDDQ
SDATA
FBIN
FBIN
VDDQ
FBOUT
FBOUT
GND
Y8
Y8
VDDQ
Y9
Y9
GND
The CDCV850 is a high-performance, low-skew,
21
28
low-jitter zero delay buffer that distributes a
22
27
differential clock input pair (CLK, CLK) to ten
23
26
differential pairs of clock outputs (Y[0:9], Y[0:9])
24
25
and one differential pair of feedback clock outputs
(FBOUT, FBOUT). The clock outputs are controlled by the clock inputs (CLK, CLK), the feedback clocks (FBIN, FBIN), the 2-line serial interface (SDATA,
SCLK), and the analog power input (AVDD). A two-line serial interface can put the individual output clock pairs
in a high-impedance state. When the AVDD terminal is tied to GND, the PLL is turned off and bypassed for test
purposes.
The device provides a standard mode (100 Kbits/s) 2-line serial interface for device control. The implementation
is as a slave/receiver. The device address is specified in the 2-line serial device address table. Both of the 2-line
serial inputs (SDATA and SCLK) provide integrated pullup resistors (typically 100 kΩ).
Two 8-bit, 2-line serial registers provide individual enable control for each output pair. All outputs default to
enabled at powerup. Each output pair can be placed in a high-impedance mode, when a low-level control bit
is written to the control register. The registers must be accessed in sequential order (i.e., random access of the
registers not supported). The serial interface circuit can be supplied with either 2.5 V or 3.3 V (at VDDI) in
applications where this programming option is not required (after power up, all output pairs will then be enabled).
When the input frequency falls below a suggested detection frequency that is below 20 MHz (typically 10 MHz),
the output pairs are put into a high-impedance condition, the PLL is shut down, and the device will enter a low
power mode. The CDCV850 is also able to track spread spectrum clocking for reduced EMI.
Since the CDCV850 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL.
This stabilization time is required following power up, as well as changes to various 2-line serial registers that
affect the PLL. The CDCV850 is characterized for both commercial and industrial temperature ranges.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002, Texas Instruments Incorporated
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1
SCAS647B − OCTOBER 2000 − REVISED DECEMBER 2002
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
TSSOP (DGG)
0°C to 85°C
CDCV850DGG
−40°C to 85°C
CDCV850IDGG
FUNCTION TABLE
(Select Functions)
OUTPUTS†
INPUTS
PLL
AVDD
GND
CLK
CLK
Y[0:9]
Y[0:9]
FBOUT
FBOUT
L
H
L
H
L
H
Bypassed/Off
GND
H
L
H
L
H
L
Bypassed/Off
2.5 V (nom)
L
H
L
H
L
H
On
2.5 V (nom)
H
L
H
L
H
L
On
2.5 V (nom)
<20 MHz <20 MHz
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Off
† Each output pair (except FBOUT, FBOUT) can be put into a high-impedance state through the 2-line
serial interface.
functional block diagram
VDDI
3
2
Y0
Y0
5
Y1
6 Y1
10
12
SCLK
SDATA
37
2-Line Serial
Interface
Logic
9
10
20
19
22
23
46
47
CLK
13
CLK
14
FBIN
36
FBIN
44
43
PLL
39
35
40
29
AVDD
30
16
27
26
32
33
2
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Y2
Y2
Y3
Y3
Y4
Y4
Y5
Y5
Y6
Y6
Y7
Y7
Y8
Y8
Y9
Y9
FBOUT
FBOUT
SCAS647B − OCTOBER 2000 − REVISED DECEMBER 2002
Terminal Functions
TERMINAL
NAME
AGND
NO.
I/O
Ground for 2.5-V analog supply
17
AVDD
CLK, CLK
13, 14
FBIN, FBIN
FBOUT, FBOUT
2.5-V analog supply
16
I
Differential clock input
35, 36
I
Feedback differential clock input
32, 33
O
Feedback differential clock output
GND
1, 7, 8, 18,
24, 25, 31,
41, 42, 48
SCLK
12
I
SDATA
37
I/O
VDDQ
4, 11, 21,
28, 34, 38,
45
VDDI
Y[0:9]
Y[0:9]
DESCRIPTION
Ground
Clock input for 2-line serial interface
Data input/output for 2-line serial interface
2.5-V supply
15
I
2.5-V or 3.3-V supply for 2-line serial interface
3, 5, 10,
20, 22, 27,
29, 39, 44,
46
O
Buffered output copies of input clock, CLK
2, 6, 9, 19,
23, 26, 30,
40, 43, 47
O
Buffered output copies of input clock, CLK
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SCAS647B − OCTOBER 2000 − REVISED DECEMBER 2002
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range: VDDQ, AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 3.6 V
VDDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Input voltage range: VI (except SCLK and SDATA) (see Notes 1 and 2) . . . . . . . . –0.5 V to VDDQ + 0.5 V
VI (SCLK, SDATA) (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . –0.5 V to VDDI + 0.5 V
Output voltage range: VO (except SDATA) (see Notes 1 and 2) . . . . . . . . . . . . . . . . . –0.5 V to VDDQ + 0.5 V
VO (SDATA) (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VDDQ + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Output clamp current, IOK (VO < 0 or VO > VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89°C/W
Storage temperature range Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 3.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
MIN
VDDQ, AVDD
VDDI (see Note 5)
Supply voltage
3.6
−0.3
CLK, CLK, HCSL Buffer only
0.66
CLK, CLK
0.4
FBIN, FBIN
DC input signal voltage (see Note 6)
–0.3
DC
CLK, FBIN
0.36
AC
CLK, FBIN
0.2
0.45×(VIH−VIL)
High-level output current, IOH
Low-level output current, IOL
SDATA
Input slew rate, SR (see Figure 8)
SSC clock input frequency deviation
8.
4
Commericial
VDDQ + 0.3
VDDQ + 0.6
VDDQ + 0.6
0.55×(VIH−VIL)
V
V
V
V
−12
mA
12
V
mA
4
V/ns
30
33.3
kHz
0
−0.50
kHz
0
85
°C
−40
85
Industrial
Unused inputs must be held high or low to prevent them from floating.
All devices on the serial interface bus, with input levels related to VDDI, must have one common supply line to which the pullup resistor
is connected to.
DC input signal voltage specifies the allowable dc execution of differential input.
Differential input signal voltage specifies the differential voltage |VTR − VCP| required for switching, where VTR is the true input level
and VCP is the complementary input level.
Differential cross-point voltage is expected to track variations of VCC and is the voltage at which the differential signals must be
crossing.
Operating free-air temperature, TA
6.
7.
VDDQ + 0.3
3
1
SSC modulation frequency
NOTES: 4.
5.
0.71
VDDQ/2 + 0.18
0.7 × VDDI
SDATA, SCLK
Input differential pair cross-voltage, VIX (see Note 8)
V
0.3 × VDDI
SDATA, SCLK
Differential input signal voltage, VID (see Note 7)
V
0.24
VDDQ − 0.4
VDDQ/2 − 0.18
FBIN, FBIN
High level input voltage, VIH
UNIT
2.3
0
CLK, CLK
MAX
2.7
CLK, CLK, HCSL Buffer only
Low level input voltage, VIL
TYP
2.3
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SCAS647B − OCTOBER 2000 − REVISED DECEMBER 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
Input voltage
All inputs
VOH
High-level output voltage
VOL
Low-level output
voltage
SDATA
VDDQ = 2.3 V,
II = –18 mA
VDDQ = min to max, IOH = –1 mA
VDDQ = 2.3 V,
IOH = –12 mA
VDDQ = min to max, IOL = 1 mA
VDDQ = 2.3 V,
VDDI = 3.0 V,
IOL = 12 mA
IOL = 3 mA
MIN
TYP†
MAX
UNIT
–1.2
V
VDDQ – 0.1
1.7
V
0.1
0.6
V
0.4
IOH
IOL
High-level output current
VDDQ = 2.3 V,
VDDQ = 2.3 V,
VO = 1 V
VO = 1.2 V
–18
–32
Low-level output current
26
35
VO
Output voltage swing
For load condition see Figure 3
1.1
VOX
Output differential cross
voltage
II
Input current
IOZ
High-impedance-state output
current
IDDPD
Power-down current on VDDQ
+ AVDD
CLK at 0 MHz; Σ of IDD and AIDD
Power down current on VDDI
CLK at 0 MHz; VDDQ = 3.6 V
VDDQ/2 − 0.2
VDDQ/2
mA
mA
VDDQ – 0.4
V
VDDQ/2 + 0.2
V
SDATA,
SCLK
VDDQ = 3.6 V,
VI = 0 V to 3.6 V
+10/−50
µA
CLK, FBIN
VDDQ = 2.7 V,
VI = 0 V to 2.7 V
±10
µA
VDDQ = 2.7 V,
VO = VDDQ or GND
±10
µA
150
250
µA
3
20
µA
205
230
mA
4
6
mA
1
2
mA
2.5
3
pF
IDD
Dynamic current on VDDQ
AI(DD)
Supply current on AVDD
VDDQ = 2.7 V,
fO = 100 MHz
All differential output pairs are terminated
with 120 Ω / CL = 4 pF
AVDD = 2.7 V,
fO = 100 MHz
IDDI
Supply current on VDDI
VDDI = 3.6 V
SCLK and
SDATA = 3.6 V
CI
Input capacitance
VDDQ = 2.5 V
VDDQ = 2.5 V
VI = VDDQ or GND
VO = VDDQ or GND
2
CO
Output capacitance
2.5
3
3.5
pF
† All typical values are at respective nominal VDDQ.
‡ The value of VOC is expected to be |VTR + VCP|/2. In case of each clock directly terminated by a 120-Ω resistor, where VTR is the true input
signal voltage and VCP is the complementary input signal voltage (see Figure 3).
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SCAS647B − OCTOBER 2000 − REVISED DECEMBER 2002
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
f(CLK)
Clock frequency
Input clock duty cycle
MIN
MAX
UNIT
60
140
MHz
40%
60%
Stabilization time†
µs
10
† Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a
fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew,
and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under
SSC application.
timing requirements for the 2-line serial interface over recommended ranges of operating
free-air temperature and VDDI from 3.3 V to 3.6 V (see Figure 10)
MIN
MAX
UNIT
100
kHz
f(SCLK)
t(BUS)
SCLK frequency
Bus free time
4.7
µs
tsu(START)
START setup time†
4.7
µs
th(START)
START hold time†
4.0
µs
tw(SCLL)
SCLK low pulse duration
4.7
µs
tw(SCLH)
SLCK high pulse duration
4.0
µs
tr(SDATA)
tf(SDATA)
SDATA input rise time
1000
ns
SDATA input fall time
300
ns
tsu(SDATA)
th(SDATA)
SDATA setup time
250
ns
SDATA hold time
0
ns
tsu(STOP)
STOP setup time
† This conforms to I2C specification, version 2.1.
4
µs
6
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SCAS647B − OCTOBER 2000 − REVISED DECEMBER 2002
switching characteristics over recommended ranges of operating free-air temperature (unless
otherwisw noted)
PARAMETER
TEST CONDITIONS
tpd
tPHL
Propagation delay time
Test mode/CLK to any output
High-to low-level propagation delay time
SCLK to SDATA (acknowledge)
ten
tdis
Output enable time
MIN
TYP
MAX
UNIT
4
{
500
ns
Test mode/SDATA to Y-output
85
ns
Output disable time
Test mode/SDATA to Y-output
35
ns
tjit(per)
tjit(cc)
Jitter (period), See Figure 6
100/133 MHz
−30
30
ps
Jitter (cycle-to-cycle), See Figure 3
100/133 MHz
−30
30
ps
tjit(hper)
Half-period jitter, See Figure 7
100/133 MHz
ps
ns
−75
75
100 MHz/VID on CLK = 0.71 V}
100 MHz/VID on CLK = 0.59 Vw
−120
120
−50
160
100 MHz/VID on CLK = 0.82 VW
133 MHz/VID on CLK = 0.71 VW
−170
70
−50
180
100 MHz/VID on CLK = 0.71 V}
100 MHz/VID on CLK = 0.59 Vw
−160
80
−90
120
100 MHz/VID on CLK = 0.82 VW
133 MHz/VID on CLK = 0.71 VW
−210
30
−80
150
Dynamic phase offset, SSC on, See Figure 4b and
Figure 9
100 MHz/VID on CLK = 0.71 V}
133 MHz/VID on CLK = 0.71 V}
−190
190
ps
−140
140
ps
−160
160
ps
Dynamic phase offset, SSC off, See Figure 4b
100 MHz/VID on CLK = 0.71 V}
133 MHz/VID on CLK = 0.71 V}
−130
130
ps
tslr(o)
Output clock slew rate, terminated with 120
Ω/14 pF, See Figures 1 and 8
1
2
V/ns
tslr(o)
Output clock slew rate, terminated with 120
Ω/4 pF, See Figures 1 and 8
1
3
V/ns
tsk(o)
Output skew, See Figure 5
75
ps
0°C to 85°C
t(∅)
( )
Static phase offset, See Figure 4a
−40°C to 85°C
td(∅)
( )#
SSC modulation frequency
SSC clock input frequency deviation
ps
ps
30
33.3
kHz
0.00
−0.50
%
† This time is for a PLL frequency of 100 MHz.
‡ According CK00 spec: 6 x Iref at 50 Ω and Rref = 475 Ω
§ According CK00 spec: 5 x Iref at 50 Ω and Rref = 475 Ω
¶ According CK00 spec: 7 x Iref at 50 Ω and Rref = 475 Ω
# The parameter is assured by design but cannot be 100% production tested.
|| All differential output pins are terminated with 120 Ω/4 pF
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SCAS647B − OCTOBER 2000 − REVISED DECEMBER 2002
2-line serial interface
2-line serial interface slave address
A7
A6
A5
A4
A3
A2
A1
1
1
0
1
0
0
1
R/W
0
Writing to the device is accomplished by sequentially sending the device address D2H, the dummy bytes
(command code and the number of bytes), and the data bytes. This sequence is illustrated in the following
tables:
1 bit
7 bits
Start Bit
Ack
1 bit
1 bit
Slave Address
Data Byte 0
8 bits
R/W
1 bit
8 bits
Ack
1 bit
Command Code
Ack
Data Byte 1
1 bit
8 bits
Ack
8 bits
Ack
Byte Count = N
Data Byte N
1 bit
8 bits
Ack
1 bit
Stop
1 bit
2-line serial interface configuration command bitmap
The 2-line serial command bytes are used to control the output clock pairs (Y[0:9], Y[0:9]). The output clock pairs
are enabled after power up. During normal operation, the clock pairs can be disabled (set Hi-Z) or enabled
(running) by writing the corresponding bit to the data bytes in the following tables:
Byte 0: Enable/Disable Register
(H = Enable, L = Disable)
8
Byte 1: Enable/Disable Register
(H = Enable, L = Disable)
BIT
PINS
INITIAL
VALUE
DESCRIPTION
BIT
PINS
INITIAL
VALUE
DESCRIPTION
7
3, 2
H
Y0, Y0
7
29, 30
H
Y8, Y8
6
5, 6
H
Y1, Y1
6
27, 26
H
Y9, Y9
5
10, 9
H
Y2, Y2
5
−
L
Reserved
4
20, 19
H
Y3, Y3
4
−
L
Reserved
3
22, 23
H
Y4, Y4
3
−
L
Reserved
2
46, 47
H
Y5, Y5
2
−
L
Reserved
1
44, 43
H
Y6, Y6
1
−
L
Reserved
0
39, 40
H
Y7, Y7
0
−
L
Reserved
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SCAS647B − OCTOBER 2000 − REVISED DECEMBER 2002
PARAMETER MEASUREMENT INFORMATION
VDD
V(Y)
R = 60 Ω
R = 60 Ω
VDD/2
V(Y)
CDCV850
GND
Figure 1. IBIS Model Output Load (used for slew rate measurement)
VDD/2
C = 4 pF
CDCV850
Z = 60 Ω
SCOPE
−VDD/2
Z = 50 Ω
R = 10 Ω
R = 50 Ω
GND
Z = 60 Ω
R = 10 Ω
Z = 50 Ω
R = 50 Ω
C = 4 pF
GND
−VDD/2
−VDD/2
Figure 2. Output Load Test Circuit
Yx, FBOUT
Yx, FBOUT
tc(n)
tc(n+1)
tjit(cc) = tc(n) − tc(n+1)
Figure 3. Cycle-to-Cycle Jitter
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9
SCAS647B − OCTOBER 2000 − REVISED DECEMBER 2002
PARAMETER MEASUREMENT INFORMATION
CLK
CLK
FBIN
FBIN
t( ) n
∑1
t ( ) n+1
n=N
t( ) =
t( ) n
N
(N is a large number of samples)
(a) Static Phase Offset
CLK
CLK
FBIN
FBIN
t( )
td( )
t( )
td( )
td( )
(b) Dynamic Phase Offset
Figure 4. Static Phase Offset
Yx
Yx
Yx, FBOUT
Yx, FBOUT
tsk(o)
Figure 5. Output Skew
10
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td( )
SCAS647B − OCTOBER 2000 − REVISED DECEMBER 2002
PARAMETER MEASUREMENT INFORMATION
Yx, FBOUT
Yx, FBOUT
tc(n)
Yx, FBOUT
Yx, FBOUT
1
f
O
tjit)per) = tc(n) −
1
fO
Figure 6. Period Jitter
Yx, FBOUT
Yx, FBOUT
t(hper_N+1)
t(hper_n)
1
fO
tjit(hper) = t(hper_n)
1
2xf O
Figure 7. Half-Period Jitter
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SCAS647B − OCTOBER 2000 − REVISED DECEMBER 2002
PARAMETER MEASUREMENT INFORMATION
80%
80%
VID, VOD
20%
Clock Inputs
20%
and Outputs
tslrf(i), tslrf(o)
tslrr(i), tslrr(o)
Period of Output Frequency − %
Figure 8. Input and Output Slew Rates
100
99.9
99.8
99.7
99.6
99.5
5
10
15
20
25
30
35
Period of Modulation Signal − µs
Figure 9. SSC Modulation Profile
12
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40
45
SCAS647B − OCTOBER 2000 − REVISED DECEMBER 2002
VO = 3.3 V
RL = 1 kΩ
DUT
CL = 10 pF
GND
TEST CIRCUIT
4 to N Bytes for Complete Device Programming
Start
Condition
(S)
Bit 7
MSB
Bit 0
LSB
(R/W)
Bit 6
tw(SCLL)
Acknowledge
(A)
Stop
Condition
(P)
tsu(START)
tw(SCLH)
0.7 VCC
SCLOCK
tsu(START)
0.3 VCC
tr
tPHL
tf
t(BUS)
tPLH
0.7 VCC
0.3 VCC
SDATA
tf(SDATA)
tr(SDATA)
tsu(SDATA)
th(START)
th(SDATA)
Repeat Start
Condition
(see Note A)
Start or Repeat Start
Condition
tsu(STOP)
Stop Condition
VOLTAGE WAVEFORMS
BYTE
DESCRIPTION
1
Slave Address
2
Common (Dummy Value, Ignored)
3
Byte Count = N
4
Data Byte 0
5−N
Data Byte 1 − N
NOTE A: The repeat start condition is supported. If PWRDWN# is asserted SDATA will be set to off-state, high impedance.
Figure 10. Propagation Delay Times, tr and tf
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13
SCAS647B − OCTOBER 2000 − REVISED DECEMBER 2002
MECHANICAL DATA
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°−ā 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: B.
C.
D.
E.
14
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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