MB9B360L Series 32-Bit ARM® Cortex® - M4F FM4 Microcontroller Devices in the MB9B360L Series are highly integrated 32-bit microcontrollers with high performance and competitive cost. ® ® This series is based on the ARM Cortex -M4F Processor with on-chip Flash memory and SRAM. The series has peripheral 2 functions such as Motor Control Timers, ADCs and Communication Interfaces (USB, UART, CSIO, I C, LIN). Features ® ® 32-bit ARM Cortex -M4F Core [SRAM] Processor version: r0p1 This is composed of three independent SRAMs (SRAM0, SRAM1, and SRAM2). SRAM0 is connected to I-code bus and D-code bus of Cortex-M4F core. SRAM1 and SRAM2 are connected to System bus of Cortex-M4F core. Up to 160 MHz Frequency Operation FPU built-in SRAM0: Up to 32 Kbytes Support DSP instruction Memory Protection Unit (MPU): improves the reliability of an embedded system Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 128 peripheral interrupts and 16 priority levels 24-bit System timer (Sys Tick): System timer for OS task management SRAM1: Up to 16 Kbytes SRAM2: Up to 16 Kbytes USB Interface USB interface is composed of Function and Host. USB function USB2.0 Full-Speed supported 6 Endpoint supported • Endpoint 0 is control transfer • Endpoint 1, 2 can be selected Bulk-transfer, Interrupt-transfer or Isochronous-transfer • Endpoint 3 to 5 can select Bulk-transfer or Interrupt-transfer • Endpoint 1 to 5 comprise Double Buffer The size of each endpoint is according to the follows. • Endpoint 0, 2 to 5: 64 bytes • Endpoint 1: 256 bytes Max On-chip Memories [Flash memory] These series are based on two independent on-chip Flash memories. MainFlash memory Up to 512 Kbytes Flash Accelerator System with 16 Kbytes trace buffer memory The read access to Flash memory can be achieved without wait-cycle up to operation frequency of 72 MHz. Even at the operation frequency more than 72 MHz, an equivalent access to Flash memory can be obtained by Flash Accelerator System. Security function for code protection Built-in WorkFlash memory 32 Kbytes cycle: • 6wait-cycle: the operation frequency more than 120 MHz, and up to 160 MHz • 4wait-cycle: the operation frequency more than 72 MHz, and up to 120 MHz • 2wait-cycle: the operation frequency more than 40 MHz, and up to 72 MHz • 0wait-cycle: the operation frequency up to 40 MHz Security function is shared with code protection Read Cypress Semiconductor Corporation Document Number: 002-04930 Rev.*A USB host USB2.0 Full/Low-speed supported interrupt-transfer and Isochronous-transfer Bulk-transfer, support Device connected/dis-connected automatically detect IN/OUT token handshake packet automatically Max 256-byte packet-length supported Wake-up function supported USB • 198 Champion Court • San Jose, CA 95134-1709 408-943-2600 Revised May 12, 2016 MB9B360L Series Multi-function Serial Interface (Max 6 channels) 64 bytes with FIFO (the FIFO step numbers are variable depending on the settings of the communication mode or bit length.) Operation mode is selectable from the followings for each channel. UART CSIO LIN 2 I C UART Full-duplex double buffer Selection with or without parity supported Built-in dedicated baud rate generator External clock available as a serial clock Hardware Flow control : Automatically control the transmission by CTS/RTS (only ch.4) Various error detect functions available (parity errors, framing errors, and overrun errors) CSIO Full-duplex double buffer dedicated baud rate generator Overrun error detect function available Serial chip select function (ch.6 only) Supports high-speed SPI (ch.0 and ch.6 only) Data length 5 to 16-bit Built-in LIN LIN protocol Rev.2.1 supported double buffer Master/Slave mode supported LIN break field generation (can change to 13 to 16-bit length) LIN break delimiter generation (can change to 1 to 4-bit length) Various error detect functions available (parity errors, framing errors, and overrun errors) I2 C Standard mode (Max 100 kbps) / High-speed mode (Max 400 kbps) supported Fast mode Plus (Fm+) (Max 1000 kbps, only for ch.3=ch.A and ch.4=ch.B) supported Full-duplex DMA Controller (8 channels) DMA Controller has an independent bus for CPU, so CPU and DMA Controller can process simultaneously. DSTC (Descriptor System data Transfer Controller) (128 channels) The DSTC can transfer data at high-speed without going via the CPU. The DSTC adopts the Descriptor system and, following the specified contents of the Descriptor which has already been constructed on the memory, can access directly the memory /peripheral device and performs the data transfer operation. It supports the software activation, the hardware activation and the chain activation functions. A/D Converter (Max 15 channels) [12-bit A/D Converter] Successive Approximation type Built-in 2 units Conversion time: 0.5 μs @ 5 V Priority conversion available (priority at 2levels) Scanning conversion mode Built-in FIFO for conversion data storage (for SCAN conversion: 16steps, for Priority conversion: 4steps) DA Converter (Max 2 channels) R-2R type 12-bit resolution Base Timer (Max 8 channels) Operation mode is selectable from the followings for each channel. 16-bit PWM timer 16-bit PPG timer 16-/32-bit reload timer 16-/32-bit PWC timer General Purpose I/O Port This series can use its pins as general purpose I/O ports when they are not used for external bus or peripherals. Moreover, the port relocate function is built in. It can set which I/O port the peripheral function can be allocated. Capable of pull-up control per pin 8 independently configured and operated channels Capable of reading pin level directly Transfer can be started by software or request from the Built-in the port relocate function built-in peripherals Transfer address area: 32-bit (4 Gbytes) Transfer mode: Block transfer/Burst transfer/Demand transfer Transfer data type: bytes/half-word/word Up to 48 high-speed general-purpose I/O ports @ 64 pin Package Some pin is 5 V tolerant I/O. See 4. Pin Description and 5. I/O Circuit Type for the corresponding pins. Transfer block count: 1 to 16 Number of transfers: 1 to 65536 Document Number: 002-04930 Rev.*A Page 2 of 124 MB9B360L Series Multi-function Timer (Max 2 units) Dual Timer (32-/16-bit Down Counter) The Multi-function timer is composed of the following blocks. 16-bit free-run timer × 3 ch./unit The Dual Timer consists of two programmable 32-/16-bit down counters. Operation mode is selectable from the followings for each channel. Input capture × 4 ch./unit Free-running Output compare × 6 ch./unit Periodic (=Reload) A/D activation compare × 6 ch./unit One-shot Minimum resolution: 6.25 ns Waveform generator × 3 ch./unit 16-bit PPG timer × 3 ch./unit Watch Counter The following function can be used to achieve the motor control. The Watch counter is used for wake up from the low-power consumption mode. It is possible to select the main clock, sub clock, built-in high-speed CR clock or built-in low-speed CR clock as the clock source. PWM signal output function Interval timer: up to 64 s (Max) @ Sub Clock: 32.768 kHz DC chopper waveform output function External Interrupt Controller Unit Dead time function External interrupt input pin: Max 16 pins Input capture function Include one non-maskable interrupt (NMI) A/D convertor activate function DTIF (Motor emergency stop) interrupt function Real-time clock (RTC) The Real-time clock can count Year/Month/Day/Hour/Minute/Second/A day of the week from 01 to 99. Interrupt function with specifying date and time (Year/Month/Day/Hour/Minute/Second/A day of the week.) is available. This function is also available by specifying only Year, Month, Day, Hour or Minute. Watchdog Timer (2 channels) A watchdog timer can generate interrupts or a reset when a time-out value is reached. This series consists of two different watchdogs, a "Hardware" watchdog and a "Software" watchdog. "Hardware" watchdog timer is clocked by low-speed internal CR oscillator. Therefore, "Hardware" watchdog is active in any power saving mode except STOP. CRC (Cyclic Redundancy Check) Accelerator Timer interrupt function after set time or each set time. The CRC accelerator helps a verify data transmission or storage integrity. Capable of rewriting the time with continuing the time count. CCITT CRC16 and IEEE-802.3 CRC32 are supported. Leap year automatic count is available. CCITT CRC16 Generator Polynomial: 0x1021 Quadrature Position/Revolution Counter (QPRC) (1 channel) IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7 The Quadrature Position/Revolution Counter (QPRC) is used to measure the position of the position encoder. Moreover, it is possible to use up/down counter. The detection edge of the three external event input pins AIN, BIN, and ZIN is configurable. 16-bit position counter 16-bit revolution counter Two 16-bit compare registers Document Number: 002-04930 Rev.*A Page 3 of 124 MB9B360L Series Clock and Reset VBAT Five clock sources (2 external oscillators, 2 internal CR oscillator, and Main PLL) that are dynamically selectable. The consumption power during the RTC operation can be reduced by supplying the power supply independent from the RTC (calendar circuit)/32 kHz oscillation circuit. The following circuits can also be used. Main clock: 4 MHz to 48 MHz RTC Sub Clock: 32.768 kHz 32 kHz oscillation circuit [Clocks] High-speed internal CR Clock: 4 MHz Power-on circuit Low-speed internal CR Clock: 100 kHz Back up register: 32 bytes Main PLL Clock Port circuit [Resets] Debug Reset requests from INITX pin Serial Wire JTAG Debug Port (SWJ-DP) Power on reset Software reset Unique ID Unique value of the device (41-bit) is set. Watchdog timers reset Low voltage detector reset Power Supply Clock supervisor reset Wide range voltage: Clock Super Visor (CSV) Clocks generated by internal CR oscillators are used to supervise abnormality of the external clocks. Three Power Supplies VCC Power supply for USB I/O: USBVCC = 3.0 V to 3.6 V (when USB is used) = 2.7 V to 5.5 V (when GPIO is used) External OSC clock failure (clock stop) is detected, reset is asserted. External OSC frequency anomaly is detected, interrupt or = 2.7 V to 5.5 V Power supply for VBAT: VBAT = 2.7 V to 5.5 V reset is asserted. Low-Voltage Detector (LVD) This Series include 2-stage monitoring of voltage on the VCC pins. When the voltage falls below the voltage has been set, Low-Voltage Detector generates an interrupt or reset. LVD1: error reporting via interrupt LVD2: auto-reset operation Low-power Consumption Mode Six low-power consumption modes are supported. SLEEP TIMER RTC STOP Deep standby RTC (selectable from with/without RAM retention) Deep standby stop (selectable from with/without RAM retention) Document Number: 002-04930 Rev.*A Page 4 of 124 MB9B360L Series Contents Features................................................................................................................................................................................... 1 1. Product Lineup .................................................................................................................................................................. 7 2. Packages ........................................................................................................................................................................... 8 3. Pin Assignment ................................................................................................................................................................. 9 4. Pin Description ................................................................................................................................................................ 13 4.1 List of Pin Numbers ..................................................................................................................................................... 13 4.2 List of Pin Functions .................................................................................................................................................... 19 5. I/O Circuit Type................................................................................................................................................................ 28 6. Handling Precautions ..................................................................................................................................................... 35 6.1 Precautions for Product Design ................................................................................................................................... 35 6.2 Precautions for Package Mounting .............................................................................................................................. 36 6.3 Precautions for Use Environment ................................................................................................................................ 37 7. Handling Devices ............................................................................................................................................................ 38 8. Block Diagram ................................................................................................................................................................. 40 9. Memory Size .................................................................................................................................................................... 41 10. Memory Map .................................................................................................................................................................... 41 11. Pin Status in Each CPU State ........................................................................................................................................ 44 12. Electrical Characteristics ............................................................................................................................................... 51 12.1 Absolute Maximum Ratings ......................................................................................................................................... 51 12.2 Recommended Operating Conditions.......................................................................................................................... 52 12.3 DC Characteristics....................................................................................................................................................... 55 12.3.1 Current Rating .............................................................................................................................................................. 55 12.3.2 Pin Characteristics ....................................................................................................................................................... 62 12.4 AC Characteristics ....................................................................................................................................................... 64 12.4.1 Main Clock Input Characteristics .................................................................................................................................. 64 12.4.2 Sub Clock Input Characteristics ................................................................................................................................... 65 12.4.3 Built-in CR Oscillation Characteristics .......................................................................................................................... 65 12.4.4 Operating Conditions of Main PLL (In the Case of Using Main Clock for Input Clock of PLL) ...................................... 66 12.4.5 Operating Conditions of USB PLL (In the Case of Using Main Clock for Input Clock of PLL) ...................................... 66 12.4.6 Operating Conditions of Main PLL (In the Case of Using Built-in High-speed CR Clock for Input Clock of Main PLL) 66 12.4.7 Reset Input Characteristics .......................................................................................................................................... 67 12.4.8 Power-on Reset Timing................................................................................................................................................ 67 12.4.9 GPIO Output Characteristics ........................................................................................................................................ 68 12.4.10 Base Timer Input Timing........................................................................................................................................... 69 12.4.11 UART Timing ............................................................................................................................................................ 70 12.4.12 External Input Timing ................................................................................................................................................ 95 12.4.13 Quadrature Position/Revolution Counter Timing ...................................................................................................... 96 2 12.4.14 I C Timing ................................................................................................................................................................. 98 12.4.15 JTAG Timing ........................................................................................................................................................... 100 12.5 12-bit A/D Converter .................................................................................................................................................. 101 12.6 12-bit D/A Converter .................................................................................................................................................. 104 12.7 USB Characteristics .................................................................................................................................................. 105 12.8 Low-Voltage Detection Characteristics ...................................................................................................................... 109 12.8.1 Low-Voltage Detection Reset ..................................................................................................................................... 109 12.8.2 Interrupt of Low-Voltage Detection ............................................................................................................................. 109 12.9 MainFlash Memory Write/Erase Characteristics ........................................................................................................ 110 Document Number: 002-04930 Rev.*A Page 5 of 124 MB9B360L Series 12.10 WorkFlash Memory Write/Erase Characteristics ....................................................................................................... 110 12.11 Standby Recovery Time ............................................................................................................................................ 111 12.11.1 Recovery cause: Interrupt/WKUP ........................................................................................................................... 111 12.11.2 Recovery Cause: Reset .......................................................................................................................................... 113 13. Ordering Information .................................................................................................................................................... 115 14. Package Dimensions .................................................................................................................................................... 116 15. Major Changes .............................................................................................................................................................. 121 Document History ............................................................................................................................................................... 123 Sales, Solutions, and Legal Information ........................................................................................................................... 124 Document Number: 002-04930 Rev.*A Page 6 of 124 MB9B360L Series 1. Product Lineup Memory Size Product name MainFlash memory WorkFlash memory On-chip SRAM SRAM0 SRAM1 SRAM1 MB9BF364K/L 256 Kbytes 32 Kbytes 32 Kbytes 16 Kbytes 8 Kbytes 8 Kbytes MB9BF365K/L MB9BF366K/L 384 Kbytes 32 Kbytes 48 Kbytes 24 Kbytes 12 Kbytes 12 Kbytes 512 Kbytes 32 Kbytes 64 Kbytes 32 Kbytes 16 Kbytes 16 Kbytes Function MB9BF364K MB9BF365K MB9BF366K Product name Pin count 48 Cortex-M4F, MPU, NVIC 128ch. 160 MHz 2.7 V to 5.5 V 1ch. 8ch. 128ch. 6ch. (Max) (In ch.1, only I2C is available.) CPU MF Timer Freq. Power supply voltage range USB2.0 (Function/Host) DMAC DSTC Multi-function Serial Interface (UART/CSIO/LIN/I2C) Base Timer (PWC/Reload timer/PWM/PPG) A/D activation compare Input capture Free-run timer Output compare Waveform generator PPG QPRC Dual Timer Real-Time Clock Watch Counter CRC Accelerator Watchdog Timer External Interrupts I/O Ports MB9BF364L MB9BF365L MB9BF366L 64 6ch. (Max) 8ch. (Max) 6ch. 4ch. 3ch. 6ch. 3ch. 3ch. 1 unit 2 units (Max) 1ch. 1 unit 1 unit 1 unit Yes 1ch. (SW) + 1ch. (HW) 15 pins (Max) + NMI × 1 33 pins (Max) 16 pins (Max) + NMI × 1 48 pins (Max) 12-bit A/D Converter 8ch. (2 units) 15ch. (2 units) 12-bit D/A Converter 2 units (Max) CSV (Clock Super Visor) LVD (Low-Voltage Detector) High-speed Built-in CR Low-speed Debug Function Unique ID Yes 2ch. 4 MHz (±2%) 100 kHz (Typ) SWJ-DP Yes Note: − All signals of the peripheral function in each product cannot be allocated by limiting the pins of package. It is necessary to use the port relocate function of the I/O port according to your function use. Document Number: 002-04930 Rev.*A Page 7 of 124 MB9B360L Series 2. Packages Product name Package LQFP: FPT-64P-M39 (0.65mm pitch) LQFP: FPT-64P-M38 (0.5mm pitch) LQFP: FPT-48P-M49 (0.5mm pitch) QFN: LCC-64P-M24 (0.5mm pitch) QFN: LCC-48P-M73 (0.5mm pitch) MB9BF364K MB9BF365K MB9BF366K - - - MB9BF364L MB9BF365L MB9BF366L - : Supported Note: − See 14. Package Dimensions for detailed information on each package. Document Number: 002-04930 Rev.*A Page 8 of 124 MB9B360L Series 3. Pin Assignment FPT-64P-M38/M39 VSS P81/UDP0 P80/UDM0 USBVCC P60/SCK1_1/NMIX/WKUP0/IC01_2 P61/AN14/ADTG_5/SOT1_1/INT15_1/UHCONX0/IC00_2 P62/AN13/SIN1_1/RX0_0/TIOB3_1/INT14_1 P63/AN12/SIN0_1/TX0_0/TIOA3_1/INT13_1/ADTG_4 P64/AN11/SOT0_1/TIOB2_1/INT12_1 P65/AN10/SCK0_1/TIOA2_1/INT11_1/RTCCO_0/SUBOUT_0 P66/AN09/INT10_1/IC13_0/CROUT_1 P00/TRSTX P01/TCK/SWCLK P02/TDI P03/TMS/SWDIO P04/TDO/SWO 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 (TOP VIEW) VCC 1 48 P26/AN08/SIN1_0/INT09_1/IC12_0 P50/AIN0_0/INT00_0/TIOA0_0/CTS4_0 2 47 P25/AN07/SOT1_0/INT08_1/IC11_0/CROUT_0 P51/BIN0_0/INT01_0/TIOB0_0/RTS4_0 3 46 P24/AN06/SCK1_0/INT07_1/IC10_0 P52/IC00_0/ZIN0_0/INT02_0/TIOA1_0/SIN4_0 4 45 P23/AN05/SCK0_0/TIOB1_1/INT06_1/DTTI1X_0 P53/IC01_0/INT03_0/TIOB1_0/SOT4_0 5 44 P22/AN04/SOT0_0/TIOA1_1/INT05_1/FRCK1_0 P54/IC02_0/INT04_0/TIOA2_0/SCK4_0 6 43 P21/AN03/ADTG_3/SIN0_0/TIOB0_1/INT04_1/RTO15_0 P55/IC03_0/INT05_0/TIOB2_0/SIN3_0 7 42 AVRH LQFP - 64 P56/FRCK0_0/INT06_0/TIOA3_0/SOT3_0 8 41 AVRL P57/DTTI0X_0/INT07_0/TIOB3_0/SCK3_0/ADTG_0 9 40 AVSS P30/RTO00_0/AIN0_1/INT08_0/TIOA4_0/SIN2_0 10 39 AVCC P31/RTO01_0/BIN0_1/INT09_0/TIOB4_0/SOT2_0 11 38 P20/AN02/SIN6_0/TIOA0_1/INT03_1/RTO14_0/RTCCO_1/SUBOUT_1/WKUP1 P32/RTO02_0/ZIN0_1/INT10_0/TIOA5_0/SCK2_0 12 37 P13/AN01/SOT6_0/TIOB7_1/RTO13_0/IC00_1/TX0_1 22 23 24 25 26 27 28 29 30 31 32 INITX C VSS VCC P40/TIOA7_0/INT14_0 P41/TIOB7_0/INT15_0/ADTG_1/WKUP3 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS VCC 21 33 P49/VWAKEUP 16 20 P10/DA0/TIOA4_1/INT00_1/AIN0_2/RTO10_0/IC03_1 VSS P48/VREGCTL 34 19 15 18 P11/DA1/ADTG_2/SCS6_0/TIOB4_1/INT01_1/BIN0_2/RTO11_0/IC02_1 P35/WKUP2/RTO05_0/INT13_0/TIOB6_0/SCK4_1 17 P12/AN00/SCK6_0/TIOA7_1/INT02_1/ZIN0_2/RTO12_0/IC01_1/RX0_1 35 VBAT 36 14 P47/X1A 13 P46/X0A P33/RTO03_0/INT11_0/TIOB5_0/SIN4_1 P34/RTO04_0/INT12_0/TIOA6_0/SOT4_1 Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: 002-04930 Rev.*A Page 9 of 124 MB9B360L Series LCC-64P-M24 VSS P81/UDP0 P80/UDM0 USBVCC P60/SCK1_1/NMIX/WKUP0/IC01_2 P61/AN14/ADTG_5/SOT1_1/INT15_1/UHCONX0/IC00_2 P62/AN13/SIN1_1/RX0_0/TIOB3_1/INT14_1 P63/AN12/SIN0_1/TX0_0/TIOA3_1/INT13_1/ADTG_4 P64/AN11/SOT0_1/TIOB2_1/INT12_1 P65/AN10/SCK0_1/TIOA2_1/INT11_1/RTCCO_0/SUBOUT_0 P66/AN09/INT10_1/IC13_0/CROUT_1 P00/TRSTX P01/TCK/SWCLK P02/TDI P03/TMS/SWDIO P04/TDO/SWO 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 (TOP VIEW) VCC 1 48 P26/AN08/SIN1_0/INT09_1/IC12_0 P50/AIN0_0/INT00_0/TIOA0_0/CTS4_0 2 47 P25/AN07/SOT1_0/INT08_1/IC11_0/CROUT_0 P51/BIN0_0/INT01_0/TIOB0_0/RTS4_0 3 46 P24/AN06/SCK1_0/INT07_1/IC10_0 P52/IC00_0/ZIN0_0/INT02_0/TIOA1_0/SIN4_0 4 45 P23/AN05/SCK0_0/TIOB1_1/INT06_1/DTTI1X_0 P53/IC01_0/INT03_0/TIOB1_0/SOT4_0 5 44 P22/AN04/SOT0_0/TIOA1_1/INT05_1/FRCK1_0 P54/IC02_0/INT04_0/TIOA2_0/SCK4_0 6 43 P21/AN03/ADTG_3/SIN0_0/TIOB0_1/INT04_1/RTO15_0 P55/IC03_0/INT05_0/TIOB2_0/SIN3_0 7 P56/FRCK0_0/INT06_0/TIOA3_0/SOT3_0 8 P57/DTTI0X_0/INT07_0/TIOB3_0/SCK3_0/ADTG_0 9 40 AVSS P30/RTO00_0/AIN0_1/INT08_0/TIOA4_0/SIN2_0 10 39 AVCC P31/RTO01_0/BIN0_1/INT09_0/TIOB4_0/SOT2_0 11 38 P20/AN02/SIN6_0/TIOA0_1/INT03_1/RTO14_0/RTCCO_1/SUBOUT_1/WKUP1 P32/RTO02_0/ZIN0_1/INT10_0/TIOA5_0/SCK2_0 12 37 P13/AN01/SOT6_0/TIOB7_1/RTO13_0/IC00_1/TX0_1 P33/RTO03_0/INT11_0/TIOB5_0/SIN4_1 13 36 P12/AN00/SCK6_0/TIOA7_1/INT02_1/ZIN0_2/RTO12_0/IC01_1/RX0_1 P34/RTO04_0/INT12_0/TIOA6_0/SOT4_1 14 35 P11/DA1/ADTG_2/SCS6_0/TIOB4_1/INT01_1/BIN0_2/RTO11_0/IC02_1 P35/WKUP2/RTO05_0/INT13_0/TIOB6_0/SCK4_1 15 34 P10/DA0/TIOA4_1/INT00_1/AIN0_2/RTO10_0/IC03_1 VSS 16 33 VCC 42 AVRH QFN - 64 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P46/X0A P47/X1A VBAT P48/VREGCTL P49/VWAKEUP INITX C VSS VCC P40/TIOA7_0/INT14_0 P41/TIOB7_0/INT15_0/ADTG_1/WKUP3 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS 41 AVRL Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: 002-04930 Rev.*A Page 10 of 124 MB9B360L Series FPT-48P-M49 VSS P81/UDP0 P80/UDM0 USBVCC P60/SCK1_1/NMIX/WKUP0/IC01_2 P61/AN14/ADTG_5/SOT1_1/INT15_1/UHCONX0/IC00_2 P66/AN09/INT10_1/CROUT_1 P00/TRSTX P01/TCK/SWCLK P02/TDI P03/TMS/SWDIO P04/TDO/SWO 48 47 46 45 44 43 42 41 40 39 38 37 (TOP VIEW) VCC 1 36 P23/AN05/SCK0_0/TIOB1_1/INT06_1 P54/IC02_0/INT04_0/TIOA2_0 2 35 P22/AN04/SOT0_0/TIOA1_1/INT05_1 P55/IC03_0/INT05_0/TIOB2_0/SIN3_0 3 34 P21/AN03/ADTG_3/SIN0_0/TIOB0_1/INT04_1 P56/FRCK0_0/INT06_0/TIOA3_0/SOT3_0 4 33 AVRH P57/DTTI0X_0/INT07_0/TIOB3_0/SCK3_0/ADTG_0 5 P30/RTO00_0/AIN0_1/INT08_0/TIOA4_0/SIN2_0 6 P31/RTO01_0/BIN0_1/INT09_0/TIOB4_0/SOT2_0 7 P32/RTO02_0/ZIN0_1/INT10_0/TIOA5_0/SCK2_0 8 29 P20/AN02/SIN6_0/TIOA0_1/INT03_1/RTCCO_1/SUBOUT_1/WKUP1 P33/RTO03_0/INT11_0/TIOB5_0/SIN4_1 9 28 P13/AN01/SOT6_0/TIOB7_1/IC00_1/TX0_1 P34/RTO04_0/INT12_0/TIOA6_0/SOT4_1 10 27 P12/AN00/SCK6_0/TIOA7_1/INT02_1/ZIN0_2/IC01_1/RX0_1 P35/WKUP2/RTO05_0/INT13_0/TIOB6_0/SCK4_1 11 26 P11/DA1/ADTG_2/SCS6_0/TIOB4_1/INT01_1/BIN0_2/IC02_1 VSS 12 25 P10/DA0/TIOA4_1/INIT00_1/AIN0_2/IC03_1 32 AVRL 31 AVSS LQFP - 48 13 14 15 16 17 18 19 20 21 22 23 24 P46/X0A P47/X1A VBAT INITX C VSS VCC PE0/MD1 MD0 PE2/X0 PE3/X1 VSS 30 AVCC Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: 002-04930 Rev.*A Page 11 of 124 MB9B360L Series LCC-48P-M73 VSS P81/UDP0 P80/UDM0 USBVCC P60/SCK1_1/NMIX/WKUP0/IC01_2 P61/AN14/ADTG_5/SOT1_1/INT15_1/UHCONX0/IC00_2 P66/AN09/INT10_1/CROUT_1 P00/TRSTX P01/TCK/SWCLK P02/TDI P03/TMS/SWDIO P04/TDO/SWO 48 47 46 45 44 43 42 41 40 39 38 37 (TOP VIEW) VCC 1 36 P23/AN05/SCK0_0/TIOB1_1/INT06_1 P54/IC02_0/INT04_0/TIOA2_0 2 35 P22/AN04/SOT0_0/TIOA1_1/INT05_1 P55/IC03_0/INT05_0/TIOB2_0/SIN3_0 3 34 P21/AN03/ADTG_3/SIN0_0/TIOB0_1/INT04_1 P56/FRCK0_0/INT06_0/TIOA3_0/SOT3_0 4 33 AVRH P57/DTTI0X_0/INT07_0/TIOB3_0/SCK3_0/ADTG_0 5 P30/RTO00_0/AIN0_1/INT08_0/TIOA4_0/SIN2_0 6 P31/RTO01_0/BIN0_1/INT09_0/TIOB4_0/SOT2_0 7 P32/RTO02_0/ZIN0_1/INT10_0/TIOA5_0/SCK2_0 8 29 P20/AN02/SIN6_0/TIOA0_1/INT03_1/RTCCO_1/SUBOUT_1/WKUP1 P33/RTO03_0/INT11_0/TIOB5_0/SIN4_1 9 28 P13/AN01/SOT6_0/TIOB7_1/IC00_1/TX0_1 P34/RTO04_0/INT12_0/TIOA6_0/SOT4_1 10 27 P12/AN00/SCK6_0/TIOA7_1/INT02_1/ZIN0_2/IC01_1/RX0_1 P35/WKUP2/RTO05_0/INT13_0/TIOB6_0/SCK4_1 11 26 P11/DA1/ADTG_2/SCS6_0/TIOB4_1/INT01_1/BIN0_2/IC02_1 VSS 12 25 P10/DA0/TIOA4_1/INIT00_1/AIN0_2/IC03_1 32 AVRL 31 AVSS QFN - 48 13 14 15 16 17 18 19 20 21 22 23 24 P46/X0A P47/X1A VBAT INITX C VSS VCC PE0/MD1 MD0 PE2/X0 PE3/X1 VSS 30 AVCC Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: 002-04930 Rev.*A Page 12 of 124 MB9B360L Series 4. Pin Description 4.1 List of Pin Numbers The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Pin No LQFP64 QFN64 1 LQFP48 QFN48 1 2 - 3 - 4 - 5 - Pin Name VCC P50 AIN0_0 INT00_0 TIOA0_0 CTS4_0 P51 BIN0_0 INT01_0 TIOB0_0 RTS4_0 P52 IC00_0 ZIN0_0 INT02_0 TIOA1_0 SIN4_0 P53 IC01_0 INT03_0 TIOB1_0 I/O circuit type Pin state type - - E K E K I K N K N K I K N K SOT4_0 (SDA4_0) 2 6 - 7 3 8 4 Document Number: 002-04930 Rev.*A P54 IC02_0 INT04_0 TIOA2_0 SCK4_0 (SCL4_0) P55 IC03_0 INT05_0 TIOB2_0 SIN3_0 P56 FRCK0_0 INT06_0 TIOA3_0 SOT3_0 (SDA3_0) Page 13 of 124 MB9B360L Series Pin No LQFP64 LQFP48 QFN64 QFN48 9 5 Pin Name P57 DTTI0X_0 INT07_0 TIOB3_0 I/O circuit Pin state type type N K G K G K G K G K G K G Q SCK3_0 (SCL3_0) 10 6 11 7 12 8 13 9 14 10 15 11 Document Number: 002-04930 Rev.*A ADTG_0 P30 RTO00_0 AIN0_1 INT08_0 TIOA4_0 SIN2_0 P31 RTO01_0 BIN0_1 INT09_0 TIOB4_0 SOT2_0 (SDA2_0) P32 RTO02_0 ZIN0_1 INT10_0 TIOA5_0 SCK2_0 (SCL2_0) P33 RTO03_0 INT11_0 TIOB5_0 SIN4_1 P34 RTO04_0 INT12_0 TIOA6_0 SOT4_1 (SDA4_1) P35 WKUP2 RTO05_0 INT13_0 TIOB6_0 SCK4_1 (SCL4_1) Page 14 of 124 MB9B360L Series Pin No LQFP64 QFN64 16 LQFP48 QFN48 12 17 13 18 14 19 15 20 - 21 - 22 23 24 25 16 17 18 19 26 - 27 - 28 20 29 21 30 22 31 23 32 33 24 - 34 25 - 35 26 - Document Number: 002-04930 Rev.*A Pin Name VSS P46 X0A P47 X1A VBAT P48 VREGCTL P49 VWAKEUP INITX C VSS VCC P40 TIOA7_0 INT14_0 P41 TIOB7_0 INT15_0 ADTG_1 WKUP3 PE0 MD1 MD0 PE2 X0 PE3 X1 VSS VCC P10 DA0 TIOA4_1 INT00_1 AIN0_2 IC03_1 RTO10_0 P11 DA1 ADTG_2 SCS6_0 TIOB4_1 INT01_1 BIN0_2 IC02_1 RTO11_0 I/O circuit type Pin state type - - P S Q T O U O U B - C - E K E Q C E J D A A A B - - R J R J Page 15 of 124 MB9B360L Series Pin No LQFP64 QFN64 36 LQFP48 QFN48 27 - 37 28 - 38 39 40 41 42 43 29 30 31 32 33 34 - 44 35 - 45 36 - Document Number: 002-04930 Rev.*A Pin Name P12 AN00 SCK6_0 TIOA7_1 INT02_1 ZIN0_2 IC01_1 RTO12_0 P13 AN01 SOT6_0 (SDA6_0) TIOB7_1 IC00_1 RTO13_0 P20 AN02 SIN6_0 TIOA0_1 INT03_1 RTCCO_1 SUBOUT_1 WKUP1 RTO14_0 AVCC AVSS AVRL AVRH P21 AN03 ADTG_3 SIN0_0 TIOB0_1 INT04_1 RTO15_0 P22 AN04 SOT0_0 (SDA0_0) TIOA1_1 INT05_1 FRCK1_0 P23 AN05 SCK0_0 (SCL0_0) TIOB1_1 INT06_1 DTTI1X_0 I/O circuit type Pin state type M M M L F O - - F M F M F M Page 16 of 124 MB9B360L Series Pin No LQFP64 QFN64 LQFP48 QFN48 46 - 47 - 48 - 49 37 50 38 51 39 52 40 53 41 54 42 - 55 - 56 - Document Number: 002-04930 Rev.*A Pin Name P24 AN06 SCK1_0 (SCL1_0) INT07_1 IC10_0 P25 AN07 SOT1_0 (SDA1_0) INT08_1 IC11_0 CROUT_0 P26 AN08 SIN1_0 INT09_1 IC12_0 P04 TDO SWO P03 TMS SWDIO P02 TDI P01 TCK SWCLK P00 TRSTX P66 AN09 INT10_1 CROUT_1 IC13_0 P65 AN10 SCK0_1 (SCL0_1) TIOA2_1 INT11_1 RTCCO_0 SUBOUT_0 P64 AN11 SOT0_1 (SDA0_1) TIOB2_1 INT12_1 I/O circuit type Pin state type F M F M F M E G E G E G E G E G F M L M L M Page 17 of 124 MB9B360L Series Pin No LQFP64 QFN64 LQFP48 QFN48 Pin Name I/O circuit type Pin state type F M F M F M I F - - H R H R - - P63 AN12 57 - SIN0_1 TIOA3_1 INT13_1 ADTG_4 P62 AN13 58 - 59 43 60 44 61 45 62 46 63 47 64 48 Document Number: 002-04930 Rev.*A SIN1_1 TIOB3_1 INT14_1 P61 AN14 ADTG_5 SOT1_1 (SDA1_1) INT15_1 UHCONX0 IC00_2 P60 SCK1_1 (SCK1_1) NMIX WKUP0 IC01_2 USBVCC P80 UDM0 P81 UDP0 VSS Page 18 of 124 MB9B360L Series 4.2 List of Pin Functions The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Pin function ADC Base Timer 0 Base Timer 1 Base Timer 2 Base Timer 3 Base Timer 4 Base Timer 5 Pin No Pin name ADTG_0 ADTG_1 ADTG_2 ADTG_3 ADTG_4 ADTG_5 AN00 AN01 AN02 AN03 AN04 AN05 AN06 AN07 AN08 AN09 AN10 AN11 AN12 AN13 AN14 TIOA0_0 TIOA0_1 TIOB0_0 TIOB0_1 TIOA1_0 TIOA1_1 TIOB1_0 TIOB1_1 TIOA2_0 TIOA2_1 TIOB2_0 TIOB2_1 TIOA3_0 TIOA3_1 TIOB3_0 TIOB3_1 TIOA4_0 TIOA4_1 TIOB4_0 TIOB4_1 TIOA5_0 TIOB5_0 Function description A/D converter external trigger input pin A/D converter analog input pin. ANxx describes ADC ch.xx. Base timer ch.0 TIOA pin Base timer ch.0 TIOB pin Base timer ch.1 TIOA pin Base timer ch.1 TIOB pin Base timer ch.2 TIOA pin Base timer ch.2 TIOB pin Base timer ch.3 TIOA pin Base timer ch.3 TIOB pin Base timer ch.4 TIOA pin Base timer ch.4 TIOB pin Base timer ch.5 TIOA pin Base timer ch.5 TIOB pin Document Number: 002-04930 Rev.*A LQFP64 QFN64 9 27 35 43 57 59 36 37 38 43 44 45 46 47 48 54 55 56 57 58 59 2 38 3 43 4 44 5 45 6 55 7 56 8 57 9 58 10 34 11 35 12 13 LQFP48 QFN48 5 26 34 43 27 28 29 34 35 36 42 43 29 34 35 36 2 3 4 5 6 25 7 26 8 9 Page 19 of 124 MB9B360L Series Pin function Base Timer 6 Base Timer 7 Debugger External Interrupt Pin No Pin name TIOA6_0 TIOB6_0 TIOA7_0 TIOA7_1 TIOB7_0 TIOB7_1 SWCLK SWDIO SWO TCK TDI TDO TMS TRSTX INT00_0 INT00_1 INT01_0 INT01_1 INT02_0 INT02_1 INT03_0 INT03_1 INT04_0 INT04_1 INT05_0 INT05_1 Function description Base timer ch.6 TIOA pin Base timer ch.6 TIOB pin Base timer ch.7 TIOA pin Base timer ch.7 TIOB pin Serial wire debug interface clock input pin Serial wire debug interface data input / output pin Serial wire viewer output pin JTAG test clock input pin JTAG test data input pin JTAG debug data output pin JTAG test mode state input/output pin JTAG test reset Input pin External interrupt request 00 input pin External interrupt request 01 input pin External interrupt request 02 input pin External interrupt request 03 input pin External interrupt request 04 input pin External interrupt request 05 input pin Document Number: 002-04930 Rev.*A LQFP64 QFN64 14 15 26 36 27 37 52 50 49 52 51 49 50 53 2 34 3 35 4 36 5 38 6 43 7 44 LQFP48 QFN48 10 11 27 28 40 38 37 40 39 37 38 41 25 26 27 29 2 34 3 35 Page 20 of 124 MB9B360L Series Pin function External Interrupt GPIO Pin No Pin name INT06_0 INT06_1 INT07_0 INT07_1 INT08_0 INT08_1 INT09_0 INT09_1 INT10_0 INT10_1 INT11_0 INT11_1 INT12_0 INT12_1 INT13_0 INT13_1 INT14_0 INT14_1 INT15_0 INT15_1 NMIX P00 P01 P02 P03 P04 P10 P11 P12 P13 P20 P21 P22 P23 P24 P25 P26 P30 P31 P32 P33 P34 P35 Function description External interrupt request 06 input pin External interrupt request 07 input pin External interrupt request 08 input pin External interrupt request 09 input pin External interrupt request 10 input pin External interrupt request 11 input pin External interrupt request 12 input pin External interrupt request 13 input pin External interrupt request 14 input pin External interrupt request 15 input pin Non-Maskable Interrupt input pin General-purpose I/O port 0 General-purpose I/O port 1 General-purpose I/O port 2 General-purpose I/O port 3 Document Number: 002-04930 Rev.*A LQFP64 QFN64 8 45 9 46 10 47 11 48 12 54 13 55 14 56 15 57 26 58 27 59 60 53 52 51 50 49 34 35 36 37 38 43 44 45 46 47 48 10 11 12 13 14 15 LQFP48 QFN48 4 36 5 6 7 8 42 9 10 11 43 44 41 40 39 38 37 25 26 27 28 29 34 35 36 6 7 8 9 10 11 Page 21 of 124 MB9B360L Series Pin No Pin function Pin name GPIO P40 P41 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P60 P61 P62 P63 P64 P65 P66 P80 P81 PE0 PE2 PE3 Function description General-purpose I/O port 4 General-purpose I/O port 5 General-purpose I/O port 6 General-purpose I/O port 8 General-purpose I/O port E Document Number: 002-04930 Rev.*A LQFP64 QFN64 26 27 17 18 20 21 2 3 4 5 6 7 8 9 60 59 58 57 56 55 54 62 63 28 30 31 LQFP48 QFN48 13 14 2 3 4 5 44 43 42 46 47 20 22 23 Page 22 of 124 MB9B360L Series Pin function Pin No Pin name SIN0_0 SIN0_1 Multifunction Serial 0 SOT0_0 (SDA0_0) SOT0_1 (SDA0_1) SCK0_0 (SCL0_0) SCK0_1 (SCL0_1) SIN1_0 SIN1_1 Multifunction Serial 1 SOT1_0 (SDA1_0) SOT1_1 (SDA1_1) SCK1_0 (SCL1_0) SCK1_1 (SCL1_1) SIN2_0 Multifunction Serial 2 SOT2_0 (SDA2_0) SCK2_0 (SCL2_0) Function description LQFP64 QFN64 43 LQFP48 QFN48 34 57 - Multi-function serial interface ch.0 output pin. This pin operates as SOT0 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA0 when it is used in an I2C (operation mode 4). 44 35 56 - Multi-function serial interface ch.0 clock I/O pin. This pin operates as SCK0 when it is used in a CSIO (operation modes 2) and as SCL0 when it is used in an I2C (operation mode 4). 45 36 55 - 48 - 58 - Multi-function serial interface ch.1 output pin. This pin operates as SOT1 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA1 when it is used in an I2C (operation mode 4). 47 - 59 43 Multi-function serial interface ch.1 clock I/O pin. This pin operates as SCK1 when it is used in a CSIO (operation modes 2) and as SCL1 when it is used in an I2C (operation mode 4). 46 - 60 44 Multi-function serial interface ch.2 input pin 10 6 11 7 12 8 Multi-function serial interface ch.0 input pin Multi-function serial interface ch.1 input pin Multi-function serial interface ch.2 output pin. This pin operates as SOT2 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA2 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.2 clock I/O pin. This pin operates as SCK2 when it is used in a CSIO (operation modes 2) and as SCL2 when it is used in an I2C (operation mode 4). Document Number: 002-04930 Rev.*A Page 23 of 124 MB9B360L Series Pin No Pin function Multifunction Serial 3 Multifunction Serial 4 Multifunction Serial 6 Pin name Function description SIN3_0 Multi-function serial interface ch.3 input pin Multi-function serial interface ch.3 output pin. This pin operates as SOT3 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA3 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.3 clock I/O pin. This pin operates as SCK3 when it is used in a CSIO (operation modes 2) and as SCL3 when it is used in an I2C (operation mode 4). SOT3_0 (SDA3_0) SCK3_0 (SCL3_0) SIN4_0 SIN4_1 SOT4_0 (SDA4_0) SOT4_1 (SDA4_1) SCK4_0 (SCL4_0) SCK4_1 (SCL4_1) CTS4_0 RTS4_0 SIN6_0 SOT6_0 (SDA6_0) SCK6_0 (SCL6_0) SCS6_0 Multi-function serial interface ch.4 input pin Multi-function serial interface ch.4 output pin. This pin operates as SOT4 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA4 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.4 clock I/O pin. This pin operates as SCK4 when it is used in a CSIO (operation modes 2) and as SCL4 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.4 CTS input pin Multi-function serial interface ch.4 RTS output pin Multi-function serial interface ch.6 input pin This pin operates as SOT6 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA6 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.6 clock I/O pin. This pin operates as SCK6 when it is used in a CSIO (operation modes 2) and as SCL6 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.6 serial chip select pin Document Number: 002-04930 Rev.*A LQFP64 QFN64 7 LQFP48 QFN48 3 8 4 9 5 4 13 9 5 - 14 10 6 - 15 11 2 3 38 29 37 28 36 27 35 26 Page 24 of 124 MB9B360L Series Pin No Pin function Pin name LQFP64 QFN64 LQFP48 QFN48 DTTI0X_0 Input signal controlling wave form generator outputs RTO00 to RTO05 of Multi-function timer 0. 9 5 FRCK0_0 16-bit free-run timer ch.0 external clock input pin 8 4 IC00_0 4 - IC00_1 37 28 IC00_2 59 43 IC01_0 5 - 36 27 IC01_1 IC01_2 Multifunction Timer 0 Function description 16-bit input capture ch.0 input pin of Multi-function timer 0. ICxx describes channel number. 60 44 IC02_0 6 2 IC02_1 35 26 IC03_0 7 3 34 25 10 6 11 7 12 8 13 9 14 10 15 11 IC03_1 RTO00_0 (PPG00_0) RTO01_0 (PPG00_0) RTO02_0 (PPG02_0) RTO03_0 (PPG02_0) RTO04_0 (PPG04_0) RTO05_0 (PPG04_0) Wave form generator output pin of Multi-function timer 0. This pin operates as PPG00 when it is used in PPG0 output modes. Wave form generator output pin of Multi-function timer 0. This pin operates as PPG00 when it is used in PPG0 output modes. Wave form generator output pin of Multi-function timer 0. This pin operates as PPG02 when it is used in PPG0 output modes. Wave form generator output pin of Multi-function timer 0. This pin operates as PPG02 when it is used in PPG0 output modes. Wave form generator output pin of Multi-function timer 0. This pin operates as PPG04 when it is used in PPG0 output modes. Wave form generator output pin of Multi-function timer 0. This pin operates as PPG04 when it is used in PPG0 output modes. Document Number: 002-04930 Rev.*A Page 25 of 124 MB9B360L Series Pin No Pin function Pin name DTTI1X_0 FRCK1_0 IC10_0 IC11_0 IC12_0 IC13_0 RTO10_0 (PPG10_0) Multifunction Timer 1 RTO11_0 (PPG10_0) RTO12_0 (PPG12_0) RTO13_0 (PPG12_0) RTO14_0 (PPG14_0) RTO15_0 (PPG14_0) Quadrature Position/ Revolution Counter 0 AIN0_0 AIN0_1 AIN0_2 BIN0_0 BIN0_1 BIN0_2 ZIN0_0 ZIN0_1 ZIN0_2 Function description Input signal controlling wave form generator outputs RTO10 to RTO15 of Multi-function timer 1. 16-bit free-run timer ch.1 external clock input pin 16-bit input capture ch.1 input pin of Multi-function timer 1. ICxx describes channel number. Wave form generator output pin of Multi-function timer 1. This pin operates as PPG10 when it is used in PPG1 output modes. Wave form generator output pin of Multi-function timer 1. This pin operates as PPG10 when it is used in PPG1 output modes. Wave form generator output pin of Multi-function timer 1. This pin operates as PPG12 when it is used in PPG1 output modes. Wave form generator output pin of Multi-function timer 1. This pin operates as PPG12 when it is used in PPG1 output modes. Wave form generator output pin of Multi-function timer 1. This pin operates as PPG14 when it is used in PPG1 output modes. Wave form generator output pin of Multi-function timer 1. This pin operates as PPG14 when it is used in PPG1 output modes. QPRC ch.0 AIN input pin QPRC ch.0 BIN input pin QPRC ch.0 ZIN input pin Document Number: 002-04930 Rev.*A LQFP64 QFN64 LQFP48 QFN48 45 - 44 46 47 48 54 - 34 - 35 - 36 - 37 - 38 - 43 - 2 10 34 3 11 35 4 12 36 6 25 7 26 8 36 Page 26 of 124 MB9B360L Series Pin No Pin function Real-time clock USB Low-Power Consumpti on Mode DAC VBAT Reset Pin name RTCCO_0 RTCCO_1 SUBOUT_0 SUBOUT_1 UDM0 UDP0 UHCONX0 WKUP0 WKUP1 WKUP2 WKUP3 DA0 DA1 VREGCTL VWAKEUP INITX MD1 Mode MD0 Power VCC USBVCC GND Clock Analog Power VBAT Power Analog GND C pin VSS X0 X1 X0A X1A CROUT_0 CROUT_1 AVCC AVRH VBAT AVSS AVRL C Function description 0.5 seconds pulse output pin of Real-time clock Sub clock output pin Sub clock output pin USB function/host D – pin USB function/host D + pin USB external pull-up control pin Deep standby mode return signal input pin 0 Deep standby mode return signal input pin 1 Deep standby mode return signal input pin 2 Deep standby mode return signal input pin 3 D/A converter ch.0 analog output pin D/A converter ch.1 analog output pin On-board regulator control pin The return signal input pin from a hibernation state External Reset Input pin. A reset is valid when INITX="L". Mode 1 pin. During serial programming to Flash memory, MD1="L" must be input. Mode 0 pin. During normal operation, MD0="L" must be input. During serial programming to Flash memory, MD0="H" must be input. Power supply Pin 3.3V Power supply port for USB I/O GND Pin Main clock (oscillation) input pin Main clock (oscillation) I/O pin Sub clock (oscillation) input pin Sub clock (oscillation) I/O pin Built-in high-speed CR-osc clock output port A/D converter and D/A converter analog power supply pin A/D converter analog reference voltage input pin VBAT power supply pin. Backup power supply (battery etc.) and system power supply. A/D converter and D/A converter GND pin A/D converter analog reference voltage input pin Power supply stabilization capacity pin Document Number: 002-04930 Rev.*A LQFP64 QFN64 55 38 55 38 62 63 59 60 38 15 27 34 35 20 21 LQFP48 QFN48 29 29 46 47 43 44 29 11 25 26 - 22 16 28 20 29 21 1 25 33 61 16 24 32 64 30 31 17 18 47 54 39 42 1 19 45 12 18 24 48 22 23 13 14 42 30 33 19 15 40 31 41 23 32 17 Page 27 of 124 MB9B360L Series 5. I/O Circuit Type Type Circuit P-ch P-ch Remarks Digital output X1 N-ch Digital output R It is possible to select the main oscillation / GPIO function Pull-up resistor control Digital input Standby mode control Clock input A When the main oscillation is selected. • Oscillation feedback resistor : Approximately 1 MΩ • With Standby mode control When the GPIO is selected. Standby mode control Digital input Standby mode control • • • • • CMOS level output. CMOS level hysteresis input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50 kΩ • IOH = -4 mA, IOL = 4 mA R P-ch P-ch Digital output N-ch Digital output X0 Pull-up resistor control B • CMOS level hysteresis input • Pull-up resistor : Approximately 50 kΩ Pull-up resistor Digital input Document Number: 002-04930 Rev.*A Page 28 of 124 MB9B360L Series Type Circuit Remarks Digital input C Digital output N-ch P-ch P-ch Digital output E N-ch • Open drain output • CMOS level hysteresis input Digital output R • • • • • CMOS level output CMOS level hysteresis input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50 kΩ • IOH = -4 mA, IOL = 4 mA Pull-up resistor control Digital input Standby mode control P-ch P-ch N-ch Digital output Digital output F Pull-up resistor control R Digital input Standby mode control • • • • • • • CMOS level output CMOS level hysteresis input With input control Analog input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50 kΩ • IOH = -4 mA, IOL = 4 mA 2 • When this pin is used as an I C pin, the digital output P-ch transistor is always off Analog input Input control Document Number: 002-04930 Rev.*A Page 29 of 124 MB9B360L Series Type Circuit P-ch P-ch Remarks Digital output G N-ch Digital output R • • • • • CMOS level output CMOS level hysteresis input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50 kΩ • IOH = -12 mA, IOL = 12 mA 2 • When this pin is used as an I C pin, the digital output P-ch transistor is always off Pull-up resistor control Digital input Standby mode control GPIO Digital output GPIO Digital input/output direction GPIO Digital input GPIO Digital input circuit control UDP output UDP/Pxx It is possible to select the USB I/O / GPIO function. USB Full-speed/Low-speed control UDP input When the USB I/O is selected. • Full-speed, Low-speed control H Differential UDM/Pxx Differential input USB/GPIO select UDM input UDM output When the GPIO is selected. • • • • CMOS level output CMOS level hysteresis input With standby mode control IOH = -20.5 mA, IOL = 18.5 mA USB Digital input/output direction GPIO Digital output GPIO Digital input/output direction GPIO Digital input GPIO Digital input circuit control Document Number: 002-04930 Rev.*A Page 30 of 124 MB9B360L Series Type Circuit P-ch P-ch Remarks Digital output I N-ch Digital output R Pull-up resistor control Digital input • • • • • • • CMOS level output CMOS level hysteresis input With pull-up resistor control 5 V tolerant With standby mode control IOH = -4 mA, IOL = 4 mA Available to control of PZR registers. 2 • When this pin is used as an I C pin, the digital output P-ch transistor is always off Standby mode control J Mode input P-ch L P-ch N-ch R Digital output Digital output Pull-up resistor control Digital input CMOS level hysteresis input • • • • • CMOS level output CMOS level hysteresis input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50 kΩ • IOH = -8 mA, IOL = 8 mA 2 • When this pin is used as an I C pin, the digital output P-ch transistor is always off Standby mode control Document Number: 002-04930 Rev.*A Page 31 of 124 MB9B360L Series Type Circuit P-ch P-ch N-ch Remarks Digital output Digital output M Pull-up resistor control Digital input R • • • • • • • CMOS level output CMOS level hysteresis input With input control Analog input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50 kΩ • IOH = -8 mA, IOL = 8 mA 2 • When this pin is used as an I C pin, the digital output P-ch transistor is always off Standby mode control Analog input Input control Pull-up resistor control P-ch P-ch N N-ch N-ch Digital output Digital output Fast mode control R • • • • • CMOS level output CMOS level hysteresis input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50 kΩ • IOH = -4 mA, IOL = 4 mA (GPIO) • IOL = 20 mA (Fast Mode Plus) 2 • When this pin is used as an I C pin, the digital output P-ch transistor is always off Digital input Standby mode control Document Number: 002-04930 Rev.*A Page 32 of 124 MB9B360L Series Type Circuit P-ch P-ch O N-ch Remarks Pull-up resistor control Digital output Digital output • • • • • • CMOS level output CMOS level hysteresis input 5 V tolerant With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50 kΩ • IOH = -4 mA, IOL = 4 mA • For I/O setting, refer to VBAT Domain in the Peripheral Manual R Digital input Standby mode control P-ch P-ch X0A N-ch P Pull-up resistor control Digital output Digital output • • • • • CMOS level output CMOS level hysteresis input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50 kΩ • IOH = -4 mA, IOL = 4 mA • For I/O setting, refer to VBAT Domain in the Peripheral Manual R Digital input Standby mode control OSC Document Number: 002-04930 Rev.*A Page 33 of 124 MB9B360L Series Type Circuit Pull-up resistor control Digital output P-ch P-ch X1A Remarks It is possible to select the sub oscillation / GPIO function When the sub oscillation is selected. Digital output N-ch Q R Digital input Standby mode control OSC RX • Oscillation feedback resistor : Approximately 10 MΩ • With Standby mode control When the GPIO is selected. • CMOS level output. • CMOS level hysteresis input • With pull-up resistor control • With standby mode control • Pull-up resistor : Approximately 50 kΩ • IOH = -4 mA, IOL = 4 mA • For I/O setting, refer to VBAT Domain in the Peripheral Manual Standby mode control Clock input P-ch P-ch N-ch Digital output Digital output R R Pull-up resistor control Digital input • • • • • • • CMOS level output CMOS level hysteresis input With input control Analog output With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50 kΩ • IOH = -12 mA, IOL = 12 mA (4.5 V to 5.5 V) • IOH = -8 mA, IOL = 8 mA (2.7 V to 4.5 V) Standby mode control Analog output Document Number: 002-04930 Rev.*A Page 34 of 124 MB9B360L Series 6. Handling Precautions Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices. 6.1 Precautions for Product Design This section describes precautions when designing electronic equipment using semiconductor devices. Absolute Maximum Ratings Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings. Recommended Operating Conditions Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their sales representative beforehand. Processing and Protection of Pins These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. 1. Preventing Over-Voltage and Over-Current Conditions Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the design stage. 2. Protection of Output Pins Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such conditions if present for extended periods of time can damage the device. Therefore, avoid this type of connection. 3. Handling of Unused Input Pins Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected through an appropriate resistance to a power supply pin or ground pin. Latch-up Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred mA to flow continuously at the power supply pin. This condition is called latch-up. CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the following: 1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal noise, surge levels, etc. 2. Be sure that abnormal current flows do not occur during the power-on sequence. Observance of Safety Regulations and Standards Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the design of products. Fail-Safe Design Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Document Number: 002-04930 Rev.*A Page 35 of 124 MB9B360L Series Precautions Related to Usage of Devices Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. 6.2 Precautions for Package Mounting Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you should only mount under Cypress's recommended conditions. For detailed information about mount conditions, contact your sales representative. Lead Insertion Type Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress recommended mounting conditions. If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be verified before mounting. Surface Mount Type Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and have established a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended conditions. Lead-Free Packaging CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be reduced under some conditions of use. Storage of Semiconductor Devices Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following: 1. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in locations where temperature changes are slight. 2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C and 30°C. When you open Dry Package that recommends humidity 40% to 70% relative humidity. 3. When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage. 4. Avoid storing packages where they are exposed to corrosive gases or high levels of dust. Baking Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended conditions for baking. Condition: 125°C/24 h Document Number: 002-04930 Rev.*A Page 36 of 124 MB9B360L Series Static Electricity Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: 1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be needed to remove electricity. 2. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. 3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 MΩ). Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. 4. Ground all fixtures and instruments, or protect with anti-static measures. 5. Avoid the use of Styrofoam or other highly static-prone materials for storage of completed board assemblies. 6.3 Precautions for Use Environment Reliability of semiconductor devices depends on ambient temperature and other conditions as described above. For reliable performance, do the following: 1. Humidity Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are anticipated, consider anti-humidity processing. 2. Discharge of Static Electricity When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use anti-static measures or processing to prevent discharges. 3. Corrosive Gases, Dust, or Oil Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. 4. Radiation, Including Cosmic Radiation Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding as appropriate. 5. Smoke, Flame CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic gases. Customers considering the use of Cypress products in other special environmental conditions should consult with sales representatives. Document Number: 002-04930 Rev.*A Page 37 of 124 MB9B360L Series 7. Handling Devices Power Supply Pins In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with each POWER pins and GND pins of this device at low impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between VCC and VSS near this device. Power Supply Pins A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the guaranteed operating range of the VCC power supply voltage. As a rule of voltage stabilization, suppress voltage fluctuation so that the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the standard VCC value, and the transient fluctuation rate does not exceed 0.1 V/μs at a momentary fluctuation such as switching the power supply. Crystal Oscillator Circuit Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1, X0A/X1A pins, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground are located as close to the device as possible. It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by ground plane as this is expected to produce stable operation. Evaluate oscillation of your using crystal oscillator by your mount board. Sub Crystal Oscillator This series sub oscillator circuit is low gain to keep the low current consumption. The crystal oscillator to fill the following conditions is recommended for sub crystal oscillator to stabilize the oscillation. • Surface mount type Size Load capacitance • Lead type Load capacitance : More than 3.2 mm × 1.5 mm : Approximately 6 pF to 7 pF : Approximately 6 pF to 7 pF Using an External Clock When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input the clock to X0. X1 (PE3) can be used as a general-purpose I/O port. Similarly, when using an external clock as an input of the sub clock, set X0A/X1A to the external clock input, and input the clock to X0A. X1A (P47) can be used as a general-purpose I/O port. Example of Using an External Clock Device X0(X0A) Set as External clock input Can be used as general-purpose I/O ports. Document Number: 002-04930 Rev.*A X1(PE3), X1A (P47) Page 38 of 124 MB9B360L Series 2 Handling when Using Multi-function Serial Pin as I C Pin 2 If it is using the multi-function serial pin as I C pins, P-ch transistor of digital output is always disabled. 2 2 However, I C pins need to keep the electrical characteristic like other pins and not to connect to the external I C bus system with power OFF. C Pin This series contains the regulator. Be sure to connect a smoothing capacitor (C S) for the regulator between the C pin and the GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor. However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor. A smoothing capacitor of about 4.7 μF would be recommended for this series. C Device CS VSS GND Mode Pins (MD0) Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance stays low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is because of preventing the device erroneously switching to test mode due to noise. Notes on Power-on Turn power on/off in the following order or at the same time. If not using the A/D converter and D/A converter, connect AVCC = VCC and AVSS = VSS. Turning on: Turning off: VBAT → VCC → USBVCC VCC → AVCC → AVRH USBVCC → VCC → VBAT AVRH → AVCC → VCC Serial Communication There is a possibility to receive wrong data due to the noise or other causes on the serial communication. Therefore, design a printed circuit board so as to avoid noise. Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end. If an error is detected, retransmit the data. Differences in Features among the Products with Different Memory Sizes and between Flash Products and MASK Products The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics among the products with different memory sizes and between Flash products and MASK products are different because chip layout and memory structures are different. If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics. Pull-Up Function of 5 V Tolerant I/O Please do not input the signal more than VCC voltage at the time of pull-up function use of 5V tolerant I/O. Handling when Using Debug Pins When debug pins (TDO/TMS/TDI/TCK/TRSTX or SWO/SWDIO/SWCLK) are set to GPIO or other peripheral functions, only set them as output, do not set them as input. Document Number: 002-04930 Rev.*A Page 39 of 124 MB9B360L Series 8. Block Diagram MB9BF364K/L, F365K/L, F366K/L TRSTX,TCK, TDI,TMS TDO SRAM0 16/24/32 Kbytes SWJ-DP ROM Table SRAM1 8/12/16 Kbytes Cortex-M4F Core I @160 MHz(Max) MPU Multi-layer AHB (Max 160 MHz) D FPU NVIC Sys AHB-APB Bridge: APB0(Max 80 MHz) Dual-Timer Watchdog Timer (Software) Clock Reset Generator INITX Watchdog Timer (Hardware) SRAM2 8/12/16 Kbytes MainFlash I/F MainFlash 512 Kbytes/ 384 Kbytes/ 256 Kbytes Trace Buffer (16 Kbytes) Security WorkFlash 32 Kbytes WorkFlash I/F USB2.0 (Host/ Func) CSV PHY USBVCC UDP0,UDM0 UHCONX0 DMAC 8ch. CLK DSTC X0A X1A Main Osc PLL VBAT Domain Sub Osc AHB-AHB Bridge Source Clock X0 X1 CR 100 kHz CR 4 MHz GPIO PIN-FunctionCtrl CROUT ADTGx TIOAx TIOBx AINx BINx ZINx 12-bit A/D Converter Unit 0 Base Timer 16-bit 16ch./ 32-bit 8ch. QPRC 1ch. A/D Activation Compare 6ch. ICxx FRCKx 16-bit Input Capture 4ch. 16-bit Free-run Timer 3ch. 16-bit Output Compare 6ch. DTTIxX RTOxx USB Clock Ctrl Unit 1 Waveform Generator 3ch. 16-bit PPG 3ch. Multi-function Timer × 2 Document Number: 002-04930 Rev.*A PLL . . . PEx Power-On Reset LVD Ctrl LVD IRQ-Monitor Regulator C CRC Accelerator AHB-APB Bridge : APB2 (Max 80 MHz) ANxx AHB-APB Bridge : APB1 (Max 160 MHz) AVCC, AVSS, AVRH P0x, P1x, Watch Counter Deep Standby Ctrl WKUPx Peripheral Clock Gating Low-speed CR Prescaler VBAT Domain Real-Time Clock Port Ctrl. VWAKEUP VREGCTL RTCCO, SUBOUT External Interrupt Controller 16pin + NMI INTxx NMIX MODE-Ctrl MD0, MD1 Multi-function Serial I/F 6ch. HW flow control(ch.4) SCKx SINx SOTx CTS4 RTS4 12-bit D/A Converter 2units DAx Page 40 of 124 MB9B360L Series 9. Memory Size See Memory size in 1. Product Lineup to confirm the memory size. 10. Memory Map Memory Map (1) Peripherals Area 0x41FF_FFFF Reserved 0x4007_0000 0x4006_F000 GPIO Reserved 0xFFFF_FFFF Reserved 0xE010_0000 0xE000_0000 Cortex-M4F Private Peripherals 0x4006_2000 0x4006_1000 0x4006_0000 0x4005_0000 0x4004_0000 External Device Area 0x6000_0000 Reserved 0x4400_0000 0x4200_0000 32 Mbytes Bit band alias Peripherals 0x4000_0000 Reserved 0x2400_0000 0x2200_0000 32 Mbytes Bit band alias Reserved 0x2010_0000 0x200E_0000 0x200C_0000 See "lMemory Map (2)" for the memory size details. 0x2004_4000 0x2004_0000 0x2003_C000 0x2000_0000 0x1FFF_8000 0x0050_0000 0x0040_0000 WorkFlash I/F WorkFlash Reserved SRAM2 SRAM1 Reserved SRAM0 Reserved Security/CR Trim MainFlash 0x0000_0000 Reserved USB ch.0 Reserved 0x4003_C800 0x4003_C100 Peripheral Clock Gating 0x4003_C000 Low Speed CR Prescaler 0x4003_B000 RTC/Port Ctrl 0x4003_A000 Watch Counter 0x4003_9000 CRC 0x4003_8000 MFS Reserved 0x4003_7000 0x4003_6000 USB Clock ctrl 0x4003_5000 LVD/DS mode 0x4003_4000 Reserved 0x4003_3000 D/AC Reserved 0x4003_2000 0x4003_1000 Int-Req.Read 0x4003_0000 EXTI 0x4002_F000 Reserved 0x4002_E000 CR Trim 0x4002_8000 0x4002_7000 0x4002_6000 0x4002_5000 0x4002_4000 0x4002_2000 0x4002_1000 0x4002_0000 0x4001_6000 0x4001_5000 0x4001_3000 0x4001_2000 0x4001_1000 0x4001_0000 0x4000_1000 0x4000_0000 Document Number: 002-04930 Rev.*A DSTC DMAC Reserved A/DC QPRC Base Timer PPG Reserved MFT Unit1 MFT Unit0 Reserved Dual Timer Reserved SW WDT HW WDT Clock/Reset Reserved MainFlash I/F Page 41 of 124 MB9B360L Series Memory Map (2) MB9BF366K/L 0x2008_0000 MB9BF365K/L 0x2008_0000 Reserved 0x200C_8000 0x200C_0000 0x2008_0000 Reserved 0x200C_8000 WorkFlash 32 Kbytes MB9BF364K/L 0x200C_0000 Reserved Reserved 0x200C_8000 WorkFlash 32 Kbytes 0x200C_0000 Reserved 0x2004_4000 WorkFlash 32 Kbytes Reserved 0x2004_3000 SRAM2 16 Kbytes 0x2004_0000 0x2004_0000 SRAM1 16 Kbytes 0x2003_D000 SRAM2 12 Kbytes SRAM1 12 Kbytes 0x2004_2000 0x2004_0000 0x2003_E000 SRAM2 8 Kbytes SRAM1 8 Kbytes 0x2003_C000 0x2000_0000 0x2000_0000 SRAM0 32 Kbytes Reserved Reserved Reserved 0x1FFF_A000 0x2000_0000 SRAM0 24 Kbytes 0x1FFF_C000 SRAM0 16 Kbytes 0x1FFF_8000 0x0050_0000 0x0040_2000 0x0040_0000 0x0050_0000 CR trimming Security Reserved Reserved Reserved 0x0040_2000 0x0040_0000 0x0050_0000 CR trimming Security 0x0040_2000 0x0040_0000 CR trimming Security Reserved Reserved 0x0008_0000 Reserved 0x0006_0000 MainFlash 512 Kbytes 0x0000_0000 Document Number: 002-04930 Rev.*A 0x0004_0000 MainFlash 384 Kbytes 0x0000_0000 MainFlash 256 Kbytes 0x0000_0000 Page 42 of 124 MB9B360L Series Peripheral Address Map Start address End address 0x4000_0000 0x4000_1000 0x4001_0000 0x4001_1000 0x4001_2000 0x4001_3000 0x4001_5000 0x4001_6000 0x4002_0000 0x4002_1000 0x4002_2000 0x4002_4000 0x4002_5000 0x4002_6000 0x4002_7000 0x4002_8000 0x4002_E000 0x4002_F000 0x4003_0000 0x4003_1000 0x4003_2000 0x4003_3000 0x4003_4000 0x4003_5000 0x4003_5800 0x4003_6000 0x4003_7000 0x4003_8000 0x4003_9000 0x4003_A000 0x4003_B000 0x4003_C000 0x4003_C100 0x4003_C800 0x4004_0000 0x4005_0000 0x4006_0000 0x4006_1000 0x4006_2000 0x4006_F000 0x4006_7000 0x200E_0000 0x4000_0FFF 0x4000_FFFF 0x4001_0FFF 0x4001_1FFF 0x4001_2FFF 0x4001_4FFF 0x4001_5FFF 0x4001_FFFF 0x4002_0FFF 0x4002_1FFF 0x4003_FFFF 0x4002_4FFF 0x4002_5FFF 0x4002_6FFF 0x4002_7FFF 0x4002_DFFF 0x4002_EFFF 0x4002_FFFF 0x4003_0FFF 0x4003_1FFF 0x4003_4FFF 0x4003_3FFF 0x4003_4FFF 0x4003_57FF 0x4003_5FFF 0x4003_6FFF 0x4003_7FFF 0x4003_8FFF 0x4003_9FFF 0x4003_AFFF 0x4003_BFFF 0x4003_C0FF 0x4003_C7FF 0x4003_FFFF 0x4004_FFFF 0x4005_FFFF 0x4006_0FFF 0x4006_1FFF 0x4006_EFFF 0x4006_FFFF 0x41FF_FFFF 0x200E_FFFF Document Number: 002-04930 Rev.*A Bus AHB APB0 APB1 APB2 AHB Peripherals MainFlash I/F register Reserved Clock/Reset Control Hardware Watchdog timer Software Watchdog timer Reserved Dual-Timer Reserved Multi-function timer unit0 Multi-function timer unit1 Reserved PPG Base Timer Quadrature Position/Revolution Counter A/D Converter Reserved Internal CR trimming Reserved External Interrupt Controller Interrupt Request Batch-Read Function Reserved D/A Converter Reserved Low Voltage Detector Deep standby mode Controller USB clock generator Reserved Multi-function serial Interface CRC Watch Counter RTC/Port Ctrl Low-speed CR Prescaler Peripheral Clock Gating Reserved USB ch.0 Reserved DMAC register DSTC register Reserved GPIO Reserved WorkFlash I/F register Page 43 of 124 MB9B360L Series 11. Pin Status in Each CPU State The terms used for pin status have the following meanings. INITX=0 This is the period when the INITX pin is the L level. INITX=1 This is the period when the INITX pin is the H level. SPL=0 This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 0. SPL=1 This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 1. Input enabled Indicates that the input function can be used. Internal input fixed at 0 This is the status that the input function cannot be used. Internal input is fixed at L. Hi-Z Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state. Setting disabled Indicates that the setting is disabled. Maintain previous state Maintains the state that was immediately prior to entering the current mode. If a built-in peripheral function is operating, the output follows the peripheral function. If the pin is being used as a port, that output is maintained. Analog input is enabled Indicates that the analog input is enabled. Trace output Indicates that the trace function can be used. GPIO selected In Deep standby mode, pins switch to the general-purpose I/O port. Setting prohibition Prohibition of a setting by specification limitation. Document Number: 002-04930 Rev.*A Page 44 of 124 MB9B360L Series Pin status Type List of Pin Status A Function Group Power-on Reset or Low-voltage Detection State Power Supply Unstable ‐ ‐ INITX Input State Device Internal Reset State Power Supply Stable INITX=0 ‐ INITX=1 ‐ Run Mode or Sleep Mode State Power Supply Stable INITX=1 ‐ Timer Mode, RTC Mode, or Stop Mode State Deep Standby RTC Mode or Deep Standby Stop Mode State Power Supply Stable Power Supply Stable INITX=1 SPL=0 SPL=1 INITX=1 SPL=0 SPL=1 GPIO Hi-Z / selected Internal Internal input fixed input fixed at 0 at 0 Return from Deep Standby Mode State Power Supply Stable INITX=1 - GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 Main crystal oscillator input pin/ External main clock input selected Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Maintain previous state Hi-Z / Internal input fixed at 0 Maintain previous state Hi-Z / Internal input fixed at 0 Maintain previous state GPIO selected GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state External main clock input selected Setting disabled Setting disabled Setting disabled Maintain previous state Main crystal oscillator output pin Hi-Z / Internal input fixed at "0"/ or Input enable Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Maintain previous state / When oscillation stops*1, Hi-Z / Internal input fixed at 0 C INITX input pin Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled D Mode input pin Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled B Document Number: 002-04930 Rev.*A Page 45 of 124 Pin status Type MB9B360L Series E F Function Group Power-on Reset or Low-voltage Detection State INITX Input State Device Internal Reset State Mode input pin Power Supply Unstable ‐ ‐ Input enabled INITX=0 ‐ Input enabled INITX=1 ‐ Input enabled GPIO selected Setting disabled Setting disabled Setting disabled NMIX selected Setting disabled Setting disabled Setting disabled Resource other than above selected Hi-Z GPIO selected JTAG selected Hi-Z Power Supply Stable Hi-Z / Input enabled Hi-Z / Input enabled Pull-up / Input enabled Pull-up / Input enabled G J GPIO selected Setting disabled Setting disabled Setting disabled Analog output selected Setting disabled Setting disabled Setting disabled Resource other than above selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Setting disabled Setting disabled Setting disabled GPIO selected K External interrupt enabled selected Resource other than above selected GPIO selected Hi-Z Hi-Z / Input enabled Document Number: 002-04930 Rev.*A Hi-Z / Input enabled Run Mode or SLEEP Mode State Power Supply Stable INITX=1 ‐ Input enabled Maintain previous state TIMER Mode, RTC Mode, or STOP Mode State Deep Standby RTC Mode or Deep Standby STOP Mode State Power Supply Stable Power Supply Stable SPL=0 Input enabled Maintain previous state INITX=1 SPL=1 Input enabled Hi-Z / Input enabled INITX=1 SPL=0 SPL=1 Input Input enabled enabled Hi-Z / GPIO Input selected enabled GPIO selected Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state *2 Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 Maintain previous state GPIO selected Hi-Z / WKUP input enabled Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected *3 Hi-Z / Internal input fixed at 0 Maintain previous state Maintain previous state WKUP input enabled Return from Deep Standby Mode State Power Supply Stable INITX=1 Input enabled Hi-Z / Internal input fixed at 0 Page 46 of 124 Pin status Type MB9B360L Series Function Group Power-on Reset or Low-voltage Detection State Power Supply Unstable ‐ ‐ INITX Input State Device Internal Reset State Run Mode or Sleep Mode State Timer Mode, RTC Mode, or Stop Mode State Deep Standby RTC Mode or Deep Standby Stop Mode State Power Supply Stable Power Supply Stable INITX=1 SPL=0 SPL=1 INITX=1 SPL=0 SPL=1 Return from Deep Standby Mode State Power Supply Stable INITX=1 - INITX=0 ‐ INITX=1 ‐ Power Supply Stable INITX=1 ‐ Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Power Supply Stable Analog input selected Hi-Z Hi-Z / Internal input fixed at 0 / Analog input enabled Resource other than above selected GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Hi-Z Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected L Analog input selected M External interrupt enabled selected Resource other than above selected GPIO selected Maintain previous state Setting disabled Setting disabled Document Number: 002-04930 Rev.*A Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 Page 47 of 124 Pin status Type MB9B360L Series Function Group Analog input selected Power-on Reset or Low-voltage Detection State Power Supply Unstable ‐ ‐ Hi-Z INITX Input State Device Internal Reset State Power Supply Stable INITX=0 ‐ Hi-Z / Internal input fixed at 0 / Analog input enabled INITX=1 ‐ Hi-Z / Internal input fixed at 0 / Analog input enabled Setting disabled Setting disabled Run Mode or Sleep Mode State Power Supply Stable INITX=1 ‐ Hi-Z / Internal input fixed at 0 / Analog input enabled Timer Mode, RTC Mode, or Stop Mode State Deep Standby RTC Mode or Deep Standby Stop Mode State Power Supply Stable Power Supply Stable INITX=1 SPL=0 SPL=1 Hi-Z / Hi-Z / Internal Internal input fixed input fixed at 0 / at 0 / Analog Analog input input enabled enabled WKUP enabled O External interrupt enabled selected Resource other than above selected Setting disabled Maintain previous state Hi-Z Hi-Z Input enabled Hi-Z Input enabled Hi-Z Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled GPIO selected Analog input selected P Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled WKUP enabled Resource other than above selected Setting disabled Setting disabled GPIO selected Document Number: 002-04930 Rev.*A Setting disabled Maintain previous state Maintain previous state INITX=1 SPL=0 SPL=1 Hi-Z / Hi-Z / Internal Internal input fixed input fixed at 0 / at 0 / Analog Analog input input enabled enabled WKUP WKUP input input enabled enabled GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Maintain previous state WKUP input enabled Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / WKUP input enabled Hi-Z / Internal input fixed at 0 Return from Deep Standby Mode State Power Supply Stable INITX=1 Hi-Z / Internal input fixed at 0 / Analog input enabled GPIO selected Hi-Z / Internal input fixed at 0 / Analog input enabled GPIO selected Page 48 of 124 Pin status Type MB9B360L Series Function Group Power-on Reset or Low-voltage Detection State INITX Input State Device Internal Reset State Run Mode or Sleep Mode State Power Supply Unstable ‐ INITX=0 INITX=1 Power Supply Stable INITX=1 ‐ ‐ ‐ ‐ Power Supply Stable Timer Mode, RTC Mode, or Stop Mode State Deep Standby RTC Mode or Deep Standby Stop Mode State Power Supply Stable Power Supply Stable INITX=1 SPL=0 WKUP enabled External interrupt enabled Q selected Resource other than above selected GPIO selected GPIO selected Setting disabled Setting disabled Maintain previous state Setting disabled Maintain previous state Hi-Z Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z / Internal input fixed at 0 Hi-Z / Input enabled Maintain previous state USB I/O pin Setting disabled Setting disabled Maintain previous state Hi-Z / Input enabled R Setting disabled INITX=1 SPL=1 SPL=0 SPL=1 Return from Deep Standby Mode State Power Supply Stable INITX=1 - WKUP input enabled Hi-Z / WKUP input enabled GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at "0" Hi-Z / Input enabled GPIO selected Hi-Z / Input enabled Hi-Z / Input enabled Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at "0" Hi-Z / Input enabled Hi-Z at transmission/ Input enabled/ Internal input fixed at 0 at reception Hi-Z at transmission/ Input enabled/ Internal input fixed at 0 at reception Hi-Z / Input enabled GPIO selected *1: Oscillation is stopped at Sub timer mode, sub CR timer mode, RTC mode, Stop mode, Deep Standby RTC mode, and Deep Standby Stop mode. *2: Maintain previous state at timer mode. GPIO selected Internal input fixed at 0 at RTC mode, Stop mode. *3: Maintain previous state at timer mode. Hi-Z/Internal input fixed at 0 at RTC mode, Stop mode. Document Number: 002-04930 Rev.*A Page 49 of 124 MB9B360L Series VBAT Pin Status Type List of VBAT Domain Pin Status S VBAT Power-on Reset Device Internal Reset State INITX Input State Function Group Power Supply Unstable ‐ ‐ Power Supply Stable INITX=0 ‐ INITX=1 ‐ Run Mode or Sleep Mode State Power Supply Stable INITX=1 ‐ Timer Mode, RTC Mode, or Stop Mode State Deep Standby RTC Mode or Deep Standby Stop Mode State Power Supply Stable Power Supply Stable INITX=1 SPL=0 INITX=1 SPL=1 SPL=0 SPL=1 Return from Deep Standby Mode State VBAT RTC Mode State Return from VBAT RTC Mode State Power Supply Stable INITX=1 - Power Supply Stable - Power Supply Stable - GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at "0" GPIO selected Internal input fixed at "0" Sub crystal oscillator input pin / External sub clock input selected Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Maintain previous state Maintain previous state Maintain previous state Hi-Z / Internal input fixed at "0" GPIO selected Internal input fixed at "0" Hi-Z / Internal input fixed at "0" GPIO selected Setting prohibition - Maintain previous state Maintain previous state Maintain previous state Maintain previous state/ When oscillation stops*, Hi-Z/ Internal input fixed at "0" Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state External sub clock input selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at "0" Maintain previous state/ When oscillation stops*, Hi-Z / Internal input fixed at "0" Maintain previous state T Sub crystal oscillator output pin Hi-Z / Internal input fixed at 0/ or Input enable Hi-Z / Internal Input fixed at "0" Hi-Z / Internal Input fixed at "0" Maintain previous state Maintain previous state/ When oscillation stops*, Hi-Z / Internal input fixed at "0" Hi-Z Maintain previous state Maintain previous state Maintain previous state Maintain previous state Resource selected U GPIO selected Hi-Z / Internal input fixed at "0" GPIO selected Setting prohibition - Maintain previous state/ When oscillation stops*, Hi-Z/ Internal input fixed at "0" Hi-Z / Internal input fixed at "0" Maintain previous state/ When oscillation stops*, Hi-Z/ Internal input fixed at "0" Maintain previous state Maintain previous state Maintain previous state *: Oscillation is stopped at Stop mode and Deep Standby Stop mode. Document Number: 002-04930 Rev.*A Page 50 of 124 MB9B360L Series 12. Electrical Characteristics 12.1 Absolute Maximum Ratings Parameter Rating Symbol Min Unit Max Power supply voltage *1, *2 VCC VSS - 0.5 VSS + 6.5 V Power supply voltage (for USB)*1, * 3 USBVCC VSS - 0.5 VSS + 6.5 V Power supply voltage (VBAT) * * VBAT VSS - 0.5 VSS + 6.5 V Analog power supply voltage *1 ,*5 Analog reference voltage *1 ,*5 AVCC AVRH VSS - 0.5 VSS - 0.5 VSS + 6.5 VSS + 6.5 VCC + 0.5 (≤ 6.5V) USBVCC + 0.5 (≤ 6.5V) V V VSS + 6.5 1, 4 VSS - 0.5 Input voltage *1 VI VSS - 0.5 VSS - 0.5 Analog pin input voltage * 1 Output voltage *1 6 VIA VSS - 0.5 VO VSS - 0.5 "L" level maximum output current * IOL - "L" level average output current *7 IOLAV - "L" level total maximum output current "L" level total maximum output current *8 ∑IOL ∑IOLAV - "H" level maximum output current *6 IOH - "H" level average output current *7 IOHAV - "H" level total maximum output current "H" level total average output current *8 Storage temperature ∑IOH ∑IOHAV TSTG - 55 AVCC + 0.5 (≤ 6.5V) VCC + 0.5 (≤ 6.5V) 10 20 20 22.4 4 8 12 20 100 50 Remarks V Except for USB pin V USB pin V 5 V tolerant V V mA mA mA mA mA mA mA mA mA mA 4 mA type 8 mA type 12 mA type I2C Fm+ 4 mA type 8 mA type 12 mA type I2C Fm+ - 10 mA 4 mA type - 20 mA 8 mA type - 20 -4 -8 - 12 - 100 - 50 + 150 mA mA mA mA mA mA °C 12 mA type 4 mA type 8 mA type 12 mA type *1: These parameters are based on the condition that VSS = AVSS = 0.0 V. *2: VCC must not drop below VSS - 0.5 V. *3: USBVCC must not drop below VSS - 0.5 V. *4: VBAT must not drop below VSS - 0.5 V. *5: Ensure that the voltage does not exceed VCC + 0.5 V, for example, when the power is turned on. *6: The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins. *7: The average output current is defined as the average current value flowing through any one of the corresponding pins for a 100ms period. *8: The total average output current is defined as the average current value flowing through all of corresponding pins for a period of 100 ms. WARNING: − Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings. Document Number: 002-04930 Rev.*A Page 51 of 124 MB9B360L Series 12.2 Recommended Operating Conditions Parameter Symbol Power supply voltage VCC Conditions - Value Min 2.7 3.0 Power supply voltage (for USB) USBVCC 2.7 Power supply voltage (VBAT) Analog power supply voltage Analog reference voltage Junction temperature Operating temperature Ambient temperature VBAT AVCC AVRH Tj TA - 2.7 2.7 *3 - 40 - 40 Max 5.5 3.6 (≤ VCC) 5.5 (≤ VCC) 5.5 5.5 AVCC + 125 *4 Unit Remarks V *1 V *2 V V V °C °C AVCC=VCC *1: When P81/UDP0 and P80/UDM0 pins are used as USB (UDP0, UDM0). *2: When P81/UDP0 and P80/UDM0 pins are used as GPIO (P81, P80). *3: The minimum value of Analog reference voltage depends on the value of compare clock cycle (Tcck). See "5. 12-bit A/D Converter" for the details. *4: The maximum temperature of the ambient temperature (Ta) can guarantee a range that does not exceed the junction temperature (Tj). The calculation formula of the ambient temperature (Ta) is shown below. TA(Max) = Tj(Max) - Pd(Max) × θja Pd: Power dissipation (W) θja: Package thermal resistance (°C/W) Pd (Max) = VCC × ICC (Max) + Σ (IOL×VOL) + Σ ((VCC-VOH) × (- IOH)) IOL: L level output current IOH: H level output current VOL: L level output voltage VOH: H level output voltage Package thermal resistance and maximum permissible power for each package are shown below. The operation is guaranteed maximum permissible power or less for semiconductor devices. Table for Package Thermal Resistance and Maximum Permissible Power Package FPT-48P-M49 (0.5mm pitch) LCC-48P-M73 (0.5mm pitch) FPT-64P-M38 (0.5mm pitch) FPT-64P-M39 (0.65mm pitch) LCC-64P-M24 (0.5mm pitch) Printed circuit board Single-layered both sides 4 layers Single-layered both sides 4 layers Single-layered both sides 4 layers Single-layered both sides 4 layers Single-layered both sides 4 layers Thermal resistance θja (°C/W) 87 53 30 24 70 45 61 40 24 21 Maximum permissible power (mW) TA=+85°C 460 755 1333 1667 571 889 656 1000 1667 1905 TA=+105°C 230 377 667 833 286 444 328 500 833 952 WARNING: 1. The recommended operating conditions are required to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated under these conditions. Any use of semiconductor devices will be under their recommended operating condition. Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device failure. No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you are considering application under any conditions other than listed herein, please contact sales representatives beforehand. Document Number: 002-04930 Rev.*A Page 52 of 124 MB9B360L Series Calculation Method of Power Dissipation (Pd) The power dissipation is shown in the following formula. Pd = VCC × ICC + Σ (IOL × VOL) + Σ ((VCC-VOH) × (-IOH)) IOL: "L" level output current IOH: "H" level output current VOL: "L" level output voltage VOH: "H" level output voltage ICC is a current consumed in device. It can be analyzed as follows. ICC = ICC(INT) + ΣICC(IO) ICC(INT): Current consumed in internal logic and memory, etc. through regulator ΣICC(IO): Sum of current (I/O switching current) consumed in output pin For ICC (INT), it can be anticipated by "(1) Current Rating" in "3. DC Characteristics" (This rating value does not include ICC (IO) for a value at pin fixed). For Icc (IO), it depends on system used by customers. The calculation formula is shown below. ICC(IO) = (CINT + CEXT) × VCC × fsw CINT: Pin internal load capacitance CEXT: External load capacitance of output pin fSW: Pin switching frequency Parameter Pin internal load capacitance Symbol CINT Conditions Capacitance Value 4 mA type 1.93 pF 8 mA type 3.45 pF 12 mA type 3.42 pF Calculate ICC (Max) as follows when the power dissipation can be evaluated. 1. Measure current value ICC (Typ) at normal temperature (+25°C). 2. Add maximum leak current value ICC (leak_max) at operating on a value in (1). ICC(Max) = ICC(Typ) + ICC(leak_max) Parameter Maximum leak current at operating Document Number: 002-04930 Rev.*A Symbol ICC(leak_max) Conditions Tj = +125 °C Tj = +105 °C Tj = +85 °C Current Value 28 mA 17 mA 13 mA Page 53 of 124 MB9B360L Series Current Explanation Diagram Pd = VCC×ICC + Σ(IOL×VOL)+Σ((VCC-VOH)×(-IOH)) ICC = ICC(INT)+ΣICC(IO) VCC A ICC Chip ICC(INT) ΣICC(IO) A Regulator VOL V A ・・・ V IOL Flash VOH ・・・ Logic IOH RAM ICC(IO) CEXT ・・・ Document Number: 002-04930 Rev.*A Page 54 of 124 MB9B360L Series 12.3 DC Characteristics 12.3.1 Current Rating Parameter Power supply current Parameter Power supply current Symbol ICC Symbol ICC Pin Name VCC Pin Name VCC Conditions Normal operation (PLL) *5, *6 Conditions Normal operation (PLL) *8 Frequency* 4 Value 2 Max* 1 Typ* 160 MHz 44 72 144 MHz 120 MHz 100 MHz 80 MHz 60 MHz 40 MHz 20 MHz 8 MHz 4 MHz 160 MHz 144 MHz 120 MHz 100 MHz 80 MHz 60 MHz 40 MHz 20 MHz 8 MHz 4 MHz 40 34 29 23 18 13 7.7 4.6 3.6 30 27 23 20 16 13 9 5.7 3.7 3 67 60 55 48 42 37 31 27 26 58 54 49 46 41 38 33 30 27 26 Frequency* 7 Value 2 Max* 1 Typ* 160 MHz 64 101 144 MHz 120 MHz 100 MHz 80 MHz 60 MHz 40 MHz 20 MHz 8 MHz 4 MHz 160 MHz 144 MHz 120 MHz 100 MHz 80 MHz 60 MHz 40 MHz 20 MHz 8 MHz 4MHz 60 52 46 39 32 25 15 7.8 5.2 47 43 39 35 30 25 20 13 6.7 4.6 96 88 81 73 65 58 47 39 36 80 75 71 66 61 55 50 42 36 34 Unit Remarks mA *3 When all peripheral clocks are ON mA *3 When all peripheral clocks are OFF Unit Remarks mA *3 When all peripheral clocks are ON mA *3 When all peripheral clocks are OFF *1: TA=+25 °C, VCC=3.3 V *2: Tj=+125 °C, VCC=5.5 V *3: When all ports are fixed. *4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2 *5: When operating flash accelerator mode and trace buffer function (FRWTR.RWT = 10, FBFCR.BE = 1) *6: Data access is nothing to MainFlash memory *7: Frequency is a value of HCLK. PCLK0=PCLK2=HCLK/2, PCLK1=HCLK *8: When stopping flash accelerator mode and trace buffer function (FRWTR.RWT = 10, FBFCR.BE = 0) Document Number: 002-04930 Rev.*A Page 55 of 124 MB9B360L Series Parameter Power supply current Symbol ICC Pin Name VCC Frequency* (MHz) Conditions Normal operation (PLL) *5 4 Value 1 2 Typ* Max* 72 MHz 41 75 60 MHz 36 69 48 MHz 31 64 36 MHz 25 57 24 MHz 18 50 12 MHz 8 MHz 4 MHz 72 MHz 60 MHz 48 MHz 36 MHz 24 MHz 11 8.1 5.4 32 28 24 20 15 42 39 37 63 58 54 50 45 12 MHz 9.1 38 8 MHz 4 MHz 6.9 4.6 36 34 Unit Remarks mA *3 When all peripheral clocks are ON mA *3 When all peripheral clocks are OFF *1: TA=+25 °C, VCC=3.3 V *2: Tj=+125 °C, VCC=5.5 V *3: When all ports are fixed. *4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK *5: When 0 wait-cycle mode (FRWTR.RWT = 00, FSYNDN.SD = 00) Parameter Symbol Pin Name Conditions Normal operation (built-in high-speed CR) Power supply current ICC VCC Normal operation (sub oscillation) Normal operation (built-in low-speed CR) Frequency* *5 *5 *5 4 Value 1 2 Typ* Max* Unit Remarks *3 When all peripheral clocks are ON *3 When all peripheral clocks are OFF 3.3 29 mA 2.8 29 mA 0.51 27 mA *3 When all peripheral clocks are ON 0.50 27 mA *3 When all peripheral clocks are OFF 0.54 27 mA *3 When all peripheral clocks are ON 0.52 27 mA *3 When all peripheral clocks are OFF 4 MHz 32 kHz 100 kHz *1: TA=+25 °C, VCC=3.3 V *2: Tj=+125 °C, VCC=5.5 V *3: When all ports are fixed. *4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2 *5: When 0 wait-cycle mode (FRWTR.RWT = 00, FSYNDN.SD = 000) Document Number: 002-04930 Rev.*A Page 56 of 124 MB9B360L Series Parameter Power supply current Parameter Power supply current Symbol ICCS Symbol ICCS Pin Name VCC Pin Name VCC Conditions Sleep operation (PLL) Conditions Sleep operation (PLL) Frequency* Value 4 1 2 Typ* Max* 160 MHz 28 58 144 MHz 120 MHz 100 MHz 80 MHz 60 MHz 40 MHz 20 MHz 8 MHz 4 MHz 160 MHz 144 MHz 120 MHz 100 MHz 80 MHz 60 MHz 40 MHz 20 MHz 8 MHz 4 MHz 25 21 18 15 12 8.8 5.6 3.8 3.2 14 13 11 9.7 8.1 6.7 5.2 3.7 2.9 2.6 55 50 46 43 39 36 32 30 29 44 43 40 38 36 34 32 30 29 29 Frequency* 5 Value 2 Max* 1 Typ* 72 MHz 19 47 60 MHz 16 43 48 MHz 13 40 36 MHz 10 37 24 MHz 7.8 34 12 MHz 8 MHz 4 MHz 72 MHz 60 MHz 48 MHz 36 MHz 24 MHz 5.2 4.3 3.5 8.8 7.7 6.6 5.5 4.4 31 30 29 36 35 34 32 31 12 MHz 3.4 30 8 MHz 4 MHz 3 2.7 29 29 Unit Remarks mA *3 When all peripheral clocks are ON mA *3 When all peripheral clocks are OFF Unit Remarks mA *3 When all peripheral clocks are ON mA *3 When all peripheral clocks are OFF *1: TA=+25 °C, VCC=3.3 V *2: Tj=+125 °C, VCC=5.5 V *3: When all ports are fixed. *4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2 *5: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK Document Number: 002-04930 Rev.*A Page 57 of 124 MB9B360L Series Parameter Symbol Pin Name Conditions Sleep operation (built-in high-speed CR) Power supply current ICCS VCC Sleep operation (sub oscillation) Sleep operation (built-in low-speed CR) Frequency* Value 4 1 2 Unit Remarks Typ* Max* 1.3 27 mA 0.91 27 mA 0.49 27 mA 0.48 27 mA 0.51 27 mA *3 When all peripheral clocks are ON 0.49 27 mA *3 When all peripheral clocks are OFF 4 MHz 32 kHz 100 kHz *3 When all peripheral clocks are ON *3 When all peripheral clocks are OFF *3 When all peripheral clocks are ON *3 When all peripheral clocks are OFF *1: TA=+25 °C, VCC=3.3 V *2: Tj=+125 °C, VCC=5.5 V *3: When all ports are fixed. *4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2 Document Number: 002-04930 Rev.*A Page 58 of 124 MB9B360L Series Parameter Symbol Pin Name ICCH Conditions STOP mode TIMER mode (built-in high-speed CR) Power supply current ICCT VCC TIMER mode (sub oscillation) TIMER mode (built-in low-speed CR) ICCR RTC mode (sub oscillation) Frequency - 4 MHz 32 kHz 100 kHz 32 kHz Value 1 2 Unit Remarks Typ* Max* 0.25 1.0 mA - 11 mA - 14 mA 0.54 1.54 mA - 12 mA - 15 mA 0.25 1.0 mA *3, *4 TA =+25°C - 11 mA *3, *4 TA =+85°C - 14 mA 0.26 1.0 mA - 11 mA - 14 mA 0.25 1.0 mA - 11 mA - 14 mA *3, *4 TA=+25°C *3, *4 TA =+85°C *3, *4 TA =+105°C *3, *4 TA =+25°C *3, *4 TA =+85°C *3, *4 TA =+105°C *3, *4 TA =+105°C *3, *4 TA =+25°C *3, *4 TA =+85°C *3, *4 TA =+105°C *3, *4 TA =+25°C *3, *4 TA =+85°C *3, *4 TA =+105°C *1: VCC=3.3 V *2: VCC=5.5 V *3: When all ports are fixed. *4: When LVD is OFF Document Number: 002-04930 Rev.*A Page 59 of 124 MB9B360L Series Parameter Pin Name Symbol Conditions Frequency Deep standby STOP mode (When RAM is OFF) ICCHD Value Typ *1 2 Max* Unit 27 140 µA - 590 µA - 770 µA 32 180 µA - 870 µA - 1200 µA 27 140 µA - 590 µA - 770 µA 32 180 µA - 870 µA - 1200 µA 0.015 0.14 µA - 4.0 µA - 9.4 µA 1.3 2.4 µA - 6.2 µA - 12 µA Deep standby STOP mode (When RAM is ON) VCC Power supply current Deep standby RTC mode (When RAM is OFF) ICCRD 32 kHz Deep standby RTC mode (When RAM is ON) RTC stop ICCVBAT VBAT - RTC operation Remarks *3, *4 TA=+25°C *3, *4 TA =+85°C *3, *4 TA =+105°C *3, *4 TA =+25°C *3, *4 TA =+85°C *3, *4 TA =+105°C *3, *4 TA =+25°C *3, *4 TA =+85°C *3, *4 TA =+105°C *3, *4 TA =+25°C *3, *4 TA =+85°C *3, *4 TA =+105°C *3, *4, *5 TA =+25°C *3, *4, *5 TA =+85°C *3, *4, *5 TA =+105°C *3, *4 TA =+25°C *3, *4 TA =+85°C *3, *4 TA =+105°C *1: VCC=3.3 V *2: VCC=5.5 V *3: When all ports are fixed. *4: When LVD is OFF *5: When sub oscillation is OFF Document Number: 002-04930 Rev.*A Page 60 of 124 MB9B360L Series Parameter Low-voltage detection circuit (LVD) power supply current ICCLVD Main flash memory write/erase current ICCFLASH Work flash memory write/erase current ICCWFLASH Value Pin Name Symbol VCC Conditions Min Typ Max Unit At operation - 4 7 μA At Write/Erase - 13.4 15.9 mA At Write/Erase - 11.5 13.6 mA Remarks For occurrence of interrupt Peripheral current dissipation Clock System Peripheral Unit Frequency (MHz) 40 80 160 GPIO All ports 0.21 0.43 0.92 DMAC - 0.71 1.43 2.74 DSTC - 0.36 0.72 1.46 USB 1ch. 0.42 0.80 1.60 Base timer 4ch. 0.18 0.36 0.70 1 unit/4ch. 0.57 1.13 2.24 1 unit 0.04 0.08 0.16 A/DC 1 unit 0.21 0.40 0.79 Multi-function serial 1ch. 0.33 0.67 - HCLK PCLK1 PCLK2 Unit Remarks mA Multi-functional timer/PPG Quadrature position/Revolution counter Document Number: 002-04930 Rev.*A mA mA Page 61 of 124 MB9B360L Series 12.3.2 Pin Characteristics (VCC = USBVCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V) Value Parameter "H" level input voltage (hysteresis input) "L" level input voltage (hysteresis input) Symbol VIHS VILS Pin Name CMOS hysteresis input pin, MD0, MD1 5V tolerant input pin Input pin doubled as I2C Fm+ CMOS hysteresis input pin, MD0, MD1 5V tolerant input pin Input pin doubled as I2C Fm+ 4mA type 8mA type "H" level output voltage VOH 12mA type The pin doubled as USB I/O The pin doubled as I2C Fm+ Document Number: 002-04930 Rev.*A Conditions Min Typ Max Unit - VCC×0.8 - VCC + 0.3 V - VCC×0.8 - VSS + 5.5 V - VCC×0.7 - VSS + 5.5 V - VSS - 0.3 - VCC×0.2 V - VSS - 0.3 - VCC×0.2 V - VSS - VCC×0.3 V VCC - 0.5 - VCC V VCC - 0.5 - VCC V VCC - 0.5 - VCC V USBVCC - 0.4 - USBVCC V VCC - 0.5 - VCC V VCC ≥ 4.5 V, IOH = - 4 mA VCC < 4.5 V, IOH = - 2 mA VCC ≥ 4.5 V, IOH = - 8 mA VCC < 4.5 V, IOH = - 4 mA VCC ≥ 4.5 V, IOH = - 12 mA VCC < 4.5 V, IOH = - 8 mA USBVCC ≥ 4.5 V, IOH = - 20.5 mA USBVCC < 4.5 V, IOH = - 13.0 mA VCC ≥ 4.5 V, IOH = - 4 mA VCC < 4.5 V, IOH = - 3 mA Remarks At GPIO Page 62 of 124 MB9B360L Series Value Parameter Symbol Pin Name Conditions Min Typ Unit Max Remarks VCC ≥ 4.5 V, IOL = 4 mA 4 mA type VSS - 0.4 V VSS - 0.4 V VSS - 0.4 V VSS - 0.4 V VSS - 0.4 V VCC < 4.5 V, IOL = 2 mA VCC ≥ 4.5 V, IOH = 8 mA 8 mA type VCC < 4.5 V, IOH = 4 mA VCC ≥ 4.5 V, IOL = 12 mA 12 mA type "L" level output voltage VCC < 4.5 V, IOL = 8 mA VOL The pin doubled as USB I/O USBVCC ≥ 4.5 V, IOL = 18.5 mA USBVCC < 4.5 V, IOL = 10.5 mA VCC ≥ 4.5 V, IOH = 4 mA The pin doubled as I2C Fm+ At GPIO VCC < 4.5 V, IOH = 3 mA VCC ≤ 5.5 V, IOH = 20 mA Input leak current IIL - Pull-up resistor value RPU Pull-up pin CIN Other than VCC, USBVCC, VBAT, VSS, AVCC, AVSS, AVRH Input capacitance Document Number: 002-04930 Rev.*A At I2C Fm+ - -5 - +5 VCC ≥ 4.5 V 25 50 100 VCC < 4.5 V 30 80 200 - - 5 15 μA kΩ pF Page 63 of 124 MB9B360L Series 12.4 AC Characteristics 12.4.1 Main Clock Input Characteristics (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Pin Name Symbol Input frequency fCH Input clock cycle tCYLH Input clock pulse width Input clock rising time and falling time Internal operating clock*1 frequency Internal operating clock*1 cycle time X0, X1 tCF, tCR Value Conditions Min Max VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V PWH/tCYLH, PWL/tCYLH 4 4 4 4 20.83 50 48 20 48 20 250 250 45 - Unit Remarks MHz When crystal oscillator is connected MHz When using external clock ns When using external clock 55 % When using external clock - 5 ns When using external clock fCC - - - 160 MHz Base clock (HCLK/FCLK) fCP0 fCP1 - - - 80 160 MHz MHz APB0 bus clock*2 APB1 bus clock*2 fCP2 - - - 80 MHz APB2 bus clock*2 tCYCC - - 6.25 - ns Base clock (HCLK/FCLK) tCYCP0 tCYCP1 - - 12.5 6.25 - ns ns APB0 bus clock*2 APB1 bus clock*2 tCYCP2 - - 12.5 - ns APB2 bus clock*2 *1: For more information about each internal operating clock, see CHAPTER 2-1: Clock in FM4 Family Peripheral Manual Main part (002-04856). *2: For about each APB bus which each peripheral is connected to, see 8. Block Diagram in this data sheet. X0 Document Number: 002-04930 Rev.*A Page 64 of 124 MB9B360L Series 12.4.2 Sub Clock Input Characteristics (VBAT = 2.7V to 5.5V, VSS = 0V) Parameter Pin Name Symbol Input frequency 1/ tCYLL Input clock cycle tCYLL Input clock pulse width - X0A, X1A Value Conditions Min Typ Max Unit Remarks - - 32.768 - kHz - 32 - 100 kHz When crystal oscillator is connected When using external clock - 10 - 31.25 μs When using external clock PWH/tCYLL, PWL/tCYLL 45 - 55 % When using external clock 0.8 × VBAT VBAT VBAT VBAT VBAT X0A 12.4.3 Built-in CR Oscillation Characteristics Built-in High-speed CR (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions Value Min Typ Max TJ = -20°C to +105°C 3.92 4 4.08 TJ = - 40°C to +125°C 3.88 4 4.12 TJ = - 40°C to +125°C 3 4 5 Unit Remarks When trimming * Clock frequency fCRH MHz When not trimming *: In the case of using the values in CR trimming area of Flash memory at shipment for frequency/temperature trimming. Built-in Low-speed CR (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Clock frequency Symbol fCRL Condition - Document Number: 002-04930 Rev.*A Value Min 50 Typ 100 Max 150 Unit Remarks kHz Page 65 of 124 MB9B360L Series 12.4.4 Operating Conditions of Main PLL (In the Case of Using Main Clock for Input Clock of PLL) (VCC = 2.7V to 5.5V, VSS = 0V) Value Parameter Symbol Unit Remarks Min Typ Max PLL oscillation stabilization wait time*1 (LOCK UP time) PLL input clock frequency tLOCK 200 - - μs fPLLI 4 - 16 MHz PLL multiplication rate - 13 - 80 multiplier PLL macro oscillation clock frequency fPLLO 200 - 320 MHz Main PLL clock frequency*2 fCLKPLL - - 160 MHz *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock (CLKPLL), see CHPATER 2-1: Clock in FM4 Family Peripheral Manual Main part (002-04856). 12.4.5 Operating Conditions of USB PLL (In the Case of Using Main Clock for Input Clock of PLL) (VCC = 2.7V to 5.5V, VSS = 0V) Value Parameter Symbol Min Typ Unit Max PLL oscillation stabilization wait time*1 (LOCK UP time) tLOCK 100 - - μs PLL input clock frequency fPLLI 4 - 16 MHz PLL multiplication rate - 13 - 80 multiplier PLL macro oscillation clock frequency fPLLO 200 - 320 MHz fCLKSPLL - - 48 MHz USB clock frequency* 2 Remarks After the M frequency division *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about USB clock, see CHAPTER 2-2: USB Clock Generation in FM4 Family Peripheral Manual Communication Macro part (002-04862). 12.4.6 Operating Conditions of Main PLL (In the Case of Using Built-in High-speed CR Clock for Input Clock of Main PLL) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter PLL oscillation stabilization wait time*1 (LOCK UP time) PLL input clock frequency PLL multiplication rate PLL macro oscillation clock frequency Main PLL clock frequency*2 Symbol Value Min Typ Unit Max tLOCK 200 - - μs fPLLI fPLLO fCLKPLL 3.8 50 190 - 4 - 4.2 75 320 160 MHz multiplier MHz MHz Remarks *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock (CLKPLL), see CHAPTER 2-1: Clock in FM4 Family Peripheral Manual Main part (002-04856). Note: − Make sure to input to the main PLL source clock, the high-speed CR clock (CLKHC) that the frequency and temperature has been trimmed. Document Number: 002-04930 Rev.*A Page 66 of 124 MB9B360L Series 12.4.7 Reset Input Characteristics (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Reset input time Symbol tINITX Pin Name Value Condition INITX - Min Unit Max 500 - Remarks ns 12.4.8 Power-on Reset Timing (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Power supply rising time Tr Power supply shut down time Toff Time until releasing Power-on reset Tprt Value Pin Name VCC Min Max Unit 0 - ms 1 - ms 0.33 0.60 ms Remarks VCC_minimum VCC VDL_minimum 0.2V 0.2V 0.2V Tr Tprt Internal RST RST Active Toff Release CPU Operation start Glossary • VCC_minimum: Minimum VCC of recommended operating conditions. • VDL_minimum: Minimum detection voltage of Low-Voltage detection reset. See 12.8. Low-Voltage Detection Characteristics. Document Number: 002-04930 Rev.*A Page 67 of 124 MB9B360L Series 12.4.9 GPIO Output Characteristics (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Output frequency Symbol tPCYCLE Pin Name Pxx* Value Conditions Min Unit Max VCC ≥ 4.5 V - 50 MHz VCC < 4.5 V - 32 MHz *: GPIO is a target. Pxx tPCYCLE Document Number: 002-04930 Rev.*A Page 68 of 124 MB9B360L Series 12.4.10 Base Timer Input Timing Timer Input Timing (VCC = 2.7V to 5.5V, VSS = 0V) Value Parameter Symbol tTIWH, tTIWL Input pulse width Pin Name Conditions TIOAn/TIOBn (when using as ECK, TIN) - Min 2tCYCP tTIWH Unit Max - Remarks ns tTIWL ECK VIHS VIHS VILS TIN VILS Trigger Input Timing (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol tTRGH, tTRGL Input pulse width Pin Name Conditions TIOAn/TIOBn (when using as TGIN) - 2tCYCP tTRGH TGIN VIHS Value Min Unit Max - Remarks ns tTRGL VIHS VILS VILS Note: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which the Base Timer is connected to, see 8. Block Diagram in this data sheet. Document Number: 002-04930 Rev.*A Page 69 of 124 MB9B360L Series 12.4.11 UART Timing Synchronous Serial (SPI = 0, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Serial clock cycle time tSCYC SCK↓→SOT delay time tSLOVI SIN→SCK↑ setup time tIVSHI SCK↑→SIN hold time tSHIXI Serial clock "L" pulse width Serial clock "H" pulse width tSLSH tSHSL SCK↓→SOT delay time tSLOVE SIN→SCK↑ setup time tIVSHE SCK↑→SIN hold time tSHIXE SCK falling time SCK rising time tF tR Pin Name SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx Internal shift clock operation External shift clock operation VCC ≥ 4.5 V Min Max VCC < 4.5 V Min Max Conditions Unit 4tCYCP - 4tCYCP - ns - 30 + 30 - 20 + 20 ns 50 - 30 - ns 0 - 0 - ns 2tCYCP - 10 tCYCP + 10 - 2tCYCP - 10 tCYCP + 10 - ns ns - 50 - 30 ns 10 - 10 - ns 20 - 20 - ns - 5 5 - 5 5 ns ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see 8. Block Diagram in this data sheet. − These characteristics only guarantee the same relocate port number. For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 30 pF. Document Number: 002-04930 Rev.*A Page 70 of 124 MB9B360L Series tSCYC VOH SCK VOL VOL tSLOVI VOH VOL SOT tIVSHI VIH VIL SIN tSHIXI VIH VIL MS bit = 0 tSLSH VIH SCK tF VIL tSHSL VIL SIN VIH tR tSLOVE SOT VIH VOH VOL tIVSHE VIH VIL tSHIXE VIH VIL MS bit = 1 Document Number: 002-04930 Rev.*A Page 71 of 124 MB9B360L Series Synchronous Serial (SPI = 0, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Serial clock cycle time SCK↑→SOT delay time Symbol tSCYC SCKx tSHOVI SCKx, SOTx SIN→SCK↓ setup time tIVSLI SCK↓→SIN hold time tSLIXI Serial clock "L" pulse width tSLSH SCKx, SINx SCKx, SINx SCKx Serial clock "H" pulse width tSHSL SCKx SCKx, SOTx SCKx, SINx SCKx, SINx VCC ≥ 4.5 V VCC < 4.5 V Pin Name Conditions Internal shift clock operation Min Max Min Max Unit 4tCYCP - 4tCYCP - ns - 30 + 30 - 20 + 20 ns 50 - 30 - ns 0 - 0 - ns 2tCYCP - 10 - 2tCYCP - 10 - ns tCYCP + 10 - tCYCP + 10 - ns - 50 - 30 ns 10 - 10 - ns 20 - 20 - ns SCK↑→SOT delay time tSHOVE SIN→SCK↓ setup time tIVSLE SCK↓→SIN hold time tSLIXE SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns External shift clock operation Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see 8. Block Diagram in this data sheet. − These characteristics only guarantee the same relocate port number. For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 30 pF. Document Number: 002-04930 Rev.*A Page 72 of 124 MB9B360L Series tSCYC VOH SCK VOH VOL tSHOVI VOH VOL SOT tIVSLI VIH VIL SIN tSLIXI VIH VIL MS bit = 0 tSHSL tSLSH VIH SCK VIH VIL tR VIL tF tSHOVE SOT SIN VIL VOH VOL tIVSLE VIH VIL tSLIXE VIH VIL MS bit = 1 Document Number: 002-04930 Rev.*A Page 73 of 124 MB9B360L Series Synchronous Serial (SPI = 1, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name VCC ≥ 4.5 V VCC < 4.5 V Conditions Min Max Min Max Unit Serial clock cycle time tSCYC SCKx 4tCYCP - 4tCYCP - ns SCK↑→SOT delay time tSHOVI SCKx, SOTx - 30 + 30 - 20 + 20 ns SIN→SCK↓ setup time tIVSLI 50 - 30 - ns SCK↓→SIN hold time tSLIXI 0 - 0 - ns SOT→SCK↓ delay time tSOVLI 2tCYCP - 30 - 2tCYCP - 30 - ns Serial clock "L" pulse width tSLSH SCKx, SINx SCKx, SINx SCKx, SOTx SCKx 2tCYCP - 10 - 2tCYCP - 10 - ns Serial clock "H" pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns - 50 - 30 ns 10 - 10 - ns 20 - 20 - ns SCK↑→SOT delay time tSHOVE SCKx, SOTx SCKx, SINx SCKx, SINx Internal shift clock operation External shift clock operation SIN→SCK↓ setup time tIVSLE SCK↓→SIN hold time tSLIXE SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see 8. Block Diagram in this data sheet. − These characteristics only guarantee the same relocate port number. For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 30 pF. Document Number: 002-04930 Rev.*A Page 74 of 124 MB9B360L Series tSCYC VOH VOL SCK SOT VOH VOL VOH VOL tIVSLI tSLIXI VIH VIL SIN VOL tSHOVI tSOVLI VIH VIL MS bit = 0 tSLSH VIH VIL tSHSL VIH VIL SCK tF * tR VIH tSHOVE VOH VOL VOH VOL tIVSLE SOT SIN tSLIXE VIH VIL VIH VIL MS bit = 1 *: Changes when writing to TDR register Document Number: 002-04930 Rev.*A Page 75 of 124 MB9B360L Series Synchronous Serial (SPI = 1, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Serial clock cycle time tSCYC SCK↓→SOT delay time tSLOVI Pin Name Conditions SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx, SOTx Internal shift clock operation VCC < 4.5 V VCC ≥ 4.5 V Min Min Max Max Unit 4tCYCP - 4tCYCP - ns - 30 + 30 - 20 + 20 ns 50 - 30 - ns 0 - 0 - ns 2tCYCP - 30 - 2tCYCP - 30 - ns SIN→SCK↑ setup time tIVSHI SCK↑→SIN hold time tSHIXI SOT→SCK↑ delay time tSOVHI Serial clock "L" pulse width tSLSH SCKx 2tCYCP - 10 - 2tCYCP - 10 - ns Serial clock "H" pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns - 50 - 30 ns 10 - 10 - ns 20 - 20 - ns SCK↓→SOT delay time tSLOVE SCKx, SOTx SCKx, SINx SCKx, SINx External shift clock operation SIN→SCK↑ setup time tIVSHE SCK↑→SIN hold time tSHIXE SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see 8. Block Diagram in this data sheet. − These characteristics only guarantee the same relocate port number. For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 30 pF. Document Number: 002-04930 Rev.*A Page 76 of 124 MB9B360L Series tSCYC VOH SCK tSOVHI SOT tSLOVI VOH VOL VOH VOL tSHIXI tIVSHI VIH VIL SIN VOH VOL VIH VIL MS bit = 0 tSHSL tR SCK VIL VIH tSLSH VIH VIL tF VIL VIH tSLOVE SOT VOH VOL VOH VOL tIVSHE SIN tSHIXE VIH VIL VIH VIL MS bit = 1 Document Number: 002-04930 Rev.*A Page 77 of 124 MB9B360L Series High-speed Synchronous Serial (SPI = 0, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name VCC ≥ 4.5V VCC < 4.5V Conditions Min Max Min Max Unit Serial clock cycle time tSCYC SCKx 4tCYCP - 4tCYCP - ns SCK↓→SOT delay time tSLOVI SCKx, SOTx -10 +10 -10 +10 ns SIN→SCK↑ setup time tIVSHI SCKx, SINx - 12.5 - ns SCK↑→SIN hold time tSHIXI SCKx, SINx 5 - 5 - ns Serial clock "L" pulse width tSLSH SCKx 2tCYCP – 5 - 2tCYCP – 5 - ns Serial clock "H" pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK↓→SOT delay time tSLOVE SCKx, SOTx - 15 - 15 ns SIN→SCK↑ setup time tIVSHE SCKx, SINx 5 - 5 - ns SCK↑→SIN hold time tSHIXE 5 - 5 - ns SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Internal shift clock operation 14 12.5* External shift clock operation SCKx, SINx Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see 8. Block Diagram in this data sheet. − These characteristics only guarantee the following pins. − − − No chip select: SIN0_1, SOT0_1, SCK0_1 Chip select: SIN6_0, SOT6_0, SCK6_0, SCS6_0 When the external load capacitance CL = 30 pF. (For *, when CL = 10 pF) Document Number: 002-04930 Rev.*A Page 78 of 124 MB9B360L Series tSCYC VOH SCK VOL VOL tSLOVI VOH VOL SOT tIVSHI VIH VIL SIN tSHIXI VIH VIL MS bit = 0 tSLSH SCK VIH tF VIL tSHSL VIL SIN VIH tR tSLOVE SOT VIH VOH VOL tIVSHE VIH VIL tSHIXE VIH VIL MS bit = 1 Document Number: 002-04930 Rev.*A Page 79 of 124 MB9B360L Series High-speed Synchronous Serial (SPI = 0, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Serial clock cycle time tSCYC SCKx SCK↑→SOT delay time tSHOVI SCKx, SOTx Internal shift clock operation VCC ≥ 4.5 V VCC < 4.5 V Conditions Min Max Min Max Unit 4tCYCP - 4tCYCP - ns -10 +10 -10 +10 ns - 12.5 - ns 14 SIN→SCK↓ setup time tIVSLI SCKx, SINx SCK↓→SIN hold time tSLIXI SCKx, SINx 5 - 5 - ns Serial clock "L" pulse width tSLSH SCKx 2tCYCP – 5 - 2tCYCP – 5 - ns Serial clock "H" pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK↑→SOT delay time tSHOVE SCKx, SOTx - 15 - 15 ns 5 - 5 - ns 12.5* External shift clock operation SIN→SCK↓ setup time tIVSLE SCKx, SINx SCK↓→SIN hold time tSLIXE SCKx, SINx 5 - 5 - ns SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see 8. Block Diagram in this data sheet. − These characteristics only guarantee the following pins. − − No chip select: SIN0_1, SOT0_1, SCK0_1 − Chip select: SIN6_0, SOT6_0, SCK6_0, SCS6_0 When the external load capacitance CL = 30 pF. (For *, when CL = 10 pF) Document Number: 002-04930 Rev.*A Page 80 of 124 MB9B360L Series tSCYC VOH SCK VOH VOL tSHOVI VOH VOL SOT tIVSLI VIH VIL SIN tSLIXI VIH VIL MS bit = 0 tSHSL SCK tSLSH VIH VIH VIL tR VIL tF tSHOVE SOT SIN VIL VOH VOL tIVSLE VIH VIL tSLIXE VIH VIL MS bit = 1 Document Number: 002-04930 Rev.*A Page 81 of 124 MB9B360L Series High-speed Synchronous Serial (SPI = 1, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions VCC < 4.5 V VCC ≥ 4.5 V Min Min Max Max Unit Serial clock cycle time tSCYC SCKx 4tCYCP - 4tCYCP - ns SCK↑→SOT delay time tSHOVI SCKx, SOTx -10 +10 -10 +10 ns SIN→SCK↓ setup time tIVSLI SCKx, SINx - 12.5 - ns SCK↓→SIN hold time tSLIXI SCKx, SINx 5 - 5 - ns SOT→SCK↓ delay time tSOVLI SCKx, SOTx 2tCYCP – 10 - 2tCYCP – 10 - ns Serial clock "L" pulse width tSLSH SCKx 2tCYCP – 5 - 2tCYCP – 5 - ns Serial clock "H" pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK↑→SOT delay time tSHOVE SCKx, SOTx - 15 - 15 ns 5 - 5 - ns Internal shift clock operation 14 12.5* External shift clock operation SIN→SCK↓ setup time tIVSLE SCKx, SINx SCK↓→SIN hold time tSLIXE SCKx, SINx 5 - 5 - ns SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see 8. Block Diagram in this data sheet. − These characteristics only guarantee the following pins. − − − No chip select: SIN0_1, SOT0_1, SCK0_1 Chip select: SIN6_0, SOT6_0, SCK6_0, SCS6_0 When the external load capacitance CL = 30 pF. (For *, when CL = 10 pF) Document Number: 002-04930 Rev.*A Page 82 of 124 MB9B360L Series tSCYC VOH VOL SCK SOT VOH VOL VOH VOL tIVSLI tSLIXI VIH VIL SIN VOL tSHOVI tSOVLI VIH VIL MS bit = 0 tSLSH VIH SCK VIH VIL tF * SOT VIL tSHSL tR VIH tSHOVE VOH VOL SIN VOH VOL tIVSLE tSLIXE VIH VIL VIH VIL MS bit = 1 *: Changes when writing to TDR register Document Number: 002-04930 Rev.*A Page 83 of 124 MB9B360L Series High-speed Synchronous Serial (SPI = 1, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Conditions VCC < 4.5 V VCC ≥ 4.5 V Min Min Symbol Pin Name Internal shift clock operation tSCYC SCKx 4tCYCP - 4tCYCP - ns SCK↓→SOT delay time tSLOVI SCKx, SOTx -10 +10 -10 +10 ns SIN→SCK↑ setup time tIVSHI SCKx, SINx - 12.5 - ns SCK↑→SIN hold time tSHIXI SCKx, SINx 5 - 5 - ns SOT→SCK↑ delay time tSOVHI SCKx, SOTx 2tCYCP – 10 - 2tCYCP – 10 - ns Serial clock "L" pulse width tSLSH SCKx 2tCYCP – 5 - 2tCYCP – 5 - ns Serial clock "H" pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK↓→SOT delay time tSLOVE SCKx, SOTx - 15 - 15 ns SIN→SCK↑ setup time tIVSHE SCKx, SINx 5 - 5 - ns SCK↑→SIN hold time tSHIXE SCKx, SINx 5 - 5 - ns SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Internal shift clock operation External shift clock operation Max Max Unit 14 12.5* Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see 8. Block Diagram in this data sheet. − These characteristics only guarantee the following pins. − − − No chip select: SIN0_1, SOT0_1, SCK0_1 Chip select: SIN6_0, SOT6_0, SCK6_0, SCS6_0 When the external load capacitance CL = 30 pF. (For *, when CL = 10 pF) Document Number: 002-04930 Rev.*A Page 84 of 124 MB9B360L Series tSCYC VOH SCK tSOVHI SOT tSLOVI VOH VOL VOH VOL tSHIXI tIVSHI VIH VIL SIN VOH VOL VIH VIL MS bit = 0 tSHSL tR SCK VIL VIH tSLSH VIH VIL tF VIL VIH tSLOVE SOT VOH VOL VOH VOL tIVSHE SIN tSHIXE VIH VIL VIH VIL MS bit = 1 Document Number: 002-04930 Rev.*A Page 85 of 124 MB9B360L Series When Using High-speed Synchronous Serial Chip Select (SPI = 1, SCINV = 0, MS=0, CSLVL=1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol SCS↓→SCK↓setup time tCSSI SCK↑→SCS↑ hold time tCSHI SCS deselect time VCC ≥ 4.5 V VCC < 4.5 V Conditions Min Max Min Unit Max (*1)-20 (*1)+0 (*1)-20 (*1)+0 ns (*2)+0 (*2)+20 (*2)+0 (*2)+20 ns tCSDI (*3)-20+5tCYCP (*3)+20+5tCYCP (*3)-20+5tCYCP (*3)+20+5tCYCP ns SCS↓→SCK↓setup time tCSSE 3tCYCP+15 - 3tCYCP+15 - ns SCK↑→SCS↑ hold time tCSHE 0 - 0 - ns 3tCYCP+15 - 3tCYCP+15 - ns Internal shift clock operation External shift clock operation SCS deselect time tCSDE SCS↓→SOT delay time tDSE - 25 - 25 ns SCS↑→SOT delay time tDEE 0 - 0 - ns (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see 8. Block Diagram in this data sheet. − − About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual. When the external load capacitance CL = 30 pF. Document Number: 002-04930 Rev.*A Page 86 of 124 MB9B360L Series SCS output tCSDI tCSSI tCSHI SCK output SOT (SPI=0) SOT (SPI=1) SCS input tCSDE tCSSE tCSHE SCK input tDEE SOT (SPI=0) tDSE SOT (SPI=1) Document Number: 002-04930 Rev.*A Page 87 of 124 MB9B360L Series When Using High-speed Synchronous Serial Chip Select (SPI = 1, SCINV = 1, MS=0, CSLVL=1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol SCS↓→SCK↑setup time tCSSI SCK↓→SCS↑ hold time tCSHI SCS deselect time tCSDI SCS↓→SCK↑setup time SCK↓→SCS↑ hold time SCS deselect time tCSDE SCS↓→SOT delay time tDSE SCS↑→SOT delay time tDEE VCC ≥ 4.5 V VCC < 4.5 V Conditions Min Max Min Unit Max (*1)-20 (*1)+0 (*1)-20 (*1)+0 ns (*2)+0 (*2)+20 (*2)+0 (*2)+20 ns (*3)-20+5tCYCP (*3)+20+5tCYCP (*3)-20+5tCYCP (*3)+20+5tCYCP ns tCSSE 3tCYCP+15 - 3tCYCP+15 - ns tCSHE 0 - 0 - ns 3tCYCP+15 - 3tCYCP+15 - ns - 25 - 25 ns 0 - 0 - ns Internal shift clock operation External shift clock operation (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see 8. Block Diagram in this data sheet. − About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part (002-04856). − When the external load capacitance CL = 30 pF. Document Number: 002-04930 Rev.*A Page 88 of 124 MB9B360L Series SCS output tCSDI tCSSI tCSHI SCK output SOT (SPI=0) SOT (SPI=1) SCS input tCSDE tCSSE tCSHE SCK input tDEE SOT (SPI=0) tDSE SOT (SPI=1) Document Number: 002-04930 Rev.*A Page 89 of 124 MB9B360L Series When Using High-speed Synchronous Serial Chip Select (SPI = 1, SCINV = 0, MS=0, CSLVL=0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol SCS↑→SCK↓setup time tCSSI SCK↑→SCS↓ hold time tCSHI SCS deselect time tCSDI SCS↑→SCK↓setup time tCSSE SCK↑→SCS↓ hold time tCSHE SCS deselect time tCSDE SCS↑→SOT delay time tDSE SCS↓→SOT delay time tDEE Internal shift clock operation External shift clock operation VCC ≥ 4.5 V VCC < 4.5 V Conditions Min Max Min Max Unit (*1)-20 (*1)+0 (*1)-20 (*1)+0 ns (*2)+0 (*2)+20 (*2)+0 (*2)+20 ns (*3)-20+5tCYCP (*3)+20+5tCYCP (*3)-20+5tCYCP (*3)+20+5tCYCP ns 3tCYCP+15 - 3tCYCP+15 - ns 0 - 0 - ns 3tCYCP+15 - 3tCYCP+15 - ns - 25 - 25 ns 0 - 0 - ns (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see 8. Block Diagram in this data sheet. − About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part (002-04856). − When the external load capacitance CL = 30 pF. Document Number: 002-04930 Rev.*A Page 90 of 124 MB9B360L Series tCSDI SCS output tCSSI tCSHI SCK output SOT (SPI=0) SOT (SPI=1) tCSDE SCS input tCSSE tCSHE SCK input tDEE SOT (SPI=0) SOT (SPI=1) tDSE Document Number: 002-04930 Rev.*A Page 91 of 124 MB9B360L Series When Using High-speed Synchronous Serial Chip Select (SPI = 1, SCINV = 1, MS=0, CSLVL=0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol SCS↑→SCK↑setup time tCSSI SCK↓→SCS↓ hold time tCSHI SCS deselect time tCSDI SCS↑→SCK↑setup time tCSSE SCK↓→SCS↓ hold time tCSHE SCS deselect time tCSDE SCS↑→SOT delay time tDSE SCS↓→SOT delay time tDEE Internal shift clock operation External shift clock operation VCC ≥ 4.5 V VCC < 4.5 V Conditions Min Max Min Max Unit (*1)-20 (*1)+0 (*1)-20 (*1)+0 ns (*2)+0 (*2)+20 (*2)+0 (*2)+20 ns (*3)-20+5tCYCP (*3)+20+5tCYCP (*3)-20+5tCYCP (*3)+20+5tCYCP ns 3tCYCP+15 - 3tCYCP+15 - ns 0 - 0 - ns 3tCYCP+15 - 3tCYCP+15 - ns - 25 - 25 ns 0 - 0 - ns (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see 8. Block Diagram in this data sheet. − About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part (002-04856). − When the external load capacitance CL = 30 pF. Document Number: 002-04930 Rev.*A Page 92 of 124 MB9B360L Series tCSDI SCS output tCSSI tCSHI SCK output SOT (SPI=0) SOT (SPI=1) tCSDE SCS input tCSSE tCSHE SCK input tDEE SOT (SPI=0) tDSE SOT (SPI=1) Document Number: 002-04930 Rev.*A Page 93 of 124 MB9B360L Series External Clock (EXT = 1): when in Asynchronous Mode Only (VCC = 2.7V to 5.5V, VSS = 0V) Value Parameter Serial clock "L" pulse width Serial clock "H" pulse width SCK falling time SCK rising time Symbol tSLSH tSHSL tF tR Condition SCK VIL Document Number: 002-04930 Rev.*A tCYCP + 10 tCYCP + 10 - CL = 30 pF tR Min 5 5 tSHSL VIH Unit Max ns ns ns ns tF tSLSH VIH VIL Remarks VIL VIH Page 94 of 124 MB9B360L Series 12.4.12 External Input Timing (VCC = 2.7V to 5.5V, VSS = 0V) Value Parameter Symbol Pin Name Conditions Min Unit Max ADTG Input pulse width tINH, tINL FRCKx ICxx DTTIxX INT00 to INT31, NMIX WKUPx Remarks A/D converter trigger input - 2tCYCP*1 - ns - 2tCYCP*1 2tCYCP + 100*1 500*2 500*3 - ns ns ns ns - Free-run timer input clock Input capture Waveform generator External interrupt, NMI Deep standby wake up *1: tCYCP indicates the APB bus clock cycle time except stop when in Stop mode, in timer mode. About the APB bus number which the A/D converter, multi-function timer, external interrupt are connected to, see 8. Block Diagram in this data sheet. *2: When in Stop mode, in timer mode. *3: When in deep standby RTC mode, in Deep Standby Stop mode. Document Number: 002-04930 Rev.*A Page 95 of 124 MB9B360L Series 12.4.13 Quadrature Position/Revolution Counter Timing (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol AIN pin H width AIN pin L width BIN pin H width BIN pin L width BIN rising time from AIN pin H level AIN falling time from BIN pin H level BIN falling time from AIN pin L level AIN rising time from BIN pin L level AIN rising time from BIN pin H level BIN falling time from AIN pin H level AIN falling time from BIN pin L level BIN rising time from AIN pin L level ZIN pin H width ZIN pin L width AIN/BIN rising and falling time from determined ZIN level Determined ZIN level from AIN/BIN rising and falling time Value Conditions Min tAHL tALL tBHL tBLL - tAUBU PC_Mode2 or PC_Mode3 tBUAD PC_Mode2 or PC_Mode3 tADBD PC_Mode2 or PC_Mode3 tBDAU PC_Mode2 or PC_Mode3 tBUAU PC_Mode2 or PC_Mode3 tAUBD PC_Mode2 or PC_Mode3 tBDAD PC_Mode2 or PC_Mode3 tADBU PC_Mode2 or PC_Mode3 tZHL tZLL QCR:CGSC = 0 QCR:CGSC = 0 tZABE QCR:CGSC = 1 tABEZ QCR:CGSC = 1 2tCYCP* Max - Unit ns *: tCYCP indicates the APB bus clock cycle time except stop when in Stop mode, in timer mode. About the APB bus number which Quadrature Position/Revolution Counter is connected to, see 8. Block Diagram in this data sheet. tALL tAHL AIN tAUBU tADBD tBUAD tBDAU BIN tBHL Document Number: 002-04930 Rev.*A tBLL Page 96 of 124 MB9B360L Series tBLL tBHL BIN tBUAU tBDAD tAUBD tADBU AIN tAHL tALL ZIN ZIN AIN/BIN Document Number: 002-04930 Rev.*A Page 97 of 124 MB9B360L Series 2 12.4.14 I C Timing Typical Mode, High-speed Mode (VCC = 2.7V to 5.5V, VSS = 0V) Typical Mode Parameter Symbol Conditions Min High-speed Mode Max Min Max Unit SCL clock frequency (Repeated) START condition hold time SDA ↓ → SCL ↓ FSCL 0 100 0 400 kHz tHDSTA 4.0 - 0.6 - μs SCL clock "L" width tLOW 4.7 - 1.3 - μs SCL clock "H" width tHIGH 4.0 - 0.6 - μs 4.7 - 0.6 - μs tHDDAT 0 3.45*2 0 0.9*3 μs tSUDAT 250 - 100 - ns tSUSTO 4.0 - 0.6 - μs tBUF 4.7 - 1.3 - μs 2tCYCP*4 - 2tCYCP*4 - ns 4tCYCP*4 - 4tCYCP*4 - ns 6tCYCP*4 - 6tCYCP*4 - ns 8tCYCP*4 - 8tCYCP*4 - ns 10tCYCP*4 - 10tCYCP*4 - ns 12tCYCP*4 - 12tCYCP*4 - ns 14tCYCP*4 - 14tCYCP*4 - ns 16tCYCP*4 - 16tCYCP*4 - ns (Repeated) START condition setup time SCL ↑ → SDA ↓ Data hold time SCL ↓ → SDA ↓ ↑ Data setup time SDA ↓ ↑ → SCL ↑ STOP condition setup time SCL ↑ → SDA ↑ Bus free time between "STOP condition" and "START condition" Noise filter tSUSTA tSP CL = 30 pF, R = (Vp/IOL)*1 2 MHz ≤ tCYCP<40 MHz 40 MHz ≤ tCYCP<60 MHz 60 MHz ≤ tCYCP<80 MHz 80 MHz ≤ tCYCP<100 MHz 100 MHz ≤ tCYCP<120 MHz 120 MHz ≤ tCYCP<140 MHz 140 MHz ≤ tCYCP<160 MHz 160 MHz ≤ tCYCP<180 MHz Remarks *5 *1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current. *2: The maximum tHDDAT must satisfy that it does not extend at least "L" period (tLOW) of device's SCL signal. 2 2 *3: A high-speed mode I C bus device can be used on a typical mode I C bus system as long as the device satisfies the requirement of tSUDAT ≥ 250 ns. *4: tCYCP is the APB bus clock cycle time. 2 About the APB bus number that I C is connected to, see "8. Block Diagram" in this data sheet. *5: The noise filter time can be changed by register settings. Change the number of the noise filter steps according to APB bus clock frequency. Document Number: 002-04930 Rev.*A Page 98 of 124 MB9B360L Series Fast Mode Plus (Fm+) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Fast Mode Plus 6 (Fm+)* Conditions Min SCL clock frequency (Repeated) START condition hold time SDA ↓ → SCL ↓ SCL clock "L" width SCL clock "H" width SCL clock frequency (Repeated) START condition hold time SDA ↓ → SCL ↓ Data setup time SDA ↓ ↑ → SCL ↑ STOP condition setup time SCL ↑ → SDA ↑ Bus free time between "STOP condition" and "START condition" Noise filter Unit FSCL 0 1000 kHz tHDSTA 0.26 - μs tLOW tHIGH tSUSTA 0.5 0.26 0.26 - μs μs μs 0 0.45*2, *3 μs tSUDAT 50 - ns tSUSTO 0.26 - μs tBUF 0.5 - μs 6 tCYCP*4 - ns 8 tCYCP*4 - ns 10 tCYCP*4 - ns 12 tCYCP*4 - ns 14 tCYCP*4 - ns 16 tCYCP*4 - ns tHDDAT tSP CL = 30 pF, R = (Vp/IOL)*1 60 MHz ≤ tCYCP<80 MHz 80 MHz ≤ tCYCP<100 MHz 100 MHz ≤ tCYCP<120 MHz 120 MHz ≤ tCYCP<140 MHz 140 MHz ≤ tCYCP<160 MHz 160 MHz ≤ tCYCP<180 MHz Remarks Max *5 *1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current. *2: The maximum tHDDAT must satisfy that it does not extend at least L period (tLOW) of device's SCL signal. 2 2 *3: A high-speed mode I C bus device can be used on a typical mode I C bus system as long as the device satisfies the requirement of "tSUDAT ≥ 250 ns". *4: tCYCP is the APB bus clock cycle time. 2 About the APB bus number that I C is connected to, see 8. Block Diagram in this data sheet. To use fast mode plus (Fm+), set the peripheral bus clock at 64 MHz or more. *5: The noise filter time can be changed by register settings. Change the number of the noise filter steps according to APB bus clock frequency. 2 *6: When using fast mode plus (Fm+), set the I/O pin to the mode corresponding to I C Fm+ in the EPFR register. See CHAPTER 12: I/O Port in FM4 Family Peripheral Manual Main part (002-04856) for the details. SDA SCL Document Number: 002-04930 Rev.*A Page 99 of 124 MB9B360L Series 12.4.15 JTAG Timing (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Value Conditions Min TMS, TDI setup time tJTAGS TCK, TMS, TDI VCC ≥ 4.5 V TMS, TDI hold time tJTAGH TCK, TMS, TDI VCC ≥ 4.5 V TDO delay time tJTAGD TCK, TDO VCC < 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V Unit Remarks Max 15 - ns 15 - ns - 25 - 45 ns Note: − When the external load capacitance CL= 30 pF. TCK TMS/TDI TDO Document Number: 002-04930 Rev.*A Page 100 of 124 MB9B360L Series 12.5 12-bit A/D Converter Electrical Characteristics for the A/D Converter (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V) Parameter Symbol Value Pin Name Min Unit Typ Resolution Integral Nonlinearity Differential Nonlinearity Zero transition voltage Full-scale transition voltage VZT VFST AN00 to AN14 AN00 to AN14 -4.5 -2.5 -15 AVRH - 15 - 12 +4.5 +2.5 +15 AVRH + 15 bit LSB LSB mV mV Conversion time - - 0.5*1 - - μs *2 10 μs Sampling time Ts - Compare clock cycle*3 Tcck - State transition time to operation permission Tstt Power supply current (analog + digital) Remarks Max *2 - 25 - 1000 50 - 1000 - 1.0 - - μs - AVCC - 0.69 0.3 0.92 12 mA μA Reference power supply current (between AVRH and AVSS) - AVRH - 1.1 1.97 mA 0.2 4.2 μA Analog input capacity CAIN - - - 10 pF Analog input resistance RAIN - - - Interchannel disparity - - - - 1.2 1.8 4 Analog port input current Analog input voltage - AN00 to AN14 AN00 to AN14 Reference voltage - AVRH AVSS 4.5 2.7 - 5 AVRH AVCC AVCC ns kΩ AVRH = 2.7 V to 5.5 V AVCC ≥ 4.5V AVCC ≥ 4.5V AVCC < 4.5V AVCC ≥ 4.5V AVCC < 4.5V A/D 1 unit operation When A/D stop A/D 1unit operation AVRH=5.5 V When A/D stop AVCC ≥ 4.5 V AVCC < 4.5 V LSB μA V V Tcck < 50 ns Tcck ≥ 50 ns *1: The conversion time is the value of sampling time (Ts) + compare time (Tc). The condition of the minimum conversion time is when the value of sampling time: 150 ns, the value of compare time: 350 ns 4 (AVCC ≥ 4.5 V). Ensure that it satisfies the value of sampling time (Ts) and compare clock cycle (Tcck). For setting* of sampling time and compare clock cycle, see CHAPTER 1-1: A/D Converter in FM4 Family Peripheral Manual Analog macro part (002-04860). The register setting of the A/D Converter is reflected by the peripheral clock timing. The sampling and compare clock are set at Base clock (HCLK). *2: A necessary sampling time changes by external impedance. Ensure that it set the sampling time to satisfy (Equation 1). *3: The compare time (Tc) is the value of (Equation 2). *4: The register setting of the A/D Converter is reflected by the timing of the APB bus clock. The sampling clock and compare clock are set in base clock (HCLK). About the APB bus number which the A/D Converter is connected to, see 8. Block Diagram in this data sheet. Document Number: 002-04930 Rev.*A Page 101 of 124 MB9B360L Series Rext AN00 to AN14 Analog input pin Comparator RAIN Analog signal source CAIN (Equation 1) Ts ≥ (RAIN + Rext ) × CAIN × 9 Ts: Sampling time RAIN: Input resistance of A/D = 1.2 kΩ at 4.5 V < AVCC < 5.5 V Input resistance of A/D = 1.8 kΩ at 2.7 V < AVCC < 4.5 V CAIN: Input capacity of A/D = 10 pF at 2.7 V < AVCC < 5.5 V Rext: Output impedance of external circuit (Equation 2) Tc = Tcck × 14 Tc: Compare time Tcck: Compare clock cycle Document Number: 002-04930 Rev.*A Page 102 of 124 MB9B360L Series Definition of 12-bit A/D Converter Terms • Resolution: • Integral Nonlinearity: Analog variation that is recognized by an A/D converter. Deviation of the line between the zero-transition point (0b000000000000 ←→ 0b000000000001) and the full-scale transition point (0b111111111110 ←→ 0b111111111111) from the actual conversion characteristics. • Differential Nonlinearity: Deviation from the ideal value of the input voltage that is required to change the output code by 1 LSB. Integral Nonlinearity Differential Nonlinearity 0xFFF Actual conversion characteristics 0xFFE Actual conversion characteristics 0x(N+1) {1 LSB(N-1) + VZT} VFST VNT 0x004 (Actually-measured value) 0x003 0x002 (Actuallymeasured value) Digital output Digital output 0xFFD 0xN Ideal characteristics V(N+1)T 0x(N-1) (Actually-measured value) Actual conversion characteristics Ideal characteristics VNT (Actually-measured value) 0x(N-2) 0x001 VZT (Actually-measured value) AVss Actual conversion characteristics AVRH AVss AVRH Analog input Integral Nonlinearity of digital output N = Analog input VNT - {1LSB × (N - 1) + VZT} 1LSB Differential Nonlinearity of digital output N = 1LSB = V(N + 1) T - VNT 1LSB [LSB] - 1 [LSB] VFST - VZT 4094 N: A/D converter digital output value. VZT: Voltage at which the digital output changes from 0x000 to 0x001. VFST: Voltage at which the digital output changes from 0xFFE to 0xFFF. VNT: Voltage at which the digital output changes from 0x(N − 1) to 0xN. Document Number: 002-04930 Rev.*A Page 103 of 124 MB9B360L Series 12.6 12-bit D/A Converter Electrical Characteristics for the D/A Converter (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V) Parameter Symbol Resolution Integral Nonlinearity* Differential Nonlinearity* INL DNL Output voltage offset VOFF Analog output impedance RO Power supply current* IDDA IDSA Pin Name DAx AVCC Value Typ Min Unit Max Remarks -16 -0.98 -20.0 3.10 2.0 260 400 3.80 330 519 12 +16 +1.5 10.0 +1.4 4.50 410 620 bit LSB LSB mV mV kΩ MΩ μA μA When setting 0x000 When setting 0xFFF D/A operation When D/A stop D/A 1unit operation AVCC=3.3 V D/A 1unit operation AVCC=5.0 V - - 14 μA When D/A stop *: During no load Document Number: 002-04930 Rev.*A Page 104 of 124 MB9B360L Series 12.7 USB Characteristics (VCC = 2.7V to 5.5V, USBVCC = 3.0V to 3.6V, VSS = 0V) Parameter Input character -istics Output character -istics Symbol Pin Name Value Conditions Min Max Unit Remarks Input H level voltage VIH - 2.0 USBVCC + 0.3 V *1 Input L level voltage VIL - VSS - 0.3 0.8 V *1 VDI - 0.2 - V *2 VCM - 0.8 2.5 V *2 2.8 3.6 V *3 0.0 0.3 V *3 1.3 4 4 2.0 20 20 V ns ns *4 *5 *5 Differential input sensitivity Different common mode range Output "H" level voltage VOH Output "L" level voltage VOL Crossover voltage Rising time Falling time Rising/falling time matching Output impedance Rising time Falling time Rising/falling time matching VCRS tFR tFF External pull-down resistance = 15 kΩ External pull-up resistance = 1.5 kΩ Full-Speed Full-Speed tFRFM Full-Speed 90 111.11 % *5 ZDRV tLR tLF Full-Speed Low-Speed Low-Speed 28 75 75 44 300 300 Ω ns ns *6 *7 *7 tLRFM Low-Speed 80 125 % *7 UDP0,UDM0 *1: The switching threshold voltage of Single-End-Receiver of USB I/O buffer is set as within VIL (Max) = 0.8 V, VIH (Min) = 2.0 V (TTL input standard). There are some hysteresises to lower noise sensitivity. Minimum differential input sensitivity [V] *2: Use differential-Receiver to receive USB differential data signal. Differential-Receiver has 200 mV of differential input sensitivity when the differential data input is within 0.8 V to 2.5 V to the local ground reference level. Above voltage range is the common mode input voltage range. Common mode input voltage [V] Document Number: 002-04930 Rev.*A Page 105 of 124 MB9B360L Series *3: The output drive capability of the driver is below 0.3 V at Low-State (VOL) (to 3.6 V and 1.5 kΩ load), and 2.8 V or above (to the VSS and 1.5 kΩ load) at High-State (VOH). *4: The cross voltage of the external differential output signal (D + /D −) of USB I/O buffer is within 1.3 V to 2.0 V. VCRS specified range *5: They indicate rising time (Trise) and falling time (Tfall) of the full-speed differential data signal. They are defined by the time between 10% and 90% of the output signal voltage. For full-speed buffer, Tr/Tf ratio is regulated as within ± 10% to minimize RFI emission. Rising time Document Number: 002-04930 Rev.*A Falling time Page 106 of 124 MB9B360L Series *6: USB Full-speed connection is performed via twist pair cable shield with 90 Ω ± 15% characteristic impedance (Differential Mode). USB standard defines that output impedance of USB driver must be in range from 28 Ω to 44 Ω. So, discrete series resistor (Rs) addition is defined in order to satisfy the above definition and keep balance. When using this USB I/O, use it with 25 Ω to 30 Ω (recommendation value 27 Ω) Series resistor Rs. 28Ω to 44Ω Equiv. Imped. 28Ω to 44Ω Equiv. Imped. Mount it as external resistance. Rs series resistor 25 Ω to 30 Ω Series resistor of 27 Ω (recommendation value) must be added. And, use "resistance with an uncertainty of 5% by E24 sequence". *7: They indicate rising time (Trise) and falling time (Tfall) of the low-speed differential data signal. They are defined by the time between 10% and 90% of the output signal voltage. Rising time Falling time See Low-Speed Load (Compliance Load) for conditions of external load. Document Number: 002-04930 Rev.*A Page 107 of 124 MB9B360L Series Low-Speed Load (Upstream Port Load) - Reference 1 CL = 50pF to 150pF CL = 50pF to 150pF Low-Speed Load (Downstream Port Load) - Reference 2 CL =200pF to 600pF CL =200pF to 600pF Low-Speed Load (Compliance Load) CL = 200pF to 450pF CL = 200pF to 450pF Document Number: 002-04930 Rev.*A Page 108 of 124 MB9B360L Series 12.8 Low-Voltage Detection Characteristics 12.8.1 Low-Voltage Detection Reset Parameter Detected voltage Released voltage Symbol Conditions VDL VDH - Value Typ Min 2.25 2.30 2.45 2.50 Unit Max 2.65 2.70 V V Remarks When voltage drops When voltage rises 12.8.2 Interrupt of Low-Voltage Detection Parameter Symbol Detected voltage Released voltage Detected voltage VDL VDH VDL Released voltage VDH Detected voltage VDL Released voltage VDH Detected voltage VDL Released voltage VDH Detected voltage VDL Released voltage VDH Detected voltage VDL Released voltage VDH Detected voltage VDL Released voltage VDH Detected voltage VDL Released voltage VDH LVD stabilization wait time TLVDW Value Conditions SVHI = 00111 SVHI = 00100 SVHI = 01100 SVHI = 01111 SVHI = 01110 SVHI = 01001 SVHI = 01000 SVHI = 11000 - Min Typ Unit Max Remarks 2.58 2.67 2.76 2.8 2.9 3.0 3.02 3.13 3.24 V V V When voltage drops When voltage rises When voltage drops 2.85 3.1 3.34 V When voltage rises 2.94 3.2 3.45 V When voltage drops 3.04 3.3 3.56 V When voltage rises 3.31 3.6 3.88 V When voltage drops 3.40 3.7 3.99 V When voltage rises 3.40 3.7 3.99 V When voltage drops 3.50 3.8 4.10 V When voltage rises 3.68 4.0 4.32 V When voltage drops 3.77 4.1 4.42 V When voltage rises 3.77 4.1 4.42 V When voltage drops 3.86 4.2 4.53 V When voltage rises 3.86 4.2 4.53 V When voltage drops 3.96 4.3 4.64 V When voltage rises - - 4480× tCYCP* μs *: tCYCP indicates the APB2 bus clock cycle time. Document Number: 002-04930 Rev.*A Page 109 of 124 MB9B360L Series 12.9 MainFlash Memory Write/Erase Characteristics (VCC = 2.7V to 5.5V) Value Parameter Sector erase time Half word (16-bit) write time Large Sector Small Sector Write cycles < 100 times Write cycles > 100 times Chip erase time Min - Typ Max 0.7 3.7 0.3 1.1 Unit Remarks s Includes write time prior to internal erase μs Not including system-level overhead time s Includes write time prior to internal erase 100 - 12 200 - 8.0 38.4 Write cycles and data hold time Erase/Write cycles (cycle) Data hold time (year) 1,000 20 * 10,000 10 * 100,000 5* *: This value comes from the technology qualification (using Arrhenius equation to translate high temperature acceleration test result into average temperature value at +85°C). 12.10 WorkFlash Memory Write/Erase Characteristics (VCC = 2.7V to 5.5V) Parameter Min Value Typ Max Unit Remarks Sector erase time - 0.3 1.5 s Includes write time prior to internal erase Half word (16-bit) write time - 20 200 μs Not including system-level overhead time Chip erase time - 1.2 6 s Includes write time prior to internal erase Write cycles and data hold time Erase/Write cycles (cycle) Data hold time (year) 1,000 20 * 10,000 10 * 100,000 5* *: This value comes from the technology qualification (using Arrhenius equation to translate high temperature acceleration test result into average temperature value at +85°C). Document Number: 002-04930 Rev.*A Page 110 of 124 MB9B360L Series 12.11 Standby Recovery Time 12.11.1 Recovery cause: Interrupt/WKUP The time from recovery cause reception of the internal circuit to the program operation start is shown. Recovery Count Time (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Value Symbol Typ Max* Unit μs Sleep mode HCLK×1 High-speed CR Timer mode Main Timer mode PLL Timer mode 40 80 μs Low-speed CR timer mode 450 900 μs Sub timer mode 881 1136 μs 270 581 μs 240 480 308 667 μs 308 667 μs RTC mode stop mode (High-speed CR /Main/PLL run mode return) RTC mode stop mode (Low-speed CR/sub run mode return) Deep standby RTC mode with RAM retention Deep standby stop mode with RAM retention Ticnt Remarks without RAM retention with RAM retention *: The maximum value depends on the built-in CR accuracy. Example of Standby Recovery Operation (when in External Interrupt Recovery*) Ext.INT Interrupt factor accept Active Ticnt CPU Operation Interrupt factor clear by CPU Start *: External interrupt is set to detecting fall edge. Document Number: 002-04930 Rev.*A Page 111 of 124 MB9B360L Series Example of Standby Recovery Operation (when in Internal Resource Interrupt Recovery*) Internal Resource INT Interrupt factor accept Active Ticnt CPU Operation Interrupt factor clear by CPU Start *: Depending on the standby mode, interrupt from the internal resource is not included in the recovery cause. Notes: − The return factor is different in each Low-Power consumption modes. See CHAPTER 6: Low Power Consumption Mode and Operations of Standby Modes in FM4 Family Peripheral Manual Main part (002-04856). − When interrupt recoveries, the operation mode that CPU recoveries depend on the state before the Low-Power consumption mode transition. See CHAPTER 6: Low Power Consumption Mode in FM4 Family Peripheral Manual Main part (002-04856). Document Number: 002-04930 Rev.*A Page 112 of 124 MB9B360L Series 12.11.2 Recovery Cause: Reset The time from reset release to the program operation start is shown. Recovery Count Time (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Value Typ Max* Unit Sleep mode 116 266 μs High-speed CR timer mode Main timer mode PLL timer mode 116 266 μs Low-speed CR timer mode 258 567 μs 258 567 μs 308 667 μs Sub timer mode Trcnt RTC mode Stop mode Deep standby RTC mode with RAM retention Deep standby stop mode with RAM retention μs 308 667 μs Remarks without RAM retention with RAM retention *: The maximum value depends on the built-in CR accuracy. Example of Standby Recovery Operation (when in INITX Recovery) INITX Internal RST RST Active Release Trcnt CPU Operation Document Number: 002-04930 Rev.*A Start Page 113 of 124 MB9B360L Series Example of Standby Recovery Operation (when in Internal Resource Reset Recovery*) Internal Resource RST Internal RST RST Active Release Trcnt CPU Operation Start *: Depending on the standby mode, the reset issue from the internal resource is not included in the recovery cause. Notes: − The return factor is different in each Low-Power consumption modes. See CHAPTER 6: Low Power Consumption Mode and Operations of Standby Modes in FM4 Family Peripheral Manual Main part (002-04856). − The time during the power-on reset/low-voltage detection reset is excluded to the recovery source. See (6) Power-on Reset Timing in 12.4 AC Characteristics in 12. Electrical Characteristics for the detail on the time during the power-on reset/low-voltage detection reset. − When in recovery from reset, CPU changes to the high-speed CR run mode. When using the main clock or the PLL clock, it is necessary to add the main clock oscillation stabilization wait time or the main PLL clock stabilization wait time. − The internal resource reset means the watchdog reset and the CSV reset. Document Number: 002-04930 Rev.*A Page 114 of 124 MB9B360L Series 13. Ordering Information Part number Package MB9BF364LPMC1 MB9BF365LPMC1 Plastic・LQFP (0.5mm pitch), 64 pin (FPT-64P-M38) MB9BF366LPMC1 MB9BF364LPMC MB9BF365LPMC Plastic・LQFP (0.65mm pitch), 64 pin (FPT-64P-M39) MB9BF366LPMC MB9BF364KPMC MB9BF365KPMC Plastic・LQFP (0.5mm pitch), 48 pin (FPT-48P-M49) MB9BF366KPMC MB9BF364LQN MB9BF365LQN Plastic・QFN (0.5mm pitch), 64 pin (LCC-64P-M24) MB9BF366LQN MB9BF364KQN MB9BF365KQN Plastic・QFN (0.5mm pitch), 48 pin (LCC-48P-M73) MB9BF366KQN Document Number: 002-04930 Rev.*A Page 115 of 124 MB9B360L Series 14. Package Dimensions 64-pin plastic LQFP Lead pitch 0.50 mm Package width × package length 10.00 mm × 10.00 mm Lead shape Gullwing Lead bend direction Normal bend Sealing method Plastic mold Mounting height 1.70 mm MAX Weight 0.32 g (FPT-64P-M38) 64-pin plastic LQFP (FPT-64P-M38) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 12.00±0.20(.472±.008)SQ *10.00±0.10(.394±.004)SQ 48 0.145 ± 0.055 (.006 ± .002) 33 49 Details of "A" part 32 +0.20 0.08(.003) 1.50 –0.10 (Mounting height) .059 +.008 –.004 0.25(.010) 0~8° INDEX 64 1 0.22±0.05 (.009±.002) 0.08(.003) 2010 FUJITSU SEMICONDUCTOR LIMITED F64038S-c-1-2 Document Number: 002-04930 Rev.*A 0.10 ± 0.10 (.004±.004) (Stand off) "A" 16 0.50(.020) C 0.50±0.20 (.020±.008) 0.60 ± 0.15 (.024±.006) 17 M Dimensions in mm (inches). Note: The values in parentheses are reference values. Page 116 of 124 MB9B360L Series Document Number: 002-04930 Rev.*A Page 117 of 124 MB9B360L Series 64-pin plastic QFN Lead pitch 0.50 mm Package width × package length 9.00 mm × 9.00 mm Sealing method Plastic mold Mounting height 0.90 mm MAX Weight - (LCC-64P-M24) 64-pin plastic QFN (LCC-64P-M24) 9.00±0.10 (.354±.004) 6.00±0.10 (.236±.004) 9.00±0.10 (.354±.004) 0.25±0.05 (.010±.002) 6.00±0.10 (.236±.004) INDEX AREA 0.45 (.018) 1PIN ID (0.20R (.008R)) 0.85±0.05 (.033±.002) 0.05 (.002) MAX C 0.40±0.05 (.016±.002) (0.20 (.008)) 2011 FUJITSU SEMICONDUCTOR LIMITED HMbC64-24Sc-2-1 Document Number: 002-04930 Rev.*A 0.50 (.020) (TYP) Dimensions in mm (inches). Note: The values in parentheses are reference values. Page 118 of 124 MB9B360L Series 48-pin plastic LQFP Lead pitch 0.50 mm Package width × package length 7.00 mm × 7.00 mm Lead shape Gullwing Lead bend direction Normal bend Sealing method Plastic mold Mounting height 1.70 mm MAX Weight 0.17 g (FPT-48P-M49) 48-pin plastic LQFP (FPT-48P-M49) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 9.00 ± 0.20(.354 ± .008)SQ *7.00± 0.10(.276 ± .004)SQ 36 0.145± 0.055 (.006 ± .002) 25 37 24 0.08(.003) Details of "A" part +0.20 1.50 –0.10 (Mounting height) +.008 .059 –.004 INDEX 48 13 "A" 0°~8° 1 0.50(.020) C 12 0.22 ± 0.05 (.008 ± .002) 0.08(.003) 2010 FUJITSU SEMICONDUCTOR LIMITED HMbF48-49Sc-1-2 Document Number: 002-04930 Rev.*A 0.10 ± 0.10 (.004 ± .004) (Stand off) 0.25(.010) M 0.60 ± 0.15 (.024 ± .006) Dimensions in mm (inches). Note: The values in parentheses are reference values. Page 119 of 124 MB9B360L Series Document Number: 002-04930 Rev.*A Page 120 of 124 MB9B360L Series 15. Major Changes Spansion Publication Number: DS709-00007 Page Section - - Change Results Preliminary → Data Sheet ■FEATURES [USB function] Added the following description : ・The size of each endpoint is according to the follows. - Endpoint 0, 2 to 5 : 64bytes - Endpoint 1 : 256bytes ■I/O CIRCUIT TYPE 31 to 34 Added the following description to Remarks of Type F, G, I, L, M, N : When this pin is used as an I2C pin, the digital output P-ch transistor is always off 35 to 36 Added the following description to Remarks of Type O, P, Q: For I/O setting, refer to VBAT Domain in the PERIPHERAL MANUAL 3 43 ■HANDLING DEVICES lHandling when using debug pins Added new section 44 ■BLOCK DIAGRAM Revised the block diagram ■ELECTRICAL CHARACTERISTICS 2. Recommended Operating Conditions Added the note to “AVRH” 57 Revised “Table for package thermal resistance and maximum permissible power” Revised “Icc(leakmax)” 58 60 to 65 ■ELECTRICAL CHARACTERISTICS 3. DC Characteristics (1) Current Rating • Revised the value of TBD • Added the note to “ICC” • Added the note to “ICCVBAT” 70 ■ELECTRICAL CHARACTERISTICS 4. AC Characteristics (3) Sub Clock Input Characteristics Revised the waveform chart : VCC → VBAT 70 ■ELECTRICAL CHARACTERISTICS 4. AC Characteristics (3) Built-in CR OscillationCharacteristics • Revised the value of TBD • Revised the table and the note of “Built-in High-speed CR” • Revised the table and the note 71 ■ELECTRICAL CHARACTERISTICS 4. AC Characteristics (4-1) Operating Conditions of Main PLL(In the case of using main clock for input clock of PLL) (4-2)Operating Conditions of USB PLL(In the case of using main clock for input clock of PLL) • Revised the value of TBD • Revised the table and the note 71 ■ELECTRICAL CHARACTERISTICS 4. AC Characteristics (4-3) Operating Conditions of Main PLL(In the case of using built-in high-speed CR clock for input clock of main PLL) ■ELECTRICAL CHARACTERISTICS 5. 12-bit A/D Converter ・Electrical Characteristics for the A/D Converter • Revised the value of TBD • Revised the condition of the electrical characteristics table • Revised the description of "Reference voltage" ■ELECTRICAL CHARACTERISTICS 6. 12-bit D/A Converter ・Electrical Characteristics for the D/A Converter • Revised the value of TBD • Revised the condition of the electrical characteristics table • Revised the remarks of “IDDA” 106 109 Document Number: 002-04930 Rev.*A Page 121 of 124 MB9B360L Series Page Section Change Results 116 ■ELECTRICAL CHARACTERISTICS 11. Standby Recovery Time (1) Recovery cause: Interrupt/WKUP • Revised the value of TBD • Revised the table of Recovery count time 118 ■ELECTRICAL CHARACTERISTICS 11. Standby Recovery Time (2) Recovery cause:Reset • Revised the value of TBD • Revised the table of Recovery count time NOTE: Please see “Document History” about later revised information. Document Number: 002-04930 Rev.*A Page 122 of 124 MB9B360L Series Document History Document Title: MB9B360L Series 32-Bit ARM® Cortex® - M4F, FM4 Microcontroller Document Number: 002-04930 Revision ECN ** - Orig. of Submission Change Date AKIH 12/25/2013 Description of Change Migrated to Cypress and assigned document number 002-04930. No change to document contents or format. *A 5273878 AKIH Document Number: 002-04930 Rev.*A 05/12/2016 Updated to Cypress format. Page 123 of 124 MB9B360L Series Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. 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Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 002-04930 Rev.*A May 12, 2016 Page 124 of 124