MB9B120J Series
32-Bit ARM® Cortex®-M3
FM3 Microcontroller
The MB9B120J Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers with low-power consumption
mode and competitive cost.
These series are based on the ARM® Cortex®-M3 Processor with on-chip Flash memory and SRAM, and have peripheral functions
such as various timers, ADCs and Communication Interfaces (UART, CSIO, I2C, LIN).
The products which are described in this data sheet are placed into TYPE10 product categories in FM3 Family Peripheral Manual.
Features
32-bit ARM® Cortex®-M3 Core
Various error detection functions available (parity errors,
framing errors, and overrun errors)
Processor version: r2p1
[CSIO]
Up to 72 MHz Frequency Operation
Integrated Nested Vectored Interrupt Controller (NVIC): 1
NMI (non-maskable interrupt) and
48 peripheral interrupts and 16 priority levels
24-bit System timer (Sys Tick): System timer for OS task
management
Full-duplex double buffer
Built-in dedicated baud rate generator
Overrun error detection function available
[LIN]
LIN protocol Rev.2.1 supported
On-chip Memories
Full-duplex double buffer
[Flash memory]
Master/Slave mode supported
64 Kbytes
LIN break field generate (can be changed 13-bit to 16-bit
Read cycle: 0 wait-cycle
length)
LIN break delimiter generate (can be changed 1-bit to 4-bit
Security function for code protection
length)
[SRAM]
This Series on-chip SRAM is composed of two independent
SRAM (SRAM0, SRAM1). SRAM0 is connected to I-code bus
and D-code bus of Cortex-M3 core. SRAM1 is connected to
System bus.
SRAM0: 4 Kbytes
SRAM1: 4 Kbytes
Various error detect functions available (parity errors, framing
errors, and overrun errors)
2
[I C]
Standard-mode (Max 100 kbps) / Fast-mode (Max 400kbps)
supported
DMA Controller (Four channels)
Multi-function Serial Interface (Max four channels)
The DMA Controller has an independent bus from the CPU, so
CPU and DMA Controller can process simultaneously.
2 channels with 16steps×9-bit FIFO (ch.0/ch.1), 2 channels
4 independently configured and operated channels
without FIFO (ch.2/ ch.5)
Operation mode is selectable from the followings for each
channel.
UART
CSIO
LIN
2
I C
Transfer can be started by software or request from the
built-in peripherals
Transfer address area: 32-bit (4 Gbytes)
Transfer mode: Block transfer/Burst transfer/Demand
transfer
Transfer data type: byte/half-word/word
[UART]
Transfer block count: 1 to 16
Full-duplex double buffer
Number of transfers: 1 to 65536
Selection with or without parity supported
Built-in dedicated baud rate generator
External clock available as a serial clock
Cypress Semiconductor Corporation
Document Number: 002-05657 Rev.*A
2016
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 14,
MB9B120J Series
A/D Converter (Max 8channels)
[12-bit A/D Converter]
Successive Approximation type
Conversion time: 1.0 μs @ 5 V
Priority conversion available (priority at 2 levels)
Not included the function to activate A/D by external trigger
input
Quadrature Position/Revolution Counter (QPRC)
(One channel)
The Quadrature Position/Revolution Counter (QPRC) is used
to measure the position of the position encoder. Moreover, it is
possible to use as the up/down counter.
The detection edge of the three external event input pins AIN,
BIN and ZIN is configurable.
16-bit position counter
Scanning conversion mode
16-bit revolution counter
Built-in FIFO for conversion data storage (for SCAN
Two 16-bit compare registers
conversion: 16 steps, for Priority conversion: 4steps)
Base Timer (Max eight channels)
Multi-function Timer
The Multi-function timer is composed of the following blocks.
Operation mode is selectable from the followings for each
channel.
16-bit free-run timer × 3ch.
16-bit PWM timer
Input capture × 4ch.
16-bit PPG timer
Output compare × 6ch.
16-/32-bit reload timer
A/D activation compare × 1ch.
16-/32-bit PWC timer
Waveform generator × 3ch.
16-bit PPG timer × 3ch.
General-Purpose I/O Port
This series can use its pins as general-purpose I/O ports when
they are not used for peripherals. Moreover, the port relocate
function is built-in. It can set which I/O port the peripheral
function can be allocated to.
The following function can be used to achieve the motor
control.
Capable of pull-up control per pin
DC chopper waveform output function
Capable of reading pin level directly
Dead time function
Built-in the port relocate function
Input capture function
Up to 23 fast general-purpose I/O Ports@32pin Package
A/D convertor activate function
Some ports are 5V tolerant
DTIF (Motor emergency stop) interrupt function
See List of Pin Functions and I/O Circuit Type to confirm the
corresponding pins.
Dual Timer (32-/16-bit Down Counter)
The Dual Timer consists of two programmable 32-/16-bit down
counters.
Operation mode is selectable from the followings for each
channel.
Free-running
PWM signal output function
Real-time clock (RTC)
The Real-time clock can count
Year/Month/Day/Hour/Minute/Second/A day of the week from
01 to 99.
The interrupt function with specifying date and time
(Year/Month/Day/Hour/Minute/Second/A day of the week.) is
available. This function is also available by specifying only
Year, Month, Day, Hour or Minute.
Periodic (=Reload)
Timer interrupt function after set time or each set time.
One-shot
Capable of rewriting the time with continuing the time count.
Leap year automatic count is available.
External Interrupt Controller Unit
Up to 7 external interrupt input pins@32 pin Package
Include one non-maskable interrupt (NMI) input pin
Document Number: 002-05657 Rev.*A
Page 2 of 77
MB9B120J Series
Watchdog Timer (Two channels)
Clock Super Visor (CSV)
A watchdog timer can generate interrupts or a reset when a
time-out value is reached.
Clocks generated by built-in CR oscillators are used to
supervise abnormality of the external clocks.
This series consists of two different watchdogs, a Hardware
watchdog and a Software watchdog.
If external clock failure (clock stop) is detected, reset is
The "Hardware" watchdog timer is clocked by the built-in
Low-speed CR oscillator. Therefore, the "Hardware" watchdog
is active in any low-power consumption modes except RTC,
Stop modes.
If external frequency anomaly is detected, interrupt or reset is
asserted.
asserted.
Low-Voltage Consumption Detector (LVD)
This Series includes 2-stage monitoring of voltage on the VCC
pins. When the voltage falls below the voltage that has been
set, Low-Voltage Detector generates an interrupt or reset.
Clock and Reset
[Clocks]
Selectable from five clock sources (2 external oscillators, 2
built-in CR oscillator, and Main PLL).
Main Clock:
4 MHz to 48 MHz
Sub Clock:
32.768 kHz
Built-in High-speed CR Clock: 4 MHz
Built-in Low-speed CR Clock: 100 kHz
Main PLL Clock
[Resets]
LVD1: error reporting via interrupt
LVD2: auto-reset operation
Low-Power Consumption Mode
Four low-power consumption modes supported.
Sleep
Timer
RTC
Reset requests from INITX pin
Stop
Power on reset
Debug
Software reset
Serial Wire Debug Port (SW-DP)
Watchdog timers reset
Low-Voltage detection reset
Clock Super Visor reset
Unique ID
Unique value of the device (41-bit) is set.
Power Supply
Wide range voltage: VCC = 2.7 V to 5.5 V
Document Number: 002-05657 Rev.*A
Page 3 of 77
MB9B120J Series
Contents
1. Product Lineup .................................................................................................................................................................. 6
2. Packages ........................................................................................................................................................................... 7
3. Pin Assignment ................................................................................................................................................................. 8
4. List of Pin Functions....................................................................................................................................................... 10
5. I/O Circuit Type ............................................................................................................................................................... 18
6. Handling Precautions ..................................................................................................................................................... 22
6.1
Precautions for Product Design ................................................................................................................................... 22
6.2
Precautions for Package Mounting .............................................................................................................................. 23
6.3
Precautions for Use Environment ................................................................................................................................ 24
7. Handling Devices ............................................................................................................................................................ 25
8. Block Diagram ................................................................................................................................................................. 27
9. Memory Size .................................................................................................................................................................... 28
10. Memory Map .................................................................................................................................................................... 28
11. Pin Status in Each CPU State ........................................................................................................................................ 31
12. Electrical Characteristics ............................................................................................................................................... 36
12.1 Absolute Maximum Ratings ......................................................................................................................................... 36
12.2 Recommended Operating Conditions ......................................................................................................................... 38
12.3 DC Characteristics ...................................................................................................................................................... 39
12.3.1 Current Rating .............................................................................................................................................................. 39
12.3.2 Pin Characteristics ....................................................................................................................................................... 41
12.4 AC Characteristics ....................................................................................................................................................... 42
12.4.1 Main Clock Input Characteristics .................................................................................................................................. 42
12.4.2 Sub Clock Input Characteristics ................................................................................................................................... 43
12.4.3 Built-in CR Oscillation Characteristics .......................................................................................................................... 44
12.4.4 Operating Conditions of Main PLL (In the case of using main clock for input of Main PLL) ......................................... 45
12.4.5 Operating Conditions of Main PLL (In the case of using built-in High-speed CR for input clock of Main PLL) ............. 45
12.4.6 Reset Input Characteristics .......................................................................................................................................... 46
12.4.7 Power-on Reset Timing ................................................................................................................................................ 46
12.4.8 Base Timer Input Timing .............................................................................................................................................. 47
12.4.9 CSIO/UART Timing ...................................................................................................................................................... 48
12.4.10 External Input Timing ................................................................................................................................................ 56
12.4.11 Quadrature Position/Revolution Counter Timing ...................................................................................................... 57
12.4.12 I2C Timing ................................................................................................................................................................. 59
12.4.13 SWD Timing ............................................................................................................................................................. 60
12.5 12-bit A/D Converter .................................................................................................................................................... 61
12.6 Low-Voltage Detection Characteristics ........................................................................................................................ 64
12.6.1 Low-Voltage Detection Reset ....................................................................................................................................... 64
12.6.2 Interrupt of Low-Voltage Detection ............................................................................................................................... 65
12.7 Flash Memory Write/Erase Characteristics ................................................................................................................. 66
12.7.1 Write / Erase time......................................................................................................................................................... 66
12.7.2 Write cycles and data hold time ................................................................................................................................... 66
12.8 Return Time from Low-Power Consumption Mode ...................................................................................................... 67
12.8.1 Return Factor: Interrupt ................................................................................................................................................ 67
12.8.2 Return Factor: Reset .................................................................................................................................................... 69
Document Number: 002-05657 Rev.*A
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MB9B120J Series
13. Ordering Information ...................................................................................................................................................... 71
14. Package Dimensions ...................................................................................................................................................... 72
15. Major Changes ................................................................................................................................................................ 74
Document History ................................................................................................................................................................. 76
Document Number: 002-05657 Rev.*A
Page 5 of 77
MB9B120J Series
1. Product Lineup
Memory Size
Product name
MB9BF121J
On-chip Flash memory
On-chip SRAM
64 Kbytes
SRAM0
4 Kbytes
SRAM1
Total
4 Kbytes
8 Kbytes
Function
Product name
MB9BF121J
Pin count
32
Cortex-M3
72 MHz
2.7 V to 5.5 V
4ch.
4ch. (Max)
ch.0/ch.1: FIFO
ch.2/ch.5: No FIFO
CPU
Freq.
Power supply voltage range
DMAC
Multi-function Serial Interface
2
(UART/CSIO/I C)
Base Timer
(PWC/Reload timer/PWM/PPG)
A/D activation
compare
Input capture
MFFree-run timer
Timer
Output compare
Waveform generator
PPG
QPRC
8ch. (Max)
1ch.
4ch.
3ch.
6ch.
3ch.
3ch.
1 unit
1ch.
Dual Timer
1 unit
Real-Time Clock
Watchdog timer
External Interrupts
I/O ports
12-bit A/D converter
CSV (Clock Super Visor)
LVD (Low-Voltage Detector)
High-speed
Built-in CR
Low-speed
Debug Function
Unique ID
1 unit
1ch. (SW) + 1ch. (HW)
7 pins (Max) + NMI × 1
23 pins (Max)
8ch. (1 unit)
Yes
2ch.
4 MHz
100 kHz
SW-DP
Yes
Note: All signals of the peripheral function in each product cannot be allocated by limiting the pins of package.
It is necessary to use the port relocate function of the I/O port according to your function use.
See 12.Electrical Characteristics 12.4.AC Characteristics 12.4.3.Built-in CR Oscillation Characteristics for accuracy of
built-in CR.
Document Number: 002-05657 Rev.*A
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MB9B120J Series
2. Packages
Product name
MB9BF121J
Package
LQFP:
FPT-32P-M30 (0.8 mm pitch)
QFN:
LCC-32P-M73 (0.5 mm pitch)
: Supported
Note: See Package Dimensions for detailed information on each package.
Document Number: 002-05657 Rev.*A
Page 7 of 77
MB9B120J Series
3. Pin Assignment
FPT-32P-M30
P0F/NMIX/SUBOUT_0/CROUT_1/RTCCO_0
P04/SWO
P03/SWDIO
P01/SWCLK
AVRH
AVRL
VSS
VCC
32
31
30
29
28
27
26
25
(TOP VIEW)
P3A/RTO00_0/TIOA0_1/INT07_0/SUBOUT_2/RTCCO_2/FRCK0_0/SCK2_0
1
24
P21/AN14/SIN0_0/INT06_1/BIN1_1
P3B/RTO01_0/TIOA1_1/IC00_0/SOT2_0
2
23
P22/AN13/SOT0_0/TIOB7_1/ZIN1_1
P3C/RTO02_0/TIOA2_1/INT18_2/IC01_0/SIN2_0
3
22
P23/AN12/SCK0_0/TIOA7_1/AIN1_1/DTTI0X_1
P3D/RTO03_0/TIOA3_1/SCK5_1/AIN1_0/IC02_0
4
21
P15/AN05/SOT0_1/INT14_0/IC03_2
P3E/RTO04_0/TIOA4_1/INT19_2/SOT5_1/BIN1_0
5
20
P14/AN04/SIN0_1/INT03_1/IC02_2/SCK0_1
P3F/RTO05_0/TIOA5_1/SIN5_1/ZIN1_0
6
19
P13/AN03/SCK1_1/SUBOUT_1/IC01_2/RTCCO_1/ZIN1_2/TIOB6_2
VCC
7
18
P12/AN02/SOT1_1/IC00_2/BIN1_2/TIOA6_2
C
8
17
P11/AN01/SIN1_1/INT02_1/FRCK0_2/AIN1_2
9
10
11
12
13
14
15
16
VSS
PE2/X0
PE3/X1
INITX
DTTI0X_0/INT07_1/P46/X0A
INT14_2/P47/X1A
MD0
PE0/MD1
LQFP - 32
Note:
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins,
there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to
select the pin.
Document Number: 002-05657 Rev.*A
Page 8 of 77
MB9B120J Series
LCC-32P-M73
P0F/NMIX/SUBOUT_0/CROUT_1/RTCCO_0
P04/SWO
P03/SWDIO
P01/SWCLK
AVRH
AVRL
VSS
VCC
32
31
30
29
28
27
26
25
(TOP VIEW)
P3A/RTO00_0/TIOA0_1/INT07_0/SUBOUT_2/RTCCO_2/FRCK0_0/SCK2_0
1
24 P21/AN14/SIN0_0/INT06_1/BIN1_1
P3B/RTO01_0/TIOA1_1/IC00_0/SOT2_0
2
23 P22/AN13/SOT0_0/TIOB7_1/ZIN1_1
P3C/RTO02_0/TIOA2_1/INT18_2/IC01_0/SIN2_0
3
22 P23/AN12/SCK0_0/TIOA7_1/AIN1_1/DTTI0X_1
P3D/RTO03_0/TIOA3_1/SCK5_1/AIN1_0/IC02_0
4
P3E/RTO04_0/TIOA4_1/INT19_2/SOT5_1/BIN1_0
5
P3F/RTO05_0/TIOA5_1/SIN5_1/ZIN1_0
6
19 P13/AN03/SCK1_1/SUBOUT_1/IC01_2/RTCCO_1/ZIN1_2/TIOB6_2
VCC
7
18 P12/AN02/SOT1_1/IC00_2/BIN1_2/TIOA6_2
C
8
17 P11/AN01/SIN1_1/INT02_1/FRCK0_2/AIN1_2
21 P15/AN05/SOT0_1/INT14_0/IC03_2
QFN - 32
9
10
11
12
13
14
15
16
VSS
PE2/X0
PE3/X1
INITX
DTTI0X_0/INT07_1/P46/X0A
INT14_2/P47/X1A
MD0
PE0/MD1
20 P14/AN04/SIN0_1/INT03_1/IC02_2/SCK0_1
Note:
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins,
there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to
select the pin.
Document Number: 002-05657 Rev.*A
Page 9 of 77
MB9B120J Series
4. List of Pin Functions
List of Pin Numbers
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins,
there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to
select the pin.
Pin No
Pin name
I/O circuit type
Pin state type
P3A
RTO00_0
(PPG00_0)
FRCK0_0
INT07_0
1
F
K
F
J
F
K
F
J
F
K
TIOA0_1
SCK2_0
(SCL2_0)
SUBOUT_2
RTCCO_2
P3B
RTO01_0
(PPG00_0)
2
IC00_0
TIOA1_1
SOT2_0
(SDA2_0)
P3C
RTO02_0
(PPG02_0)
3
IC01_0
INT18_2
TIOA2_1
SIN2_0
P3D
RTO03_0
(PPG02_0)
IC02_0
4
TIOA3_1
SCK5_1
(SCL5_1)
AIN1_0
P3E
RTO04_0
(PPG04_0)
INT19_2
5
TIOA4_1
SOT5_1
(SDA5_1)
BIN1_0
Document Number: 002-05657 Rev.*A
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MB9B120J Series
Pin No
Pin name
I/O circuit type
Pin state type
P3F
RTO05_0
(PPG04_0)
6
TIOA5_1
F
J
SIN5_1
ZIN1_0
7
VCC
-
-
8
C
-
-
9
VSS
-
-
A
A
A
B
B
C
D
F
D
G
H
D
C
E
PE2
10
X0
PE3
11
X1
12
INITX
P46
X0A
13
DTTI0X_0
INT07_1
P47
14
X1A
INT14_2
15
MD0
PE0
16
MD1
P11
AN01
SIN1_1
17
*
M
*
L
G
INT02_1
FRCK0_2
AIN1_2
P12
AN02
18
SOT1_1
(SDA1_1)
G
TIOA6_2
IC00_2
BIN1_2
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MB9B120J Series
Pin No
Pin name
I/O circuit type
Pin state type
P13
AN03
SCK1_1
(SCL1_1)
19
SUBOUT_1
*
L
*
M
*
M
*
L
*
L
G
*
M
G
TIOB6_2
IC01_2
RTCCO_1
ZIN1_2
P14
AN04
SIN0_1
20
INT03_1
G
SCK0_1
(SCL0_1)
IC02_2
P15
AN05
21
SOT0_1
(SDA0_1)
G
INT14_0
IC03_2
P23
AN12
22
SCK0_0
(SCL0_0)
G
TIOA7_1
DTTI0X_1
AIN1_1
P22
AN13
23
SOT0_0
(SDA0_0)
G
TIOB7_1
ZIN1_1
P21
AN14
24
SIN0_0
INT06_1
BIN1_1
25
VCC
-
-
26
VSS
-
-
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Page 12 of 77
MB9B120J Series
Pin No
Pin name
I/O circuit type
Pin state type
27
AVRL
-
-
28
AVRH
-
-
E
I
E
I
E
I
E
H
P01
29
SWCLK
P03
30
SWDIO
P04
31
SWO
P0F
NMIX
32
SUBOUT_0
CROUT_1
RTCCO_0
*: 5 V tolerant I/O
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Page 13 of 77
MB9B120J Series
List of Pin Functions
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins,
there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to
select the pin.
Pin function
Pin name
Pin No
Function description
AN01
17
AN02
18
AN03
19
AN04
ADC
AN05
A/D converter analog input pin.
ANxx describes ADC ch.xx.
20
21
AN12
22
AN13
23
AN14
24
Base Timer 0
TIOA0_1
Base timer ch.0 TIOA pin
1
Base Timer 1
TIOA1_1
Base timer ch.1 TIOA pin
2
Base Timer 2
TIOA2_1
Base timer ch.2 TIOA pin
3
Base Timer 3
TIOA3_1
Base timer ch.3 TIOA pin
4
Base Timer 4
TIOA4_1
Base timer ch.4 TIOA pin
5
Base Timer 5
TIOA5_1
Base timer ch.5 TIOA pin
6
TIOA6_2
Base timer ch.6 TIOA pin
18
TIOB6_2
Base timer ch.6 TIOB pin
19
TIOA7_1
Base timer ch.7 TIOA pin
22
TIOB7_1
Base timer ch.7 TIOB pin
23
SWCLK
Serial wire debug interface clock input pin
29
SWDIO
Serial wire debug interface data input / output pin
30
SWO
Serial wire viewer output pin
31
INT02_1
External interrupt request 02 input pin
17
INT03_1
External interrupt request 03 input pin
20
INT06_1
External interrupt request 06 input pin
24
Base Timer 6
Base Timer 7
Debugger
INT07_0
1
External interrupt request 07 input pin
External
Interrupt
INT07_1
13
INT14_0
21
External interrupt request 14 input pin
INT14-2
14
INT18_2
External interrupt request 18 input pin
3
INT19_2
External interrupt request 19 input pin
5
NMIX
Non-Maskable Interrupt input pin
32
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MB9B120J Series
Pin function
Pin name
Pin No
Function description
P01
29
P03
30
General-purpose I/O port 0
P04
31
P0F
32
P11
17
P12
18
P13
19
P14
20
P15
21
P21
24
P22
GPIO
General-purpose I/O port 1
General-purpose I/O port 2
23
P23
22
P3A
1
P3B
2
P3C
3
General-purpose I/O port 3
P3D
4
P3E
5
P3F
6
P46
13
General-purpose I/O port 4
P47
14
PE0
16
PE2
General-purpose I/O port E
PE3
10
11
SIN0_0
24
Multi-function serial interface ch.0 input pin
SIN0_1
Multi-function Serial 0
SOT0_0
(SDA0_0)
SOT0_1
(SDA0_1)
SCK0_0
(SCL0_0)
SCK0_1
(SCL0_1)
SIN1_1
Multi-function Serial 1
SOT1_1
(SDA1_1)
SCK1_1
(SCL1_1)
Document Number: 002-05657 Rev.*A
20
Multi-function serial interface ch.0 output pin.
This pin operates as SOT0 when it is used in a UART/CSIO/LIN (operation
2
modes 0 to 3) and as SDA0 when it is used in an I C (operation mode 4).
Multi-function serial interface ch.0 clock I/O pin.
This pin operates as SCK0 when it is used in a CSIO (operation mode 2) and
2
as SCL0 when it is used in an I C (operation mode 4).
Multi-function serial interface ch.0 clock I/O pin.
This pin operates as SCK0 when it is used in a CSIO (operation mode 2) and
2
as SCL0 when it is used in an I C (operation mode 4).
Multi-function serial interface ch.1 input pin
Multi-function serial interface ch.1 output pin.
This pin operates as SOT1 when it is used in a UART/CSIO/LIN (operation
2
modes 0 to 3) and as SDA1 when it is used in an I C (operation mode 4).
Multi-function serial interface ch.1 clock I/O pin.
This pin operates as SCK1 when it is used in a CSIO (operation mode 2) and
2
as SCL1 when it is used in an I C (operation mode 4).
23
21
22
20
17
18
19
Page 15 of 77
MB9B120J Series
Pin function
Pin name
SIN2_0
Multi-function Serial 2
SOT2_0
(SDA2_0)
SCK2_0
(SCL2_0)
SIN5_1
Multi-function Serial 5
SOT5_1
(SDA5_1)
SCK5_1
(SCL5_1)
DTTI0X_0
DTTI0X_1
Pin No
Function description
Multi-function serial interface ch.2 input pin
Multi-function serial interface ch.2 output pin.
This pin operates as SOT2 when it is used in a UART/CSIO/LIN (operation
2
modes 0 to 3) and as SDA2 when it is used in an I C (operation mode 4).
Multi-function serial interface ch.2 clock I/O pin.
This pin operates as SCK2 when it is used in a CSIO (operation mode 2) and
2
as SCL2 when it is used in an I C (operation mode 4).
Multi-function serial interface ch.5 input pin
Multi-function serial interface ch.5 output pin.
This pin operates as SOT5 when it is used in a UART/CSIO/LIN (operation
2
modes 0 to 3) and as SDA5 when it is used in an I C (operation mode 4).
Multi-function serial interface ch.5 clock I/O pin.
This pin operates as SCK5 when it is used in a CSIO (operation mode 2) and
2
as SCL5 when it is used in an I C (operation mode 4).
Input signal of waveform generator to control outputs RTO00 to RTO05 of
Multi-function timer 0.
FRCK0_0
3
2
1
6
5
4
13
22
1
16-bit free-run timer ch.0 external clock input pin
FRCK0_2
17
IC00_0
2
IC00_2
18
IC01_0
IC01_2
Multi-function Timer 0
3
16-bit input capture input pin of Multi-function timer 0.
ICxx describes channel number.
19
IC02_0
4
IC02_2
20
IC03_2
RTO00_0
(PPG00_0)
RTO01_0
(PPG00_0)
RTO02_0
(PPG02_0)
RTO03_0
(PPG02_0)
RTO04_0
(PPG04_0)
RTO05_0
(PPG04_0)
Document Number: 002-05657 Rev.*A
21
Waveform generator output pin of Multi-function timer 0.
This pin operates as PPG00 when it is used in PPG0 output mode.
Waveform generator output pin of Multi-function timer 0.
This pin operates as PPG00 when it is used in PPG0 output mode.
Waveform generator output pin of Multi-function timer 0.
This pin operates as PPG02 when it is used in PPG0 output mode.
Waveform generator output pin of Multi-function timer 0.
This pin operates as PPG02 when it is used in PPG0 output mode.
Waveform generator output pin of Multi-function timer 0.
This pin operates as PPG04 when it is used in PPG0 output mode.
Waveform generator output pin of Multi-function timer 0.
This pin operates as PPG04 when it is used in PPG0 output mode.
1
2
3
4
5
6
Page 16 of 77
MB9B120J Series
Pin function
Pin name
AIN1_0
AIN1_1
4
QPRC ch.1 AIN input pin
AIN1_2
BIN1_1
22
17
BIN1_0
Quadrature Position/
Revolution Counter
Pin No
Function description
5
QPRC ch.1 BIN input pin
24
BIN1_2
18
ZIN1_0
6
ZIN1_1
QPRC ch.1 ZIN input pin
23
ZIN1_2
19
RTCCO_0
32
RTCCO_1
0.5 seconds pulse output pin of Real-time clock
19
RTCCO_2
1
SUBOUT_0
32
Real-time clock
SUBOUT_1
Sub clock output pin
SUBOUT_2
19
1
INITX
External Reset Input pin.
A reset is valid when INITX="L".
12
MD0
Mode 0 pin.
During normal operation, MD0="L" must be input. During serial programming
to Flash memory, MD0="H" must be input.
15
MD1
Mode 1 pin.
During serial programming to Flash memory, MD1="L" must be input.
16
VCC
Analog/Digital Power supply Pin
7
VCC
Analog/Digital Power supply Pin
25
VSS
Analog/Digital GND Pin
9
VSS
Analog/Digital GND Pin
26
X0
Main clock (oscillation) input pin
10
X0A
Sub clock (oscillation) input pin
13
X1
Main clock (oscillation) I/O pin
11
X1A
Sub clock (oscillation) I/O pin
14
CROUT_1
Built-in High-speed CR-osc clock output port
32
Analog
POWER
AVRH
A/D converter analog reference voltage input pin
28
Analog
GND
AVRL
A/D converter analog reference voltage input pin
27
C pin
C
Power supply stabilization capacity pin
8
RESET
Mode
POWER
GND
CLOCK
Document Number: 002-05657 Rev.*A
Page 17 of 77
MB9B120J Series
5. I/O Circuit Type
Type
Circuit
Remarks
It is possible to select the main
oscillation / GPIO function
Pull-up
When the main oscillation is selected.
resistor
P-ch
P-ch
Digital output
X1A
• Oscillation feedback resistor
: Approximately 1 MΩ
• With standby mode control
When the GPIO is selected.
N-ch
Digital output
R
Pull-up resistor control
•
•
•
•
•
CMOS level output.
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50 kΩ
• IOH= -4 mA, IOL= 4 mA
Digital input
Standby mode control
Clock input
Feedback
A
resistor
Standby mode control
Digital input
Standby mode control
Pull-up
resistor
R
P-ch
P-ch
Digital output
N-ch
Digital output
X0A
Pull-up resistor control
• CMOS level hysteresis input
• Pull-up resistor
: Approximately 50 kΩ
Pull-up resistor
B
Digital input
Document Number: 002-05657 Rev.*A
Page 18 of 77
MB9B120J Series
Type
Circuit
Remarks
Digital input
C
• Open drain output
• CMOS level hysteresis input
Digital output
N-ch
It is possible to select the sub
oscillation / GPIO function
Pull-up
When the sub oscillation is selected.
resistor
P-ch
P-ch
Digital output
X1A
• Oscillation feedback resistor
: Approximately 5 MΩ
• With standby mode control
When the GPIO is selected.
N-ch
Digital output
R
Pull-up resistor control
•
•
•
•
•
CMOS level output.
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50 kΩ
• IOH= -4 mA, IOL= 4 mA
Digital input
Standby mode control
Clock input
Feedback
D
resistor
Standby mode control
Digital input
Standby mode control
Pull-up
resistor
R
P-ch
P-ch
Digital output
N-ch
Digital output
X0A
Pull-up resistor control
Document Number: 002-05657 Rev.*A
Page 19 of 77
MB9B120J Series
Type
Circuit
Remarks
•
•
•
•
•
P-ch
E
P-ch
N-ch
Digital output
CMOS level output
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50 kΩ
• IOH= -4 mA, IOL= 4 mA
• +B input is available
Digital output
R
Pull-up resistor control
Digital input
Standby mode control
•
•
•
•
•
P-ch
P-ch
Digital output
CMOS level output
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50 kΩ
• IOH= -12 mA, IOL= 12 mA
• When this pin is used as an I2C pin,
the digital output
P-ch transistor is always off
• +B input is available
F
N-ch
Digital output
R
Pull-up resistor control
Digital input
Standby mode control
Document Number: 002-05657 Rev.*A
Page 20 of 77
MB9B120J Series
Type
Circuit
P-ch
P-ch
N-ch
Remarks
Digital output
Digital output
G
R
•
•
•
•
•
•
•
•
CMOS level output
CMOS level hysteresis input
With input control
Analog input
5 V tolerant
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50 kΩ
• IOH= -4 mA, IOL= 4 mA
• Available to control of PZR registers.
• When this pin is used as an I2C pin,
the digital output
P-ch transistor is always off
Pull-up resistor control
Digital input
Standby mode control
Analog input
Input control
CMOS level hysteresis input
Mode input
H
Document Number: 002-05657 Rev.*A
Page 21 of 77
MB9B120J Series
6. Handling Precautions
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in
which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to
minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices.
6.1
Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of
certain established limits, called absolute maximum ratings. Do not exceed these ratings.
Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical
characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely
affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users
considering application outside the listed conditions are advised to contact their sales representative beforehand.
Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output
functions.
1. Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device,
and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at
the design stage.
2. Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows.
Such conditions if present for extended periods of time can damage the device.
Therefore, avoid this type of connection.
3. Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be
connected through an appropriate resistance to a power supply pin or ground pin.
Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally
high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of
several hundred mA to flow continuously at the power supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or
damage from high heat, smoke or flame. To prevent this from happening, do the following:
1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal
noise, surge levels, etc.
2. Be sure that abnormal current flows do not occur during the power-on sequence.
Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic
interference, etc. Customers are requested to observe applicable regulations and standards in the design of products.
Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
Document Number: 002-05657 Rev.*A
Page 22 of 77
MB9B120J Series
Precautions Related to Usage of Devices
Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office
equipment, industrial, communications, and measurement equipment, personal or household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as
aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.)
are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from
such use without prior approval.
6.2
Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you
should only mount under Cypress's recommended conditions. For detailed information about mount conditions, contact your sales
representative.
Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or
mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow
soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected
to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress
recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact
deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be
verified before mounting.
Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed
or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections
caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of
mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended
conditions.
Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength
may be reduced under some conditions of use.
Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of
moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing
moisture resistance and causing packages to crack. To prevent, do the following:
1. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in
locations where temperature changes are slight.
2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C
and 30°C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
3. When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica
gel desiccant. Devices should be sealed in their aluminum laminate bags for storage.
4. Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended
conditions for baking.
Condition: 125°C/24 h
Document Number: 002-05657 Rev.*A
Page 23 of 77
MB9B120J Series
Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions:
1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be
needed to remove electricity.
2. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level
of 1 MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is
recommended.
4. Ground all fixtures and instruments, or protect with anti-static measures.
5. Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies.
6.3
Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described above.
For reliable performance, do the following:
1. Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are
anticipated, consider anti-humidity processing.
2. Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases,
use anti-static measures or processing to prevent discharges.
3. Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If
you use devices in such conditions, consider ways to prevent such exposure or to protect the devices.
4. Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide
shielding as appropriate.
5. Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices
begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Cypress products in other special environmental conditions should consult with sales
representatives.
Document Number: 002-05657 Rev.*A
Page 24 of 77
MB9B120J Series
7. Handling Devices
Power supply pins
In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to
prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground
lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the
ground level, and to conform to the total output current rating.
Moreover, connect the current supply source with each Power supply pin and GND pin of this device at low impedance. It is also
advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between each Power supply pin and
GND pin, between AVRH pin and AVRL pin near this device.
Stabilizing supply voltage
A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the recommended
operating conditions of the VCC power supply voltage. As a rule, with voltage stabilization, suppress the voltage fluctuation so that
the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC
value in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a
momentary fluctuation on switching the power supply.
Crystal oscillator circuit
Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1,
X0A/X1A pins, the crystal oscillator, and the bypass capacitor to ground are located as close to the device as possible.
It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by
ground plane as this is expected to produce stable operation.
Evaluate oscillation of your using crystal oscillator by your mount board.
Sub crystal oscillator
This series sub oscillator circuit is low gain to keep the low current consumption. The crystal oscillator to fill the following conditions
is recommended for sub crystal oscillator to stabilize the oscillation.
Surface mount type
Size : More than 3.2 mm × 1.5 mm
Load capacitance: Approximately 6 pF to 7 pF
Lead type
Load capacitance : Approximately 6 pF to 7 pF
Using an external clock
When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input the clock to X0. X1(PE3)
can be used as a general-purpose I/O port.
Similarly, when using an external clock as an input of the sub clock, set X0A/X1A to the external clock input, and input the clock to
X0A. X1A (P47) can be used as a general-purpose I/O port.
Example of Using an External Clock
Device
X0(X0A)
Can be used as
general-purpose
I/O ports.
Document Number: 002-05657 Rev.*A
X1(PE3),
X1A (P47)
Set as
External clock
input
Page 25 of 77
MB9B120J Series
Handling when using Multi-function serial pin as I2C pin
If it is using the multi-function serial pin as I2C pins, P-ch transistor of digital output is always disabled. However, I2C pins need to
keep the electrical characteristic like other pins and not to connect to the external I2C bus system with power OFF.
C Pin
This series contains the regulator. Be sure to connect a smoothing capacitor (CS) for the regulator between the C pin and the GND
pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor.
However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F
characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to use
by evaluating the temperature characteristics of a capacitor.
A smoothing capacitor of about 4.7μF would be recommended for this series.
C
Device
CS
VSS
GND
Mode pins (MD0)
Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance stays
low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection
impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is
because of preventing the device erroneously switching to test mode due to noise.
Notes on power-on
Turn power on/off in the following order or at the same time.
Turning on : VCC → AVRH
Turning off : AVRH → VCC
Serial Communication
There is a possibility to receive wrong data due to the noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end.
If an error is detected, retransmit the data.
Differences in features among the products with different memory sizes and between Flash memory
products and MASK products
The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics among
the products with different memory sizes and between Flash memory products and MASK products are different because chip
layout and memory structures are different.
If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics.
Pull-Up function of 5 V tolerant I/O
Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5 V tolerant I/O.
Document Number: 002-05657 Rev.*A
Page 26 of 77
MB9B120J Series
8. Block Diagram
MB9BF121J
SWCLK,
SWDIO
SWO
SRAM0
4 Kbyte
SW-DP
ROM Table
Multi-layer AHB (Max 72MHz)
Cortex-M3 Core I
@72MHz(Max)
D
NVIC
Sys
AHB-APB Bridge:
APB0(Max 40MHz)
Dual-Timer
WatchDog Timer
(Software)
INITX
Clock Reset
Generator
WatchDog Timer
(Hardware)
SRAM1
4 Kbyte
Flash I/F
On-Chip Flash
64 Kbyte
Security
DMAC
4ch.
CSV
CLK
X0A
X1A
Main
Osc
Sub
Osc
PLL
CR
4MHz
Source Clock
AHB-AHB
Bridge
X0
X1
CR
100kHz
CROUT
TIOAx
TIOBx
AINx
BINx
ZINx
Base Timer
16-bit 8ch./
32-bit 4ch.
QPRC
1ch.
A/D Activation
Compare 1ch.
IC0x
FRCKx
16-bit Input Capture
4ch.
16-bit Free-run Timer
3ch.
16-bit Output
Compare 6ch.
DTTI0X
RTO0x
Power On
Reset
Unit 0
Waveform Generator
3ch.
16-bit PPG
3ch.
Multi-function Timer
Document Number: 002-05657 Rev.*A
AHB-APB Bridge : APB2 (Max 40MHz)
ANxx
12-bit A/D Converter
AHB-APB Bridge : APB1 (Max 40MHz)
AVRH,
AVRL
LVD Ctrl
LVD
IRQ-Monitor
Regulator
C
RTCCO,
SUBOUT
Real-Time Clock
External Interrupt
Controller
7-pin + NMI
INTx
NMIX
MODE-Ctrl
MD0,
MD1
GPIO
P0x,
P1x,
.
.
.
Pxx
Multi-function Serial I/F
4ch.
(with FIFO ch.0/ch.1)
PIN-Function-Ctrl
SCKx
SINx
SOTx
Page 27 of 77
MB9B120J Series
9. Memory Size
See Memory size in Product Lineup to confirm the memory size.
10. Memory Map
Memory Map (1)
Peripherals Area
0x41FF_FFFF
Reserved
0xFFFF_FFFF
Reserved
0xE010_0000
0xE000_0000
Cortex-M3 Private
Peripherals
0x4006_1000
0x4006_0000
DMAC
Reserved
Reserved
0x4003_C000
0x4003_B000
0x4003_9000
0x4003_8000
0x4400_0000
0x4200_0000
0x4000_0000
32Mbytes
Bit band alias
0x4003_6000
0x4003_5000
Peripherals
0x4003_4000
0x4003_3000
0x4003_2000
Reserved
0x4003_1000
0x4003_0000
32Mbytes
Bit band alias
0x4002_F000
0x4002_E000
Reserved
0x4002_8000
0x2400_0000
0x2200_0000
0x2008_0000
0x2000_0000
0x1FF8_0000
0x0010_0008
See "lMemory map(2)" for
the memory size details.
0x0010_0000
0x4002_7000
SRAM1
SRAM0
Reserved
0x4002_6000
0x4002_5000
0x4002_4000
Security/CR Trim
MFS
Reserved
LVD/DS mode
Reserved
GPIO
Reserved
Int-Req.Read
EXTI
Reserved
CR Trim
Reserved
A/DC
QPRC
Base Timer
PPG
Reserved
0x4002_1000
0x4002_0000
Flash
MFT unit0
Reserved
0x4001_5000
0x0000_0000
0x4001_3000
0x4001_2000
0x4001_1000
0x4001_0000
0x4000_1000
0x4000_0000
Document Number: 002-05657 Rev.*A
RTC
Reserved
Dual Timer
Reserved
SW WDT
HW WDT
Clock/Reset
Reserved
Flash I/F
Page 28 of 77
MB9B120J Series
Memory Map (2)
MB9BF121J
0x2008_0000
Reserved
0x2000_1000
0x2000_0000
0x1FFF_F000
SRAM1
4Kbytes
SRAM0
4Kbytes
Reserved
0x0010_0008
0x0010_0004
0x0010_0000
CR trimming
Security
Reserved
0x0000_FFF8
SA0-7 (8KBx8)
Flash 64Kbytes *
0x0000_0000
*: See “MB9A420L/120L/MB9B120J Series Flash Programming Manual” to confirm the detail of Flash memory.
Document Number: 002-05657 Rev.*A
Page 29 of 77
MB9B120J Series
Peripheral Address Map
Start address
0x4000_0000
End address
Bus
0x4000_0FFF
Peripherals
Flash memory I/F register
AHB
0x4000_1000
0x4000_FFFF
Reserved
0x4001_0000
0x4001_0FFF
Clock/Reset Control
0x4001_1000
0x4001_1FFF
Hardware Watchdog timer
0x4001_2000
0x4001_2FFF
Software Watchdog timer
APB0
0x4001_3000
0x4001_4FFF
Reserved
0x4001_5000
0x4001_5FFF
Dual Timer
0x4001_6000
0x4001_FFFF
Reserved
0x4002_0000
0x4002_0FFF
Multi-function timer unit0
0x4002_1000
0x4002_3FFF
Reserved
0x4002_4000
0x4002_4FFF
PPG
0x4002_5000
0x4002_5FFF
Base Timer
0x4002_6000
0x4002_6FFF
0x4002_7000
0x4002_7FFF
A/D Converter
0x4002_8000
0x4002_DFFF
Reserved
0x4002_E000
0x4002_EFFF
Built-in CR trimming
0x4002_F000
0x4002_FFFF
Reserved
0x4003_0000
0x4003_0FFF
External Interrupt Controller
0x4003_1000
0x4003_1FFF
Interrupt Request Batch-Read Function
0x4003_2000
0x4003_2FFF
Reserved
0x4003_3000
0x4003_3FFF
GPIO
0x4003_4000
0x4003_4FFF
Reserved
0x4003_5000
0x4003_57FF
0x4003_5800
0x4003_7FFF
Reserved
0x4003_8000
0x4003_8FFF
Multi-function serial Interface
0x4003_9000
0x4003_AFFF
Reserved
0x4003_B000
0x4003_BFFF
Real-time clock
0x4003_C000
0x4003_FFFF
Reserved
0x4004_0000
0x4005_FFFF
Reserved
0x4006_0000
0x4006_0FFF
0x4006_1000
0x41FF_FFFF
Document Number: 002-05657 Rev.*A
APB1
APB2
AHB
Quadrature Position/Revolution Counter
Low-Voltage Detector
DMAC register
Reserved
Page 30 of 77
MB9B120J Series
11. Pin Status in Each CPU State
The terms used for pin status have the following meanings.
INITX=0
This is the period when the INITX pin is the L level.
INITX=1
This is the period when the INITX pin is the H level.
SPL=0
This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 0.
SPL=1
This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 1.
Input enabled
Indicates that the input function can be used.
Internal input fixed at 0
This is the status that the input function cannot be used. Internal input is fixed at L.
Hi-Z
Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state.
Setting disabled
Indicates that the setting is disabled.
Maintain previous state
Maintains the state that was immediately prior to entering the current mode.
If a built-in peripheral function is operating, the output follows the peripheral function.
If the pin is being used as a port, that output is maintained.
Analog input is enabled
Indicates that the analog input is enabled.
Document Number: 002-05657 Rev.*A
Page 31 of 77
MB9B120J Series
Pin status type
List of Pin Status
Function group
Power-on
reset or
low-voltage
detection
state
Power supply
unstable
-
INITX
input state
Device internal
reset state
Power supply stable
INITX = 0
-
INITX = 1
-
Run mode or
SLEEP mode
state
Power supply
stable
INITX = 1
-
TIMER mode,
RTC mode or
STOP mode state
Power supply stable
INITX = 1
SPL = 0
SPL = 1
GPIO selected
Setting
disabled
Setting
disabled
Setting disabled
Maintain previous
state
Maintain
previous state
Hi-Z / Internal
input fixed at "0"
Main crystal
oscillator input pin
/External main
clock input
selected
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
GPIO selected
Setting
disabled
Setting
disabled
Setting disabled
Maintain previous
state
Maintain
previous state
Hi-Z / Internal
input fixed at 0
External main
clock input
selected
Setting
disabled
Setting
disabled
Setting disabled
Maintain previous
state
Maintain
previous state
Hi-Z / Internal
input fixed at 0
Main crystal
oscillator output
pin
Hi-Z /
Internal input
fixed at 0
or Input enable
Hi-Z / Internal
input fixed at 0
Hi-Z / Internal
input fixed at 0
Maintain previous
state / When
1
oscillation stops* ,
Hi-Z /
Internal input
fixed at 0
Maintain
previous state /
When oscillation
1
stops* ,
Hi-Z /
Internal input
fixed at 0
Maintain
previous state /
When oscillation
1
stops* ,
Hi-Z /
Internal input
fixed at 0
C
INITX input pin
Pull-up / Input
enabled
Pull-up / Input
enabled
Pull-up / Input
enabled
Pull-up / Input
enabled
Pull-up / Input
enabled
Pull-up / Input
enabled
D
Mode input pin
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
A
B
Document Number: 002-05657 Rev.*A
Page 32 of 77
Pin status type
MB9B120J Series
Function group
Power-on
reset or
low-voltage
detection
state
Power supply
unstable
-
INITX
input state
Device internal
reset state
Power supply stable
INITX = 0
-
INITX = 1
-
Run mode or
SLEEP mode
state
Power supply
stable
INITX = 1
-
TIMER mode,
RTC mode or
STOP mode state
Power supply stable
INITX = 1
SPL = 0
SPL = 1
Mode input pin
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
GPIO selected
Setting
disabled
Setting
disabled
Setting disabled
Maintain previous
state
Maintain
previous state
Hi-Z /
Input enabled
GPIO selected
Setting
disabled
Setting
disabled
Setting disabled
Maintain previous
state
Maintain
previous state
Hi-Z / Internal
input fixed at 0
External interrupt
enabled selected
Setting
disabled
Setting
disabled
Setting disabled
Maintain previous
state
Maintain
previous state
Maintain
previous state
Sub crystal
oscillator input pin
/External sub clock
input selected
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
GPIO selected
Setting
disabled
Setting
disabled
Setting disabled
Maintain previous
state
Maintain
previous state
Hi-Z / Internal
input fixed at 0
External sub clock
input selected
Setting
disabled
Setting
disabled
Setting disabled
Maintain previous
state
Maintain
previous state
Hi-Z / Internal
input fixed at 0
Sub crystal
oscillator output
pin
Hi-Z /
Internal input
fixed at 0
or Input enable
Maintain previous
state
Maintain
previous state /
When oscillation
2
stops* ,
Hi-Z / Internal
input fixed at 0
Maintain
previous state /
When oscillation
2
stops* ,
Hi-Z / Internal
input fixed at 0
E
F
G
Document Number: 002-05657 Rev.*A
Hi-Z / Internal
input fixed at 0
Hi-Z / Internal
input fixed at 0
Page 33 of 77
Pin status type
MB9B120J Series
Function group
NMIX selected
H
Resource other
than above
selected
Power-on
reset or
low-voltage
detection
state
Power supply
unstable
Setting
disabled
INITX
input state
Device internal
reset state
Power supply stable
INITX = 0
Setting
disabled
INITX = 1
-
Run mode or
SLEEP mode
state
Power supply
stable
INITX = 1
-
TIMER mode,
RTC mode or
STOP mode state
Power supply stable
INITX = 1
SPL = 0
Setting disabled
Hi-Z
Hi-Z /
Input enabled
Hi-Z /
Input enabled
Hi-Z
Pull-up / Input
enabled
Pull-up / Input
enabled
Maintain previous
state
Maintain
previous state
SPL = 1
Maintain
previous state
Hi-Z / Internal
input fixed at 0
GPIO selected
Serial wire debug
selected
Maintain
previous state
Maintain previous
state
I
GPIO selected
Setting
disabled
Setting
disabled
Setting disabled
Hi-Z
Hi-Z /
Input enabled
Hi-Z /
Input enabled
Setting
disabled
Setting
disabled
Setting disabled
Maintain
previous state
Hi-Z / Internal
input fixed at 0
Resource selected
J
Maintain previous
state
Maintain
previous state
Hi-Z / Internal
input fixed at 0
GPIO selected
External interrupt
enabled selected
K
Resource other
than above
selected
Maintain
previous state
Maintain previous
state
Maintain
previous state
Hi-Z
Hi-Z /
Input enabled
Hi-Z /
Input enabled
Hi-Z / Internal
input fixed at 0
Hi-Z
Hi-Z /
Internal input
fixed at 0 /
Analog input
enabled
Hi-Z /
Internal input
fixed at 0 /
Analog input
enabled
Hi-Z /
Internal input
fixed at 0 /
Analog input
enabled
Hi-Z /
Internal input
fixed at 0 /
Analog input
enabled
Hi-Z /
Internal input
fixed at 0 /
Analog input
enabled
Setting
disabled
Setting
disabled
Setting disabled
Maintain previous
state
Maintain
previous state
Hi-Z / Internal
input fixed at 0
GPIO selected
Analog input
selected
L
Resource other
than above
selected
GPIO selected
Document Number: 002-05657 Rev.*A
Page 34 of 77
Pin status type
MB9B120J Series
Function group
Power-on
reset or
low-voltage
detection
state
Power supply
unstable
-
Analog input
selected
Hi-Z
INITX
input state
Device internal
reset state
Power supply stable
INITX = 0
-
INITX = 1
-
Hi-Z /
Internal input
fixed at 0 /
Analog input
enabled
Hi-Z /
Internal input
fixed at 0 /
Analog input
enabled
Run mode or
SLEEP mode
state
TIMER mode,
RTC mode or
STOP mode state
Power supply
stable
INITX = 1
-
Hi-Z /
Internal input
fixed at 0 /
Analog input
enabled
Power supply stable
INITX = 1
SPL = 0
SPL = 1
Hi-Z /
Internal input
fixed at 0 /
Analog input
enabled
Hi-Z /
Internal input
fixed at 0 /
Analog input
enabled
M
External interrupt
enabled selected
Resource other
than above
selected
Maintain
previous state
Setting
disabled
Setting
disabled
Setting disabled
Maintain previous
state
Maintain
previous state
Hi-Z / Internal
input fixed at 0
GPIO selected
*1: Oscillation is stopped at Sub Timer mode, Low-speed CR Timer mode, RTC mode, Stop mode.
*2: Oscillation is stopped at Stop mode.
Document Number: 002-05657 Rev.*A
Page 35 of 77
MB9B120J Series
12. Electrical Characteristics
12.1 Absolute Maximum Ratings
Parameter
1, 2
Power supply voltage* *
1, 3
Analog reference voltage* *
Input voltage*
VCC
AVRH
1
Rating
Symbol
VI
Min
VSS - 0.5
VSS - 0.5
VSS - 0.5
VSS - 0.5
Analog pin input voltage*
Output voltage*
1
1
Clamp maximum current
Clamp total maximum current
L level maximum output current*
L level average output current*
4
5
L level total maximum output current
6
L level total average output current*
H level maximum output current*
H level average output current*
4
5
H level total maximum output current
6
H level total average output current*
Power consumption
Storage temperature
VIA
VSS - 0.5
VO
VSS - 0.5
ICLAMP
Σ[ICLAMP]
-2
IOL
-
IOLAV
-
∑IOL
∑IOLAV
-
IOH
-
IOHAV
-
∑IOH
∑IOHAV
PD
TSTG
- 55
Max
Unit
Remarks
VSS + 6.5
VSS + 6.5
VCC + 0.5
(≤ 6.5 V)
VSS + 6.5
VCC + 0.5
(≤ 6.5 V)
VCC + 0.5
(≤ 6.5 V)
+2
+20
10
V
V
mA
mA
mA
*7
*7
4 mA type
20
4
12
100
50
- 10
mA
mA
mA
mA
mA
mA
12 mA type
4 mA type
12 mA type
- 20
-4
- 12
- 100
- 50
350
+ 150
mA
mA
mA
mA
mA
mW
°C
12 mA type
4 mA type
12 mA type
V
V
5 V tolerant
V
V
4 mA type
*1: These parameters are based on the condition that VSS = 0 V.
*2: VCC must not drop below VSS - 0.5 V.
*3: Ensure that the voltage does not to exceed VCC + 0.5 V, for example, when the power is turned on.
*4: The maximum output current is the peak value for a single pin.
*5: The average output is the average current for a single pin over a period of 100 ms.
*6: The total average output current is the average current for all pins over a period of 100 ms.
*7:
•
•
•
•
•
See List of Pin Functions and I/O Circuit Type about +B input available pin.
Use within recommended operating conditions.
Use at DC voltage (current) the +B input.
The +B signal should always be applied a limiting resistance placed between the +B signal and the device.
The value of the limiting resistance should be set so that when the +B signal is applied the input current to the device pin does
not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the device drive current is low, such as in the low-power consumption modes, the +B input potential may pass
through the protective diode and increase the potential at the VCC pin, and this may affect other devices.
• Note that if a +B signal is input when the device power supply is off (not fixed at 0 V), the power supply is provided from the
pins, so that incomplete operation may result.
• The following is a recommended circuit example (I/O equivalent circuit).
Document Number: 002-05657 Rev.*A
Page 36 of 77
MB9B120J Series
Protection Diode
VCC
VCC
P-ch
Limiting
+B input (0V to 16V)
resistor
N-ch
Digital output
Digital input
R
VCC
Analog input
WARNING:
Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or
temperature) in excess of absolute maximum ratings.
Do not exceed any of these ratings.
Document Number: 002-05657 Rev.*A
Page 37 of 77
MB9B120J Series
12.2 Recommended Operating Conditions
(VSS = AVRL = 0.0V)
Parameter
Power supply voltage
Analog reference voltage
Smoothing capacitor
Operating
temperature
FPT-32P-M30,
LCC-32P-M19
Symbol
VCC
AVRH
AVRL
CS
TA
Value
Conditions
When mounted on
four-layer
PCB
When mounted on
double-sided
single-layer
PCB
Min
2.7*
2.7
VSS
1
2
Max
Unit
5.5
VCC
VSS
10
V
V
V
μF
- 40
+ 105
°C
- 40
+ 85
°C
Remarks
For regulator*
1
*1: See C Pin in Handling Devices for the connection of the smoothing capacitor.
*2: In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage or more, instruction
execution and low voltage detection function by built-in High-speed CR (including Main PLL is used) or built-in Low-speed CR is
possible to operate only.
WARNING:
The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the
device's electrical characteristics are warranted when the device is operated under these conditions.
Any use of semiconductor devices will be under their recommended operating condition. Operation under any conditions other than
these conditions may adversely affect reliability of device and could result in device failure. No warranty is made with respect to any
use, operating conditions or combinations not represented on this data sheet. If you are considering application under any
conditions other than listed herein, please contact sales representatives beforehand.
Document Number: 002-05657 Rev.*A
Page 38 of 77
MB9B120J Series
12.3 DC Characteristics
12.3.1
Current Rating
(VCC = 2.7V to 5.5V, VSS = AVRL = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Pin
name
Conditions
PLL
Run mode
Run
mode
current
ICC
VCC
Sleep
mode
current
ICCS
High-speed
CR
Run mode
Sub
Run mode
Low-speed
CR
Run mode
PLL
Sleep mode
High-speed
CR
Sleep mode
Sub
Sleep mode
Low-speed
CR
Sleep mode
Typ
CPU : 72 MHz,
Peripheral : 36 MHz
Instruction on Flash
CPU:72 MHz,
Peripheral : the clock stops NOP
operation
Instruction on Flash
CPU : 72 MHz,
Peripheral : 36 MHz
Instruction on RAM
Value
Max
Unit
Remarks
27
35
mA
*1, *5
18
22
mA
*1, *5
23
29
mA
*1
2.2
3.1
mA
*1
CPU/ Peripheral : 32 kHz
Instruction on Flash
73
910
μA
*1, *6
CPU/ Peripheral : 100k Hz
Instruction on Flash
105
930
μA
*1
Peripheral : 36 MHz
17
20
mA
*1, *5
1.3
2.2
mA
*1
Peripheral : 32 kHz
64
890
μA
*1, *6
Peripheral : 100 kHz
80
910
μA
*1
CPU/ Peripheral : 4 MHz*
Instruction on Flash
Peripheral : 4 MHz*
2
2
*1: When all ports are fixed.
*2: When setting it to 4 MHz by trimming.
*3: TA = +25°C, VCC = 5.5 V
*4: TA = +105°C, VCC = 5.5 V
*5: When using the crystal oscillator of 4 MHz (Including the current consumption of the oscillation circuit)
*6: When using the crystal oscillator of 32 kHz (Including the current consumption of the oscillation circuit)
Document Number: 002-05657 Rev.*A
Page 39 of 77
MB9B120J Series
(VCC = 2.7V to 5.5V, VSS = AVRL = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Pin
name
Conditions
TA = + 25°C,
When LVD is off
TA = + 105°C,
When LVD is off
TA = + 25°C,
When LVD is off
TA = + 105°C,
When LVD is off
TA = + 25°C,
When LVD is off
TA = + 105°C,
When LVD is off
TA = + 25°C,
When LVD is off
TA = + 105°C,
When LVD is off
Main
Timer mode
ICCT
Timer
mode
current
Sub
Timer mode
ICCT
VCC
RTC
mode
current
ICCR
Stop
mode
current
ICCH
Typ
RTC mode
Stop mode
Value
Max
Unit
Remarks
3.5
4.1
mA
*1
-
4.6
mA
*1
15
45
μA
*1
-
740
μA
*1
13
39
μA
*1
-
580
μA
*1
12
33
μA
*1
-
550
μA
*1
*1: When all ports are fixed.
*2: VCC = 5.5 V
*3: When using the crystal oscillator of 4 MHz (Including the current consumption of the oscillation circuit)
*4: When using the crystal oscillator of 32 kHz (Including the current consumption of the oscillation circuit)
LVD current
(VCC = 2.7V to 5.5V, VSS = AVRL = 0V, TA = - 40°C to + 105°C)
Parameter
Low-Voltage
detection circuit
(LVD) power supply
current
Symbol
ICCLVD
Pin
name
VCC
Value
Conditions
At operation
for reset
VCC = 5.5V
At operation
for interrupt
VCC = 5.5 V
Typ
Max
Unit
Remarks
0.13
0.3
μA
At not detect
0.13
0.3
μA
At not detect
Flash memory current
(VCC = 2.7V to 5.5V, VSS = AVRL = 0V, TA = - 40°C to + 105°C)
Parameter
Flash
memory
write/erase
current
Symbol
ICCFLASH
Pin
name
VCC
Value
Conditions
At Write/Erase
Typ
9.5
Max
11.2
Unit
Remarks
mA
A/D convertor current
(VCC = 2.7V to 5.5V, VSS = AVRL = 0V, TA = - 40°C to + 105°C)
Parameter
Power supply
current
Reference power
supply current
Symbol
ICCAD
ICCAVRH
Document Number: 002-05657 Rev.*A
Pin
name
VCC
AVRH
Value
Conditions
Typ
Max
Unit
At operation
0.7
0.9
mA
At operation
AVRH = 5.5 V
1.1
1.97
mA
At stop
AVRH = 5.5 V
0.1
1.7
μA
Remarks
Page 40 of 77
MB9B120J Series
12.3.2
Pin Characteristics
(VCC = 2.7V to 5.5V, VSS = AVRL = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
H level input
voltage
(hysteresis
input)
VIHS
L level input
voltage
(hysteresis
input)
VILS
Pin name
CMOS
hysteresis input
pin, MD0, MD1
5 V tolerant input
pin
CMOS
hysteresis input
pin, MD0, MD1
5 V tolerant input
pin
4 mA type
H level
output voltage
VOH
12 mA type
4 mA type
L level
output voltage
VOL
12 mA type
Input leak current
IIL
-
Pull-up resistance
value
RPU
Pull-up pin
Input capacitance
CIN
Other than VCC,
VSS,
AVRH,
AVRL
Document Number: 002-05657 Rev.*A
Conditions
Min
Value
Typ
Max
Unit
-
VCC × 0.8
-
VCC + 0.3
V
-
VCC × 0.8
-
VSS + 5.5
V
-
VSS - 0.3
-
VCC × 0.2
V
-
VSS - 0.3
-
VCC × 0.2
V
VCC - 0.5
-
VCC
V
VCC - 0.5
-
VCC
V
VSS
-
0.4
V
VSS
-
0.4
V
-5
-
+5
μA
VCC ≥ 4.5 V
33
50
90
VCC < 4.5 V
-
-
180
-
-
5
15
VCC ≥ 4.5 V,
IOH = - 4 mA
VCC < 4.5 V,
IOH = - 2 mA
VCC ≥ 4.5 V,
IOH = - 12 mA
VCC < 4.5 V,
IOH = - 8 mA
VCC ≥ 4.5 V,
IOL = 4 mA
VCC < 4.5 V,
IOL = 2 mA
VCC ≥ 4.5 V,
IOL = 12 mA
VCC < 4.5 V,
IOL = 8 mA
-
Remarks
kΩ
pF
Page 41 of 77
MB9B120J Series
12.4 AC Characteristics
12.4.1
Main Clock Input Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Input frequency
Pin
name
Symbol
fCH
X0,
X1
Value
Conditions
Min
Max
Unit
VCC ≥ 4.5 V
VCC < 4.5 V
4
4
48
20
MHz
When crystal oscillator is
connected
-
4
48
MHz
When using external
Clock
-
20.83
250
ns
Input clock cycle
tCYLH
Input clock pulse width
-
PWH/tCYLH,
PWL/tCYLH
45
55
%
Input clock rise time and
fall time
tCF,
tCR
-
-
5
ns
Internal operating
1
clock* frequency
Internal operating
1
clock* cycle time
Remarks
When using external
Clock
When using external
Clock
When using external
Clock
fCM
-
-
-
72
MHz
Master clock
fCC
-
-
-
72
MHz
Base clock (HCLK/FCLK)
fCP0
fCP1
-
-
-
40
40
MHz
MHz
APB0 bus clock*
2
APB1 bus clock*
fCP2
-
-
-
40
MHz
APB2 bus clock*
tCYCC
tCYCP0
tCYCP1
tCYCP2
-
-
13.8
-
ns
Base clock (HCLK/FCLK)
-
-
25
-
ns
APB0 bus clock*
2
-
-
25
-
ns
APB1 bus clock*
2
-
-
25
-
ns
APB2 bus clock*
2
2
2
*1: For more information about each internal operating clock, see Chapter 2-1: Clock in FM3 Family Peripheral Manual.
*2: For about each APB bus which each peripheral is connected to, see Block Diagram in this data sheet.
X0
Document Number: 002-05657 Rev.*A
Page 42 of 77
MB9B120J Series
12.4.2
Sub Clock Input Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Input frequency
fCL
Input clock cycle
tCYLL
Input clock pulse width
-
Pin
name
X0A,
X1A
Value
Conditions
Min
Typ
Max
Unit
Remarks
-
-
32.768
-
kHz
-
32
-
100
kHz
When crystal oscillator is
connected*
When using external clock
-
10
-
31.25
μs
When using external clock
PWH/tCYLL,P
WL/tCYLL
45
-
55
%
When using external clock
*: See Sub crystal oscillator in Handling Devices for the crystal oscillator used.
X0A
Document Number: 002-05657 Rev.*A
Page 43 of 77
MB9B120J Series
12.4.3
Built-in CR Oscillation Characteristics
Built-in High-speed CR
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Value
Conditions
Min
TA = + 25°C,
3.6 V < VCC ≤ 5.5 V
Clock frequency
Frequency stabilization
time
fCRH
tCRWT
Typ
3.92
4
4.08
3.9
4
4.1
3.88
4
4.12
3.94
4
4.06
3.92
4
4.08
3.9
4
4.1
TA = - 40°C to + 105°C,
2.7 V ≤ VCC ≤ 3.6 V
3.88
4
4.12
TA = - 40°C to + 105°C
2.8
4
5.2
-
-
-
30
TA =0°C to + 85°C,
3.6 V < VCC ≤ 5.5 V
TA = - 40°C to + 105°C,
3.6 V < VCC ≤ 5.5 V
TA = + 25°C,
2.7 V ≤ VCC ≤ 3.6 V
TA = - 20°C to + 85°C,
2.7 V ≤ VCC ≤ 3.6 V
TA = - 20°C to + 105°C,
2.7 V ≤ VCC ≤ 3.6 V
Unit
Max
Remarks
When trimming
*1
MHz
When not trimming
μs
*2
*1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency trimming/temperature trimming.
*2: This is time from the trim value setting to stable of the frequency of the High-speed CR clock.
After setting the trim value, the period when the frequency stability time passes can use the High-speed CR clock as a source
clock.
Built-in Low-speed CR
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Clock frequency
Symbol
fCRL
Document Number: 002-05657 Rev.*A
Conditions
-
Value
Min
50
Typ
100
Max
150
Unit
Remarks
kHz
Page 44 of 77
MB9B120J Series
12.4.4
Operating Conditions of Main PLL (In the case of using main clock for input of Main PLL)
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Value
Min
Typ
Max
Unit
Remarks
1
PLL oscillation stabilization wait time* (LOCK UP
time)
tLOCK
100
-
-
μs
PLL input clock frequency
PLL multiple rate
PLL macro oscillation clock frequency
2
Main PLL clock frequency*
fPLLI
fPLLO
fCLKPLL
4
5
75
-
-
16
37
150
72
MHz
multiple
MHz
MHz
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM3 Family Peripheral Manual.
12.4.5
Operating Conditions of Main PLL (In the case of using built-in High-speed CR for input clock of Main PLL)
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Value
Min
Typ
Unit
Max
Remarks
1
PLL oscillation stabilization wait time* (LOCK UP
time)
tLOCK
100
-
-
μs
PLL input clock frequency
PLL multiple rate
PLL macro oscillation clock frequency
2
Main PLL clock frequency*
fPLLI
fPLLO
fCLKPLL
3.8
19
72
-
4
-
4.2
35
150
72
MHz
multiple
MHz
MHz
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM3 Family Peripheral Manual.
Note: Make sure to input to the Main PLL source clock, the High-speed CR clock (CLKHC) that the frequency/temperature has been
trimmed.
When setting PLL multiple rate, please take the accuracy of the built-in High-speed CR clock into account and prevent the
master clock from exceeding the maximum frequency.
Main PLL connection
K
divider
PLL input
clock
PLL macro
oscillation clock
Main
PLL
M
divider
Main PLL
clock
(CLKPLL)
N
divider
Document Number: 002-05657 Rev.*A
Page 45 of 77
MB9B120J Series
12.4.6
Reset Input Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Reset input time
12.4.7
Symbol
Pin name
tINITX
INITX
Value
Conditions
Min
-
Unit
Max
500
-
Remarks
ns
Power-on Reset Timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Power supply rising time
tVCCR
Power supply shut down time
tOFF
Time until releasing
Power-on reset
tPRT
Value
Pin
name
Symbol
VCC
Min
Unit
Max
0
-
ms
1
-
ms
0.34
3.15
ms
Remarks
VCC_minimum
VCC
VDH_minimum
0.2V
0.2V
0.2V
tVCCR
tPRT
Internal reset
CPU Operation
Reset active
tOFF
Release
start
Glossary
• VCC_minimum : Minimum VCC of recommended operating conditions.
• VDH_minimum : Minimum detection voltage (when SVHR=00000) of Low-Voltage detection reset.
See 12.6. Low-Voltage Detection Characteristics.
Document Number: 002-05657 Rev.*A
Page 46 of 77
MB9B120J Series
12.4.8
Base Timer Input Timing
Timer input timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Input pulse width
Symbol
Pin name
Conditions
TIOAn/TIOBn
(when using as ECK,
TIN)
tTIWH,
tTIWL
-
tTIWH
Value
Min
Max
2tCYCP
-
Unit
Remarks
ns
tTIWL
ECK
TIN
VIHS
VIHS
VILS
VILS
Trigger input timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Input pulse width
Symbol
tTRGH,
tTRGL
Pin name
TIOAn/TIOBn
(when using as
TGIN)
Conditions
-
tTRGH
Value
Min
2tCYCP
Max
-
Unit
Remarks
ns
tTRGL
TGIN
VIHS
VIHS
VILS
VILS
Note: tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Base Timer is connected to, see Block Diagram in this data sheet.
Document Number: 002-05657 Rev.*A
Page 47 of 77
MB9B120J Series
12.4.9
CSIO/UART Timing
CSIO (SPI = 0, SCINV = 0)
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Serial clock cycle time
tSCYC
SCK ↓ → SOT delay time
tSLOVI
SIN → SCK ↑ setup time
tIVSHI
SCK ↑ → SIN hold time
tSHIXI
Serial clock L pulse width
Serial clock H pulse width
tSLSH
tSHSL
SCK ↓ → SOT delay time
tSLOVE
SIN → SCK ↑ setup time
tIVSHE
SCK ↑ → SIN hold time
tSHIXE
SCK falling time
SCK rising time
tF
tR
Pin
name
SCKx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
Master mode
Slave mode
VCC ≥ 4.5 V
Min
Max
VCC < 4.5 V
Min
Max
Conditions
Unit
4tCYCP
-
4tCYCP
-
ns
- 30
+ 30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
2tCYCP - 10
tCYCP + 10
-
2tCYCP - 10
tCYCP + 10
-
ns
ns
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
Notes:
• The above characteristics apply to clock synchronous mode.
• tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see Block Diagram in this data sheet.
• These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
• When the external load capacitance CL = 30 pF.
Document Number: 002-05657 Rev.*A
Page 48 of 77
MB9B120J Series
tSCYC
VOH
SCK
VOL
VOL
tSLOVI
VOH
SOT
VOL
tIVSHI
SIN
tSHIXI
VIH
VIH
VIL
VIL
Master mode
tSLSH
SCK
tSHSL
VIH
VIH
tF
VIL
VIL
VIH
tR
tSLOVE
SOT
VOH
VOL
tIVSHE
SIN
VIH
VIL
tSHIXE
VIH
VIL
Slave mode
Document Number: 002-05657 Rev.*A
Page 49 of 77
MB9B120J Series
CSIO (SPI = 0, SCINV = 1)
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Serial clock cycle time
Symbol
Pin
name
VCC ≥ 4.5 V
Min
Max
VCC < 4.5 V
Min
Max
Conditions
Unit
tSCYC
SCKx
4tCYCP
-
4tCYCP
-
ns
SCK ↑ → SOT delay time
tSHOVI
SCKx,
SOTx
- 30
+ 30
- 20
+ 20
ns
SIN → SCK ↓ setup time
tIVSLI
50
-
30
-
ns
SCK ↓ → SIN hold time
tSLIXI
0
-
0
-
ns
Serial clock L pulse width
Serial clock H pulse width
tSLSH
tSHSL
2tCYCP - 10
tCYCP + 10
-
2tCYCP - 10
tCYCP + 10
-
ns
ns
SCK ↑ → SOT delay time
tSHOVE
-
50
-
30
ns
SIN → SCK ↓ setup time
tIVSLE
10
-
10
-
ns
SCK ↓ → SIN hold time
tSLIXE
20
-
20
-
ns
SCK falling time
SCK rising time
tF
tR
-
5
5
-
5
5
ns
ns
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
Master mode
Slave mode
Notes:
• The above characteristics apply to clock synchronous mode.
• tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see Block Diagram in this data sheet.
• These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
• When the external load capacitance CL = 30 pF.
Document Number: 002-05657 Rev.*A
Page 50 of 77
MB9B120J Series
tSCYC
SCK
VOH
VOH
VOL
tSHOVI
VOH
SOT
VOL
tIVSLI
SIN
tSLIXI
VIH
VIH
VIL
VIL
Master mode
tSHSL
SCK
tSLSH
VIH
VIH
VIL
tR
SOT
tF
tSHOVE
VOH
VOL
tIVSLE
SIN
VIL
VIL
VIH
VIL
tSLIXE
VIH
VIL
Slave mode
Document Number: 002-05657 Rev.*A
Page 51 of 77
MB9B120J Series
CSIO (SPI = 1, SCINV = 0)
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Serial clock cycle time
Symbol
Pin
name
VCC ≥ 4.5 V
Min
Max
VCC < 4.5 V
Min
Max
Conditions
Unit
tSCYC
SCKx
4tCYCP
-
4tCYCP
-
ns
SCK ↑ → SOT delay time
tSHOVI
SCKx,
SOTx
- 30
+ 30
- 20
+ 20
ns
SIN → SCK ↓ setup time
tIVSLI
50
-
30
-
ns
SCK ↓→ SIN hold time
tSLIXI
0
-
0
-
ns
SOT → SCK ↓ delay time
tSOVLI
2tCYCP - 30
-
2tCYCP - 30
-
ns
Serial clock L pulse width
Serial clock H pulse width
tSLSH
tSHSL
2tCYCP - 10
tCYCP + 10
-
2tCYCP - 10
tCYCP + 10
-
ns
ns
SCK ↑ → SOT delay time
tSHOVE
-
50
-
30
ns
SIN → SCK ↓ setup time
tIVSLE
10
-
10
-
ns
SCK ↓→ SIN hold time
tSLIXE
20
-
20
-
ns
SCK falling time
SCK rising time
tF
tR
-
5
5
-
5
5
ns
ns
SCKx,
SINx
SCKx,
SINx
SCKx,
SOTx
SCKx
SCKx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
Master mode
Slave mode
Notes:
• The above characteristics apply to clock synchronous mode.
• tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see Block Diagram in this data sheet.
• These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
• When the external load capacitance CL = 30 pF.
Document Number: 002-05657 Rev.*A
Page 52 of 77
MB9B120J Series
tSCYC
VOH
SCK
VOL
VOH
VOL
SOT
VOH
VOL
tIVSLI
tSLIXI
VIH
VIL
SIN
VOL
tSHOVI
tSOVLI
VIH
VIL
Master mode
tSLSH
VIH
SCK
VIL
tF
*
SOT
VIL
tSHSL
tR
VOH
VOL
tIVSLE
SIN
VIH
VIH
tSHOVE
VOH
VOL
tSLIXE
VIH
VIL
VIH
VIL
Slave mode
*: Changes when writing to TDR register
Document Number: 002-05657 Rev.*A
Page 53 of 77
MB9B120J Series
CSIO (SPI = 1, SCINV = 1)
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Pin
name
VCC ≥ 4.5 V
Min
Max
VCC < 4.5 V
Min
Max
Conditions
Unit
Serial clock cycle time
tSCYC
SCKx
4tCYCP
-
4tCYCP
-
ns
SCK ↓ → SOT delay time
tSLOVI
SCKx,
SOTx
- 30
+ 30
- 20
+ 20
ns
SIN → SCK ↑ setup time
tIVSHI
50
-
30
-
ns
SCK ↑ → SIN hold time
tSHIXI
0
-
0
-
ns
SOT → SCK ↑ delay time
tSOVHI
2tCYCP - 30
-
2tCYCP - 30
-
ns
Serial clock L pulse width
Serial clock H pulse width
tSLSH
tSHSL
2tCYCP - 10
tCYCP + 10
-
2tCYCP - 10
tCYCP + 10
-
ns
ns
SCK ↓ → SOT delay time
tSLOVE
-
50
-
30
ns
SIN → SCK ↑ setup time
tIVSHE
10
-
10
-
ns
SCK ↑ → SIN hold time
tSHIXE
20
-
20
-
ns
SCK falling time
SCK rising time
tF
tR
-
5
5
-
5
5
ns
ns
SCKx,
SINx
SCKx,
SINx
SCKx,
SOTx
SCKx
SCKx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
Master mode
Slave mode
Notes:
• The above characteristics apply to clock synchronous mode.
• tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see Block Diagram in this data sheet.
• These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
• When the external load capacitance CL = 30 pF.
Document Number: 002-05657 Rev.*A
Page 54 of 77
MB9B120J Series
tSCYC
VOH
SCK
tSOVHI
tSLOVI
VOH
VOL
SOT
VOH
VOL
tSHIXI
tIVSHI
VIH
VIL
SIN
VOH
VOL
VIH
VIL
Master mode
tF
SCK
VIH
VIH
VIL
tSLSH
VIL
VIL
tSLOVE
VOH
VOL
SOT
VOH
VOL
tIVSHE
tSHIXE
VIH
VIL
SIN
VIH
VIL
Slave mode
UART external clock input (EXT = 1)
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Serial clock L pulse width
Serial clock H pulse width
SCK falling time
SCK rising time
tSLSH
tSHSL
tF
tR
Value
Conditions
CL = 30 pF
Min
tCYCP + 10
tCYCP + 10
-
tR
Document Number: 002-05657 Rev.*A
VIL
5
5
Unit
Remarks
ns
ns
ns
ns
tF
tSHSL
SCK
Max
VIH
tSLSH
VIH
VIL
VIL
Page 55 of 77
MB9B120J Series
12.4.10 External Input Timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Pin name
FRCKx
Input pulse width
tINH,
tINL
ICxx
DTTIxX
INTxx,
NMIX
Value
Min
Conditions
Max
Unit
-
2tCYCP*
1
-
ns
-
2tCYCP*
1
-
ns
*2
2tCYCP + 100*
-
ns
*3
500
-
ns
1
Remarks
Free-run timer input clock
Input capture
Wave form generator
External interrupt,
NMI
*1: tCYCP indicates the APB bus clock cycle time.
About the APB bus number which, Multi-function Timer, External interrupt is connected to, see Block Diagram in this data sheet.
*2: When in Run mode, in Sleep mode.
*3: When in Stop mode, in RTC mode, in Timer mode.
Document Number: 002-05657 Rev.*A
Page 56 of 77
MB9B120J Series
12.4.11 Quadrature Position/Revolution Counter Timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
AIN pin H width
AIN pin L width
BIN pin H width
BIN pin L width
Time from AIN pin H level to BIN rise
Time from BIN pin H level to AIN fall
Time from AIN pin L level to BIN fall
Time from BIN pin L level to AIN rise
Time from BIN pin H level to AIN rise
Time from AIN pin H level to BIN fall
Time from BIN pin L level to AIN fall
Time from AIN pin L level to BIN rise
ZIN pin H width
ZIN pin L width
Time from determined ZIN level to
AIN/BIN rise and fall
Time from AIN/BIN rise and fall time
to determined ZIN level
Value
Conditions
tAHL
tALL
tBHL
tBLL
tAUBU
tBUAD
tADBD
tBDAU
tBUAU
tAUBD
tBDAD
tADBU
tZHL
tZLL
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
QCR:CGSC=0
QCR:CGSC=0
tZABE
QCR:CGSC=1
tABEZ
QCR:CGSC=1
Min
Max
2tCYCP*
-
Unit
ns
*: tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Quadrature Position/Revolution Counter is connected to, see Block Diagram in this data sheet.
tALL
tAHL
AIN
tAUBU
tADBD
tBUAD
tBDAU
BIN
tBHL
Document Number: 002-05657 Rev.*A
tBLL
Page 57 of 77
MB9B120J Series
tBLL
tBHL
BIN
tBUAU
tBDAD
tAUBD
tADBU
AIN
tAHL
tALL
ZIN
ZIN
AIN/BIN
Document Number: 002-05657 Rev.*A
Page 58 of 77
MB9B120J Series
12.4.12 I2C Timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
SCL clock frequency
(Repeated) START condition hold time
SDA ↓ → SCL ↓
SCL clock L width
SCL clock H width
(Repeated) Start condition setup time
SCL ↑ → SDA ↓
Data hold time
SCL ↓ → SDA ↓ ↑
Data setup time
SDA ↓ ↑ → SCL ↑
Stop condition setup time
SCL ↑ → SDA ↑
Bus free time between
Stop condition and
Start condition
Noise filter
Symbol
Standard-mode
Min
Max
Conditions
Fast-mode
Min
Max
Un
it
fSCL
0
100
0
400
kH
z
tHDSTA
4.0
-
0.6
-
μs
tLOW
tHIGH
4.7
4.0
-
1.3
0.6
-
μs
μs
4.7
-
0.6
-
μs
0
3.45*
0
0.9*
tSUDAT
250
-
100
-
ns
tSUSTO
4.0
-
0.6
-
μs
tBUF
4.7
-
1.3
-
μs
-
2 tCYCP*
-
ns
tSUSTA
tHDDAT
tSP
CL = 30 pF,
1
R = (Vp/IOL)*
-
2 tCYCP*
4
2
4
3
Remarks
μs
*1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively.
Vp indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current.
*2: The maximum tHDDAT must satisfy that it doesn't extend at least L period (tLOW) of device's SCL signal.
*3: A Fast-mode I2C bus device can be used on a Standard-mode I2C bus system as long as the device satisfies the requirement of
“tSUDAT ≥ 250 ns”.
*4: tCYCP is the APB bus clock cycle time.
About the APB bus number that I2C is connected to, see Block Diagram in this data sheet.
To use Standard-mode, set the APB bus clock at 2 MHz or more
To use Fast-mode, set the APB bus clock at 8 MHz or more.
SDA
SCL
Document Number: 002-05657 Rev.*A
Page 59 of 77
MB9B120J Series
12.4.13 SWD Timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Pin name
Value
Conditions
Min
Max
Unit
SWDIO setup time
tSWS
SWCLK,
SWDIO
-
15
-
ns
SWDIO hold time
tSWH
SWCLK,
SWDIO
-
15
-
ns
SWDIO delay time
tSWD
SWCLK,
SWDIO
-
-
45
ns
Remarks
Note: When the external load capacitance CL = 30 pF.
SWCLK
SWDIO
(When input)
SWD
SWDIO
(When output)
Document Number: 002-05657 Rev.*A
Page 60 of 77
MB9B120J Series
12.5 12-bit A/D Converter
Electrical characteristics for the A/D converter
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Resolution
Integral Nonlinearity
Differential Nonlinearity
Zero transition voltage
Full-scale transition voltage
Conversion time
2
Sampling time*
Compare clock cycle*
3
Pin name
Value
Typ
Min
Unit
Max
VZT
VFST
tS
ANxx
ANxx
-
1
1.0*
0.3
± 3.0
± 2.5
± 15
AVRH ± 15
-
12
± 4.5
± 3.5
± 20
AVRH ± 20
10
bit
LSB
LSB
mV
mV
μs
μs
tCCK
-
50
-
1000
ns
State transition time to
operation permission
tSTT
-
-
-
1.0
μs
Analog input capacity
CAIN
-
-
-
9.7
pF
Analog input resistance
RAIN
-
-
-
Interchannel disparity
Analog port input leak current
-
ANxx
-
-
2.2
4
5
Analog input voltage
-
ANxx
AVRL
-
AVRH
V
-
AVRH
AVRL
2.7
VSS
-
VCC
VSS
V
V
Reference voltage
1.5
kΩ
Remarks
AVRH
= 2.7 V to 5.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
LSB
μA
*1: Conversion time is the value of sampling time (tS) + compare time (tC).
The condition of the minimum conversion time is when the value of sampling time: 300 ns, the value of sampling time: 700 ns.
Ensure that it satisfies the value of sampling time (tS) and compare clock cycle (tCCK).
For setting of sampling time and compare clock cycle, see Chapter 1-1: A/D Converter in FM3 Family Peripheral Manual Analog
Macro Part.
The register settings of the A/D Converter are reflected in the operation according to the APB bus clock timing.
For the number of the APB bus to which the A/D Converter is connected, see Block Diagram.
The base clock (HCLK) is used to generate the sampling time and the compare clock cycle.
*2: A necessary sampling time changes by external impedance.
Ensure that it set the sampling time to satisfy (Equation 1).
*3: Compare time (tC) is the value of (Equation 2).
Document Number: 002-05657 Rev.*A
Page 61 of 77
MB9B120J Series
ANxx
Analog input pin
Comparator
REXT
RAIN
Analog signal
source
CAIN
(Equation 1) tS ≥ (RAIN + REXT ) × CAIN × 9
tS:
RAIN:
Sampling time
Input resistance of A/D = 1.5 kΩ at 4.5 V < VCC < 5.5 V
Input resistance of A/D = 2.2 kΩ at 2.7 V < VCC < 4.5 V
CAIN:
Input capacity of A/D = 9.7 pF at 2.7 V < VCC < 5.5 V
REXT:
Output impedance of external circuit
(Equation 2) tC = tCCK × 14
tC:
Compare time
tCCK:
Compare clock cycle
Document Number: 002-05657 Rev.*A
Page 62 of 77
MB9B120J Series
Definition of 12-bit A/D Converter Terms
Resolution:
Analog variation that is recognized by an A/D converter.
Integral Nonlinearity:
Deviation of the line between the zero-transition point (0b000000000000 ←→ 0b000000000001)
and the full-scale transition point (0b111111111110 ←→ 0b111111111111) from the actual conversion
characteristics.
Differential Nonlinearity:
Deviation from the ideal value of the input voltage that is required to change the output code
by 1 LSB.
Integral Nonlinearity
Differential Nonlinearity
0xFFF
Actual conversion
characteristics
0xFFE
Actual conversion
characteristics
0x(N+1)
{1 LSB(N-1) + VZT}
VFSTtSHSL
VNT
0x004
(Actuallymeasured
value)
(Actually-measured
value)
0x003
Ideal characteristics
Digital output
Digital output
0xFFD
0xN
V(N+1)T
0x(N-1)
(Actually-measured
value)
Actual conversion
characteristics
Ideal characteristics
0x002
VNT
(Actually-measured
value)
0x(N-2)
0x001
VZTtR(Actually-measured value)
AVRL
Actual conversion characteristics
AVRH
AVRL
AVRH
Analog input
Integral Nonlinearity of digital output N =
Differential Nonlinearity of digital output N =
1LSB =
Analog input
VNT - {1LSB × (N - 1) + VZT}
1LSB
V(N + 1) T - VNT
1LSB
[LSB]
- 1 [LSB]
VFST – VZT
4094
N:
A/D converter digital output value.
VZT:
Voltage at which the digital output changes from 0x000 to 0x001.
VFST:
Voltage at which the digital output changes from 0xFFE to 0xFFF.
VNT:
Voltage at which the digital output changes from 0x(N − 1) to 0xN.
Document Number: 002-05657 Rev.*A
Page 63 of 77
MB9B120J Series
12.6 Low-Voltage Detection Characteristics
12.6.1
Low-Voltage Detection Reset
(TA = - 40°C to + 105°C)
Parameter
Symbol
Conditions
Value
Typ
Min
Max
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
LVD stabilization wait
time
tLVDW
-
-
-
8160 ×
*2
tCYCP
μs
LVD detection delay
time
tLVDDL
-
-
-
200
μs
*1
SVHR = 00000
*1
SVHR = 00001
*1
SVHR = 00010
*1
SVHR = 00011
*1
SVHR = 00100
*1
SVHR = 00101
*1
SVHR = 00110
*1
SVHR = 00111
*1
SVHR = 01000
*1
SVHR = 01001
*1
SVHR = 01010
2.25
2.45
2.65
2.30
2.50
2.70
2.39
2.60
2.81
Same as SVHR = 0000 value
2.48
2.70
2.92
Same as SVHR = 0000 value
2.58
2.80
3.02
Same as SVHR = 0000 value
2.76
3.00
3.24
Same as SVHR = 0000 value
2.94
3.20
3.46
Same as SVHR = 0000 value
3.31
3.60
3.89
Same as SVHR = 0000 value
3.40
3.70
4.00
Same as SVHR = 0000 value
3.68
4.00
4.32
Same as SVHR = 0000 value
3.77
4.10
4.43
Same as SVHR = 0000 value
3.86
4.20
4.54
Same as SVHR = 0000 value
Uni
t
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Remarks
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
*1: SVHR bit of Low-Voltage Detection Voltage Control Register (LVD_CTL) is reset to SVHR = 00000 by low voltage detection
reset.
*2: tCYCP indicates the APB2 bus clock cycle time.
Document Number: 002-05657 Rev.*A
Page 64 of 77
MB9B120J Series
12.6.2
Interrupt of Low-Voltage Detection
(TA = - 40°C to + 105°C)
Parameter
Symbol
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
VDH
VDL
VDH
VDL
VDH
VDL
VDH
LVD stabilization wait time
tLVDW
LVD detection delay time
tLVDDL
Conditions
Value
Typ
Min
Max
Unit
Remarks
2.58
2.80
3.02
V
When voltage drops
2.67
2.90
3.13
V
When voltage rises
2.76
3.00
3.24
V
When voltage drops
2.85
3.10
3.35
V
When voltage rises
2.94
3.20
3.46
V
When voltage drops
3.04
3.30
3.56
V
When voltage rises
3.31
3.60
3.89
V
When voltage drops
3.40
3.70
4.00
V
When voltage rises
3.40
3.70
4.00
V
When voltage drops
3.50
3.68
3.77
3.77
3.86
3.86
3.96
3.80
4.00
4.10
4.10
4.20
4.20
4.30
V
V
V
V
V
V
V
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
-
-
-
-
-
-
4.10
4.32
4.43
4.43
4.54
4.54
4.64
8160 ×
tCYCP*
200
SVHI = 00011
SVHI = 00100
SVHI = 00101
SVHI = 00110
SVHI = 00111
SVHI = 01000
SVHI = 01001
SVHI = 01010
μs
μs
*: tCYCP indicates the APB2 bus clock cycle time.
Document Number: 002-05657 Rev.*A
Page 65 of 77
MB9B120J Series
12.7 Flash Memory Write/Erase Characteristics
12.7.1
Write / Erase time
(VCC = 2.7V to 5.5V, TA = - 40°C to + 105°C)
Value
Parameter
Typ
Unit
Max
Remarks
Sector erase time
0.3
0.7
s
Includes write time prior to internal erase
Half word (16-bit) write time
16
282
μs
Not including system-level overhead time
Chip erase time
2.4
5.6
s
Includes write time prior to internal erase
*: The typical value is immediately after shipment, the maximum value is guarantee value under 10,000 cycle of erase/write.
12.7.2
Write cycles and data hold time
Erase/write cycles (cycle)
Data hold time (year)
1,000
20*
10,000
10*
Remarks
*: At average + 85°C
Document Number: 002-05657 Rev.*A
Page 66 of 77
MB9B120J Series
12.8 Return Time from Low-Power Consumption Mode
12.8.1 Return Factor: Interrupt
The return time from Low-Power consumption mode is indicated as follows. It is from receiving the return factor to starting the
program operation.
Return Count Time
(VCC = 2.7V to 5.5V, TA = - 40°C to + 105°C)
Parameter
Value
Symbol
Sleep mode
High-speed CR Timer mode,
Main Timer mode,
PLL Timer mode
Typ
Unit
Max*
μs
tCYCC
43
83
μs
310
620
μs
Sub Timer mode
534
724
μs
RTC mode,
Stop mode
278
479
μs
Low-speed CR Timer mode
tICNT
Remarks
*: The maximum value depends on the accuracy of built-in CR.
Operation example of return from Low-Power consumption mode (by external interrupt*)
External
interrupt
Interrupt factor
accept
Active
tICNT
CPU
Operation
Interrupt factor
clear by CPU
Start
*: External interrupt is set to detecting fall edge.
Document Number: 002-05657 Rev.*A
Page 67 of 77
MB9B120J Series
Operation example of return from Low-Power consumption mode (by internal resource interrupt*)
Internal
resource
interrupt
Interrupt factor
accept
Active
tICNT
CPU
Operation
Interrupt factor
clear by CPU
Start
*: Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode.
Notes:
• The return factor is different in each Low-Power consumption modes.
See Chapter 6: Low Power Consumption Mode and Operations of Standby Modes in FM3 Family Peripheral Manual.
• When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the Low-Power consumption
mode transition. See Chapter 6: Low Power Consumption Mode in FM3 Family Peripheral Manual.
Document Number: 002-05657 Rev.*A
Page 68 of 77
MB9B120J Series
12.8.2 Return Factor: Reset
The return time from Low-Power consumption mode is indicated as follows. It is from releasing reset to starting the program
operation.
Return Count Time
(VCC = 2.7V to 5.5V, TA = - 40°C to + 105°C)
Parameter
Value
Symbol
Typ
Max*
Unit
149
264
μs
149
264
μs
318
603
μs
Sub Timer mode
308
583
μs
RTC mode,
Stop mode
248
443
μs
Sleep mode
High-speed CR Timer mode,
Main Timer mode,
PLL Timer mode
Low-speed CR Timer mode
tRCNT
Remarks
*: The maximum value depends on the accuracy of built-in CR.
Operation example of return from Low-Power consumption mode (by INITX)
INITX
Internal reset
Reset active
Release
tRCNT
CPU
Operation
Document Number: 002-05657 Rev.*A
Start
Page 69 of 77
MB9B120J Series
Operation example of return from low power consumption mode (by internal resource reset*)
Internal
resource
reset
Internal reset
Reset active
Release
tRCNT
CPU
Operation
Start
*: Internal resource reset is not included in return factor by the kind of Low-Power consumption mode.
Notes:
• The return factor is different in each Low-Power consumption modes.
See Chapter 6: Low Power Consumption Mode and Operations of Standby Modes in FM3 Family Peripheral Manual.
• When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the Low-Power consumption
mode transition. See Chapter 6: Low Power Consumption Mode in FM3 Family Peripheral Manual.
• The time during the power-on reset/low-voltage detection reset is excluded. See 12.4.7. Power-on Reset Timing in
12.4. AC Characteristics in 12.Electrical Characteristics for the detail on the time during the power-on reset/low -voltage
detection reset.
• When in recovery from reset, CPU changes to the High-speed CR Run mode. When using the main clock or the PLL clock, it
is necessary to add the main clock oscillation stabilization wait time or the Main PLL clock stabilization wait time.
• The internal resource reset means the watchdog reset and the CSV reset.
Document Number: 002-05657 Rev.*A
Page 70 of 77
MB9B120J Series
13. Ordering Information
Part number
Package
MB9BF121JPMC
Plastic・LQFP32 (0.8 mm pitch), 32 pin
(FPT-32P-M30)
MB9BF121JWQN
Plastic・QFN32 (0.5 mm pitch), 32 pin
(LCC-32P-M73)
Document Number: 002-05657 Rev.*A
Page 71 of 77
MB9B120J Series
14. Package Dimensions
Document Number: 002-05657 Rev.*A
Page 72 of 77
MB9B120J Series
Document Number: 002-05657 Rev.*A
Page 73 of 77
MB9B120J Series
15. Major Changes
Spansion Publication Number: MB9B120J_DS706-00053
Page
Revision 0.1
Revision 1.0
2
4
Section
-
Initial release
Features
Features
Preliminary → Data Sheet
Company name and layout design change
2
Revised I C operation mode name
Revised Channel number of MFT A/D activation compare
・Revised channel number of MFT A/D activation compare
・Added notes of Built-in high speed CR accuracy
Corrected Package code
Corrected Package code
Corrected the remarks of type E and F
Revised Channel number of MFT A/D activation compare
6
Product Lineup
7
9
20
29
Packages
Pin Assignment
I/O Circuit Type
Block Diagram
Electrical Characteristics
3.Dc Characteristics(1) Current Rating
Electrical Characteristics
3.Ac Characteristics(6)Power-On Reset Timing
40,42
48
Change Results
Revised the values of “TBD”
Revised the values of “TBD”
2
61
Electrical Characteristics
2
3.Ac Characteristics(11) I c Timing
・Revised I C operation mode name
・Revised the value of noise filter
・Revised the notes explanation
62
Electrical Characteristics
3.Ac Characteristics(12) Swd Timing
Added the value of SWDIO delay time
63
Electrical Characteristics
5. 12-Bit A/D Converter Electrical Characteristics
68
Electrical Characteristics
7. Flash Memory Write/Erase Characteristics
69,71
Electrical Characteristics
8. Return Time From Low-Power Consumption
Mode
Package Dimensions
75
Revision 2.0
20
I/O Circuit Type
Memory Map
31
· Memory Map(2)
Electrical Characteristics
38, 39
1. Absolute Maximum Ratings
Electrical Characteristics
40
2. Recommended Operation Conditions
Electrical Characteristics
41, 42
3. DC Characteristics
(1) Current Rating
Electrical Characteristics
4. AC Characteristics
47
(4-1) Operating Conditions Of Main PLL
(4-2) Operating Conditions Of Main PLL
Electrical Characteristics
48
4. AC Characteristics
(6) Power-On Reset Timing
Document Number: 002-05657 Rev.*A
・Added the value of sampling time
・Revised the notes explanation
・Revised the value of Differential Nonlinearity +/-2.5LSB →+/-3.5LSB
・Deleted (Preliminary value) description
・Revised the values of “TBD”
・Revised the notes of Erase/write cycles and data hold time
・Deleted (target value) description
Revised the values of “TBD”
Corrected Package code
Added about +B input
Added the summary of Flash memory sector and the note
· Added the Clamp maximum current
· Added about +B input
Added the note about less than the minimum power supply voltage
· Changed the table format
· Added Main Timer mode current
Added the figure of Main PLL connection
Changed the figure of timing
Page 74 of 77
MB9B120J Series
Page
50-57
63
73
Section
Electrical Characteristics
4. Ac Characteristics
(8) Csio/Uart Timing
Electrical Characteristics
5. 12bit A/D Converter
Ordering Information
Change Results
· Modified from UART Timing to CSIO/UART Timing
· Changed from Internal shift clock operation to Master mode
· Changed from External shift clock operation to Slave mode
Added the typical value of Integral Nonlinearity, Differential Nonlinearity,
Zero transition voltage and Full-scale transition voltage
Changed notation of part number
NOTE: Please see “Document History” about later revised information.
Document Number: 002-05657 Rev.*A
Page 75 of 77
MB9B120J Series
Document History
Document Title: MB9B120J Series 32-Bit ARM® Cortex®-M3, FM3 Microcontroller
Document Number: 002-05657
Revision
ECN
**
–
Orig. of
Submission
Change
Date
AKIH
03/31/2015
Description of Change
Migrated to Cypress and assigned document number 002-05657.
No change to document contents or format.
*A
5167951
AKIH
Document Number: 002-05657 Rev.*A
03/14/2016
Updated to Cypress format.
Page 76 of 77
MB9B120J Series
Sales, Solutions, and Legal Information
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© Cypress Semiconductor Corporation 2013-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes to this document without further notice. Cypress does not
assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or
programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application
made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of
weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or
hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any
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whole or in part, and Company shall and hereby does release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. Company shall
indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the
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Document Number: 002-05657 Rev.*A
March 14, 2016
Page 77 of 77