74HC138-Q100; 74HCT138-Q100 3-to-8 line decoder/demultiplexer; inverting Rev. 1 — 16 July 2012 Product data sheet 1. General description The 74HC138-Q100; 74HCT138-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). The 74HC138-Q100; 74HCT138-Q100 decoder accepts three binary weighted address inputs (A0, A1 and A3) and when enabled, provides 8 mutually exclusive active LOW outputs (Y0 to Y7). The 74HC138-Q100; 74HCT138-Q100 features three enable inputs: two active LOW (E1 and E2) and one active HIGH (E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion of the 74HC138-Q100; 74HCT138-Q100 to a 1-of-32 (5 lines to 32 lines) decoder with just four 74HC138-Q100; 74HCT138-Q100 ICs and one inverter. The 74HC138-Q100; 74HCT138-Q100 can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes. Not used enable inputs must be permanently tied to their appropriate active HIGH- or LOW-state. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from 40 C to +85 C and from 40 C to +125 C Demultiplexing capability Multiple input enable for easy expansion Complies with JEDEC standard no. 7A Ideal for memory chip select decoding Active LOW mutually exclusive outputs ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) Multiple package options 74HC138-Q100; 74HCT138-Q100 NXP Semiconductors 3-to-8 line decoder/demultiplexer; inverting 3. Ordering information Table 1. Ordering information Type number Package 74HC138D-Q100 Temperature range Name Description Version 40 C to +125 C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal enhanced SOT763-1 very thin quad flat package; no leads; 16 terminals; body 2.5 3.5 0.85 mm 74 HCT138D-Q100 74HC138PW-Q100 74HCT138PW-Q100 74HC138BQ-Q100 74HCT138BQ-Q100 4. Functional diagram 1 A0 Y0 15 2 A1 Y1 14 3 A2 Y2 13 Y3 12 E1 Y4 11 E2 Y5 10 E3 Y6 9 Y7 7 4 5 6 Y0 15 1 A0 Y1 14 2 A1 Y2 13 3 A2 Y3 12 Y4 11 Y5 10 Y6 9 Y7 7 3-to-8 DECODER 4 mna370 ENABLE EXITING E1 5 E2 6 E3 mna372 Fig 1. Logic symbol 74HC_HCT138_Q100 Product data sheet Fig 2. Functional diagram All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 July 2012 © NXP B.V. 2012. All rights reserved. 2 of 18 74HC138-Q100; 74HCT138-Q100 NXP Semiconductors 3-to-8 line decoder/demultiplexer; inverting Y7 A2 Y6 A1 Y5 A0 Y4 E1 Y3 E2 Y2 E3 Y1 Y0 001aae059 Fig 3. Logic diagram 5. Pinning information 5.1 Pinning 74HC138/Q100 74HCT138/Q100 1 A0 terminal 1 index area A1 2 15 Y0 A2 3 14 Y1 15 Y0 E1 4 13 Y2 14 Y1 E2 5 E3 6 Y7 7 2 A2 3 12 Y3 GND(1) E1 4 13 Y2 E2 5 12 Y3 9 A1 E3 6 11 Y4 Y6 16 VCC 8 1 GND A0 Y7 7 10 Y5 GND 8 9 Y6 aaa-003153 Fig 4. 16 VCC 74HC138/Q100 74HCT138/Q100 Pin configuration SO16 and TSSOP16 74HC_HCT138_Q100 Product data sheet 11 Y4 10 Y5 aaa-003154 Transparent top view (1) The die substrate is attached to this pad using conductive die attach material. It cannot be used as supply pin or input. Fig 5. Pin configuration DHVQFN16 All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 July 2012 © NXP B.V. 2012. All rights reserved. 3 of 18 74HC138-Q100; 74HCT138-Q100 NXP Semiconductors 3-to-8 line decoder/demultiplexer; inverting 5.2 Pin description Table 2. Pin description Symbol Pin Description A0, A1, A2 1, 2, 3 address input A0, A1, A2 E1, E2 4, 5 enable input E1, E2 (active LOW) E3 6 enable input E3 (active HIGH) Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7 15, 14, 13, 12, 11, 10, 9, 7 output Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7 (active LOW) GND 8 ground (0 V) VCC 16 positive supply voltage 6. Functional description Function table[1] Table 3. Control Input Output E1 E2 E3 A2 A1 A0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 H X X X X X H H H H H H H H X H X X X L L L H L L L H H H H H H H L L L H H H H H H H L H L H L H H H H H L H H L H H H H H H L H H H H L L H H H L H H H H H L H H H L H H H H H H H L H L H H H H H H H H H L H H H H H H H [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care. 74HC_HCT138_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 July 2012 © NXP B.V. 2012. All rights reserved. 4 of 18 NXP Semiconductors 74HC138-Q100; 74HCT138-Q100 3-to-8 line decoder/demultiplexer; inverting 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage Conditions Min Max Unit 0.5 +7 V IIK input clamping current VI < 0.5 V or VI > VCC + 0.5 V - 20 mA IOK output clamping current VO < 0.5 V or VO > VCC + 0.5 V - 20 mA IO output current VO = 0.5 V to (VCC + 0.5 V) - 25 mA ICC supply current - 50 mA IGND ground current - 50 mA Tstg storage temperature 65 +150 C - 500 mW total power dissipation Ptot [1] [1] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C. For TSSOP16 package: Ptot derates linearly with 5.5 mW/K above 60 C. For DHVQFN16 package: Ptot derates linearly with 4.5 mW/K above 60 C. 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions 74HC138-Q100 74HCT138-Q100 Unit Min Typ Max Min Typ Max VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V VI input voltage 0 - VCC 0 - VCC V VO output voltage 0 - VCC 0 - VCC V Tamb ambient temperature t/V input transition rise and fall rate 74HC_HCT138_Q100 Product data sheet 40 +25 +125 40 +25 +125 C VCC = 2.0 V - - 625 - - - ns/V VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V VCC = 6.0 V - - 83 - - - ns/V All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 July 2012 © NXP B.V. 2012. All rights reserved. 5 of 18 74HC138-Q100; 74HCT138-Q100 NXP Semiconductors 3-to-8 line decoder/demultiplexer; inverting 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = 25 C Conditions Min Typ VCC = 2.0 V 1.5 VCC = 4.5 V 3.15 VCC = 6.0 V 4.2 VCC = 2.0 V - VCC = 4.5 V - VCC = 6.0 V Tamb = 40 C to +85 C Tamb = 40 C to Unit +125 C Max Min Max Min Max 1.2 - 1.5 - 1.5 - V 2.4 - 3.15 - 3.15 - V 3.2 - 4.2 - 4.2 - V 0.8 0.5 - 0.5 - 0.5 V 2.1 1.35 - 1.35 - 1.35 V - 2.8 1.8 - 1.8 - 1.8 V IO = 20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = 20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = 20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V IO = 4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V IO = 5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V IO = 20 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V - - 0.1 - 1.0 - 1.0 A - - 0.5 - 5.0 - - - 8.0 - 80 - 160 - 3.5 - 74HC138-Q100 VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VI = VIH or VIL VI = VIH or VIL II input leakage current VI = VCC or GND; VCC = 6.0 V IOZ OFF-state output current per input pin; VI = VIH or VIL; VO = VCC or GND; other inputs at VCC or GND; VCC = 6.0 V; IO = 0 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V CI input capacitance 10 A pF 74HCT138-Q100 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V VOH HIGH-level output voltage VI = VIH or VIL; VCC = 4.5 V 74HC_HCT138_Q100 Product data sheet IO = 20 A 4.4 4.5 - 4.4 - 4.4 - V IO = 4 mA 3.98 4.32 - 3.84 - 3.7 - V All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 July 2012 © NXP B.V. 2012. All rights reserved. 6 of 18 74HC138-Q100; 74HCT138-Q100 NXP Semiconductors 3-to-8 line decoder/demultiplexer; inverting Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = 25 C Conditions Min VOL LOW-level output voltage Tamb = 40 C to +85 C Tamb = 40 C to Unit +125 C Typ Max Min Max Min Max VI = VIH or VIL; VCC = 4.5 V IO = 20 A - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA - 0.15 0.26 - 0.33 - 0.4 V II input leakage current VI = VCC or GND; VCC = 5.5 V - - 0.1 - 1.0 - 1.0 A IOZ OFF-state output current per input pin; VI = VIH or VIL; VO = VCC or GND; other inputs at VCC or GND; VCC = 5.5 V; IO = 0 A - - 0.5 - 5.0 - 10 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 8.0 - 80 - 160 A ICC additional supply current VI = VCC 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A - 150 540 - 675 - 735 A per input pin; An inputs CI input capacitance 74HC_HCT138_Q100 Product data sheet per input pin; En inputs - 125 450 - 562.5 - 612.5 A per input pin; E3 input - 100 360 - 450 - 490 A - 3.5 - All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 July 2012 pF © NXP B.V. 2012. All rights reserved. 7 of 18 74HC138-Q100; 74HCT138-Q100 NXP Semiconductors 3-to-8 line decoder/demultiplexer; inverting 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 8. Symbol Parameter Tamb = 25 C Conditions Tamb = 40 C to +85 C Tamb = 40 C to +125 C Unit Min Typ Max Min Max Min Max - 41 150 - 190 - 225 ns VCC = 4.5 V - 15 30 - 38 - 45 ns VCC = 5 V; CL = 15 pF - 12 - - - - - ns - 12 26 - 33 - 38 ns For type 74HC138-Q100 tpd propagation An to Yn; see Figure 6 delay VCC = 2.0 V [1] VCC = 6.0 V E3 to Yn; see Figure 6 [1] VCC = 2.0 V - 47 150 - 190 - 225 ns VCC = 4.5 V - 17 20 - 38 - 45 ns VCC = 5 V; CL = 15 pF - 14 - - - - - ns - 14 26 - 33 - 38 ns VCC = 2.0 V - 47 150 - 190 - 225 ns VCC = 4.5 V - 17 20 - 38 - 45 ns VCC = 5 V; CL = 15 pF - 14 - - - - - ns - 14 26 - 33 - 38 ns VCC = 2.0 V - 19 75 - 95 - 110 ns VCC = 4.5 V - 7 15 - 19 - 22 ns VCC = 6.0 V - 6 13 - 16 - 19 ns - 67 - - - - - pF VCC = 6.0 V En to Yn; see Figure 7 [1] VCC = 6.0 V tt CPD transition time Yn; see Figure 6 and Figure 7 power CL = 50 pF; f = 1 MHz; dissipation VI = GND to VCC capacitance 74HC_HCT138_Q100 Product data sheet [2] [3] All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 July 2012 © NXP B.V. 2012. All rights reserved. 8 of 18 74HC138-Q100; 74HCT138-Q100 NXP Semiconductors 3-to-8 line decoder/demultiplexer; inverting Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 8. Symbol Parameter Tamb = 25 C Conditions Tamb = 40 C to +85 C Tamb = 40 C to +125 C Unit Min Typ Max Min Max Min Max - 20 35 - 44 - 53 ns - 17 - - - - - ns - 18 40 - 50 - 60 ns - 19 - - - - - ns VCC = 4.5 V - 19 40 - 50 - 60 ns VCC = 5 V; CL = 15 pF - 19 - - - - - ns - 7 15 - 19 - 22 ns - 67 - - - - - pF For type 74HCT138-Q100 tpd propagation An to Yn; see Figure 6 delay VCC = 4.5 V [1] VCC = 5 V; CL = 15 pF E3 to Yn; see Figure 6 [1] VCC = 4.5 V VCC = 5 V; CL = 15 pF En to Yn; see Figure 7 tt transition time Yn; see Figure 6 and Figure 7 CPD power CL = 50 pF; f = 1 MHz; dissipation VI = GND to VCC capacitance [1] [2] VCC = 4.5 V [1] [3] tpd is the same as tPLH and tPHL. [2] tt is the same as tTHL and tTLH. [3] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD VCC2 fi N + (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL VCC2 fo) = sum of outputs. 74HC_HCT138_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 July 2012 © NXP B.V. 2012. All rights reserved. 9 of 18 74HC138-Q100; 74HCT138-Q100 NXP Semiconductors 3-to-8 line decoder/demultiplexer; inverting 11. Waveforms VCC An, E3 input VM GND tPHL tPLH VOH Yn output VM VOL tTHL tTLH mna373 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 6. Propagation delay input (An) and enable input (E3) to output (Yn) and transition time output (Yn) VCC E1, E2 VM input GND tPHL tPLH VOH Yn output VM VOL tTHL tTLH mna374 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. Table 8. Propagation delay enable input (En) to output (Yn) and transition time output (Yn) Measurement points Type Input Output VM VM 74HC138-Q100 0.5VCC 0.5VCC 74HCT138-Q100 1.3 V 1.3 V 74HC_HCT138_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 July 2012 © NXP B.V. 2012. All rights reserved. 10 of 18 74HC138-Q100; 74HCT138-Q100 NXP Semiconductors 3-to-8 line decoder/demultiplexer; inverting VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VCC VCC G VI VO RL S1 open DUT CL RT 001aad983 Test data is given in Table 9. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch. Fig 8. Table 9. Load circuitry for measuring switching times Test data Type Input VI tr, tf CL RL tPHL, tPLH tPZH, tPHZ tPZL, tPLZ 74HC138-Q100 VCC 6 ns 15 pF, 50 pF 1 k open GND VCC 74HCT138-Q100 3 V 6 ns 15 pF, 50 pF 1 k open GND VCC 74HC_HCT138_Q100 Product data sheet Load S1 position All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 July 2012 © NXP B.V. 2012. All rights reserved. 11 of 18 74HC138-Q100; 74HCT138-Q100 NXP Semiconductors 3-to-8 line decoder/demultiplexer; inverting 12. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.16 0.15 0.05 0.244 0.041 0.228 0.01 0.01 0.028 0.004 0.012 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. Fig 9. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Package outline SOT109-1 (SO16) 74HC_HCT138_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 July 2012 © NXP B.V. 2012. All rights reserved. 12 of 18 74HC138-Q100; 74HCT138-Q100 NXP Semiconductors 3-to-8 line decoder/demultiplexer; inverting TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 E D A X c y HE v M A Z 9 16 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 8 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig 10. Package outline SOT403-1 (TSSOP16) 74HC_HCT138_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 July 2012 © NXP B.V. 2012. All rights reserved. 13 of 18 74HC138-Q100; 74HCT138-Q100 NXP Semiconductors 3-to-8 line decoder/demultiplexer; inverting DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT763-1 16 terminals; body 2.5 x 3.5 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 7 y y1 C v M C A B w M C b L 1 8 Eh e 16 9 15 10 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b 1 0.05 0.00 0.30 0.18 mm c D (1) Dh E (1) Eh 0.2 3.6 3.4 2.15 1.85 2.6 2.4 1.15 0.85 e 0.5 e1 L v w y y1 2.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT763-1 --- MO-241 --- EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 11. Package outline SOT763-1 (DHVQFN16) 74HC_HCT138_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 July 2012 © NXP B.V. 2012. All rights reserved. 14 of 18 74HC138-Q100; 74HCT138-Q100 NXP Semiconductors 3-to-8 line decoder/demultiplexer; inverting 13. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model LSTTL Low-power Schottky Transistor-Transistor Logic MM Machine Model MIL Military 14. Revision history Table 11. Revision history Document ID Release date 74HC_HCT138_Q100 v.1 20120716 74HC_HCT138_Q100 Product data sheet Data sheet status Change notice Doc. number Supersedes Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 July 2012 - - © NXP B.V. 2012. All rights reserved. 15 of 18 74HC138-Q100; 74HCT138-Q100 NXP Semiconductors 3-to-8 line decoder/demultiplexer; inverting 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 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This document supersedes and replaces all information supplied prior to the publication hereof. 74HC_HCT138_Q100 Product data sheet Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 July 2012 © NXP B.V. 2012. All rights reserved. 16 of 18 NXP Semiconductors 74HC138-Q100; 74HCT138-Q100 3-to-8 line decoder/demultiplexer; inverting No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74HC_HCT138_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 July 2012 © NXP B.V. 2012. All rights reserved. 17 of 18 NXP Semiconductors 74HC138-Q100; 74HCT138-Q100 3-to-8 line decoder/demultiplexer; inverting 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Contact information. . . . . . . . . . . . . . . . . . . . . 17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 16 July 2012 Document identifier: 74HC_HCT138_Q100