CYBL10X6X Family Datasheet Programmable Radio-on-Chip With Bluetooth Low Energy (PRoC BLE) General Description PRoC BLE is a 32-bit, 48-MHz ARM® Cortex®-M0 BLE solution with CapSense®, 12-bit ADC, four timer, counter, pulse-width modulators (TCPWM), thirty-six GPIOs, two serial communication blocks (SCBs), LCD, and I2S. PRoC BLE includes a royalty-free BLE stack compatible with Bluetooth® 4.1 and provides a complete, programmable, and flexible solution for HID, remote controls, toys, beacons, and wireless chargers. In addition to these applications, PRoC BLE provides a simple, low-cost way to add BLE connectivity to any system. Features Bluetooth® Smart Connectivity ■ Bluetooth 4.1 single-mode device ■ 2.4-GHz BLE radio and baseband with integrated balun ■ TX output power: –18 dBm to +3 dBm ■ Received signal strength indicator (RSSI) with 1-dB resolution ■ RX sensitivity: –89 dBm ■ TX current: 15.6 mA at 0 dBm ■ RX current: 16.4 mA ■ ■ ■ Clock, Reset, and Supply ■ ■ ■ ARM Cortex-M0 CPU Core 32-bit processor (0.9 DMIPS/MHz) with single-cycle 32-bit multiply, operating at up to 48 MHz ■ 128-KB flash memory ■ 16-KB SRAM memory ■ Emulated EEPROM using flash memory ■ Watchdog timer with dedicated internal low-speed oscillator (ILO) ■ ■ Wide supply-voltage range: 1.9 V to 5.5 V 3-MHz to 48-MHz internal main oscillator (IMO) with 2% accuracy 24-MHz external clock oscillator (ECO) without load capacitance 32-kHz WCO Programmable GPIOs ■ ■ 36 GPIOs configurable as open drain high/low, pull-up/pull-down, HI-Z, or strong output Any GPIO pin can be CapSense, LCD, or analog, with flexible pin routing Programming and Debug Ultra-Low-Power 1.3-µA Deep-Sleep mode with watch crystal oscillator (WCO) on ■ 150-nA Hibernate mode current with SRAM retention ■ 60-nA Stop mode current with GPIO wakeup ■ ® CapSense Touch Sensing with Two-Finger Gestures Up to 36 capacitive sensors for buttons, sliders, and touchpads ■ Two-finger gestures: scroll, inertial scroll, pinch, stretch, and edge-swipe ■ Cypress Capacitive Sigma-Delta (CSD) provides best-in-class SNR (> 5:1) and liquid tolerance ■ Automatic hardware-tuning algorithm (SmartSense™) ■ Peripherals ■ ■ ■ ■ • Operating temperature range: –40 °C to +105 °C Available in 56-pin QFN (7 mm × 7 mm) and 68-ball WLCSP (3.52 mm × 3.91 mm) packages PSoC® Creator™ Design Environment ■ ■ Easy-to-use IDE to configure, develop, program, and test a BLE application Option to export the design to Keil, IAR, or Eclipse Bluetooth Low Energy Protocol Stack ■ 12-bit, 1-Msps SAR ADC with internal reference, sample-and-hold (S/H), and channel sequencer ■ Ultra-low-power LCD segment drive for 128 segments with operation in Deep-Sleep mode 2 ■ Two serial communication blocks (SCBs) supporting I C (Master/Slave), SPI (Master/Slave), or UART 2-pin SWD In-system flash programming support Temperature and Packaging ■ Cypress Semiconductor Corporation Document Number: 001-90478 Rev. *K Four dedicated 16-bit TCPWMs ❐ Additional four 8-bit or two 16-bit PWMs Programmable LVD from 1.8 V to 4.5 V I2S Master interface ■ 198 Champion Court Bluetooth Low Energy protocol stack supporting generic access profile (GAP) Central, Peripheral, Observer, or Broadcaster roles ❐ Switches between Central and Peripheral roles on-the-go Standard Bluetooth Low Energy profiles and services for interoperability ❐ Custom profile and service for specific use cases • San Jose, CA 95134-1709 • 408-943-2600 Revised August 19, 2015 PRoC BLE: CYBL10X6X Family Datasheet Contents Blocks and Functionality ................................................. 3 CPU Subsystem .......................................................... 4 BLE Subsystem........................................................... 4 System Resources Subsystem ................................... 4 Peripheral Blocks ........................................................ 6 Pinouts .............................................................................. 8 Power............................................................................... 13 Low-Power Modes..................................................... 13 Development Support .................................................... 15 Documentation .......................................................... 15 Online ........................................................................ 15 Tools.......................................................................... 15 Kits ............................................................................ 15 Electrical Specifications ................................................ 16 Absolute Maximum Ratings ...................................... 16 BLE Subsystem......................................................... 16 Device-Level Specifications ...................................... 19 Analog Peripherals .................................................... 24 Document Number: 001-90478 Rev. *K Digital Peripherals ..................................................... Memory ..................................................................... System Resources .................................................... Ordering Information...................................................... Part Numbering Conventions .................................... Packaging........................................................................ Acronyms ........................................................................ Document Conventions ................................................. Units of Measure ....................................................... Revision History ............................................................. Sales, Solutions, and Legal Information ...................... Worldwide Sales and Design Support....................... Products .................................................................... PSoC® Solutions ...................................................... Cypress Developer Community................................. Technical Support ..................................................... 26 29 29 33 34 35 38 40 40 41 42 42 42 42 42 42 Page 2 of 42 PRoC BLE: CYBL10X6X Family Datasheet Blocks and Functionality The CYBL10X6X block diagram is shown in Figure 1. There are five major subsystems: CPU subsystem, BLE subsystem, system resources, peripheral blocks, and I/O subsystem. Figure 1. Block Diagram CPU Subsystem P0.6 P0.7 ARM Cortex-M0 SWD FLASH 128 kB NVIC SRAM 16 kB CONFIG 512 B ROM 8 kB System Interconnect BLE Subsystem System Resources Clock Control LVD IMO XRES XRES Link Layer Engine BOD ILO WDT WCO ECO RF PHY XTAL32I/P6.1 XTAL32O/P6.0 XTAL24I XTAL24O ANT Peripherals GPIOs GPIOs GPIOs 12-Bit SAR ADC CSD 4x TCPWM I2S Peripheral Interconnect GPIOs SCB0 I2C/UART/SPI GPIOs SCB1 I2C/UART/SPI GPIOs 4x PWM LCD GPIOs GPIOs High Speed I/O Matrix The PRoC BLE family includes extensive support for programming, testing, debugging, and tracing both hardware and firmware. The complete debug-on-chip functionality enables full-device debugging in the final system using the standard production device. It does not require special interfaces, debugging pods, simulators, or emulators. Only the standard programming connections are required to fully support debug. Document Number: 001-90478 Rev. *K The PSoC Creator IDE provides fully integrated programming and debug support for PRoC BLE devices. The SWD interface is fully compatible with industry-standard third-party tools. PRoC BLE also supports disabling the SWD interface and has a robust flash-protection feature. Page 3 of 42 PRoC BLE: CYBL10X6X Family Datasheet CPU Subsystem CPU The CYBL10X6X device is based on an energy-efficient ARM Cortex-M0 32-bit processor, offering low power consumption, high performance, and reduced code size using 16-bit thumb instructions. The Cortex-M0’s ability to perform single-cycle 32-bit arithmetic and logic operations, including single-cycle 32-bit multiplication, helps in better performance. The inclusion of the tightly-integrated Nested Vectored Interrupt Controller (NVIC) with 32 interrupt lines enables the Cortex-M0 to achieve a low latency and a deterministic interrupt response. The CPU also includes a 2-pin interface, the serial wire debug (SWD), which is a 2-wire form of JTAG. The debug circuits are enabled by default and can only be disabled in firmware. If disabled, the only way to re-enable them is to erase the entire device, clear flash protection, and reprogram the device with the new firmware that enables debugging. In addition, it is possible to use the debug pins as GPIO too. The device has four breakpoints and two watchpoints for effective debugging. The physical layer consists of a modem and an RF transceiver that transmits and receives BLE packets at the rate of 1 Mbps over the 2.4-GHz ISM band. In the transmit direction, this block performs GFSK modulation and then converts the digital baseband signal of these BLE packets into radio frequency before transmitting them to air through an antenna. In the receive direction, this block converts an RF signal from the antenna to a digital bit stream after performing GFSK demodulation. The RF transceiver contains an integrated balun, which provides a single-ended RF port pin to drive a 50-Ω antenna terminal through a pi-matching network. The output power is programmable from –18 dBm to +3 dBm to optimize the current consumption for different applications. The 8-KB supervisory ROM contains a library of executable functions for flash programming. These functions are accessed through supervisory calls (SVC) and enable in-system programming of the flash memory. The Bluetooth Low Energy protocol stack uses the BLE subsystem and provides the following features: ■ Link Layer (LL) ❐ Master and Slave roles ❐ 128-bit AES engine ❐ Encryption ❐ Low-duty-cycle advertising (Bluetooth 4.1 feature) ❐ LE ping (Bluetooth 4.1 feature) ■ Bluetooth Low Energy 4.1 single-mode protocol stack with logical link control and adaptation protocol (L2CAP), attribute (ATT), and security manager (SM) protocols ■ Master and slave roles ■ API access to generic attribute profile (GATT), generic access profile (GAP), and L2CAP ■ L2CAP connection-oriented channel (Bluetooth 4.1 feature) ■ GAP features ❐ Broadcaster, Observer, Peripheral, and Central roles ❐ Security mode 1: Level 1, 2, and 3 ❐ Security mode 2: Level 1 and 2 ❐ User-defined advertising data ❐ Multiple-bond support ■ GATT features ❐ GATT client and server ❐ Supports GATT subprocedures ❐ 32-bit universally unique identifiers (UUID) (Bluetooth 4.1 feature) ■ Security Manager (SM) ❐ Pairing methods: Just Works, Passkey Entry, and Out of Band ❐ Authenticated man-in-the-middle (MITM) protection and data signing ■ Supports all SIG-adopted BLE profiles BLE Subsystem System Resources Subsystem Flash The device has a 128-KB flash memory with a flash accelerator, tightly coupled to the CPU to improve average access times from flash. The flash is designed to deliver 1-wait-state (WS) access time at 48 MHz and with 0-WS access time at 24 MHz. The flash accelerator delivers 85% of single-cycle SRAM access performance on average. Part of the flash can be used to emulate EEPROM operation, if required. During flash erase and programming operations (the maximum erase and program time is 20 ms per row), the IMO will be set to 48 MHz for the duration of the operation. This also applies to the emulated EEPROM. System design must take this into account because peripherals operating from different IMO frequencies will be affected. If it is critical that peripherals continue to operate with no change during flash programming, always set the IMO to 48 MHz and derive the peripheral clocks by dividing down from this frequency. SRAM The low-power 16-KB SRAM memory retains its contents even in Hibernate mode. ROM The BLE subsystem consists of the link layer engine and physical layer. The link layer engine supports both master and slave roles. The link layer engine implements time-critical functions such as encryption in the hardware to reduce the power consumption, and provides minimal processor intervention and a high performance. The key protocol elements, such as host control interface (HCI) and link control, are implemented in firmware. The direct test mode (DTM) is included to test the radio performance using a standard Bluetooth tester. Document Number: 001-90478 Rev. *K Power The power block includes internal LDOs that supply required voltage levels for different blocks. The power system also includes POR, BOD, and LVD circuits. The POR circuit holds the device in the reset state until the power supplies have stabilized at appropriate levels and the clock is ready. The BOD circuit resets the device when the supply voltage is too low for proper device operation. The LVD circuit generates an interrupt if the supply voltage drops below a user-selectable level. Page 4 of 42 PRoC BLE: CYBL10X6X Family Datasheet An external active-LOW reset pin (XRES) can be used to reset the device. The XRES pin has an internal pull-up resistor and, in most applications, does not require any additional pull-up resistors. The power system is described in detail in the “Power” section on page 13. peripherals. The system clock (SYSCLK) driving buses, registers, and the processor must be higher than all the other clocks in the system that are divided off HFCLK. The ECO and WCO are present in the BLE subsystem and the clock outputs are routed to the system resources. Clock Control Internal Main Oscillator (IMO) The PRoC BLE clock control is responsible for providing clocks to all subsystems and also for switching between different clock sources without glitching. The clock control for PRoC BLE consists of the IMO and the internal low-speed oscillator (ILO). It uses the 24-MHz external crystal oscillator (ECO) and the 32-kHz WCO. In addition, an external clock may be supplied from a pin. The IMO is the primary system clock source, which can be adjusted in the range of 3 MHz to 48 MHz in steps of 1 MHz. The IMO accuracy is ±2%. The device has 12 dividers with 16 divider outputs. Two dividers have additional fractional division capability. The HFCLK signal is divided down, as shown in Figure 2, to generate the system clock (SYSCLK) and peripheral clock (PERx_CLK) for different Internal Low-Speed Oscillator (ILO) The ILO is a very-low-power 32-kHz oscillator, which is primarily used to generate clocks for peripheral operations in Deep-Sleep mode. The ILO-driven counters can be calibrated to the IMO to improve accuracy. Cypress provides a software component, which does the calibration. Figure 2. Clock Control BLE Subsystem HFCLK ECO Prescaler Divider /2n (n=0..3) ` Divider 0 (/16) SYSCLK PER0_CLK IMO EXTCLK Divider 9 (/16) Fractional Divider 0 (/16.5) WCO Fractional Divider 1 (/16.5) PER15_CLK LFCLK ILO External Crystal Oscillator (ECO) Voltage Reference The ECO is used as the active clock for the BLE subsystem to meet the ±50-ppm clock accuracy requirement of the Bluetooth 4.1 specification. The ECO includes a tunable load capacitor to tune the crystal clock frequency by measuring the actual clock frequency. The high-accuracy ECO clock can also be used as a system clock. The internal bandgap reference circuit with 1% accuracy provides the voltage reference for the 12-bit SAR ADC. To enable better SNRs and absolute accuracy, it will be possible to bypass the internal bandgap reference using a REF pin and to use an external reference for the SAR. Watch Crystal Oscillator (WCO) A watchdog timer is implemented in the system resources subsystem running from the ILO; this allows watchdog operations during Deep-Sleep mode and generates a watchdog reset if not serviced before the timeout occurs. The watchdog reset is recorded in the ‘Reset Cause’ register. The WCO is used as the sleep clock for the BLE subsystem to meet the ±500-ppm clock accuracy requirement of the Bluetooth 4.1 specification. The sleep clock provides accurate sleep timing and enables wakeup at specified advertisement and connection intervals. With the WCO and firmware, an accurate real-time clock (within the bounds of the 32.768-kHz crystal accuracy) can be realized. Document Number: 001-90478 Rev. *K Watchdog Timer (WDT) Page 5 of 42 PRoC BLE: CYBL10X6X Family Datasheet Peripheral Blocks Serial Communication Block (SCB0/SCB1) 12-Bit SAR ADC The ADC is a 12-bit, 1-Msps SAR ADC with a built-in sample-and-hold (S/H) circuit. The ADC can operate with either an internal voltage reference or an external voltage reference. Preceding the SAR ADC is the SARMUX, which can route external pins and internal signals (analog mux bus and temperature sensor output) to the eight internal channels of the SAR ADC. The sequencer controller (SARSEQ) is used to control the SARMUX and SAR ADC to do an automatic scan on all enabled channels without CPU intervention and for preprocessing tasks such as averaging the output data. A Cypress-supplied software driver (Component) is used to control the ADC peripheral. Figure 3. SAR ADC System Diagram Control P3.0 - P3.7 Configure Registers SARSEQ AHB, DSI VPLUS SARMUX SARADC Data Sequencer VMINUS I2C mode: The I2C peripheral is compatible with the I2C Standard-mode, Fast-mode, and Fast-Mode-Plus devices as defined in the NXP I2C-bus specification and user manual (UM10204). The I2C bus I/O is implemented with GPIOs in open-drain modes. The hardware I2C block implements a full multimaster and slave interface (it is capable of multimaster arbitration). This block is capable of operating at speeds of up to 1 Mbps (Fast-Mode Plus) and has flexible buffering options to reduce the interrupt overhead and latency for the CPU. The I2C function is implemented using the Cypress-provided software Component (EzI2C) that creates a mailbox address range in the memory of PRoC BLE and effectively reduces the I2C communication to reading from and writing to an array in memory. In addition, the block supports an 8-byte FIFO for receive and transmit, which, by increasing the time given for the CPU to read data, greatly reduces the need for clock stretching caused by the CPU not having read the data on time. When SCB0 is used, Serial Data (SDA) and Serial Clock (SCL) of I2C can be connected to P0.4 and P0.5, or P1.4 and P1.5, or P3.0 and P3.1. SARREF Analog Mux Bus A/B The SCB can be configured as an I2C, UART, or SPI interface. It supports an 8-byte FIFO for receive and transmit buffers to reduce CPU intervention. A maximum of two SCBs (SCB0, SCB1) are available. Vrefs When SCB1 is used, SDA and SCL can be connected to P0.0 and P0.1, or P3.4 and P3.5, or P5.0 and P5.1. Ref-bypass A diode based, on-chip temperature sensor is used to measure the die temperature. The temperature sensor is connected to the ADC, which digitizes the reading and produces a temperature value using the Cypress-supplied software that includes calibration and linearization. 4x Timer Counter PWM (TCPWM) The 16-bit TCPWM module can be used to generate the PWM output or to capture the timing of edges of input signals or to provide a timer functionality. TCPWM can also be used as a 16-bit counter that supports up, down, and up/down counting modes. Rising edge, falling edge, combined rising/falling edge detection, or pass-through on all hardware input signals can be used to derive counter events. Three routed output signals are available to indicate underflow, overflow, and counter/compare match events. A maximum of four TCPWMs are available. 4x PWM These PWMs are in addition to the TCPWMs. The PWM peripheral can be configured as 8-bit or 16-bit resolution. The PWM provides compare outputs to generate single or continuous timing and control signals in hardware. It also provides an easy method of generating complex real-time events accurately with minimal CPU intervention. A maximum of four 8-bit PWMs or two 16-bit PWMs are available. Document Number: 001-90478 Rev. *K Configurations for I2C are as follows: ■ SCB1 is fully compliant with the Standard-mode (100 kHz), Fast-mode (400 kHz), and Fast-Mode-Plus (1 MHz) I2C signaling specifications when routed to GPIO pins P5.0 and P5.1, except for hot-swap capability during I2C active communication. ■ SCB1 is compliant only with Standard mode (100 kHz) when not used with P5.0 and P5.1. ■ SCB0 is compliant with Standard mode (100 kHz) only. UART mode: This is a full-feature UART operating up to 1 Mbps. It supports automotive single-wire interface (LIN), infrared interface (IrDA), and SmartCard (ISO7816) protocols. In addition, it supports the 9-bit multiprocessor mode, which allows addressing of peripherals connected over common RX and TX lines. The UART hardware flow control is supported to allow slow and fast devices to communicate with each other over UART without the risk of losing data. Refer to Table 4 on page 11 for possible UART connections to the GPIOs. SPI Mode: The SPI mode supports full Motorola® SPI, Texas Instruments® Secure Simple Pairing (SSP) (essentially adds a start pulse used to synchronize SPI Codecs), and National Microwire (half-duplex form of SPI). This block supports an 8-byte FIFO for receive and transmit. Refer to Table 4 on page 11 for the possible SPI connections to the GPIOs. Inter-IC Sound Bus (I2S) Inter-IC Sound Bus (I2S) is a serial bus interface standard used for connecting digital audio devices. The specification is from Philips® Semiconductor (I2S bus specification; February 1986, revised June 5, 1996). Page 6 of 42 PRoC BLE: CYBL10X6X Family Datasheet I2S operates only in the Master mode, supporting the transmitter (TX) and the receiver (RX), which have independent data byte streams. These byte streams are packed with the most significant byte first. The number of bytes used for each sample (a sample for the left or right channel) is the minimum number of bytes to hold a sample. LCD The LCD controller can drive up to four commons and up to 32 segments. It uses full digital methods to drive the LCD segments providing ultra-low power consumption. The two methods used are referred to as digital correlation and PWM. The digital correlation method modulates the frequency and signal levels of the commons and segments to generate the highest RMS voltage across a segment to light it up or to maintain the RMS signal as zero. This method is good for STN displays but may result in reduced contrast in TN (cheaper) displays. The PWM method drives the panel with PWM signals to effectively use the capacitance of the panel to provide the integration of the modulated pulse-width to generate the desired LCD voltage. This method results in higher power consumption but provides better results in driving TN displays. LCD operation is supported during Deep-Sleep mode by refreshing a small display buffer (four bits; one 32-bit register per port). CapSense CapSense is supported on all GPIOs through a Capacitive Sigma-Delta (CSD) block, which can be connected to any GPIO through an analog mux bus. Any GPIO pin can be connected to the analog mux bus via an analog switch. The CapSense function can thus be provided on any pin or group of pins in a system under software control. A software Component in PSoC Creator is provided for the CapSense block to make it easy for the user. The shield voltage can be driven on another mux bus to provide liquid-tolerance capability. Driving the shield electrode Document Number: 001-90478 Rev. *K in phase with the sense electrode keeps the shield capacitance from attenuating the sensed input. The CapSense trackpad/touchpad with gestures has the following features: ■ Supports 1-finger and 2-finger touch applications ■ Supports up to 35 X/Y sensor inputs ■ Includes a gesture-detection library: ❐ 1-finger touch: tracing, pan, click, double-click ❐ 2-finger touch: pan, click, zoom I/O Subsystem The I/O subsystem, which comprises the GPIO block, implements the following: ■ Eight drive-strength modes: ❐ Analog input mode (input and output buffers disabled) ❐ Input only ❐ Weak pull-up with strong pull-down ❐ Weak pull-up with weak pull-down ❐ Strong pull-up with weak pull-down ❐ Strong pull-up with strong pull-down ❐ Open drain with strong pull-down ❐ Open drain with strong pull-up ■ Port pins: 36 ■ Input threshold select (CMOS or LVTTL) ■ Individual control of input and output buffers (enabling/disabling) in addition to drive-strength modes ■ Hold mode for latching the previous state (used for retaining the I/O state in Deep Sleep and Hibernate modes) ■ Selectable slew rates for dV/dt to improve EMI ■ The GPIO pins P5.0 and P5.1 are overvoltage-tolerant ■ The GPIO cells, including P5.0 and P5.1, cannot be hot-swapped or powered up independent of the rest of the system. Page 7 of 42 PRoC BLE: CYBL10X6X Family Datasheet Pinouts Table 1 shows the pin list for the CYBL10X6X device. Table 1. CYBL10X6X Pin List (QFN Package) Pin Name Type 1 VDDD POWER 1.71-V to 5.5-V digital supply 2 XTAL32O/P6.0 CLOCK 32.768-kHz crystal 3 XTAL32I/P6.1 CLOCK 32.768-kHz crystal or external clock input 4 XRES RESET 5 P4.0 GPIO Port 4 Pin 0, analog/digital/lcd/csd 6 P4.1 GPIO Port 4 Pin 1, analog/digital/lcd/csd 7 P5.0 GPIO Port 5 Pin 0, analog/digital/lcd/csd 8 P5.1 GPIO 9 VSSD GROUND Description Reset, active LOW Port 5 Pin 1, analog/digital/lcd/csd Digital ground 10 VDDR POWER 1.9-V to 5.5-V radio supply 11 GANT1 GROUND Antenna shielding ground 12 ANT ANTENNA Antenna pin 13 GANT2 GROUND Antenna shielding ground 14 VDDR POWER 1.9-V to 5.5-V radio supply 15 VDDR POWER 1.9-V to 5.5-V radio supply 16 XTAL24I CLOCK 24-MHz crystal or external clock input 17 XTAL24O CLOCK 24-MHz crystal 18 VDDR POWER 1.9-V to 5.5-V radio supply 19 P0.0 GPIO Port 0 Pin 0, analog/digital/lcd/csd 20 P0.1 GPIO Port 0 Pin 1, analog/digital/lcd/csd 21 P0.2 GPIO Port 0 Pin 2, analog/digital/lcd/csd 22 P0.3 GPIO 23 VDDD POWER 24 P0.4 GPIO Port 0 Pin 4, analog/digital/lcd/csd 25 P0.5 GPIO Port 0 Pin 5, analog/digital/lcd/csd 26 P0.6 GPIO Port 0 Pin 6, analog/digital/lcd/csd 27 P0.7 GPIO Port 0 Pin 7, analog/digital/lcd/csd 28 P1.0 GPIO Port 1 Pin 0, analog/digital/lcd/csd 29 P1.1 GPIO Port 1 Pin 1, analog/digital/lcd/csd 30 P1.2 GPIO Port 1 Pin 2, analog/digital/lcd/csd 31 P1.3 GPIO Port 1 Pin 3, analog/digital/lcd/csd 32 P1.4 GPIO Port 1 Pin 4, analog/digital/lcd/csd 33 P1.5 GPIO Port 1 Pin 5, analog/digital/lcd/csd 34 P1.6 GPIO Port 1 Pin 6, analog/digital/lcd/csd 35 P1.7 GPIO Port 1 Pin 7, analog/digital/lcd/csd 36 VDDA POWER 37 P2.0 GPIO Port 2 Pin 0, analog/digital/lcd/csd 38 P2.1 GPIO Port 2 Pin 1, analog/digital/lcd/csd 39 P2.2 GPIO Port 2 Pin 2, analog/digital/lcd/csd 40 P2.3 GPIO Port 2 Pin 3, analog/digital/lcd/csd Document Number: 001-90478 Rev. *K Port 0 Pin 3, analog/digital/lcd/csd 1.71-V to 5.5-V digital supply 1.71-V to 5.5-V analog supply Page 8 of 42 PRoC BLE: CYBL10X6X Family Datasheet Table 1. CYBL10X6X Pin List (QFN Package) (continued) Pin Name Type 41 P2.4 GPIO Port 2 Pin 4, analog/digital/lcd/csd 42 P2.5 GPIO Port 2 Pin 5, analog/digital/lcd/csd 43 P2.6 GPIO Port 2 Pin 6, analog/digital/lcd/csd 44 P2.7 GPIO Port 2 Pin 7, analog/digital/lcd/csd 45 VREF REF 1.024-V reference 46 VDDA POWER 47 P3.0 GPIO Port 3 Pin 0, analog/digital/lcd/csd 48 P3.1 GPIO Port 3 Pin 1, analog/digital/lcd/csd 49 P3.2 GPIO Port 3 Pin 2, analog/digital/lcd/csd 50 P3.3 GPIO Port 3 Pin 3, analog/digital/lcd/csd 51 P3.4 GPIO Port 3 Pin 4, analog/digital/lcd/csd 52 P3.5 GPIO Port 3 Pin 5, analog/digital/lcd/csd 53 P3.6 GPIO Port 3 Pin 6, analog/digital/lcd/csd 54 P3.7 GPIO 55 VSSA GROUND 56 VCCD POWER 57 EPAD GROUND Description 1.71-V to 5.5-V analog supply Port 3 Pin 7, analog/digital/lcd/csd Analog ground Regulated 1.8-V supply; connect to 1-µF capacitor Ground paddle for the QFN package Table 2 shows the pin list for the CYBL10X6X device (WLCSP package). Table 2. CYBL10X6X Pin List (WLCSP Package) Pin Name Type Description A1 VREF REF A2 VSSA GROUND 1.024-V reference A3 P3.3 GPIO Port 3 Pin 3, analog/digital/lcd/csd A4 P3.7 GPIO Port 3 Pin 7, analog/digital/lcd/csd A5 VSSD GROUND Digital ground A6 VSSA GROUND Analog ground A7 VCCD POWER Regulated 1.8-V supply, connect to 1-μF capacitor A8 VDDD POWER 1.71-V to 5.5-V digital supply Analog ground B1 P2.3 GPIO B2 VSSA GROUND B3 P2.7 GPIO Port 2 Pin 7, analog/digital/lcd/csd B4 P3.4 GPIO Port 3 Pin 4, analog/digital/lcd/csd B5 P3.5 GPIO Port 3 Pin 5, analog/digital/lcd/csd B6 P3.6 GPIO Port 3 Pin 6, analog/digital/lcd/csd B7 XTAL32I/P6.1 CLOCK 32.768-kHz crystal or external clock input B8 XTAL32O/P6.0 CLOCK 32.768-kHz crystal C1 VSSA GROUND C2 P2.2 GPIO Port 2 Pin 2, analog/digital/lcd/csd C3 P2.6 GPIO Port 2 Pin 6, analog/digital/lcd/csd C4 P3.0 GPIO Port 3 Pin 0, analog/digital/lcd/csd Document Number: 001-90478 Rev. *K Port 2 Pin 3, analog/digital/lcd/csd Analog ground Analog ground Page 9 of 42 PRoC BLE: CYBL10X6X Family Datasheet Table 2. CYBL10X6X Pin List (WLCSP Package) (continued) Pin Name Type C5 P3.1 GPIO Port 3 Pin 1, analog/digital/lcd/csd Description C6 P3.2 GPIO Port 3 Pin 2, analog/digital/lcd/csd C7 XRES RESET C8 P4.0 GPIO Port 4 Pin 0, analog/digital/lcd/csd D1 P1.7 GPIO Port 1 Pin 7, analog/digital/lcd/csd D2 VDDA POWER D3 P2.0 GPIO Port 2 Pin 0, analog/digital/lcd/csd D4 P2.1 GPIO Port 2 Pin 1, analog/digital/lcd/csd D5 P2.5 GPIO Port 2 Pin 5, analog/digital/lcd/csd D6 VSSD GROUND Reset, active LOW 1.71-V to 5.5-V analog supply Digital ground D7 P4.1 GPIO Port 4 Pin 1, analog/digital/lcd/csd D8 P5.0 GPIO Port 5 Pin 0, analog/digital/lcd/csd, overvoltage-tolerant E1 P1.2 GPIO Port 1 Pin 2, analog/digital/lcd/csd E2 P1.3 GPIO Port 1 Pin 3, analog/digital/lcd/csd E3 P1.4 GPIO Port 1 Pin 4, analog/digital/lcd/csd E4 P1.5 GPIO Port 1 Pin 5, analog/digital/lcd/csd E5 P1.6 GPIO Port 1 Pin 6, analog/digital/lcd/csd E6 P2.4 GPIO Port 2 Pin 4, analog/digital/lcd/csd Port 5 Pin 1, analog/digital/lcd/csd, overvoltage-tolerant E7 P5.1 GPIO E8 VSSD GROUND Digital ground F1 VSSD GROUND Digital ground F2 P0.7 GPIO Port 0 Pin 7, analog/digital/lcd/csd F3 P0.3 GPIO Port 0 Pin 3, analog/digital/lcd/csd F4 P1.0 GPIO Port 1 Pin 0, analog/digital/lcd/csd F5 P1.1 GPIO Port 1 Pin 1, analog/digital/lcd/csd F6 VSSR GROUND F7 VSSR GROUND F8 VDDR POWER G1 P0.6 GPIO G2 VDDD POWER Radio ground Radio ground 1.9-V to 5.5-V radio supply Port 0 Pin 6, analog/digital/lcd/csd 1.71-V to 5.5-V digital supply G3 P0.2 GPIO G4 VSSD GROUND Digital ground G5 VSSR GROUND Radio ground G6 VSSR GROUND Radio ground G7 GANT GROUND Antenna shielding ground G8 VSSR GROUND Radio ground H1 P0.5 GPIO Port 0 Pin 5, analog/digital/lcd/csd H2 P0.1 GPIO Port 0 Pin 1, analog/digital/lcd/csd H3 XTAL24O CLOCK 24-MHz crystal H4 XTAL24I CLOCK 24-MHz crystal or external clock input Document Number: 001-90478 Rev. *K Port 0 Pin 2, analog/digital/lcd/csd Page 10 of 42 PRoC BLE: CYBL10X6X Family Datasheet Table 2. CYBL10X6X Pin List (WLCSP Package) (continued) Pin Name Type H5 VSSR GROUND Radio ground Description H6 VSSR GROUND Radio ground H7 ANT ANTENNA J1 P0.4 GPIO Port 0 Pin 4, analog/digital/lcd/csd J2 P0.0 GPIO Port 0 Pin 0, analog/digital/lcd/csd J3 VDDR POWER 1.9-V to 5.5-V radio supply J6 VDDR POWER 1.9-V to 5.5-V radio supply J7 NO CONNECT - Antenna pin The I/O subsystem consists of a high-speed I/O matrix (HSIOM), which is a group of high-speed switches that routes GPIOs to the resources inside the device. These resources include CapSense, TCPWMs, I2C, SPI, UART, and LCD. HSIOM_PORT_SELx are 32-bit-wide registers that control the routing of GPIOs. Each register controls one port; four dedicated bits are assigned to each GPIO in the port. This provides up to 16 different options for GPIO routing as shown in Table 3. Table 3. HSIOM Port Settings Value Description 0 Firmware-controlled GPIO 1 Reserved 2 Reserved 3 Reserved 4 Pin is a CSD sense pin 5 Pin is a CSD shield pin 6 Pin is connected to AMUXA 7 Pin is connected to AMUXB 8 Pin-specific Active function #0 9 Pin-specific Active function #1 10 Pin-specific Active function #2 11 Reserved 12 Pin is an LCD common pin 13 Pin is an LCD segment pin 14 Pin-specific Deep-Sleep function #0 15 Pin-specific Deep-Sleep function #1 The selection of peripheral functions for different GPIO pins is given in Table 4. Table 4. Port Pin Connections Digital (HSIOM_PORT_SELx.SELy) ('x' denotes port number and 'y' denotes pin number) Name Analog 0 8 9 10 14 15 GPIO Active #0 Active #1 Active #2 Deep Sleep #0 Deep Sleep #1 P0.0 GPIO TCPWM0_P[3] SCB1_UART_RX[1] SCB1_I2C_SDA[1] SCB1_SPI_MOSI[1] P0.1 GPIO TCPWM0_N[3] SCB1_UART_TX[1] SCB1_I2C_SCL[1] SCB1_SPI_MISO[1] P0.3 GPIO TCPWM1_N[3] SCB1_UART_CTS[1] P0.4 GPIO TCPWM1_P[0] SCB0_UART_RX[1] P0.5 GPIO TCPWM1_N[0] SCB0_UART_TX[1] Document Number: 001-90478 Rev. *K SCB1_SPI_SCLK[1] EXT_CLK[0]/ ECO_OUT[0] SCB0_I2C_SDA[1] SCB0_SPI_MOSI[1] SCB0_I2C_SCL[1] SCB0_SPI_MISO[1] Page 11 of 42 PRoC BLE: CYBL10X6X Family Datasheet Table 4. Port Pin Connections (continued) Digital (HSIOM_PORT_SELx.SELy) ('x' denotes port number and 'y' denotes pin number) Name Analog 0 8 9 10 14 Active #2 15 GPIO Active #0 Active #1 Deep Sleep #0 Deep Sleep #1 P0.6 GPIO TCPWM2_P[0] SCB0_UART_RTS[1] SWDIO[0] SCB0_SPI_SS0[1] P0.7 GPIO TCPWM2_N[0] SCB0_UART_CTS[1] SWDCLK[0] SCB0_SPI_SCLK[1] P1.0 GPIO TCPWM0_P[1] WCO_OUT[2] P1.1 GPIO TCPWM0_N[1] SCB1_SPI_SS1 P1.2 GPIO TCPWM1_P[1] SCB1_SPI_SS2 P1.3 GPIO TCPWM1_N[1] SCB1_SPI_SS3 P1.4 GPIO TCPWM2_P[1] SCB0_UART_RX[0] SCB0_I2C_SDA[0] SCB0_SPI_MOSI[1] P1.5 GPIO TCPWM2_N[1] SCB0_UART_TX[0] SCB0_I2C_SCL[0] SCB0_SPI_MISO[1] P1.6 GPIO TCPWM3_P[1] SCB0_UART_RTS[0] SCB0_SPI_SS0[1] P1.7 GPIO TCPWM3_N[1] SCB0_UART_CTS[0] SCB0_SPI_SCLK[1] P2.0 GPIO SCB0_SPI_SS1 P2.1 GPIO SCB0_SPI_SS2 P2.2 GPIO P2.3 GPIO P2.4 GPIO P2.5 GPIO P2.6 GPIO P2.7 GPIO P3.0 SARMUX_0 GPIO TCPWM0_P[2] SCB0_UART_RX[2] SCB0_I2C_SDA[2] P3.1 SARMUX_1 GPIO TCPWM0_N[2] SCB0_UART_TX[2] SCB0_I2C_SCL[2] P3.2 SARMUX_2 GPIO TCPWM1_P[2] SCB0_UART_RTS[2] P3.3 SARMUX_3 GPIO TCPWM1_N[2] SCB0_UART_CTS[2] P3.4 SARMUX_4 GPIO TCPWM2_P[2] SCB1_UART_RX[2] SCB1_I2C_SDA[2] P3.5 SARMUX_5 GPIO TCPWM2_N[2] SCB1_UART_TX[2] SCB1_I2C_SCL[2] P3.6 SARMUX_6 GPIO TCPWM3_P[2] SCB1_UART_RTS[2] P3.7 SARMUX_7 GPIO TCPWM3_N[2] SCB1_UART_CTS[2] WCO_OUT[0] WAKEUP SCB0_SPI_SS3 WCO_OUT[1] EXT_CLK[1]/ ECO_OUT[1] P4.0 CMOD GPIO TCPWM0_P[0] SCB1_UART_RTS[0] SCB1_SPI_MOSI[0] P4.1 CTANK GPIO TCPWM0_N[0] SCB1_UART_CTS[0] SCB1_SPI_MISO[0] P5.0 GPIO TCPWM3_P[0] SCB1_UART_RX[0] EXTPA_EN SCB1_I2C_SDA[0] SCB1_SPI_SS0[0] P5.1 GPIO TCPWM3_N[0] SCB1_UART_TX[0] EXT_CLK[2]/ ECO_OUT[2] SCB1_I2C_SCL[0] SCB1_SPI_SCLK[0] P6.0_XTAL32O GPIO P6.1_XTAL32I GPIO Document Number: 001-90478 Rev. *K Page 12 of 42 PRoC BLE: CYBL10X6X Family Datasheet Power Power Supply PRoC BLE can be supplied from batteries with a voltage range of 1.9 V to 5.5 V by directly connecting to the digital supply (VDDD), analog supply (VDDA), and radio supply (VDDR) pins. The internal LDOs in the device regulate the supply voltage to required levels for different blocks. The device has one regulator for the digital circuitry and separate regulators for radio circuitry for noise isolation. The analog circuits run directly from the analog supply (VDDA) input. The device uses separate regulators for Deep Sleep and Hibernate modes to minimize the power consumption. The radio stops working below 1.9 V, but the rest of the system continues to function down to 1.71 V without RF. Note that VDDR must be supplied whenever VDDD is supplied. Bypass capacitors must be used from VDDx (x = A, D, or R) to ground. The typical practice for systems in this frequency range is to use a capacitor in the 1-µF range in parallel with a smaller capacitor (for example, 0.1 µF). Note that these are simply rules of thumb and that, for critical applications, the PCB layout, lead inductance, and the bypass capacitor parasitic should be simulated to design to obtain optimal bypassing. Bypass Capacitors VDDD 0.1-µF ceramic at each pin plus bulk capacitor 1 µF to 10 µF VDDA 0.1-µF ceramic at each pin plus bulk capacitor 1 µF to 10 µF VDDR 0.1-µF ceramic at each pin plus bulk capacitor 1 µF to 10 µF VCCD 1-µF ceramic capacitor at the VCCD pin VREF (optional) The internal bandgap may be bypassed with a 1-µF to 10-µF capacitor Low-Power Modes PRoC BLE supports five power modes. Refer to Table 5 for more details on the system status. The PRoC BLE device consumes the lowest current in Stop mode; the device wakeup from stop mode is with a system reset through the XRES or WAKEUP pin. It can retain the SRAM data in Hibernate mode and is capable of retaining the complete system status in Deep-Sleep mode. Table 5 shows the different power modes and the peripherals that are active. Table 5. Power Modes System Status Current Consumption Code Execution Digital Peripherals Available Analog Peripherals Available Clock Sources Available Wake Up Sources Wake-Up Time Active 850 µA + 260 µA per MHz[1] Yes All All All – – Sleep 1.1 mA at 3 MHz No All All All Any interrupt source 0 Deep Sleep 1.3 μA No WDT, LCD, I2C/SPI, Link-Layer POR, BOD WCO, ILO GPIO, WDT, I2C/SPI Link Layer 25 μs Hibernate 150 nA No No POR, BOD No GPIO 2 ms Stop 60 nA No No No No Wake-Up pin, XRES 2 ms Power Mode Note 1. For CPU subsystem. Document Number: 001-90478 Rev. *K Page 13 of 42 PRoC BLE: CYBL10X6X Family Datasheet A typical system application connection diagram for the 56-QFN package is shown in Figure 4. Figure 4. PRoC BLE Applications Diagram VDDA C1 1.0 uF C4 18 pF U1 2 EPAD VCCD VSSA P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 VDDA VREF P2.7 P2.6 Y2 1 VDDD 1 2 ANTENNA VDDR 1 2 C6 L1 PRoC BLE 56-QFN VDDR P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 VDDA P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VDDA 15 16 17 18 19 20 21 22 23 24 25 26 27 28 C5 VDDD XTAL32O/P6.0 XTAL32I/P6.1 XRES P4.0 P4.1 P5.0 P5.1 VSS VDDR GANT1 ANT GANT2 VDDR VDDR XTAL24I XTAL24O VDDR P0.0 P0.1 P0.2 P0.3 VDDD P0.4 P0.5 P0.6 P0.7 P1.0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 32.768KHz 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 C3 36 pF C2 1.0 uF 1 VDDD 2 3 Y1 24MHz 4 SWDIO SWDCLK VDDR Document Number: 001-90478 Rev. *K Page 14 of 42 PRoC BLE: CYBL10X6X Family Datasheet Development Support The CYBL10X6X family has a rich set of documentation, development tools, and online resources to assist you during your development process. Visit www.cypress.com/procble to find out more. Documentation A suite of documentation supports the CYBL10X6X family to ensure that you find answers to your questions quickly. This section contains a list of some of the key documents. Component Datasheets: PSoC Creator Components provide hardware abstraction using APIs to configure and control peripheral activity. The Component datasheet covers Component features, its usage and operation details, API description, and electrical specifications. This is the primary documentation used during development. These Components can represent peripherals on the device (such as a timer, I2C, or UART) or high-level system functions (such as the BLE Component). Application Notes: Application notes help you to understand how to use various device features. They also provide guidance on how to solve a variety of system design challenges. Document Number: 001-90478 Rev. *K Technical Reference Manual (TRM): The TRM describes all peripheral functionality in detail, with register-level descriptions. This document is divided into two parts: the Architecture TRM and the Register TRM. Online In addition to the print documentation, Cypress forums connect you with fellow users and experts from around the world, 24 hours a day, 7 days a week. Tools With industry-standard cores, programming, and debugging interfaces, the CYBL10X6X family is part of a development tool ecosystem. Visit us at www.cypress.com/go/psoccreator for the latest information on the revolutionary, easy-to-use PSoC Creator IDE, supported third-party compilers, programmers, and debuggers. Kits Cypress provides a portfolio of kits to accelerate time-to-market. Visit us at www.cypress.com/procble. Page 15 of 42 PRoC BLE: CYBL10X6X Family Datasheet Electrical Specifications Exposure to absolute maximum conditions for extended periods of time may affect device reliability. This section provides detailed electrical characteristics. Absolute maximum rating for the CYBL10X6X devices is listed in the following table. Usage above the absolute maximum conditions may cause permanent damage to the device. The maximum storage temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature Storage Life. When used below absolute maximum conditions, but above normal operating conditions, the device may not operate to the specification. Absolute Maximum Ratings Table 6. Absolute Maximum Ratings Spec ID# Parameter Description Min Typ Max Units Details/ Conditions SID1 VDDD_ABS Analog, digital, or radio supply relative to VSS (VSSD = VSSA) –0.5 – 6 V Absolute max SID2 VCCD_ABS Direct digital core voltage input relative to VSSD –0.5 – 1.95 V Absolute max SID3 VGPIO_ABS GPIO voltage –0.5 – VDD +0.5 V Absolute max SID4 IGPIO_ABS Maximum current per GPIO –25 – 25 mA Absolute max SID5 IGPIO_injection GPIO injection current, Max for VIH > VDDD, and Min for VIL < VSS –0.5 – 0.5 mA Absolute max, current injected per pin BID57 ESD_HBM Electrostatic discharge human body model 2200[2] – – V BID58 ESD_CDM Electrostatic discharge charged device model 500 – – V BID61 LU Pin current for latch up –200 – 200 mA BLE Subsystem Table 7. BLE Subsystem Spec ID# Parameter RF Receiver Specifications SID340 RXS, IDLE Description Min Typ Max Units RX sensitivity with idle transmitter – –89 – dBm Details/ Conditions SID340A RXS, IDLE RX sensitivity with idle transmitter excluding balun loss – –91 – dBm Guaranteed by design simulation SID341 RXS, DIRTY RX sensitivity with dirty transmitter – –87 – dBm RF-PHY Specification (RCV-LE/CA/01/C) SID342 RXS, HIGHGAIN RX sensitivity in high-gain mode with idle transmitter – –91 – dBm SID343 PRXMAX Maximum input power –10 –1 – dBm RF-PHY Specification (RCV-LE/CA/06/C) SID344 CI1 Co-channel interference, Wanted signal at –67 dBm and Interferer at FRX – 9 21 dB RF-PHY Specification (RCV-LE/CA/03/C) Note 2. This does not apply to the RF pins (ANT, XTALI, and XTALO). RF pins (ANT, XTALI, and XTALO) are tested for 500-V HBM. Document Number: 001-90478 Rev. *K Page 16 of 42 PRoC BLE: CYBL10X6X Family Datasheet Table 7. BLE Subsystem (continued) Spec ID# Parameter Description Min Typ Max Units Details/ Conditions SID345 CI2 Adjacent channel interference Wanted signal at –67 dBm and Interferer at FRX ±1 MHz – 3 15 dB RF-PHY Specification (RCV-LE/CA/03/C) SID346 CI3 Adjacent channel interference Wanted signal at –67 dBm and Interferer at FRX ±2 MHz – –29 – dB RF-PHY Specification (RCV-LE/CA/03/C) SID347 CI4 Adjacent channel interference Wanted signal at –67 dBm and Interferer at ≥FRX ±3 MHz – –39 – dB RF-PHY Specification (RCV-LE/CA/03/C) SID348 CI5 Adjacent channel interference Wanted Signal at –67 dBm and Interferer at Image frequency (FIMAGE) – –20 – dB RF-PHY Specification (RCV-LE/CA/03/C) SID349 CI3 Adjacent channel interference Wanted signal at –67 dBm and Interferer at Image frequency (FIMAGE ± 1 MHz) – –30 – dB RF-PHY Specification (RCV-LE/CA/03/C) SID350 OBB1 Out-of-band blocking, Wanted signal at –67 dBm and Interferer at F = 30–2000 MHz –30 –27 – dBm RF-PHY Specification (RCV-LE/CA/04/C) SID351 OBB2 Out-of-band blocking, Wanted signal at –67 dBm and Interferer at F = 2,003–2,399 MHz –35 –27 – dBm RF-PHY Specification (RCV-LE/CA/04/C) SID352 OBB3 Out-of-band blocking, Wanted signal at –67 dBm and Interferer at F = 2,484–2,997 MHz –35 –27 – dBm RF-PHY Specification (RCV-LE/CA/04/C) SID353 OBB4 Out-of-band blocking, Wanted signal a –67 dBm and Interferer at F = 3,000–12,750 MHz –30 –27 – dBm RF-PHY Specification (RCV-LE/CA/04/C) SID354 IMD Intermodulation performance Wanted signal at –64 dBm and 1-Mbps BLE, third, fourth, and fifth offset channel –50 – – dBm RF-PHY Specification (RCV-LE/CA/05/C) SID355 RXSE1 Receiver spurious emission 30 MHz to 1.0 GHz – – –57 dBm 100-kHz measurement bandwidth ETSI EN300 328 V1.8.1 SID356 RXSE2 Receiver spurious emission 1.0 GHz to 12.75 GHz – – –47 dBm 1-MHz measurement bandwidth ETSI EN300 328 V1.8.1 RF Transmitter Specifications SID357 TXP, ACC RF power accuracy – ±1 – dB SID358 TXP, RANGE RF power control range – 20 – dB SID359 TXP, 0 dBm Output power, 0-dB gain setting (PA7) – 0 – dBm Document Number: 001-90478 Rev. *K Page 17 of 42 PRoC BLE: CYBL10X6X Family Datasheet Table 7. BLE Subsystem (continued) Spec ID# Parameter Description Min Typ Max Units Details/ Conditions SID360 TXP, MAX Output power, maximum power setting (PA10) – 3 – dBm SID361 TXP, MIN Output power, minimum power setting (PA1) – –18 – dBm SID362 F2AVG Average frequency deviation for 10101010 pattern 185 – – kHz RF-PHY Specification (TRM-LE/CA/05/C) SID363 F1AVG Average frequency deviation for 11110000 pattern 225 250 275 kHz RF-PHY Specification (TRM-LE/CA/05/C) SID364 EO Eye opening = ∆F2AVG/∆F1AVG 0.8 – – SID365 FTX, ACC Frequency accuracy –150 – 150 kHz RF-PHY Specification (TRM-LE/CA/06/C) SID366 FTX, MAXDR Maximum frequency drift –50 – 50 kHz RF-PHY Specification (TRM-LE/CA/06/C) SID367 FTX, INITDR Initial frequency drift –20 – 20 kHz RF-PHY Specification (TRM-LE/CA/06/C) SID368 FTX,DR Maximum drift rate –20 – 20 kHz/ 50 µs RF-PHY Specification (TRM-LE/CA/06/C) SID369 IBSE1 In-band spurious emission at 2-MHz offset – – –20 dBm RF-PHY Specification (TRM-LE/CA/03/C) SID370 IBSE2 In-band spurious emission at ≥3-MHz offset – – –30 dBm RF-PHY Specification (TRM-LE/CA/03/C) SID371 TXSE1 Transmitter spurious emissions (average), <1.0 GHz – – –55.5 dBm FCC-15.247 SID372 TXSE2 Transmitter spurious emissions (average), >1.0 GHz – – –41.5 dBm FCC-15.247 RF-PHY Specification (TRM-LE/CA/05/C) RF Current Specification SID373 IRX Receive current in normal mode – 18.7 – mA SID373A IRX_RF Receive current in normal mode – 16.4 – mA SID374 IRX, HIGHGAIN Receive current in high-gain mode – 21.5 – mA SID375 ITX, 3 dBm TX current at 3-dBm setting (PA10) – 20 – mA SID376 ITX, 0 dBm TX current at 0-dBm setting (PA7) – 16.5 – mA SID376A ITX_RF, 0 dBm TX current at 0-dBm setting (PA7) – 15.6 – mA Measured at VDDR SID376B ITX_RF, 0 dBm TX current at 0 dBm excluding Balun loss – 14.2 – mA Guaranteed by design simulation SID377 ITX, -3 dBm TX current at –3-dBm setting (PA4) – 15.5 – mA SID378 ITX, -6 dBm TX current at –6-dBm setting (PA3) – 14.5 – mA SID379 ITX, -12 dBm TX current at –12-dBm setting (PA2) – 13.2 – mA SID380 ITX, -18 dBm TX current at –18-dBm setting (PA1) – 12.5 – mA SID380A Iavg_1sec, 0dBm Average current at 1-second BLE connection interval – 18.9 – µA Document Number: 001-90478 Rev. *K Measured at VDDR TXP: 0 dBm; ±20-ppm master and slave clock accuracy. For empty PDU exchange Page 18 of 42 PRoC BLE: CYBL10X6X Family Datasheet Table 7. BLE Subsystem (continued) Spec ID# SID380B Parameter Description Iavg_4sec, 0dBm Average current at 4-second BLE connection interval Min Typ Max Units Details/ Conditions – 6.25 – µA TXP: 0 dBm; ±20-ppm master and slave clock accuracy. For empty PDU exchange 2400 – 2482 MHz General RF Specification SID381 FREQ RF operating frequency SID382 CHBW Channel spacing – 2 – MHz SID383 DR On-air data rate – 1000 – kbps SID384 IDLE2TX BLE Radio Idle to BLE Radio TX transition time – 120 140 µs SID385 IDLE2RX BLE Radio Idle to BLE Radio RX transition time – 75 120 µs RSSI Specification SID386 RSSI, ACC RSSI accuracy – ±5 – dB SID387 RSSI, RES RSSI resolution – 1 – dB SID388 RSSI, PER RSSI sample period – 6 – µs Device-Level Specifications All specifications are valid for –40 °C TA 105 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted. Table 8. DC Specifications Spec ID# Parameter Description Min Typ Max Units Details/ Conditions SID6 VDD Power supply input voltage (VDDA = VDDD = VDD) 1.8 – 5.5 V SID7 VDD Power supply input voltage unregulated (VDDA = VDDD = VDD) 1.71 1.8 1.89 V SID8 VDDR Radio supply voltage (Radio on) 1.9 – 5.5 V SID8A VDDR Radio supply voltage (Radio off) 1.71 – 5.5 V SID9 VCCD Digital regulator output voltage (for core logic) – 1.8 – V SID10 CVCCD Digital regulator output bypass capacitor 1 1.3 1.6 µF Execute from flash; CPU at 3 MHz – 1.7 – mA T = 25 °C, VDD = 3.3 V With regulator enabled Internally unregulated supply X5R ceramic or better Active Mode, VDD = 1.71 V to 5.5 V SID13 IDD3 SID14 IDD4 Execute from flash; CPU at 3 MHz – – – mA T = –40 °C to 105 °C SID15 IDD5 Execute from flash; CPU at 6 MHz – 2.5 – mA T = 25 °C, VDD = 3.3 V SID16 IDD6 Execute from flash; CPU at 6 MHz – – – mA T = –40 °C to 105 °C SID17 IDD7 Execute from flash; CPU at 12 MHz – 4 – mA T = 25 °C, VDD = 3.3 V SID18 IDD8 Execute from flash; CPU at 12 MHz – – – mA T = –40 °C to 105 °C Document Number: 001-90478 Rev. *K Page 19 of 42 PRoC BLE: CYBL10X6X Family Datasheet Table 8. DC Specifications (continued) Spec ID# SID19 Parameter Description Min Typ Max Units IDD9 Execute from flash; CPU at 24 MHz – 7.1 – mA Details/ Conditions T = 25 °C, VDD = 3.3 V SID20 IDD10 Execute from flash; CPU at 24 MHz – – – mA T = –40 °C to 105 °C SID21 IDD11 Execute from flash; CPU at 48 MHz – 13.4 – mA T = 25 °C, VDD = 3.3 V SID22 IDD12 Execute from flash; CPU at 48 MHz – – – mA T = –40 °C to 105 °C – – – mA T = 25 °C, VDD = 3.3 V, SYSCLK = 3 MHz – – – mA T = 25 °C, VDD = 3.3 V, SYSCLK = 3 MHz Sleep Mode, VDD = 1.8 V to 5.5 V SID23 IDD13 IMO on Sleep Mode, VDD and VDDR = 1.9 V to 5.5 V SID24 IDD14 ECO on Deep-Sleep Mode, VDD = 1.8 V to 3.6 V SID25 IDD15 WDT with WCO on – 1.3 – µA T = 25 °C, VDD = 3.3 V SID26 IDD16 WDT with WCO on – – – µA T = –40 °C to 105 °C Deep-Sleep Mode, VDD = 3.6 V to 5.5 V SID27 IDD17 WDT with WCO on – – – µA T = 25 °C, VDD = 5 V SID28 IDD18 WDT with WCO on – – – µA T = –40 °C to 105 °C Deep-Sleep Mode, VDD = 1.71 V to 1.89 V (Regulator Bypassed) SID29 IDD19 WDT with WCO on – – – µA T = 25 °C SID30 IDD20 WDT with WCO on – – – µA T = –40 °C to 105 °C Hibernate Mode, VDD = 1.8 V to 3.6 V SID37 IDD27 GPIO and reset active – 150 – nA T = 25 °C, VDD = 3.3 V SID38 IDD28 GPIO and reset active – – – nA T = –40 °C to 105 °C Hibernate Mode, VDD = 3.6 V to 5.5 V SID39 IDD29 GPIO and reset active – – – nA T = 25 °C, VDD = 5 V SID40 IDD30 GPIO and reset active – – – nA T = –40 °C to 105 °C Hibernate Mode, VDD = 1.71 V to 1.89 V (Regulator Bypassed) SID41 IDD31 GPIO and reset active – – – nA T = 25 °C SID42 IDD32 GPIO and reset active – – – nA T = –40 °C to 105 °C Stop Mode, VDD = 1.8 V to 3.6 V SID43 IDD33 Stop-mode current (VDD) – 20 – nA T = 25 °C, VDD = 3.3 V SID44 IDD34 Stop-mode current (VDDR) – 40 –- nA T = 25 °C, VDDR = 3.3 V SID45 IDD35 Stop-mode current (VDD) – – – nA T = –40 °C to 105 °C SID46 IDD36 Stop-mode current (VDDR) – – – nA T = –40 °C to 105 °C, VDDR = 1.9 V to 3.6 V Document Number: 001-90478 Rev. *K Page 20 of 42 PRoC BLE: CYBL10X6X Family Datasheet Table 8. DC Specifications (continued) Spec ID# Parameter Description Min Typ Max Units Details/ Conditions Stop Mode, VDD = 3.6 V to 5.5 V SID47 IDD37 Stop-mode current (VDD) – – – nA T = 25 °C, VDD = 5 V SID48 IDD38 Stop-mode current (VDDR) – – – nA T = 25 °C, VDDR = 5 V SID49 IDD39 Stop-mode current (VDD) – – – nA T = –40 °C to 105 °C SID50 IDD40 Stop-mode current (VDDR) – – – nA T = –40 °C to 105 °C Stop Mode, VDD = 1.71 V to 1.89 V (Regulator Bypassed) SID51 IDD41 Stop-mode current (VDD) – – – nA T = 25 °C SID52 IDD42 Stop-mode current (VDD) – – – nA T = –40 °C to 105 °C Table 9. AC Specifications Spec ID# Parameter Description Min Typ Max Units Details/ Conditions 1.71 V VDD 5.5 V SID53 FCPU CPU frequency DC – 48 MHz SID54 TSLEEP Wakeup from Sleep mode – 0 – µs Guaranteed by characterization SID55 TDEEPSLEEP Wakeup from Deep-Sleep mode – – 25 µs 24-MHz IMO. Guaranteed by characterization SID56 THIBERNATE Wakeup from Hibernate mode – – 2 ms Guaranteed by characterization SID57 TSTOP Wakeup from Stop mode – – 2 ms Guaranteed by characterization Min Typ Max Units GPIO Table 10. GPIO DC Specifications Spec ID# Parameter Description Details/ Conditions SID58 VIH Input voltage HIGH threshold 0.7 × VDD – – V CMOS input SID59 VIL Input voltage LOW threshold – – 0.3 × VDD V CMOS input SID60 VIH LVTTL input, VDD < 2.7 V 0.7 × VDD – - V SID61 VIL LVTTL input, VDD < 2.7 V – – 0.3× VDD V SID62 VIH LVTTL input, VDD ≥ 2.7 V 2.0 – - V SID63 VIL LVTTL input, VDD ≥ 2.7 V – – 0.8 V SID64 VOH Output voltage HIGH level VDD –0.6 – – V IOH = 4 mA at 3.3-V VDD SID65 VOH Output voltage HIGH level VDD –0.5 – – V IOH = 1 mA at 1.8-V VDD SID66 VOL Output voltage LOW level – – 0.6 V IOL = 8 mA at 3.3-V VDD SID67 VOL Output voltage LOW level – – 0.6 V IOL = 4 mA at 1.8-V VDD Note 3. VIH must not exceed VDD + 0.2 V. Document Number: 001-90478 Rev. *K Page 21 of 42 PRoC BLE: CYBL10X6X Family Datasheet Table 10. GPIO DC Specifications (continued) Spec ID# SID68 Parameter Description VOL Output voltage LOW level Min Typ Max Units – – 0.4 V SID69 RPULLUP Pull-up resistor 3.5 5.6 8.5 kΩ SID70 RPULLDOWN Pull-down resistor 3.5 5.6 8.5 kΩ SID71 IIL Input leakage current (absolute value) – – 2 nA SID72 IIL_CTBM Input leakage on CTBm input pins – – 4 nA SID73 CIN Input capacitance – – 7 pF SID74 VHYSTTL Input hysteresis LVTTL 25 40 SID75 VHYSCMOS Input hysteresis CMOS 0.05 × VDD – – mV SID76 IDIODE Current through protection diode to VDD/VSS – – 100 µA SID77 ITOT_GPIO Maximum total source or sink chip current – – 200 mA mV Details/ Conditions IOL = 3 mA at 3.3-V VDD 25 °C, VDD = 3.3 V VDD > 2.7 V Except for overvoltage-tolerant pins (P5.0 and P5.1) Table 11. GPIO AC Specifications Spec ID# Parameter Description Min Typ Max Units Details/ Conditions SID78 TRISEF Rise time in Fast-Strong mode 2 – 12 ns 3.3-V VDDD, CLOAD = 25 pF SID79 TFALLF Fall time in Fast-Strong mode 2 – 12 ns 3.3-V VDDD, CLOAD = 25 pF SID80 TRISES Rise time in Slow-Strong mode 10 – 60 ns 3.3-V VDDD, CLOAD = 25 pF SID81 TFALLS Fall time in Slow-Strong mode 10 – 60 ns 3.3-V VDDD, CLOAD = 25 pF SID82 FGPIOUT1 GPIO Fout; 3.3 V VDD 5.5 V. Fast-Strong mode – – 33 MHz 90/10%, 25-pF load, 60/40 duty cycle SID83 FGPIOUT2 GPIO Fout; 1.7 VVDD 3.3 V. Fast-Strong mode – – 16.7 MHz 90/10%, 25-pF load, 60/40 duty cycle SID84 FGPIOUT3 GPIO Fout; 3.3 V VDD 5.5 V. Slow-Strong mode – – 7 MHz 90/10%, 25-pF load, 60/40 duty cycle SID85 FGPIOUT4 GPIO Fout; 1.7 V VDD 3.3 V. Slow-Strong mode – – 3.5 MHz 90/10%, 25-pF load, 60/40 duty cycle SID86 FGPIOIN GPIO input operating frequency. 1.71 V VDD 5.5 V – – 48 MHz 90/10% VIO Min Typ Max Units Details/ Conditions 10 µA 25°C, VDD = 0 V, VIH = 3.0 V 0.4 V IOL = 20 mA, VDD > 2.9 V Table 12. OVT GPIO DC Specifications (P5_0 and P5_1 Only) Spec ID# Parameter Description SID71A IIL Input leakage (absolute value). VIH > VDD SID66A VOL Output voltage LOW level Document Number: 001-90478 Rev. *K – – Page 22 of 42 PRoC BLE: CYBL10X6X Family Datasheet Table 13. OVT GPIO AC Specifications (P5_0 and P5_1 Only) Spec ID# Parameter Description Min Typ Max Units Details/ Conditions SID78A TRISE_OVFS Output rise time in Fast-Strong mode 1.5 – 12 ns 25-pF load, 10%–90%, VDD=3.3 V SID79A TFALL_OVFS Output fall time in Fast-Strong mode 1.5 – 12 ns 25-pF load, 10%–90%, VDD=3.3 V SID80A TRISESS Output rise time in Slow-Strong mode 10 – 60 ns 25-pF load, 10%-90%, VDD = 3.3 V SID81A TFALLSS Output fall time in Slow-Strong mode 10 – 60 ns 25-pF load, 10%-90%, VDD = 3.3 V SID82A FGPIOUT1 GPIO FOUT; 3.3 V ≤ VDD ≤ 5.5 V Fast-Strong mode – – 24 MHz 90/10%, 25-pF load, 60/40 duty cycle SID83A FGPIOUT2 GPIO FOUT; 1.71 V ≤ VDD ≤ 3.3 V Fast-Strong mode – – 16 MHz 90/10%, 25-pF load, 60/40 duty cycle Min Typ Max Units 0.7 × VDDD – – V CMOS input – – 0.3 × VDDD V CMOS input 3.5 5.6 8.5 kΩ XRES Table 14. XRES DC Specifications Spec ID# Parameter Description SID87 VIH Input voltage HIGH threshold SID88 VIL Input voltage LOW threshold SID89 RPULLUP Pull-up resistor SID90 CIN Input capacitance – 3 – pF SID91 VHYSXRES Input voltage hysteresis – 100 – mV SID92 IDIODE Current through protection diode to VDD/VSS – – 100 µA Details/ Conditions Table 15. XRES AC Specifications Spec ID# SID93 Parameter TRESETWIDTH Description Reset pulse width Document Number: 001-90478 Rev. *K Min Typ Max Units 1 – – µs Details/ Conditions Page 23 of 42 PRoC BLE: CYBL10X6X Family Datasheet Analog Peripherals Temperature Sensor Table 16. Temperature Sensor Specifications Spec ID# SID155 Parameter TSENSACC Description Temperature sensor accuracy Min Typ Max Units Details/Conditions –5 ±1 5 °C –40 to +85 °C SAR ADC Table 17. SAR ADC DC Specifications Spec ID# Parameter Description Resolution Min Typ Max Units – – 12 bits Details/Conditions SID156 A_RES SID157 A_CHNIS_S Number of channels – single-ended – – 8 8 full-speed SID158 A-CHNKS_D Number of channels – differential – – 4 Differential inputs use neighboring I/O SID159 A-MONO Monotonicity – – – SID160 A_GAINERR Gain error – – ±0.1 % SID161 A_OFFSET Input offset voltage – – 2 mV SID162 A_ISAR Current consumption – – 1 mA Yes SID163 A_VINS Input voltage range – single-ended VSS – VDDA V SID164 A_VIND Input voltage range – differential VSS – VDDA V SID165 A_INRES Input resistance – – 2.2 kΩ SID166 A_INCAP Input capacitance – – 10 pF SID312 VREFSAR Trimmed internal reference to SAR –1 – 1 % Min Typ Max Units dB With external reference Measured with 1-V VREF Percentage of Vbg (1.024 V) Table 18. SAR ADC AC Specifications Spec ID# Parameter Description SID167 A_PSRR Power supply rejection ratio 70 – – SID168 A_CMRR Common-mode rejection ratio 66 – – dB SID169 A_SAMP Sample rate – – 1 Msps SID313 Fsarintref SAR operating speed without external reference bypass – – 100 Ksps Details/ Conditions Measured at 1-V reference 12-bit resolution SID170 A_SNR Signal-to-noise ratio (SNR) 65 – – dB SID171 A_BW Input bandwidth without aliasing – – A_SAMP/ 2 kHz SID172 A_INL Integral nonlinearity (INL). VDD = 1.71 V to 5.5 V, 1 Msps –1.7 – 2 LSB VREF = 1 V to VDD SID173 A_INL Integral nonlinearity. VDDD = 1.71 V to 3.6 V, 1 Msps –1.5 – 1.7 LSB VREF = 1.71 V to VDD SID174 A_INL Integral nonlinearity. VDD = 1.71 V to 5.5 V, 500 Ksps –1.5 – 1.7 LSB VREF = 1 V to VDD Document Number: 001-90478 Rev. *K FIN = 10 kHz Page 24 of 42 PRoC BLE: CYBL10X6X Family Datasheet Table 18. SAR ADC AC Specifications (continued) Spec ID# Parameter Description Min Typ Max Units Details/ Conditions SID175 A_DNL Differential nonlinearity (DNL). VDD = 1.71 V to 5.5 V, 1 Msps –1 – 2.2 LSB VREF = 1 V to VDD SID176 A_DNL Differential nonlinearity. VDD = 1.71 V to 3.6 V, 1 Msps –1 – 2 LSB VREF = 1.71 V to VDD SID177 A_DNL Differential nonlinearity. VDD = 1.71 V to 5.5 V, 500 Ksps –1 – 2.2 LSB VREF = 1 V to VDD SID178 A_THD Total harmonic distortion – – –65 dB Description Min Typ Max Units 1.71 – 5.5 V FIN = 10 kHz CSD Table 19. CSD Block Specifications Spec ID# Parameter SID179 VCSD Voltage range of operation SID180 IDAC1 DNL for 8-bit resolution –1 – 1 LSB IDAC1 INL for 8-bit resolution –3 – 3 LSB SID182 IDAC2 DNL for 7-bit resolution –1 – 1 LSB SID183 IDAC2 INL for 7-bit resolution –3 – 3 LSB SID184 SNR Ratio of counts of finger to noise 5 – – Ratio SID185 IDAC1_CRT1 Output current of IDAC1 (8 bits) in HIGH range – 612 – µA SID186 IDAC1_CRT2 Output current of IDAC1 (8 bits) in LOW range – 306 – µA SID187 IDAC2_CRT1 Output current of IDAC2 (7 bits) in HIGH range – 305 – µA SID188 IDAC2_CRT2 Output current of IDAC2 (7 bits) in LOW range – 153 – µA SID181 Document Number: 001-90478 Rev. *K Details/ Conditions Capacitance range of 9 pF to 35 pF; 0.1-pF sensitivity. Radio is not operating during the scan Page 25 of 42 PRoC BLE: CYBL10X6X Family Datasheet Digital Peripherals 4x TCPWM Table 20. Timer DC Specifications Spec ID SID189 Parameter ITIM1 Description Block current consumption at 3 MHz ITIM2 Block current consumption at 12 MHz SID189A SID190 SID190A SID191 ITIM3 Block current consumption at 48 MHz SID191A Min – Typ – Max 42 Units µA Details/Conditions 16-bit timer, 85 °C – – – 46 µA 16-bit timer, 105 °C – 130 µA 16-bit timer, 85 °C – – 137 µA 16-bit timer, 105 °C – – 535 µA 16-bit timer, 85 °C – – 560 µA 16-bit timer, 105 °C Min FCLK Typ – Max 48 Units MHz Details/Conditions Table 21. Timer AC Specifications Spec ID SID192 Parameter TTIMFREQ Description Operating frequency SID193 TCAPWINT Capture pulse width (internal) 2 × TCLK – – ns SID194 TCAPWEXT Capture pulse width (external) 2 × TCLK – – ns SID195 TTIMRES Timer resolution TCLK – – ns SID196 TTENWIDINT Enable pulse width (internal) 2 × TCLK – – ns SID197 TTENWIDEXT Enable pulse width (external) 2 × TCLK – – ns SID198 TTIMRESWINT Reset pulse width (internal) 2 × TCLK – – ns SID199 TTIMRESEXT Reset pulse width (external) 2 × TCLK – – ns Min – Typ – Max 42 – – 46 µA 16-bit timer, 105 °C – – 130 µA 16-bit timer, 85 °C – – 137 µA 16-bit timer, 105 °C – – 535 µA 16-bit timer, 85 °C – – 560 µA 16-bit timer, 105 °C Min FCLK Typ – Max 48 Units MHz Counter Table 22. Counter DC Specifications Spec ID SID200 Parameter ICTR1 Description Block current consumption at 3 MHz ICTR2 Block current consumption at 12 MHz ICTR3 Block current consumption at 48 MHz SID200A SID201 SID201A SID202 SID202A Units Details/Conditions µA 16-bit timer, 85 °C Table 23. Counter AC Specifications Spec ID SID203 Parameter TCTRFREQ Description Operating frequency SID204 TCTRPWINT Capture pulse width (internal) 2 × TCLK – – ns SID205 TCTRPWEXT Capture pulse width (external) 2 × TCLK – – ns SID206 TCTRES Counter resolution TCLK – – ns SID207 TCENWIDINT Enable pulse width (internal) 2 × TCLK – – ns SID208 TCENWIDEXT Enable pulse width (external) 2 × TCLK – – ns SID209 TCTRRESWINT Reset pulse width (internal) 2 × TCLK – – ns SID210 TCTRRESWEXT Reset pulse width (external) 2 × TCLK – – ns Document Number: 001-90478 Rev. *K Details/Conditions Page 26 of 42 PRoC BLE: CYBL10X6X Family Datasheet Pulse Width Modulation (PWM) Table 24. PWM DC Specifications Spec ID SID211 Parameter IPWM1 Description Block current consumption at 3 MHz SID211A SID212 IPWM2 Block current consumption at 12 MHz IPWM3 Block current consumption at 48 MHz SID212A SID213 SID213A Min Typ Max Units Details/Conditions – – 42 µA 16-bit timer, 85 °C – – 46 µA 16-bit timer, 105 °C – – 130 µA 16-bit timer, 85 °C – – 137 µA 16-bit timer, 105 °C – – 535 µA 16-bit timer, 85 °C – – 560 µA 16-bit timer, 105 °C Min Typ Max Units Table 25. PWM AC Specifications Spec ID Parameter Description SID214 TPWMFREQ Operating frequency FCLK – 48 MHz SID215 TPWMPWINT Pulse width (internal) 2 × TCLK – – ns SID216 TPWMEXT Pulse width (external) 2 × TCLK – – ns SID217 TPWMKILLINT Kill pulse width (internal) 2 × TCLK – – ns SID218 TPWMKILLEXT Kill pulse width (external) 2 × TCLK – – ns SID219 TPWMEINT Enable pulse width (internal) 2 × TCLK – – ns SID220 TPWMENEXT Enable pulse width (external) 2 × TCLK – – ns SID221 TPWMRESWINT Reset pulse width (internal) 2 × TCLK – – ns SID222 TPWMRESWEXT Reset pulse width (external) 2 × TCLK – – ns Min Typ Max Units Details/Conditions I2C Table 26. I2C DC Specifications Spec ID Parameter Description SID223 II2C1 Block current consumption at 100 kHz – – 50 µA SID224 II2C2 Block current consumption at 400 kHz – – 155 µA SID225 II2C3 Block current consumption at 1 Mbps – – 390 µA II2C4 I2C – – 1.4 µA Min – Typ – Max 1 Units Mbps Min – Typ 17.5 Max – SID226 enabled in Deep-Sleep mode Details/Conditions Table 27. Fixed I2C AC Specifications Spec ID SID227 Parameter FI2C1 Description Bit rate Details/Conditions LCD Direct Drive Table 28. LCD Direct Drive DC Specifications Spec ID SID228 Parameter ILCDLOW Description Operating current in low-power mode SID229 CLCDCAP – 500 5000 SID230 LCDOFFSET LCD capacitance per segment/common driver Long-term segment offset – 20 – mV SID231 ILCDOP1 – 2 – mA SID232 ILCDOP2 LCD system operating current. Vbias = 5 V LCD system operating current. Vbias = 3.3 V – 2 – mA Document Number: 001-90478 Rev. *K Units Details/Conditions µA 16 × 4 small-segment display at 50 Hz pF 32 × 4 segments. 50 Hz. 25 °C 32 × 4 segments. 50 Hz. 25 °C Page 27 of 42 PRoC BLE: CYBL10X6X Family Datasheet Table 29. LCD Direct Drive AC Specifications Spec ID SID233 Parameter FLCD Description LCD frame rate Min 10 Typ 50 Max 150 Units Hz Details/Conditions Table 30. Fixed UART DC Specifications Description Min Typ Max Units SID234 Spec ID IUART1 Parameter Block current consumption at 100 kbps – – 55 µA SID235 IUART2 Block current consumption at 1000 kbps – – 312 µA Min Typ Max Units – – 1 Mbps Details/Conditions Table 31. Fixed UART AC Specifications Spec ID SID236 Parameter FUART Description Bit rate Details/Conditions SPI Specifications Table 32. Fixed SPI DC Specifications Min Typ Max Units SID237 Spec ID ISPI1 Parameter Block current consumption at 1 Mbps Description – – 360 µA SID238 ISPI2 Block current consumption at 4 Mbps – – 560 µA SID239 ISPI3 Block current consumption at 8 Mbps – – 600 µA Min Typ Max Units – – 8 MHz Min Typ Max Units Details/Conditions Table 33. Fixed SPI AC Specifications Spec ID SID240 Parameter FSPI Description SPI operating frequency (master; 6x oversampling) Details/Conditions Table 34. Fixed SPI Master Mode AC Specifications Spec ID Parameter Description Details/Conditions SID241 TDMO MOSI valid after SCLK driving edge – – 18 ns SID242 TDSI MISO valid before SCLK capturing edge. Full clock, late MISO sampling used 20 – – ns Full clock, late MISO sampling SID243 THMO Previous MOSI data hold time 0 – – ns Referred to Slave capturing edge Table 35. Fixed SPI Slave Mode AC Specifications Spec ID SID244 Parameter Description Min Typ Max Units ns TDMI MOSI valid before SCLK capturing edge 40 – – SID245 TDSO MISO valid after SCLK driving edge – – 42 + 3 × TSCB ns SID246 TDSO_ext MISO Valid after SCLK driving edge in external clock mode. VDD < 3.0 V – – 50 ns SID247 THSO Previous MISO data hold time 0 – – ns SID248 TSSELSCK SSEL valid to first SCK valid edge 100 – – ns Document Number: 001-90478 Rev. *K Page 28 of 42 PRoC BLE: CYBL10X6X Family Datasheet Memory Table 36. Flash DC Specifications Spec ID Parameter Description Min Typ Max Units 1.71 – 5.5 V Number of Wait states at 32–48 MHz 2 – – CPU execution from flash TWS32 Number of Wait states at 16–32 MHz 1 – – CPU execution from flash TWS16 Number of Wait states for 0–16 MHz 0 – – CPU execution from flash SID249 VPE Erase and program voltage SID309 TWS48 SID310 SID311 Details/Conditions Table 37. Flash AC Specifications Spec ID Parameter Description Min Typ Max Units Details/Conditions SID250 TROWWRITE[4] Row (block) write time (erase and program) – – 20 ms Row (block) = 128 bytes SID251 TROWERASE[4] Row erase time – – 13 ms SID252 TROWPROGRAM[4] Row program time after erase – – 7 ms SID253 Bulk erase time (128 KB) – – 35 ms SID254 TBULKERASE[4] TDEVPROG[4] Total device program time – – 25 seconds SID255 FEND Flash endurance 100 K – – cycles SID256 FRET Flash retention. TA 55 °C, 100-K P/E cycles 20 – – years SID257 FRET2 Flash retention. TA 85 °C, 10-K P/E cycles 10 – – years SID257A FRET3 Flash retention. TA 105 °C, 10-K P/E cycles 3 – – years For TA ≥ 85 °C System Resources Power-on-Reset (POR) Table 38. POR DC Specifications Min Typ Max Units SID258 Spec ID VRISEIPOR Parameter Rising trip voltage Description 0.80 – 1.45 V SID259 VFALLIPOR Falling trip voltage 0.75 – 1.40 V SID260 VIPORHYST Hysteresis 15 – 200 mV Description Min Typ Max Units Precision power-on reset (PPOR) response time in Active and Sleep modes – – 1 µs Details/Conditions Table 39. POR AC Specifications Spec ID SID264 Parameter TPPOR_TR Details/Conditions Note 4. It can take as much as 20 ms to write to flash. During this time, the device should not be reset, or flash operations will be interrupted and cannot be relied on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs. Make certain that these are not inadvertently activated. Document Number: 001-90478 Rev. *K Page 29 of 42 PRoC BLE: CYBL10X6X Family Datasheet Table 40. Brown-Out Detect Spec ID# Parameter Description Min Typ Max Units SID261 VFALLPPOR BOD trip voltage in Active and Sleep modes 1.64 – – V SID262 VFALLDPSLP BOD trip voltage in Deep Sleep 1.4 – – V Min Typ Max Units 1.1 – – V Description Min Typ Max Units Details/ Conditions Table 41. Hibernate Reset Spec ID# SID263 Parameter VHBRTRIP Description BOD trip voltage in Hibernate Details/ Conditions Voltage Monitors (LVD) Table 42. Voltage Monitor DC Specifications Spec ID Parameter SID265 VLVI1 LVI_A/D_SEL[3:0] = 0000b 1.71 1.75 1.79 V SID266 VLVI2 LVI_A/D_SEL[3:0] = 0001b 1.76 1.80 1.85 V SID267 VLVI3 LVI_A/D_SEL[3:0] = 0010b 1.85 1.90 1.95 V SID268 VLVI4 LVI_A/D_SEL[3:0] = 0011b 1.95 2.00 2.05 V SID269 VLVI5 LVI_A/D_SEL[3:0] = 0100b 2.05 2.10 2.15 V SID270 VLVI6 LVI_A/D_SEL[3:0] = 0101b 2.15 2.20 2.26 V SID271 VLVI7 LVI_A/D_SEL[3:0] = 0110b 2.24 2.30 2.36 V SID272 VLVI8 LVI_A/D_SEL[3:0] = 0111b 2.34 2.40 2.46 V SID273 VLVI9 LVI_A/D_SEL[3:0] = 1000b 2.44 2.50 2.56 V SID274 VLVI10 LVI_A/D_SEL[3:0] = 1001b 2.54 2.60 2.67 V SID275 VLVI11 LVI_A/D_SEL[3:0] = 1010b 2.63 2.70 2.77 V SID276 VLVI12 LVI_A/D_SEL[3:0] = 1011b 2.73 2.80 2.87 V SID277 VLVI13 LVI_A/D_SEL[3:0] = 1100b 2.83 2.90 2.97 V SID278 VLVI14 LVI_A/D_SEL[3:0] = 1101b 2.93 3.00 3.08 V SID279 VLVI15 LVI_A/D_SEL[3:0] = 1110b 3.12 3.20 3.28 V SID280 VLVI16 LVI_A/D_SEL[3:0] = 1111b 4.39 4.50 4.61 V SID281 LVI_IDD Block current – – 100 µA Min Typ Max Units – – 1 µs Details/ Conditions Table 43. Voltage Monitor AC Specifications Spec ID SID282 Parameter TMONTRIP Description Voltage monitor trip time Document Number: 001-90478 Rev. *K Details/ Conditions Page 30 of 42 PRoC BLE: CYBL10X6X Family Datasheet SWD Interface Table 44. SWD Interface Specifications Spec ID Parameter Description Min Typ Max Units Details/Conditions SID283 F_SWDCLK1 3.3 V VDD 5.5 V – – 14 MHz SWDCLK ≤ 1/3 CPU clock frequency SID284 F_SWDCLK2 1.71 V VDD 3.3 V – – 7 MHz SWDCLK ≤ 1/3 CPU clock frequency SID285 T_SWDI_SETUP T = 1/f SWDCLK 0.25 × T – – ns SID286 T_SWDI_HOLD 0.25 × T – – ns SID287 T_SWDO_VALID T = 1/f SWDCLK – – 0.5 × T ns SID288 T_SWDO_HOLD T = 1/f SWDCLK 1 – – ns T = 1/f SWDCLK Internal Main Oscillator Table 45. IMO DC Specifications Min Typ Max Units SID289 Spec ID IIMO1 Parameter IMO operating current at 48 MHz Description – – 1000 µA SID290 IIMO2 IMO operating current at 24 MHz – – 325 µA SID291 IIMO3 IMO operating current at 12 MHz – – 225 µA SID292 IIMO4 IMO operating current at 6 MHz – – 180 µA SID293 IIMO5 IMO operating current at 3 MHz – – 150 µA Details/Conditions Table 46. IMO AC Specifications Min Typ Max Units SID296 Spec ID FIMOTOL3 Parameter Frequency variation from 3 to 48 MHz Description – – ±2 % Details/Conditions SID297 FIMOTOL3 IMO startup time – 12 – µs Min Typ Max Units Details/Conditions – 0.3 1.05 µA Guaranteed by design With API-called calibration Internal Low-Speed Oscillator Table 47. ILO DC Specifications Spec ID SID298 Parameter IILO2 Description ILO operating current at 32 kHz Table 48. ILO AC Specifications Min Typ Max Units SID299 Spec ID TSTARTILO1 Parameter ILO startup time Description – – 2 ms SID300 FILOTRIM1 32-kHz trimmed frequency 15 32 50 kHz Details/Conditions Table 49. External Clock Specifications Min Typ Max Units Details/Conditions SID301 Spec ID ExtClkFreq Parameter External clock input frequency Description 0 – 48 MHz CMOS input level only. TTL input is not supported SID302 ExtClkDuty Duty cycle; measured at VDD/2 45 – 55 % CMOS input level only. TTL input is not supported Document Number: 001-90478 Rev. *K Page 31 of 42 PRoC BLE: CYBL10X6X Family Datasheet Table 50. ECO Specifications Spec ID# Parameter Description Min Typ Max Units – 24 – MHz SID389 FECO Crystal frequency SID390 FTOL Frequency tolerance –50 – 50 ppm SID391 ESR Equivalent series resistance – – 60 Ω SID392 PD Drive level – – 100 µW SID393 TSTART1 Startup time (Fast Charge on) – – 850 µs SID394 TSTART2 Startup time (Fast Charge off) – – 3 ms SID395 CL Load capacitance – 8 – pF SID396 C0 Shunt capacitance – 1.1 – pF SID397 IECO Operating current – 1400 – µA Min Typ Max Units Details/ Conditions Includes LDO+BG current Table 51. WCO Specifications Spec ID# Parameter Description Details/ Conditions SID398 FWCO Crystal frequency – 32.768 – kHz SID399 FTOL Frequency tolerance – 50 – ppm SID400 ESR Equivalent series resistance – 50 – kΩ SID401 PD Drive level – – 1 µW SID402 TSTART Startup time – – 500 ms SID403 CL Crystal load capacitance 6 – 12.5 pF SID404 C0 Crystal shunt capacitance – 1.35 – pF SID405 IWCO1 Operating current (high-power mode) – – 8 µA SID406 IWCO2 Operating current (low-power mode) – – 1 µA 85 °C – – 2.6 µA 105 °C SID406A Document Number: 001-90478 Rev. *K Page 32 of 42 PRoC BLE: CYBL10X6X Family Datasheet Ordering Information The CYBL10X6X part numbers and features are listed in the following table. CPU Speed (MHz) Flash Size (KB) CapSense SCB TCPWM 12-Bit SAR ADC I2S PWM LCD Package CYBL10161-56LQXI 48 128 No 1 2 1 Msps No No No 56-QFN CYBL10162-56LQXI 48 128 No 2 4 1 Msps No 4 No 56-QFN CYBL10163-56LQXI 48 128 No 2 4 1 Msps Yes No No 56-QFN CYBL10461-56LQXI 48 128 Yes 2 4 1 Msps No No No 56-QFN CYBL10462-56LQXI 48 128 Yes 2 4 1 Msps Yes No No 56-QFN CYBL10463-56LQXI 48 128 Yes 2 4 1 Msps No No Yes 56-QFN CYBL10561-56LQXI 48 128 Yes (Gestures) 2 4 1 Msps No No No 56-QFN CYBL10562-56LQXI 48 128 Yes (Gestures) 2 4 1 Msps Yes 1 No 56-QFN CYBL10563-56LQXI 48 128 Yes (Gestures) 2 4 1 Msps Yes 1 Yes 56-QFN CYBL10563-68FNXIT 48 128 Yes (Gestures) 2 4 1 Msps Yes 1 Yes 68-WLCSP CYBL10563-56LQXQ[5] 48 128 Yes (Gestures) 2 4 1 Msps Yes 1 Yes 56-QFN CYBL10563-68FLXIT[6] 48 128 Yes (Gestures) 2 4 1 Msps Yes 1 Yes 68-Thin WLCSP Part Number CYBL10999-56LQXI Contact Sales Note 5. This part is available as Engineering Sample. 6. This part is available as Engineering Sample (CYBL10563-68FLXIEST). Document Number: 001-90478 Rev. *K Page 33 of 42 PRoC BLE: CYBL10X6X Family Datasheet Part Numbering Conventions The part numbers are of the form CYBL10ABC-DEFGHIT where the fields are defined as follows. CY BL 10 A B C - DE FG H I T Example CYBL: PRoC- Smart Family Cypress Prefix 10 : CYBL10 XXX Sub - family 1: Embedded only 4: CapSense 5: Touch 6: 128 KB Product Type Flash Capacity 3: Part Identifier Feature Set 56/ 70: Number of Pins Package Pins LQ: QFN FN : WLCSP FL : Thin WLCSP Package Code Pb X : Pb - free I: Industrial Q: Extended Industrial T: Tape and Reel Blank : Tray / Tube Temperature Range Tape and Reel The Field Values are listed in the following table: Field Description Values CYBL Cypress PRoC BLE Family CYBL 10 Subfamily 10 CYBL10X6X 1 Embedded Only A Product Type 4 CapSense B Flash Capacity C Feature set DE Package Pins FG Package code H I Pb Temperature Range Document Number: 001-90478 Rev. *K Meaning 5 Touch 6 128 KB 56 68 LQ QFN FN WLCSP FL Thin WLCSP X Pb-free C Commercial 0 °C to 70 °C I Industrial –40 °C to 85 °C Q Extended Industrial –40 °C to 105 °C X Absent (with Pb) Page 34 of 42 PRoC BLE: CYBL10X6X Family Datasheet Packaging Table 52. Package Characteristics Parameter TA Description Conditions Operating ambient temperature TJ Operating junction temperature TJA Package JA (56-pin QFN) Min Typ Max Units Industrial –40 25 85 °C Extended industrial –40 25 105 °C Industrial –40 – 100 °C Extended industrial –40 – 125 °C – 16.9 – °C/watt TJC Package JC (56-pin QFN) – 9.7 – °C/watt TJA Package JA (68-ball WLCSP) – 16.6 – °C/watt TJC Package JC (68-ball WLCSP) – 0.19 – °C/watt TJA Package JA (68-ball Thin WLCSP) – 16.6 – °C/watt TJC Package JC (68-ball Thin WLCSP) – 0.19 – °C/watt Table 53. Solder Reflow Peak Temperature Package Maximum Peak Temperature Maximum Time at Peak Temperature 56-pin QFN 260 °C 30 seconds 68-ball WLCSP 260 °C 30 seconds 68-ball Thin WLCSP 260 °C 30 seconds Table 54. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2 Package MSL 56-pin QFN MSL 3 68-ball WLCSP MSL 1 68-ball Thin WLCSP MSL 1 Table 55. Package Details Spec ID Package Description 001-58740 Rev. *C 56-pin QFN 7 mm × 7 mm × 0.6 mm 001-92343 Rev. *A 68-ball WLCSP 3.52 mm × 3.91 mm × 0.55 mm 001-99408 Rev ** 68-ball Thin WLCSP 3.52 mm X 3.91 mm X 0.4 mm Document Number: 001-90478 Rev. *K Page 35 of 42 PRoC BLE: CYBL10X6X Family Datasheet Figure 5. 56-Pin QFN 7 mm × 7 mm × 0.6 mm TOP VIEW SIDE VIEW BOTTOM VIEW NOTES: 1. HATCH AREA IS SOLDERABLE EXPOSED PAD 2. BASED ON REF JEDEC # MO-248 001-58740 *C 3. ALL DIMENSIONS ARE IN MILLIMETERS The center pad on the QFN package must be connected to ground (VSS) for the proper operation of the device. Figure 6. 68-Ball WLCSP Package Outline 001-92343 *A Document Number: 001-90478 Rev. *K Page 36 of 42 PRoC BLE: CYBL10X6X Family Datasheet Figure 7. 68-Ball Thin WLCSP SIDE VIEW TOP VIEW 1 2 3 4 5 6 7 8 A BOTTOM VIEW 8 7 6 5 4 3 2 1 A B B C C D D E E F F G G H H J J NOTES: 1. REFERENCE JEDEC PUBLICATION 95, DESIGN GUIDE 4.18 2. ALL DIMENSIONS ARE IN MILLIMETERS Document Number: 001-90478 Rev. *K 001-99408 ** Page 37 of 42 PRoC BLE: CYBL10X6X Family Datasheet Acronyms Table 56. Acronyms Used in This Document Acronym Description Table 56. Acronyms Used in This Document (continued) Acronym Description ETM embedded trace macrocell FET field-effect transistor FIR finite impulse response, see also IIR FPB flash patch and breakpoint FS full-speed GPIO general-purpose input/output, applies to a PSoC pin analog multiplexer bus HCI host controller interface application programming interface HVI high-voltage interrupt, see also LVI, LVD APSR application program status register IC integrated circuit ARM® advanced RISC machine, a CPU architecture IDAC current DAC, see also DAC, VDAC ATM automatic thump mode IDE integrated development environment BW bandwidth I2C, CAN Controller Area Network, a communications protocol I2S Inter-IC Sound CMRR common-mode rejection ratio IIR infinite impulse response, see also FIR CPU central processing unit ILO internal low-speed oscillator, see also IMO CRC cyclic redundancy check, an error-checking protocol IMO internal main oscillator, see also ILO INL integral nonlinearity, see also DNL DAC digital-to-analog converter, see also IDAC, VDAC I/O input/output, see also GPIO, DIO, SIO, USBIO DFB digital filter block IPOR initial power-on reset DIO digital input/output, GPIO with only digital capabilities, no analog. See GPIO. IPSR interrupt program status register DMIPS Dhrystone million instructions per second IRQ interrupt request DMA direct memory access, see also TD DNL differential nonlinearity, see also INL DNU do not use DR ABUS analog local bus ADC analog-to-digital converter AG analog global AHB AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data transfer bus ALU arithmetic logic unit AMUXBUS API or IIC Inter-Integrated Circuit, a communications protocol ITM instrumentation trace macrocell LCD liquid crystal display LIN Local Interconnect Network, a communications protocol. port write data registers LR link register DSI digital system interconnect LUT lookup table DWT data watchpoint and trace LVD low-voltage detect, see also LVI ECC error correcting code LVI low-voltage interrupt, see also HVI ECO external crystal oscillator LVTTL low-voltage transistor-transistor logic EEPROM electrically erasable programmable read-only memory MAC multiply-accumulate EMI electromagnetic interference MCU microcontroller unit EMIF external memory interface EOC end of conversion EOF end of frame EPSR execution program status register ESD electrostatic discharge Document Number: 001-90478 Rev. *K MISO master-in slave-out NC no connect NMI nonmaskable interrupt NRZ non-return-to-zero NVIC nested vectored interrupt controller Page 38 of 42 PRoC BLE: CYBL10X6X Family Datasheet Table 56. Acronyms Used in This Document (continued) Acronym Description Table 56. Acronyms Used in This Document (continued) Acronym Description NVL nonvolatile latch, see also WOL SRAM static random access memory Opamp operational amplifier SRES software reset PAL programmable array logic, see also PLD STN super twisted nematic PC program counter SWD serial wire debug, a test protocol PCB printed circuit board SWV single-wire viewer PGA programmable gain amplifier TD transaction descriptor, see also DMA PHUB peripheral hub THD total harmonic distortion PHY physical layer TIA transimpedance amplifier PICU port interrupt control unit TN twisted nematic PLA programmable logic array TRM technical reference manual PLD programmable logic device, see also PAL TTL transistor-transistor logic PLL phase-locked loop TX transmit PMDD package material declaration data sheet UART POR power-on reset Universal Asynchronous Transmitter Receiver, a communications protocol PRES precise power-on reset USB Universal Serial Bus PRS pseudo random sequence USBIO PS port read data register USB input/output, PSoC pins used to connect to a USB port PSoC® Programmable System-on-Chip™ VDAC voltage DAC, see also DAC, IDAC PSRR power supply rejection ratio PWM pulse-width modulator RAM random-access memory RISC reduced-instruction-set computing RMS root-mean-square RTC real-time clock RTL register transfer language RTR remote transmission request RX receive SAR successive approximation register SC/CT switched capacitor/continuous time SCL I2C serial clock SDA I2C serial data S/H sample and hold SINAD signal to noise and distortion ratio SIO special input/output, GPIO with advanced features. See GPIO. SOC start of conversion SOF start of frame SPI Serial Peripheral Interface, a communications protocol SR slew rate Document Number: 001-90478 Rev. *K WDT watchdog timer WOL write once latch, see also NVL WRES watchdog timer reset XRES external reset I/O pin XTAL crystal Page 39 of 42 PRoC BLE: CYBL10X6X Family Datasheet Document Conventions Units of Measure Table 57. Units of Measure (continued) Table 57. Units of Measure Symbol Symbol Unit of Measure µH Unit of Measure microhenry degrees Celsius µs microsecond dB decibel µV microvolt dBm decibel-milliwatts µW microwatt fF femtofarads mA milliampere Hz hertz ms millisecond KB 1024 bytes mV millivolt kbps kilobits per second nA nanoampere Khr kilohour ns nanosecond kHz kilohertz nV nanovolt k kilo ohm ohm ksps kilosamples per second pF picofarad LSB least significant bit ppm parts per million Mbps megabits per second ps picosecond MHz megahertz s second M mega-ohm sps samples per second Msps megasamples per second sqrtHz square root of hertz µA microampere V volt microfarad W watt °C µF Document Number: 001-90478 Rev. *K Page 40 of 42 PRoC BLE: CYBL10X6X Family Datasheet Revision History Description Title: CYBL10X6X Family Datasheet Programmable Radio-on-Chip With Bluetooth Low Energy (PRoC BLE) Document Number: 001-90478 Orig. of Submission Revision ECN Description of Change Change Date *F 4567076 CSAI 11/11/2014 Initial release *G 4600081 SKAR 12/19/2014 Revision to 16-bit Timer Counter PWM, block current consumption at 3, 12, and 48 MHz to align with CHAR data Revision of I2C/ UART block current consumption to align with CHAR data Revision of LCD Direct Drive - operating current in low-power mode to align with CHAR data Revision of BLE RF Average Current Spec for 4-sec BLE connection interval to 6.25 µA to align with CHAR data Revision of RXS with idle transmitter, with balun loss and in high-gain mode to align with CHAR data Clarified the IECO operating current to reflect crystal current - LDO and Bandgap current as well Corrected Typo for SID#245 (CPU -> SCB) Corrected Typo for SID#275 *H 4651104 CSAI Removed errata 02/11/2015 Updated Figure 5 Updated CapSense column for CYBL10563-56LQXI and CYBL10563-68FNXIT parts to "Yes (Gestures)" in Ordering Information table and updated part number *I 4779453 HXR *J 4810822 GCG *K 4865942 SASD/ SDUR/ UTSV Document Number: 001-90478 Rev. *K Updated Part Numbering Conventions 05/28/2015 Removed min and max values for SID359 and SID360. Removed max value and added typ value for SID357. 06/29/2015 Updated Figure 1 for clarity Updated Figure 2 and Figure 3 for uniformity Updated Figure 4 with a higher resolution image Removed EZSPI reference. Updated 56-pin QFN package diagram to correct the orientation of text. 08/19/2015 Changed temperature range from –40 °C to 85 °C to –40 °C to 105 °C. Added ‘overvoltage-tolerant’ description to pins P5.0 and P5.1 in CYBL10X6X Pin List (WLCSP Package). Added clarifying note on overvoltage-tolerant pins for SID76. Updated max values in Timer, Counter, and PWM DC specifications for 105 °C. Added SID257A in Flash AC Specifications. Added Guaranteed by Design note to SID 298. Added SID406A for 105 °C. Added extended industrial temperature range in the Field Values table. Added TA and TJ for extended industrial in Package Characteristics. Added extended industrial temperature parts in Ordering Information. Added thin WLCSP (CYBL10563-68FLXIT) details in Ordering Information and Packaging sections. Page 41 of 42 PRoC BLE: CYBL10X6X Family Datasheet Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/memory PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/touch USB Controllers Wireless/RF psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support cypress.com/go/usb cypress.com/go/wireless © Cypress Semiconductor Corporation, 2013-2015. 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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-90478 Rev. *K Revised August 19, 2015 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 42 of 42