PRoC™ BLE: CYBL1XX7X
Family Datasheet
PRELIMINARY
Programmable Radio-on-Chip With
Bluetooth Low Energy (PRoC™ BLE)
General Description
PRoC™ BLE is a 32-bit, 48-MHz ARM® Cortex™-M0 BLE solution with CapSense®, 12-bit ADC, four timer, counter, pulse-width
modulators (TCPWM), Direct memory access (DMA), thirty-six GPIOs, two serial communication blocks (SCBs), LCD, and I2S.
PRoC™ BLE includes a royalty-free BLE stack compatible with Bluetooth® 4.2 and provides a complete, programmable, and flexible
solution for HID, remote controls, toys, beacons, and wireless chargers. In addition to these applications, PRoC™ BLE provides a
simple, low-cost way to add BLE connectivity to any system.
Features
Bluetooth® Smart Connectivity
■
Bluetooth 4.2 single-mode device
2.4-GHz BLE radio and baseband with integrated balun
■ TX output power: –18 dBm to +3 dBm
■ Received signal strength indicator (RSSI) with 1-dB resolution
■ RX sensitivity: –92 dBm
■ TX current: 15.6 mA at 0 dBm
■ RX current: 16.4 mA
■
■
■
■
■
Clock, Reset, and Supply
■
■
ARM Cortex-M0 CPU Core
32-bit processor (0.9 DMIPS/MHz) with single-cycle 32-bit
multiply, operating at up to 48 MHz
■ 256-KB flash memory
■ 32-KB SRAM memory
■ Emulated EEPROM using flash memory
■ Watchdog timer with dedicated internal low-speed oscillator
(ILO)
■ Eight-channel direct memory access (DMA) controller
■
Ultra-Low-Power
1.5-µA Deep-Sleep mode with watch crystal oscillator (WCO)
on
■ 150-nA Hibernate mode current with SRAM retention
■ 60-nA Stop mode current with GPIO wakeup
■
CapSense® Touch Sensing with Two-Finger Gestures
Up to 36 capacitive sensors for buttons, sliders, and touchpads
■ One-finger gestures: finger tracking, scroll, inertial scroll,
edge-swipe, click, double-click
■ Two-finger gestures: scroll, inertial scroll, zoom-in, zoom-out
■ Cypress Capacitive Sigma-Delta (CSD) provides best-in-class
SNR (> 5:1) and liquid tolerance
■ Automatic hardware-tuning algorithm (SmartSense™)
■
■
■
12-bit, 1-Msps SAR ADC with internal reference,
sample-and-hold (S/H), and channel sequencer
■ Ultra-low-power LCD segment drive for 128 segments with
operation in Deep-Sleep mode
■
■
•
36 GPIOs configurable as open drain high/low,
pull-up/pull-down, HI-Z, or strong output
Any GPIO pin can be CapSense, LCD, or analog, with flexible
pin routing
Programming and Debug
■
■
2-pin SWD
In-system flash programming support
Temperature and Packaging
■
■
Operating temperature range: –40 °C to +105 °C
Available in 56-pin QFN (7 mm × 7 mm) and 76-ball WLCSP
(3.52 mm × 3.91 mm) packages
PSoC® Creator™ Design Environment
■
■
Easy-to-use IDE to configure, develop, program, and test a
BLE application
Option to export the design to Keil, IAR, or Eclipse
Bluetooth Low Energy Protocol Stack
■
Cypress Semiconductor Corporation
Document Number: 001-95464 Rev. *G
Wide supply-voltage range: 1.9 V to 5.5 V
3-MHz to 48-MHz internal main oscillator (IMO) with 2%
accuracy
24-MHz external clock oscillator (ECO) without load
capacitance
32-kHz WCO
Programmable GPIOs
■
Peripherals
Two serial communication blocks (SCBs) supporting I2C
(Master/Slave), SPI (Master/Slave), or UART
Four dedicated 16-bit TCPWMs
❐ Additional four 8-bit or two 16-bit PWMs
Programmable LVD from 1.8 V to 4.5 V
I2S Master interface
■
198 Champion Court
Bluetooth Low Energy protocol stack supporting generic
access profile (GAP) Central, Peripheral, Observer, or
Broadcaster roles
❐ Switches between Central and Peripheral roles on-the-go
Standard Bluetooth Low Energy profiles and services for
interoperability
❐ Custom profile and service for specific use cases
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 2, 2015
PRoC™ BLE: CYBL1XX7X
Family Datasheet
PRELIMINARY
More Information
Cypress provides a wealth of data at http://www.cypress.com to
help you to select the right PSoC device for your design, and to
help you to quickly and effectively integrate the device into your
design. For a comprehensive list of resources, see the introduction page for Bluetooth® Low Energy (BLE) Products.
Following is an abbreviated list for PRoC BLE:
■ Overview: PSoC Portfolio, PSoC Roadmap
■ Product Selectors: PSoC 1, PSoC 3, PSoC 4, PRoC BLE,
PSoC 4 BLE, PSoC 5LP In addition, PSoC Creator includes a
device selection tool.
■ Application Notes: Cypress offers a large number of PSoC
application notes converting a broad range of topics, from basic
to advanced level. Recommended application notes for getting
started with PRoC BLE are:
❐ AN94020: Getting Started with PRoC BLE
❐ AN97060: PSoC 4 BLE and PRoC BLE - Over-The-Air (OTA)
Device Firmware Upgrade (DFU) Guide
❐ AN91184: PSoC 4 BLE - Designing BLE Applications
❐ AN91162: Creating a BLE Custom Profile
❐ AN91445: Antenna Design and RF Layout Guidelines
❐ AN96841: Getting Started With EZ-BLE Module
❐ AN85951: PSoC 4 CapSense Design Guide
AN95089: PSoC 4/PRoC BLE Crystal Oscillator Selection
and Tuning Techniques
❐ AN92584: Designing for Low Power and Estimating Battery
Life for BLE Applications
■ Technical Reference Manual (TRM) is in two documents:
❐ Architecture TRM details each PRoC BLE functional block
❐ Registers TRM describes each of the PRoC BLE registers
■ Development Kits:
❐ CY8CKIT-042-BLE Pioneer Kit, is a flexible, Arduino-compatible, Bluetooth LE development kit for PSoC 4 BLE and
PRoC BLE.
❐ CY5676, PRoC BLE 256KB Module, features a PRoC BLE
256KB device, two crystals for the antenna matching network, a PCB antenna and other passives, while providing
access to all GPIOs of the device.
❐ CY8CKIT-142, PSoC 4 BLE Module, features a PSoC 4 BLE
device, two crystals for the antenna matching network, a PCB
antenna and other passives, while providing access to all
GPIOs of the device.
❐ CY8CKIT-143, PSoC 4 BLE 256KB Module, features a PSoC
4 BLE 256KB device, two crystals for the antenna matching
network, a PCB antenna and other passives, while providing
access to all GPIOs of the device.
❐ The MiniProg3 device provides an interface for flash programming and debug.
❐
PSoC Creator
PSoC Creator is a free Windows-based Integrated Design Environment (IDE). It enables concurrent hardware and firmware design
of PSoC 3, PSoC 4, and PSoC 5LP based systems. Create designs using classic, familiar schematic capture supported by over 100
pre-verified, production-ready PSoC Components; see the list of component datasheets. With PSoC Creator, you can:
1. Drag and drop component icons to build your hardware
3. Configure components using the configuration tools
system design in the main design workspace
4. Explore the library of 100+ components
2. Codesign your application firmware with the PSoC hardware,
5. Review component datasheets
using the PSoC Creator IDE C compiler
Figure 1. Multiple-Sensor Example Project in PSoC Creator Contents
1
4
2
3
Document Number: 001-95464 Rev. *G
5
Page 2 of 42
PRELIMINARY
PRoC™ BLE: CYBL1XX7X
Family Datasheet
Contents
Blocks and Functionality ................................................. 3
CPU Subsystem .......................................................... 4
BLE Subsystem........................................................... 4
System Resources Subsystem ................................... 6
Peripheral Blocks ........................................................ 7
Pinouts .............................................................................. 9
Power............................................................................... 14
Low-Power Modes..................................................... 14
Development Support .................................................... 16
Documentation .......................................................... 16
Online ........................................................................ 16
Tools.......................................................................... 16
Kits ............................................................................ 16
Electrical Specifications ................................................ 17
Absolute Maximum Ratings ...................................... 17
BLE Subsystem......................................................... 17
Device-Level Specifications ...................................... 20
Analog Peripherals .................................................... 25
Document Number: 001-95464 Rev. *G
Digital Peripherals .....................................................
Memory .....................................................................
System Resources ....................................................
Ordering Information......................................................
Ordering Code Definitions .........................................
Packaging........................................................................
WLCSP Compatibility ................................................
Acronyms ........................................................................
Document Conventions .................................................
Units of Measure .......................................................
Revision History .............................................................
Sales, Solutions, and Legal Information ......................
Worldwide Sales and Design Support.......................
Products ....................................................................
PSoC® Solutions ......................................................
Cypress Developer Community.................................
Technical Support .....................................................
26
29
30
33
33
34
36
38
40
40
41
42
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Page 3 of 42
PRoC™ BLE: CYBL1XX7X
Family Datasheet
PRELIMINARY
Blocks and Functionality
The CYBL1XX7X block diagram is shown in Figure 2. There are five major subsystems: CPU subsystem, BLE subsystem, system
resources, peripheral blocks, and I/O subsystem.
Figure 2. Block Diagram
P0.6
P0.7
CPU Subsystem
ARM
Cortex-M0
SWD
FLASH
256 KB
NVIC
SRAM
32 KB
CONFIG
512 B
ROM
8 KB
DMA
Controller
System Interconnect
BLE Subsystem
System Resources
XRES
Power
BOD
LVD
XRES
WDT
Clock Control
IMO
ILO
Link Layer
Engine
WCO
ECO
XTAL32I/P6.1
XTAL32O/P6.0
XTAL24I
XTAL24O
RF PHY
ANT
SCB0
I2C/UART/SPI
GPIOs
SCB1
I2C/UART/SPI
GPIOs
Peripherals
GPIOs
12-Bit
SAR ADC
4x TCPWM
GPIOs
GPIOs
4x PWM
Peripheral Interconnect
GPIOs
I2S
LCD
CAPSENSE
GPIOs
GPIOs
I/O Subsystem
The PRoC™ BLE family includes extensive support for
programming, testing, debugging, and tracing both hardware
and firmware. The complete debug-on-chip functionality enables
full-device debugging in the final system using the standard
production device. It does not require special interfaces,
debugging pods, simulators, or emulators. Only the standard
programming connections are required to fully support debug.
Document Number: 001-95464 Rev. *G
The PSoC Creator IDE provides fully integrated programming
and debug support for PRoC™ BLE devices. The SWD interface
is fully compatible with industry-standard third-party tools.
PRoC™ BLE also supports disabling the SWD interface and has
a robust flash-protection feature.
Page 4 of 42
PRELIMINARY
CPU Subsystem
CPU
The CYBL1XX7X device is based on an energy-efficient
ARM Cortex-M0 32-bit processor, offering low power
consumption, high performance, and reduced code size using
16-bit thumb instructions. The Cortex-M0’s ability to perform
single-cycle 32-bit arithmetic and logic operations, including
single-cycle 32-bit multiplication, helps in better performance.
The inclusion of the tightly-integrated Nested Vectored Interrupt
Controller (NVIC) with 32 interrupt lines enables the Cortex-M0
to achieve a low latency and a deterministic interrupt response.
The CPU also includes a 2-pin interface, the serial wire debug
(SWD), which is a 2-wire form of JTAG. The debug circuits are
enabled by default and can only be disabled in firmware. If
disabled, the only way to re-enable them is to erase the entire
device, clear flash protection, and reprogram the device with the
new firmware that enables debugging. In addition, it is possible
to use the debug pins as GPIO too. The device has four breakpoints and two watchpoints for effective debugging.
Flash
The device has a 256-KB flash memory with a flash accelerator,
tightly coupled to the CPU to improve average access times from
flash. The flash is designed to deliver 1-wait-state (WS) access
time at 48 MHz and with 0-WS access time at 24 MHz. The flash
accelerator delivers 85% of single-cycle SRAM access
performance on average. Part of the flash can be used to
emulate EEPROM operation, if required.
During flash erase and programming operations (the maximum
erase and program time is 20 ms per row), the IMO will be set to
48 MHz for the duration of the operation. This also applies to the
emulated EEPROM. System design must take this into account
because peripherals operating from different IMO frequencies
will be affected. If it is critical that peripherals continue to operate
with no change during flash programming, always set the IMO to
48 MHz and derive the peripheral clocks by dividing down from
this frequency.
SRAM
The low-power 32-KB SRAM memory retains its contents even
in Hibernate mode.
ROM
The 8-KB supervisory ROM contains a library of executable
functions for flash programming. These functions are accessed
through supervisory calls (SVC) and enable in-system
programming of the flash memory.
DMA
DMA controller provides DataWrite (DW) and Direct Memory
Access (DMA). The DMA controller has following features
■ Supports up to 8 DMA channels with two independent
descriptors per channel
■ Four levels of priority for each channel
■ Byte, half-word (2 bytes), and word (4 bytes) transfers
■ Three modes of operation supported for each channel
■ Configurable interrupt generation
■ Output trigger on completion of transfer (transfer sizes up to
65536 data elements)
Document Number: 001-95464 Rev. *G
PRoC™ BLE: CYBL1XX7X
Family Datasheet
BLE Subsystem
The BLE subsystem consists of the link layer engine and
physical layer. The link layer engine supports both master and
slave roles. The link layer engine implements time-critical
functions such as encryption in the hardware to reduce the
power consumption, and provides minimal processor
intervention and a high performance. The key protocol elements,
such as host control interface (HCI) and link control, are
implemented in firmware. The direct test mode (DTM) is included
to test the radio performance using a standard Bluetooth tester.
The physical layer consists of a modem and an RF transceiver
that transmits and receives BLE packets at the rate of 1 Mbps
over the 2.4-GHz ISM band. In the transmit direction, this block
performs GFSK modulation and then converts the digital
baseband signal of these BLE packets into radio frequency
before transmitting them to air through an antenna. In the receive
direction, this block converts an RF signal from the antenna to a
digital bit stream after performing GFSK demodulation.
The RF transceiver contains an integrated balun, which provides
a single-ended RF port pin to drive a 50-Ω antenna terminal
through a pi-matching network. The output power is
programmable from –18 dBm to +3 dBm to optimize the current
consumption for different applications.
The Bluetooth Low Energy protocol stack uses the BLE
subsystem and provides the following features:
■ Link Layer (LL)
❐ Master and Slave roles
❐ 128-bit AES engine
❐ Encryption
❐ Low-duty-cycle advertising
❐ LE Ping
❐ LE Data Packet Length Extension (Bluetooth 4.2 feature)
❐ Link Layer Privacy (with extended scanning filter policy)
(Bluetooth 4.2 feature)
■ Bluetooth Low Energy 4.2 single-mode protocol stack with
logical link control and adaptation protocol (L2CAP), attribute
(ATT), and security manager (SM) protocols
■ Master and slave roles
■ API access to generic attribute profile (GATT), generic access
profile (GAP), and L2CAP
■ L2CAP connection-oriented channel
■ GAP features
❐ Broadcaster, Observer, Peripheral, and Central roles
❐ Security mode 1: Level 1, 2, and 3
❐ Security mode 2: Level 1 and 2
❐ User-defined advertising data
❐ Multiple-bond support
■ GATT features
❐ GATT client and server
❐ Supports GATT subprocedures
❐ 32-bit universally unique identifiers (UUID)
■ Security Manager (SM)
❐ LE Secure Connections (Bluetooth 4.2 feature)
❐ Pairing methods: Just Works, Passkey Entry, and Out of
Band
❐ Authenticated man-in-the-middle (MITM) protection and data
signing
■ Supports all SIG-adopted BLE profiles
Page 5 of 42
PRoC™ BLE: CYBL1XX7X
Family Datasheet
PRELIMINARY
System Resources Subsystem
Figure 3. Clock Control
BLE
Subsystem
Power
The power block includes internal LDOs that supply required
voltage levels for different blocks. The power system also
includes POR, BOD, and LVD circuits. The POR circuit holds the
device in the reset state until the power supplies have stabilized
at appropriate levels and the clock is ready. The BOD circuit
resets the device when the supply voltage is too low for proper
device operation. The LVD circuit generates an interrupt if the
supply voltage drops below a user-selectable level.
An external active-LOW reset pin (XRES) can be used to reset
the device. The XRES pin has an internal pull-up resistor and, in
most applications, does not require any additional pull-up
resistors. The power system is described in detail in the “Power”
section on page 14.
Clock Control
The PRoC™ BLE clock control is responsible for providing
clocks to all subsystems and also for switching between different
clock sources without glitching. The clock control for
PRoC™ BLE consists of the IMO and the internal low-speed
oscillator (ILO). It uses the 24-MHz external crystal oscillator
(ECO) and the 32-kHz WCO. In addition, an external clock may
be supplied from a pin.
The device has 12 dividers with 16 divider outputs. Two dividers
have additional fractional division capability. The HFCLK signal
is divided down, as shown in Figure 3, to generate the system
clock (SYSCLK) and peripheral clock (PERx_CLK) for different
peripherals. The system clock (SYSCLK) driving buses,
registers, and the processor must be higher than all the other
clocks in the system that are divided off HFCLK. The ECO and
WCO are present in the BLE subsystem and the clock outputs
are routed to the system resources.
Internal Main Oscillator (IMO)
The IMO is the primary system clock source, which can be
adjusted in the range of 3 MHz to 48 MHz in steps of 1 MHz. The
IMO accuracy is ±2%.
HFCLK
ECO
Prescaler
Divider
/2 n (n=0..3)
Divider 0
(/16)
SYSCLK
PER0_CLK
IMO
EXTCLK
Divider 9
(/16)
Fractional
Divider 0
(/16.5)
WCO
Fractional
Divider 1
(/16.5)
ILO
PER15_CLK
LFCLK
External Crystal Oscillator (ECO)
The ECO is used as the active clock for the BLE subsystem to
meet the ±50-ppm clock accuracy requirement of the Bluetooth
Low Energy Specification. The internal tunable load capacitor is
provided to tune the crystal clock frequency. The high-accuracy
ECO clock can also be used as a system clock.
Watch Crystal Oscillator (WCO)
The WCO is used as the sleep clock for the BLE subsystem to
meet the ±500-ppm clock accuracy requirement of the Bluetooth
Low Energy Specification. The sleep clock provides accurate
sleep timing and enables wakeup at specified advertisement and
connection intervals. With the WCO and firmware, an accurate
real-time clock (within the bounds of the 32.768-kHz crystal
accuracy) can be realized.
Voltage Reference
Internal Low-Speed Oscillator (ILO)
The ILO is a very-low-power 32-kHz oscillator, which is primarily
used to generate clocks for peripheral operations in Deep-Sleep
mode. The ILO-driven counters can be calibrated to the IMO to
improve accuracy. Cypress provides a software component,
which does the calibration.
The internal bandgap reference circuit with 1% accuracy
provides the voltage reference for the 12-bit SAR ADC. To
enable better SNRs and absolute accuracy, it will be possible to
bypass the internal bandgap reference using a REF pin and to
use an external reference for the SAR.
Watchdog Timer (WDT)
A watchdog timer is implemented in the system resources
subsystem running from the ILO; this allows watchdog
operations during Deep-Sleep mode and generates a watchdog
reset if not serviced before the timeout occurs. The watchdog
reset is recorded in the ‘Reset Cause’ register.
Document Number: 001-95464 Rev. *G
Page 6 of 42
PRELIMINARY
Peripheral Blocks
4x PWM
12-Bit SAR ADC
The ADC is a 12-bit, 1-Msps SAR ADC with a built-in
sample-and-hold (S/H) circuit. The ADC can operate with either
an internal voltage reference or an external voltage reference.
Preceding the SAR ADC is the SARMUX, which can route
external pins and internal signals (analog mux bus and
temperature sensor output) to the eight internal channels of the
SAR ADC. The sequencer controller (SARSEQ) is used to
control the SARMUX and SAR ADC to do an automatic scan on
all enabled channels without CPU intervention and for
preprocessing tasks such as averaging the output data. A
Cypress-supplied software driver (Component) is used to control
the ADC peripheral.
Figure 4. SAR ADC System Diagram
Control
P3.0 – P3.7
Configure
Registers
SARSEQ
AHB, DSI
VPLUS
SARMUX
SARADC
Data
Sequencer
VMINUS
SARREF
Analog Mux
Bus A/B
PRoC™ BLE: CYBL1XX7X
Family Datasheet
Vrefs
Ref-bypass
These PWMs are in addition to the TCPWMs. The PWM
peripheral can be configured as 8-bit or 16-bit resolution. The
PWM provides compare outputs to generate single or continuous
timing and control signals in hardware. It also provides an easy
method of generating complex real-time events accurately with
minimal CPU intervention. A maximum of four 8-bit PWMs or two
16-bit PWMs are available.
Serial Communication Block (SCB0/SCB1)
The SCB can be configured as an I2C, UART, or SPI interface. It
supports an 8-byte FIFO for receive and transmit buffers to
reduce CPU intervention. A maximum of two SCBs (SCB0,
SCB1) are available.
I2C mode: The I2C peripheral is compatible with the I2C
Standard-mode, Fast-mode, and Fast-Mode-Plus devices as
defined in the NXP I2C-bus specification and user manual
(UM10204). The I2C bus I/O is implemented with GPIOs in
open-drain modes.
The hardware I2C block implements a full multimaster and slave
interface (it is capable of multimaster arbitration). This block is
capable of operating at speeds of up to 1 Mbps (Fast-Mode Plus)
and has flexible buffering options to reduce the interrupt
overhead and latency for the CPU. The I2C function is
implemented using the Cypress-provided software Component
(EzI2C) that creates a mailbox address range in the memory of
PRoC™ BLE and effectively reduces the I2C communication to
reading from and writing to an array in memory. In addition, the
block supports an 8-byte FIFO for receive and transmit, which,
by increasing the time given for the CPU to read data, greatly
reduces the need for clock stretching caused by the CPU not
having read the data on time.
A diode based, on-chip temperature sensor is used to measure
the die temperature. The temperature sensor is connected to the
ADC, which digitizes the reading and produces a temperature
value using the Cypress-supplied software that includes
calibration and linearization.
When SCB0 is used, Serial Data (SDA) and Serial Clock (SCL)
of I2C can be connected to P0.4 and P0.5, or P1.4 and P1.5, or
P3.0 and P3.1.
4x Timer Counter PWM (TCPWM)
Configurations for I2C are as follows:
■ SCB1 is fully compliant with the Standard-mode (100 kHz),
Fast-mode (400 kHz), and Fast-Mode-Plus (1 MHz) I2C
signaling specifications when routed to GPIO pins P5.0 and
P5.1, except for hot-swap capability during I2C active
communication.
■ SCB1 is compliant only with Standard mode (100 kHz) when
not used with P5.0 and P5.1.
■ SCB0 is compliant with Standard mode (100 kHz) only.
The 16-bit TCPWM module can be used to generate the PWM
output or to capture the timing of edges of input signals or to
provide a timer functionality. TCPWM can also be used as a
16-bit counter that supports up, down, and up/down counting
modes.
Rising edge, falling edge, combined rising/falling edge detection,
or pass-through on all hardware input signals can be used to
derive counter events. Three routed output signals are available
to indicate underflow, overflow, and counter/compare match
events. A maximum of four TCPWMs are available.
Document Number: 001-95464 Rev. *G
When SCB1 is used, SDA and SCL can be connected to P0.0
and P0.1, or P3.4 and P3.5, or P5.0 and P5.1.
UART mode: This is a full-feature UART operating up to 1 Mbps.
It supports automotive single-wire interface (LIN), infrared
interface (IrDA), and SmartCard (ISO7816) protocols. In
addition, it supports the 9-bit multiprocessor mode, which allows
addressing of peripherals connected over common RX and TX
lines. The UART hardware flow control is supported to allow slow
and fast devices to communicate with each other over UART
without the risk of losing data. Refer to Table 4 on page 13 for
possible UART connections to the GPIOs.
Page 7 of 42
PRELIMINARY
SPI Mode: The SPI mode supports full Motorola® SPI, Texas
Instruments® Secure Simple Pairing (SSP) (essentially adds a
start pulse used to synchronize SPI Codecs), and National
Microwire (half-duplex form of SPI). The SPI function is
implemented using the Cypress-provided software Component
(EzSPI), which reduces the data interchange by reading and
writing an array of memory. Refer to Table 4 on page 13 for the
possible SPI connections to the GPIOs.
Inter-IC Sound Bus (I2S)
Inter-IC Sound Bus (I2S) is a serial bus interface standard used
for connecting digital audio devices. The specification is from
Philips® Semiconductor (I2S bus specification; February 1986,
revised June 5, 1996).
I2S operates only in the Master mode, supporting the transmitter
(TX) and the receiver (RX), which have independent data byte
streams. These byte streams are packed with the most
significant byte first. The number of bytes used for each sample
(a sample for the left or right channel) is the minimum number of
bytes to hold a sample.
LCD
The LCD controller can drive up to four commons and up to 32
segments. It uses full digital methods to drive the LCD segments
providing ultra-low power consumption. The two methods used
are referred to as digital correlation and PWM.
The digital correlation method modulates the frequency and
signal levels of the commons and segments to generate the
highest RMS voltage across a segment to light it up or to
maintain the RMS signal as zero. This method is good for STN
displays but may result in reduced contrast in TN (cheaper)
displays.
The PWM method drives the panel with PWM signals to
effectively use the capacitance of the panel to provide the
integration of the modulated pulse-width to generate the desired
LCD voltage. This method results in higher power consumption
but provides better results in driving TN displays.
LCD operation is supported during Deep-Sleep mode by
refreshing a small display buffer (four bits; one 32-bit register per
port).
CapSense
CapSense is supported on all GPIOs through a Capacitive
Sigma-Delta (CSD) block, which can be connected to any GPIO
through an analog mux bus. Any GPIO pin can be connected to
the analog mux bus via an analog switch. The CapSense
Document Number: 001-95464 Rev. *G
PRoC™ BLE: CYBL1XX7X
Family Datasheet
function can thus be provided on any pin or group of pins in a
system under software control. A software Component in PSoC
Creator is provided for the CapSense block to make it easy for
the user. The shield voltage can be driven on another mux bus
to provide liquid-tolerance capability. Driving the shield electrode
in phase with the sense electrode keeps the shield capacitance
from attenuating the sensed input.
The CapSense trackpad/touchpad with gestures has the
following features:
■ Supports 1-finger and 2-finger touch applications
■ Supports up to 36 X/Y sensor inputs
■ Includes a gesture-detection library:
❐ 1-finger touch: Finger tracking, scroll, inertial scroll, click,
double-click, edge swipe
❐ 2-finger touch: Scroll, inertial scroll, zoom-in, zoom-out
I/O Subsystem
The I/O subsystem, which comprises the GPIO block,
implements the following:
■ Eight drive-strength modes:
❐ Analog input mode (input and output buffers disabled)
❐ Input only
❐ Weak pull-up with strong pull-down
❐ Weak pull-up with weak pull-down
❐ Strong pull-up with weak pull-down
❐ Strong pull-up with strong pull-down
❐ Open drain with strong pull-down
❐ Open drain with strong pull-up
■ Port pins: 36
■ Input threshold select (CMOS or LVTTL)
■ Individual control of input and output buffers
(enabling/disabling) in addition to drive-strength modes
■ Hold mode for latching the previous state (used for retaining
the I/O state in Deep Sleep and Hibernate modes)
■ Selectable slew rates for dV/dt to improve EMI
■ The GPIO pins P5.0 and P5.1 are overvoltage-tolerant
■ The GPIO cells, including P5.0 and P5.1, cannot be
hot-swapped or powered up independent of the rest of the
system.
Page 8 of 42
PRELIMINARY
PRoC™ BLE: CYBL1XX7X
Family Datasheet
Pinouts
Table 1 shows the pin list for the CYBL1XX7X device.
Table 1. CYBL1XX7X Pin List (QFN Package)
Pin
Name
Type
Description
1
VDDD
POWER
1.71-V to 5.5-V digital supply
2
XTAL32O/P6.0
CLOCK
32.768-kHz crystal
3
XTAL32I/P6.1
CLOCK
32.768-kHz crystal or external clock input
4
XRES
RESET
Reset, active LOW
5
P4.0
GPIO
Port 4 Pin 0, analog/digital/lcd/csd
6
P4.1
GPIO
Port 4 Pin 1, analog/digital/lcd/csd
7
P5.0
GPIO
Port 5 Pin 0, analog/digital/lcd/csd
8
P5.1
GPIO
Port 5 Pin 1, analog/digital/lcd/csd
9
VSSD
GROUND
10
VDDR
POWER
Digital ground
1.9-V to 5.5-V radio supply
11
GANT1
GROUND
Antenna shielding ground
12
ANT
ANTENNA
Antenna pin
13
GANT2
GROUND
Antenna shielding ground
14
VDDR
POWER
1.9-V to 5.5-V radio supply
15
VDDR
POWER
1.9-V to 5.5-V radio supply
16
XTAL24I
CLOCK
24-MHz crystal or external clock input
17
XTAL24O
CLOCK
24-MHz crystal
18
VDDR
POWER
1.9-V to 5.5-V radio supply
19
P0.0
GPIO
Port 0 Pin 0, analog/digital/lcd/csd
20
P0.1
GPIO
Port 0 Pin 1, analog/digital/lcd/csd
21
P0.2
GPIO
Port 0 Pin 2, analog/digital/lcd/csd
22
P0.3
GPIO
Port 0 Pin 3, analog/digital/lcd/csd
23
VDDD
POWER
24
P0.4
GPIO
Port 0 Pin 4, analog/digital/lcd/csd
25
P0.5
GPIO
Port 0 Pin 5, analog/digital/lcd/csd
26
P0.6
GPIO
Port 0 Pin 6, analog/digital/lcd/csd
27
P0.7
GPIO
Port 0 Pin 7, analog/digital/lcd/csd
28
P1.0
GPIO
Port 1 Pin 0, analog/digital/lcd/csd
29
P1.1
GPIO
Port 1 Pin 1, analog/digital/lcd/csd
30
P1.2
GPIO
Port 1 Pin 2, analog/digital/lcd/csd
31
P1.3
GPIO
Port 1 Pin 3, analog/digital/lcd/csd
32
P1.4
GPIO
Port 1 Pin 4, analog/digital/lcd/csd
33
P1.5
GPIO
Port 1 Pin 5, analog/digital/lcd/csd
34
P1.6
GPIO
Port 1 Pin 6, analog/digital/lcd/csd
1.71-V to 5.5-V digital supply
35
P1.7
GPIO
36
VDDA
POWER
Port 1 Pin 7, analog/digital/lcd/csd
37
P2.0
GPIO
Port 2 Pin 0, analog/digital/lcd/csd
38
P2.1
GPIO
Port 2 Pin 1, analog/digital/lcd/csd
1.71-V to 5.5-V analog supply
39
P2.2
GPIO
Port 2 Pin 2, analog/digital/lcd/csd/WAKEUP
40
P2.3
GPIO
Port 2 Pin 3, analog/digital/lcd/csd
Document Number: 001-95464 Rev. *G
Page 9 of 42
PRELIMINARY
PRoC™ BLE: CYBL1XX7X
Family Datasheet
Table 1. CYBL1XX7X Pin List (QFN Package) (continued)
Pin
Name
Type
Description
41
P2.4
GPIO
Port 2 Pin 4, analog/digital/lcd/csd
42
P2.5
GPIO
Port 2 Pin 5, analog/digital/lcd/csd
43
P2.6
GPIO
Port 2 Pin 6, analog/digital/lcd/csd
44
P2.7
GPIO
Port 2 Pin 7, analog/digital/lcd/csd
45
VREF
REF
46
VDDA
POWER
1.024-V reference
47
P3.0
GPIO
Port 3 Pin 0, analog/digital/lcd/csd
48
P3.1
GPIO
Port 3 Pin 1, analog/digital/lcd/csd
49
P3.2
GPIO
Port 3 Pin 2, analog/digital/lcd/csd
50
P3.3
GPIO
Port 3 Pin 3, analog/digital/lcd/csd
51
P3.4
GPIO
Port 3 Pin 4, analog/digital/lcd/csd
52
P3.5
GPIO
Port 3 Pin 5, analog/digital/lcd/csd
53
P3.6
GPIO
Port 3 Pin 6, analog/digital/lcd/csd
54
P3.7
GPIO
Port 3 Pin 7, analog/digital/lcd/csd
55
VSSA
GROUND
56
VCCD
POWER
57
EPAD
GROUND
1.71-V to 5.5-V analog supply
Analog ground
Regulated 1.8-V supply; connect to 1.3-µF capacitor
Ground paddle for the QFN package
Table 2 shows the pin list for the CYBL1XX7X device (WLCSP package).
Table 2. CYBL1XX7X Pin List (WLCSP Package)
Pin
Name
Type
A1
NC
NC
Do not connect
Description
A2
VREF
REF
1.024-V reference
A3
VSSA
GROUND
A4
P3.3
GPIO
Port 3 Pin 3, analog/digital/lcd/csd
A5
P3.7
GPIO
Port 3 Pin 7, analog/digital/lcd/csd
A6
VSSD
GROUND
Digital ground
A7
VSSA
GROUND
Analog ground
A8
VCCD
POWER
Regulated 1.8-V supply, connect to 1-μF capacitor
A9
VDDD
POWER
1.71-V to 5.5-V digital supply
B1
NB
NO BALL
No Ball
B2
P2.3
GPIO
B3
VSSA
GROUND
B4
P2.7
GPIO
Port 2 Pin 7, analog/digital/lcd/csd
B5
P3.4
GPIO
Port 3 Pin 4, analog/digital/lcd/csd
B6
P3.5
GPIO
Port 3 Pin 5, analog/digital/lcd/csd
Port 3 Pin 6, analog/digital/lcd/csd
Analog ground
Port 2 Pin 3, analog/digital/lcd/csd
Analog ground
B7
P3.6
GPIO
B8
XTAL32I/P6.1
CLOCK
32.768-kHz crystal or external clock input
B9
XTAL32O/P6.0
CLOCK
32.768-kHz crystal
C1
NC
NC
Do not connect
C2
VSSA
GROUND
Analog ground
Document Number: 001-95464 Rev. *G
Page 10 of 42
PRELIMINARY
PRoC™ BLE: CYBL1XX7X
Family Datasheet
Table 2. CYBL1XX7X Pin List (WLCSP Package) (continued)
Pin
Name
Type
Description
C3
P2.2
GPIO
Port 2 Pin 2, analog/digital/lcd/csd
C4
P2.6
GPIO
Port 2 Pin 6, analog/digital/lcd/csd
C5
P3.0
GPIO
Port 3 Pin 0, analog/digital/lcd/csd
C6
P3.1
GPIO
Port 3 Pin 1, analog/digital/lcd/csd
C7
P3.2
GPIO
Port 3 Pin 2, analog/digital/lcd/csd
C8
XRES
RESET
C9
P4.0
GPIO
D1
NC
NC
D2
P1.7
GPIO
D3
VDDA
POWER
D4
P2.0
GPIO
Port 2 Pin 0, analog/digital/lcd/csd
D5
P2.1
GPIO
Port 2 Pin 1, analog/digital/lcd/csd
D6
P2.5
GPIO
Port 2 Pin 5, analog/digital/lcd/csd
D7
VSSD
GROUND
D8
P4.1
GPIO
Port 4 Pin 1, analog/digital/lcd/csd
D9
P5.0
GPIO
Port 5 Pin 0, analog/digital/lcd/csd
E1
NC
NC
E2
P1.2
GPIO
Port 1 Pin 2, analog/digital/lcd/csd
E3
P1.3
GPIO
Port 1 Pin 3, analog/digital/lcd/csd
E4
P1.4
GPIO
Port 1 Pin 4, analog/digital/lcd/csd
E5
P1.5
GPIO
Port 1 Pin 5, analog/digital/lcd/csd
E6
P1.6
GPIO
Port 1 Pin 6, analog/digital/lcd/csd
E7
P2.4
GPIO
Port 2 Pin 4, analog/digital/lcd/csd
E8
P5.1
GPIO
Port 5 Pin 1, analog/digital/lcd/csd
E9
VSSD
GROUND
Reset, active LOW
Port 4 Pin 0, analog/digital/lcd/csd
Do not connect
Port 1 Pin 7, analog/digital/lcd/csd
1.71-V to 5.5-V analog supply
Digital ground
Do not connect
Digital ground
F1
NC
NC
Do not connect
F2
VSSD
GROUND
Digital ground
F3
P0.7
GPIO
Port 0 Pin 7, analog/digital/lcd/csd
F4
P0.3
GPIO
Port 0 Pin 3, analog/digital/lcd/csd
F5
P1.0
GPIO
Port 1 Pin 0, analog/digital/lcd/csd
F6
P1.1
GPIO
Port 1 Pin 1, analog/digital/lcd/csd
F7
VSSR
GROUND
Radio ground
F8
VSSR
GROUND
Radio ground
F9
VDDR
POWER
G1
NC
NC
G2
P0.6
GPIO
G3
VDDD
POWER
1.9-V to 5.5-V radio supply
Do not connect
Port 0 Pin 6, analog/digital/lcd/csd
1.71-V to 5.5-V digital supply
G4
P0.2
GPIO
G5
VSSD
GROUND
Digital ground
G6
VSSR
GROUND
Radio ground
Document Number: 001-95464 Rev. *G
Port 0 Pin 2, analog/digital/lcd/csd
Page 11 of 42
PRELIMINARY
PRoC™ BLE: CYBL1XX7X
Family Datasheet
Table 2. CYBL1XX7X Pin List (WLCSP Package) (continued)
Pin
Name
Type
Description
G7
VSSR
GROUND
Radio ground
G8
GANT
GROUND
Antenna shielding ground
G9
VSSR
GROUND
Radio ground
H1
NC
NC
H2
P0.5
GPIO
Port 0 Pin 5, analog/digital/lcd/csd
Port 0 Pin 1, analog/digital/lcd/csd
Do not connect
H3
P0.1
GPIO
H4
XTAL24O
CLOCK
24-MHz crystal
H5
XTAL24I
CLOCK
24-MHz crystal or external clock input
H6
VSSR
GROUND
H7
VSSR
GROUND
Radio ground
H8
ANT
ANTENNA
Antenna pin
J1
NC
NC
J2
P0.4
GPIO
Radio ground
Do not connect
Port 0 Pin 4, analog/digital/lcd/csd
J3
P0.0
GPIO
J4
VDDR
POWER
1.9-V to 5.5-V radio supply
Port 0 Pin 0, analog/digital/lcd/csd
J7
VDDR
POWER
1.9-V to 5.5-V radio supply
J8
NO CONNECT
–
–
The I/O subsystem consists of a high-speed I/O matrix (HSIOM), which is a group of high-speed switches that routes GPIOs to the
resources inside the device. These resources include CapSense, TCPWMs, I2C, SPI, UART, and LCD. HSIOM_PORT_SELx are
32-bit-wide registers that control the routing of GPIOs. Each register controls one port; four dedicated bits are assigned to each GPIO
in the port. This provides up to 16 different options for GPIO routing as shown in Table 3.
Table 3. HSIOM Port Settings
Value
Description
0
Firmware-controlled GPIO
1
Reserved
2
Reserved
3
Reserved
4
Pin is a CSD sense pin
5
Pin is a CSD shield pin
6
Pin is connected to AMUXA
7
Pin is connected to AMUXB
8
Pin-specific Active function #0
9
Pin-specific Active function #1
10
Pin-specific Active function #2
11
Reserved
12
Pin is an LCD common pin
13
Pin is an LCD segment pin
14
Pin-specific Deep-Sleep function #0
15
Pin-specific Deep-Sleep function #1
Document Number: 001-95464 Rev. *G
Page 12 of 42
PRoC™ BLE: CYBL1XX7X
Family Datasheet
PRELIMINARY
The selection of peripheral functions for different GPIO pins is given in Table 4.
Table 4. Port Pin Connections
Digital (HSIOM_PORT_SELx.SELy) ('x' denotes port number and 'y' denotes pin number)
Name
Analog
GPIO
P0.0
–
GPIO
P0.1
–
GPIO
P0.3
–
P0.4
9
10
Active #0
Active #1
Active #2
Deep Sleep #0
Deep Sleep #1
TCPWM0_P[3]
SCB1_UART_RX[1]
–
SCB1_I2C_SDA[1]
SCB1_SPI_MOSI[1]
TCPWM0_N[3]
SCB1_UART_TX[1]
–
SCB1_I2C_SCL[1]
SCB1_SPI_MISO[1]
GPIO
TCPWM1_N[3]
SCB1_UART_CTS[1]
–
–
GPIO
TCPWM1_P[0]
SCB0_UART_RX[1]
EXT_CLK[0]/
ECO_OUT[0]
SCB0_I2C_SDA[1]
SCB0_SPI_MOSI[1]
P0.5
–
GPIO
TCPWM1_N[0]
SCB0_UART_TX[1]
–
SCB0_I2C_SCL[1]
SCB0_SPI_MISO[1]
P0.6
–
GPIO
TCPWM2_P[0]
SCB0_UART_RTS[1]
–
SWDIO[0]
SCB0_SPI_SS0[1]
P0.7
–
GPIO
TCPWM2_N[0]
SCB0_UART_CTS[1]
–
SWDCLK[0]
SCB0_SPI_SCLK[1]
P1.0
–
GPIO
TCPWM0_P[1]
–
–
–
WCO_OUT[2]
P1.1
–
GPIO
TCPWM0_N[1]
–
–
–
SCB1_SPI_SS1
P1.2
–
GPIO
TCPWM1_P[1]
–
–
–
SCB1_SPI_SS2
P1.3
–
GPIO
TCPWM1_N[1]
–
–
–
SCB1_SPI_SS3
P1.4
–
GPIO
TCPWM2_P[1]
SCB0_UART_RX[0]
–
SCB0_I2C_SDA[0]
SCB0_SPI_MOSI[1]
P1.5
–
GPIO
TCPWM2_N[1]
SCB0_UART_TX[0]
–
SCB0_I2C_SCL[0]
SCB0_SPI_MISO[1]
P1.6
–
GPIO
TCPWM3_P[1]
SCB0_UART_RTS[0]
–
–
SCB0_SPI_SS0[1]
P1.7
–
GPIO
TCPWM3_N[1]
SCB0_UART_CTS[0]
–
–
SCB0_SPI_SCLK[1]
P2.0
–
GPIO
–
–
–
–
SCB0_SPI_SS1
P2.1
–
GPIO
–
–
–
–
SCB0_SPI_SS2
P2.2
–
GPIO
–
–
–
WAKEUP
SCB0_SPI_SS3
P2.3
–
GPIO
–
–
–
–
WCO_OUT[1]
P2.4
–
GPIO
–
–
–
–
–
–
GPIO
–
–
–
–
–
–
GPIO
–
–
–
–
–
–
GPIO
–
–
EXT_CLK[1]/
ECO_OUT[1]
–
–
–
SCB0_I2C_SDA[2]
–
–
P2.5
P2.6
P2.7
0
8
14
15
SCB1_SPI_SCLK[1]
P3.0
SARMUX_0 GPIO
TCPWM0_P[2]
SCB0_UART_RX[2]
P3.1
SARMUX_1 GPIO
TCPWM0_N[2]
SCB0_UART_TX[2]
–
SCB0_I2C_SCL[2]
P3.2
SARMUX_2 GPIO
TCPWM1_P[2]
SCB0_UART_RTS[2]
–
–
–
P3.3
SARMUX_3 GPIO
TCPWM1_N[2]
SCB0_UART_CTS[2]
–
–
–
P3.4
SARMUX_4 GPIO
TCPWM2_P[2]
SCB1_UART_RX[2]
–
SCB1_I2C_SDA[2]
–
P3.5
SARMUX_5 GPIO
TCPWM2_N[2]
SCB1_UART_TX[2]
–
SCB1_I2C_SCL[2]
–
P3.6
SARMUX_6 GPIO
TCPWM3_P[2]
SCB1_UART_RTS[2]
–
–
–
P3.7
SARMUX_7 GPIO
TCPWM3_N[2]
SCB1_UART_CTS[2]
–
–
WCO_OUT[0]
P4.0
CMOD
GPIO
TCPWM0_P[0]
SCB1_UART_RTS[0]
–
–
SCB1_SPI_MOSI[0]
P4.1
CTANK
GPIO
TCPWM0_N[0]
SCB1_UART_CTS[0]
–
–
SCB1_SPI_MISO[0]
P5.0
–
GPIO
TCPWM3_P[0]
SCB1_UART_RX[0]
EXTPA_EN
SCB1_I2C_SDA[0]
SCB1_SPI_SS0[0]
Document Number: 001-95464 Rev. *G
Page 13 of 42
PRoC™ BLE: CYBL1XX7X
Family Datasheet
PRELIMINARY
Table 4. Port Pin Connections (continued)
Digital (HSIOM_PORT_SELx.SELy) ('x' denotes port number and 'y' denotes pin number)
Name
P5.1
P6.0_XTAL32O
Analog
P6.1_XTAL32I
0
8
9
10
14
15
GPIO
Active #0
Active #1
Active #2
Deep Sleep #0
Deep Sleep #1
–
GPIO
TCPWM3_N[0]
SCB1_UART_TX[0]
EXT_CLK[2]/
ECO_OUT[2]
SCB1_I2C_SCL[0]
SCB1_SPI_SCLK[0]
–
GPIO
–
–
–
–
–
–
GPIO
–
–
–
–
–
Power
PRoC™ BLE can be supplied from batteries with a voltage range
of 1.9 V to 5.5 V by directly connecting to the digital supply
(VDDD), analog supply (VDDA), and radio supply (VDDR) pins. The
internal LDOs in the device regulate the supply voltage to
required levels for different blocks. The device has one regulator
for the digital circuitry and separate regulators for radio circuitry
for noise isolation. The analog circuits run directly from the
analog supply (VDDA) input. The device uses separate regulators
for Deep Sleep and Hibernate modes to minimize the power
consumption. The radio stops working below 1.9 V, but the rest
of the system continues to function down to 1.71 V without RF.
Power Supply
Bypass capacitors must be used from VDDx (x = A, D, or R) to
ground. The typical practice for systems in this frequency range
is to use a capacitor in the 1-µF range in parallel with a smaller
capacitor (for example, 0.1 µF). Note that these are simply rules
of thumb and that, for critical applications, the PCB layout, lead
inductance, and the bypass capacitor parasitic should be
simulated to design to obtain optimal bypassing.
VREF (optional)
Bypass Capacitors
VDDD
0.1-µF ceramic at each pin plus bulk
capacitor 1-µF to 10-µF
VDDA
0.1-µF ceramic at each pin plus bulk
capacitor 1-µF to 10-µF
VDDR
0.1-µF ceramic at each pin plus bulk
capacitor 1-µF to 10-µF
VCCD
1.3-µF ceramic capacitor at the VCCD pin
The internal bandgap may be bypassed with
a 1-µF to 10-µF capacitor
Low-Power Modes
PRoC™ BLE supports five power modes. Refer to Table 5 for
more details on the system status. The PRoC™ BLE device
consumes the lowest current in Stop mode; the device wakeup
from stop mode is with a system reset through the XRES or
WAKEUP pin. It can retain the SRAM data in Hibernate mode
and is capable of retaining the complete system status in
Deep-Sleep mode. Table 5 shows the different power modes and
the peripherals that are active.
Table 5. Power Modes System Status
Current
Consumption
Code
Execution
Digital
Peripherals
Available
Analog
Peripherals
Available
Clock
Sources
Available
Wake Up
Sources
Wake-Up
Time
Active
850 µA + 260 µA
per MHz[1]
Yes
All
All
All
–
–
Sleep
1.1 mA at 3 MHz
No
All
All
All
Any interrupt
source
0
Deep Sleep
1.5 μA
No
WDT, LCD,
I2C/SPI,
Link-Layer
POR, BOD
WCO,
ILO
GPIO, WDT,
I2C/SPI Link
Layer
25 μs
Hibernate
150 nA
No
No
POR, BOD
No
GPIO
2 ms
No
Wake-Up pin,
XRES
2.2 ms
Power Mode
Stop
60 nA
No
No
No
Note
1. For CPU subsystem.
Document Number: 001-95464 Rev. *G
Page 14 of 42
PRoC™ BLE: CYBL1XX7X
Family Datasheet
PRELIMINARY
A typical system application connection diagram for the 56-QFN package is shown in Figure 5.
Figure 5. PRoC™ BLE Applications Diagram
VDDA
C1
1.3 uF
1.0
C4
18 pF
U1
2
EPAD
VCCD
VSSA
P3.7
P3.6
P3.5
P3.4
P3.3
P3.2
P3.1
P3.0
VDDA
VREF
P2.7
P2.6
Y2
1
VDDD
1
2
ANTENNA
VDDR
1
2
C6
L1
PRoC BLE
56-QFN
VDDR
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
VDDA
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDDA
15
16
17
18
19
20
21
22
23
24
25
26
27
28
C5
VDDD
XTAL32O/P6.0
XTAL32I/P6.1
XRES
P4.0
P4.1
P5.0
P5.1
VSS
VDDR
GANT1
ANT
GANT2
VDDR
VDDR
XTAL24I
XTAL24O
VDDR
P0.0
P0.1
P0.2
P0.3
VDDD
P0.4
P0.5
P0.6
P0.7
P1.0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
32.768KHz
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
C3
36 pF
C2
1.0 uF
1
VDDD
2
3
Y1
24MHz
4
SWDIO
SWDCLK
VDDR
Document Number: 001-95464 Rev. *G
Page 15 of 42
PRELIMINARY
Development Support
The CYBL1XX7X family has a rich set of documentation,
development tools, and online resources to assist you during
your development process. Visit www.cypress.com/procble to
find out more.
Documentation
A suite of documentation supports the CYBL1XX7X family to
ensure that you find answers to your questions quickly. This
section contains a list of some of the key documents.
Component Datasheets: PSoC Creator Components provide
hardware abstraction using APIs to configure and control
peripheral activity. The Component datasheet covers
Component features, its usage and operation details, API
description, and electrical specifications. This is the primary
documentation used during development. These Components
can represent peripherals on the device (such as a timer, I2C, or
UART) or high-level system functions (such as the BLE
Component).
Application Notes: Application notes help you to understand
how to use various device features. They also provide guidance
on how to solve a variety of system design challenges.
Document Number: 001-95464 Rev. *G
PRoC™ BLE: CYBL1XX7X
Family Datasheet
Technical Reference Manual (TRM): The TRM describes all
peripheral functionality in detail, with register-level descriptions.
This document is divided into two parts: the Architecture TRM
and the Register TRM.
Online
In addition to the print documentation, Cypress forums connect
you with fellow users and experts from around the world, 24
hours a day, 7 days a week.
Tools
With industry-standard cores, programming, and debugging
interfaces, the CYBL1XX7X family is part of a development tool
ecosystem.
Visit us at www.cypress.com/go/psoccreator for the latest information on the revolutionary, easy-to-use PSoC Creator IDE,
supported third-party compilers, programmers, and debuggers.
Kits
Cypress provides a portfolio of kits to accelerate time-to-market.
Visit us at www.cypress.com/procble.
Page 16 of 42
PRoC™ BLE: CYBL1XX7X
Family Datasheet
PRELIMINARY
Electrical Specifications
Exposure to absolute maximum conditions for extended periods
of time may affect device reliability.
This section provides detailed electrical characteristics. Absolute
maximum rating for the CYBL1XX7X devices is listed in Table 6
through Table 51. Usage above the absolute maximum
conditions may cause permanent damage to the device.
The maximum storage temperature is 150 °C in compliance with
JEDEC Standard JESD22-A103, High Temperature Storage
Life. When used below absolute maximum conditions, but above
normal operating conditions, the device may not operate to the
specification.
Absolute Maximum Ratings
Table 6. Absolute Maximum Ratings
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details/
Conditions
SID1
VDDD_ABS
Analog, digital, or radio supply
relative to VSS (VSSD = VSSA)
–0.5
–
6
V
Absolute max
SID2
VCCD_ABS
Direct digital core voltage input
relative to VSSD
–0.5
–
1.95
V
Absolute max
SID3
VGPIO_ABS
GPIO voltage
–0.5
–
VDD +0.5
V
Absolute max
SID4
IGPIO_ABS
Maximum current per GPIO
–25
–
25
mA
Absolute max
SID5
IGPIO_injection
GPIO injection current, Max for VIH
> VDDD, and Min for VIL < VSS
–0.5
–
0.5
mA
Absolute max,
current injected per
pin
BID57
ESD_HBM
Electrostatic discharge human body
model
2200[2]
–
–
V
–
BID58
ESD_CDM
Electrostatic discharge charged
device model
500
–
–
V
–
BID61
LU
Pin current for latch up
–200
–
200
mA
–
BLE Subsystem
Table 7. BLE Subsystem
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details/
Conditions
RF Receiver Specifications
SID340
RXS, IDLE
RX sensitivity with idle transmitter
–
–89
–
dBm
–
SID340A
RXS, IDLE
RX sensitivity with idle transmitter
excluding balun loss
–
–91
–
dBm
Guaranteed by design
simulation
SID341
RXS, DIRTY
RX sensitivity with dirty transmitter
–
–87
–70
dBm
RF-PHY Specification
(RCV-LE/CA/01/C)
SID342
RXS, HIGHGAIN
RX sensitivity in high-gain mode
with idle transmitter
–
–91
–
dBm
–
SID343
PRXMAX
Maximum input power
–10
–1
–
dBm
RF-PHY Specification
(RCV-LE/CA/06/C)
SID344
CI1
Co-channel interference,
Wanted signal at –67 dBm and
Interferer at FRX
–
9
21
dB
RF-PHY Specification
(RCV-LE/CA/03/C)
Note
2. This does not apply to the RF pins (ANT, XTALI, and XTALO). RF pins (ANT, XTALI, and XTALO) are tested for 500-V HBM.
Document Number: 001-95464 Rev. *G
Page 17 of 42
PRoC™ BLE: CYBL1XX7X
Family Datasheet
PRELIMINARY
Table 7. BLE Subsystem (continued)
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details/
Conditions
SID345
CI2
Adjacent channel interference
Wanted signal at –67 dBm and
Interferer at FRX ±1 MHz
–
3
15
dB
RF-PHY Specification
(RCV-LE/CA/03/C)
SID346
CI3
Adjacent channel interference
Wanted signal at –67 dBm and
Interferer at FRX ±2 MHz
–
–29
–
dB
RF-PHY Specification
(RCV-LE/CA/03/C)
SID347
CI4
Adjacent channel interference
Wanted signal at –67 dBm and
Interferer at ≥FRX ±3 MHz
–
–39
–
dB
RF-PHY Specification
(RCV-LE/CA/03/C)
CI5
Adjacent channel interference
Wanted Signal at –67 dBm and
Interferer at Image frequency
(FIMAGE)
–
–20
–
dB
RF-PHY Specification
(RCV-LE/CA/03/C)
SID349
CI6
Adjacent channel interference
Wanted signal at –67 dBm and
Interferer at Image frequency
(FIMAGE ± 1 MHz)
–
–30
–
dB
RF-PHY Specification
(RCV-LE/CA/03/C)
SID350
OBB1
Out-of-band blocking,
Wanted signal at –67 dBm and
Interferer at F = 30–2000 MHz
–30
–27
–
dBm
RF-PHY Specification
(RCV-LE/CA/04/C)
SID351
OBB2
Out-of-band blocking,
Wanted signal at –67 dBm and
Interferer at F = 2,003–2,399 MHz
–35
–27
–
dBm
RF-PHY Specification
(RCV-LE/CA/04/C)
SID352
OBB3
Out-of-band blocking,
Wanted signal at –67 dBm and
Interferer at F = 2,484–2,997 MHz
–35
–27
–
dBm
RF-PHY Specification
(RCV-LE/CA/04/C)
SID353
OBB4
Out-of-band blocking,
Wanted signal a –67 dBm and Interferer at F = 3,000–12,750 MHz
–30
–27
–
dBm
RF-PHY Specification
(RCV-LE/CA/04/C)
IMD
Intermodulation performance
Wanted signal at –64 dBm and
1-Mbps BLE, third, fourth, and fifth
offset channel
–50
–
–
dBm
RF-PHY Specification
(RCV-LE/CA/05/C)
dBm
100-kHz
measurement
bandwidth
ETSI EN300 328
V1.8.1
SID348
SID354
SID355
SID356
RXSE1
Receiver spurious emission
30 MHz to 1.0 GHz
RXSE2
Receiver spurious emission
1.0 GHz to 12.75 GHz
–
–
–47
dBm
1-MHz measurement
bandwidth
ETSI EN300 328
V1.8.1
–
–
–57
RF Transmitter Specifications
SID357
TXP, ACC
RF power accuracy
–
±4
–
dB
–
SID358
TXP, RANGE
RF power control range
–
20
–
dB
–
SID359
TXP, 0 dBm
Output power, 0-dB gain setting
(PA7)
–
0
–
dBm
–
Document Number: 001-95464 Rev. *G
Page 18 of 42
PRoC™ BLE: CYBL1XX7X
Family Datasheet
PRELIMINARY
Table 7. BLE Subsystem (continued)
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details/
Conditions
SID360
TXP, MAX
Output power, maximum power
setting (PA10)
–
3
–
dBm
–
SID361
TXP, MIN
Output power, minimum power
setting (PA1)
–
–18
–
dBm
–
SID362
F2AVG
Average frequency deviation for
10101010 pattern
185
–
–
kHz
RF-PHY Specification
(TRM-LE/CA/05/C)
SID363
F1AVG
Average frequency deviation for
11110000 pattern
225
250
275
kHz
RF-PHY Specification
(TRM-LE/CA/05/C)
SID364
EO
Eye opening = ∆F2AVG/∆F1AVG
0.8
–
–
SID365
FTX, ACC
Frequency accuracy
–150
–
150
kHz
RF-PHY Specification
(TRM-LE/CA/06/C)
SID366
FTX, MAXDR
Maximum frequency drift
–50
–
50
kHz
RF-PHY Specification
(TRM-LE/CA/06/C)
SID367
FTX, INITDR
Initial frequency drift
–20
–
20
kHz
RF-PHY Specification
(TRM-LE/CA/06/C)
SID368
FTX,DR
Maximum drift rate
–20
–
20
kHz/
50 µs
RF-PHY Specification
(TRM-LE/CA/06/C)
SID369
IBSE1
In-band spurious emission at
2-MHz offset
–
–
–20
dBm
RF-PHY Specification
(TRM-LE/CA/03/C)
SID370
IBSE2
In-band spurious emission at
≥3-MHz offset
–
–
–30
dBm
RF-PHY Specification
(TRM-LE/CA/03/C)
SID371
TXSE1
Transmitter spurious emissions
(average), <1.0 GHz
–
–
–55.5
dBm
FCC-15.247
SID372
TXSE2
Transmitter spurious emissions
(average), >1.0 GHz
–
–
–41.5
dBm
FCC-15.247
–
RF-PHY Specification
(TRM-LE/CA/05/C)
RF Current Specification
SID373
IRX
Receive current in normal mode
–
18.7
–
mA
SID373A
IRX_RF
Receive current in normal mode
–
16.4
–
mA
SID374
IRX, HIGHGAIN
Receive current in high-gain mode
–
21.5
–
mA
–
SID375
ITX, 3 dBm
TX current at 3-dBm setting (PA10)
–
20
–
mA
–
SID376
ITX, 0 dBm
TX current at 0-dBm setting (PA7)
–
16.5
–
mA
–
SID376A
ITX_RF, 0 dBm
TX current at 0-dBm setting (PA7)
–
15.6
–
mA
Measured at VDDR
SID376B
ITX_RF, 0 dBm
TX current at 0 dBm excluding
Balun loss
–
14.2
–
mA
Guaranteed by design
simulation
SID377
ITX, -3 dBm
TX current at –3-dBm setting (PA4)
–
15.5
–
mA
–
SID378
ITX, -6 dBm
TX current at –6-dBm setting (PA3)
–
14.5
–
mA
–
SID379
ITX, -12 dBm
TX current at –12-dBm setting
(PA2)
–
13.2
–
mA
–
SID380
ITX, -18 dBm
TX current at –18-dBm setting
(PA1)
–
12.5
–
mA
–
SID380A
Iavg_1sec, 0dBm
Average current at 1-second BLE
connection interval
–
18.9
–
µA
TXP: 0 dBm; ±20-ppm
master and slave
clock accuracy
Document Number: 001-95464 Rev. *G
Measured at VDDR
Page 19 of 42
PRoC™ BLE: CYBL1XX7X
Family Datasheet
PRELIMINARY
Table 7. BLE Subsystem (continued)
Spec ID#
SID380B
Parameter
Iavg_4sec, 0dBm
Description
Average current at 4-second BLE
connection interval
Min
Typ
Max
Units
Details/
Conditions
–
6.25
–
µA
TXP: 0 dBm; ±20-ppm
master and slave
clock accuracy
2400
–
2482
MHz
–
General RF Specification
SID381
FREQ
RF operating frequency
SID382
CHBW
Channel spacing
–
2
–
MHz
–
SID383
DR
On-air data rate
–
1000
–
kbps
–
SID384
IDLE2TX
BLE Radio Idle to BLE Radio TX
transition time
–
120
140
µs
–
SID385
IDLE2RX
BLE Radio Idle to BLE Radio RX
transition time
–
75
120
µs
–
RSSI Specification
SID386
RSSI, ACC
RSSI accuracy
–
±5
–
dB
–
SID387
RSSI, RES
RSSI resolution
–
1
–
dB
–
SID388
RSSI, PER
RSSI sample period
–
6
–
µs
–
Device-Level Specifications
All specifications are valid for –40 °C TA 85 °C and TJ 100 °C, except where noted. Specifications are valid for 1.71-V to 5.5-V,
except where noted.
Table 8. DC Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details/
Conditions
SID6
VDD
Power supply input voltage (VDDA =
VDDD = VDD)
1.8
–
5.5
V
With regulator enabled
SID7
VDD
Power supply input voltage unregulated (VDDA = VDDD = VDD)
1.71
1.8
1.89
V
Internally unregulated
supply
SID8
VDDR
Radio supply voltage (Radio on)
1.9
–
5.5
V
–
SID8A
VDDR
Radio supply voltage (Radio off)
1.71
–
5.5
V
–
SID9
VCCD
Digital regulator output voltage (for
core logic)
–
1.8
–
V
–
SID10
CVCCD
Digital regulator output bypass
capacitor
1
1.3
1.6
µF
X5R ceramic or better
Active Mode, VDD = 1.71 V to 5.5 V
SID13
IDD3
Execute from flash; CPU at 3 MHz
–
1.7
–
mA
T = 25 °C,
VDD = 3.3 V
SID14
IDD4
Execute from flash; CPU at 3 MHz
–
–
–
mA
T = –40 °C to 85 °C
SID15
IDD5
Execute from flash; CPU at 6 MHz
–
2.5
–
mA
T = 25 °C,
VDD = 3.3 V
SID16
IDD6
Execute from flash; CPU at 6 MHz
–
–
–
mA
T = –40 °C to 85 °C
SID17
IDD7
Execute from flash; CPU at 12 MHz
–
4
–
mA
T = 25 °C,
VDD = 3.3 V
SID18
IDD8
Execute from flash; CPU at 12 MHz
–
–
–
mA
T = –40 °C to 85 °C
SID19
IDD9
Execute from flash; CPU at 24 MHz
–
7.1
–
mA
T = 25 °C,
VDD = 3.3 V
Document Number: 001-95464 Rev. *G
Page 20 of 42
PRoC™ BLE: CYBL1XX7X
Family Datasheet
PRELIMINARY
Table 8. DC Specifications (continued)
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details/
Conditions
SID20
IDD10
Execute from flash; CPU at 24 MHz
–
–
–
mA
T = –40 °C to 85 °C
SID21
IDD11
Execute from flash; CPU at 48 MHz
–
13.4
–
mA
T = 25 °C,
VDD = 3.3 V
SID22
IDD12
Execute from flash; CPU at 48 MHz
–
–
–
mA
T = –40 °C to 85 °C
IMO on
–
–
–
mA
T = 25 °C,
VDD = 3.3 V,
SYSCLK = 3 MHz
–
–
–
mA
T = 25 °C,
VDD = 3.3 V, SYSCLK
= 3 MHz
Sleep Mode, VDD = 1.8 to 5.5 V
SID23
IDD13
Sleep Mode, VDD and VDDR = 1.9 to 5.5 V
SID24
IDD14
ECO on
Deep-Sleep Mode, VDD = 1.8 to 3.6 V
SID25
IDD15
WDT with WCO on
–
1.5
–
µA
T = 25 °C,
VDD = 3.3 V
SID26
IDD16
WDT with WCO on
–
–
–
µA
T = –40 °C to 85 °C
Deep-Sleep Mode, VDD = 3.6 to 5.5 V
SID27
IDD17
WDT with WCO on
–
–
–
µA
T = 25 °C,
VDD = 5 V
SID28
IDD18
WDT with WCO on
–
–
–
µA
T = –40 °C to 85 °C
Deep-Sleep Mode, VDD = 1.71 to 1.89 V (Regulator Bypassed)
SID29
IDD19
WDT with WCO on
–
–
–
µA
T = 25 °C
SID30
IDD20
WDT with WCO on
–
–
–
µA
T = –40 °C to 85 °C
Hibernate Mode, VDD = 1.8 to 3.6 V
SID37
IDD27
GPIO and reset active
–
150
–
nA
T = 25 °C,
VDD = 3.3 V
SID38
IDD28
GPIO and reset active
–
–
–
nA
T = –40 °C to 85 °C
Hibernate Mode, VDD = 3.6 to 5.5 V
SID39
IDD29
GPIO and reset active
–
–
–
nA
T = 25 °C,
VDD = 5 V
SID40
IDD30
GPIO and reset active
–
–
–
nA
T = –40 °C to 85 °C
Hibernate Mode, VDD = 1.71 to 1.89 V (Regulator Bypassed)
SID41
IDD31
GPIO and reset active
–
–
–
nA
T = 25 °C
SID42
IDD32
GPIO and reset active
–
–
–
nA
T = –40 °C to 85 °C
Stop Mode, VDD = 1.8 to 3.6 V
SID43
IDD33
Stop-mode current (VDD)
–
20
–
nA
T = 25 °C,
VDD = 3.3 V
SID44
IDD34
Stop-mode current (VDDR)
–
40
–-
nA
T = 25 °C,
VDDR = 3.3 V
SID45
IDD35
Stop-mode current (VDD)
–
–
–
nA
T = –40 °C to 85 °C
SID46
IDD36
Stop-mode current (VDDR)
–
–
–
nA
T = –40 °C to 85 °C,
VDDR = 1.9 V to 3.6 V
Stop-mode current (VDD)
–
–
–
nA
T = 25 °C,
VDD = 5 V
Stop Mode, VDD = 3.6 to 5.5 V
SID47
IDD37
Document Number: 001-95464 Rev. *G
Page 21 of 42
PRoC™ BLE: CYBL1XX7X
Family Datasheet
PRELIMINARY
Table 8. DC Specifications (continued)
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details/
Conditions
SID48
IDD38
Stop-mode current (VDDR)
–
–
–
nA
T = 25 °C,
VDDR = 5 V
SID49
IDD39
Stop-mode current (VDD)
–
–
–
nA
T = –40 °C to 85 °C
SID50
IDD40
Stop-mode current (VDDR)
–
–
–
nA
T = –40 °C to 85 °C
Stop Mode, VDD = 1.71 to 1.89 V (Regulator Bypassed)
SID51
IDD41
Stop-mode current (VDD)
–
–
–
nA
T = 25 °C
SID52
IDD42
Stop-mode current (VDD)
–
–
–
nA
T = –40 °C to 85 °C
Table 9. AC Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details/
Conditions
1.71 V VDD 5.5 V
SID53
FCPU
CPU frequency
DC
–
48
MHz
SID54
TSLEEP
Wakeup from Sleep mode
–
0
–
µs
Guaranteed by
characterization
SID55
TDEEPSLEEP
Wakeup from Deep-Sleep mode
–
–
25
µs
24-MHz IMO.
Guaranteed by
characterization
SID56
THIBERNATE
Wakeup from Hibernate mode
–
–
2
ms
Guaranteed by
characterization
SID57
TSTOP
Wakeup from Stop mode
–
–
2.2
ms
Guaranteed by
characterization
Min
Typ
Max
Units
GPIO
Table 10. GPIO DC Specifications
Spec ID#
Parameter
Description
Details/
Conditions
SID58
VIH
Input voltage HIGH threshold
0.7 × VDD
–
–
V
CMOS input
SID59
VIL
Input voltage LOW threshold
–
–
0.3 × VDD
V
CMOS input
SID60
VIH
LVTTL input, VDD < 2.7 V
0.7 × VDD
–
-
V
–
SID61
VIL
LVTTL input, VDD < 2.7 V
–
–
0.3× VDD
V
–
SID62
VIH
LVTTL input, VDD >= 2.7 V
2.0
–
-
V
–
SID63
VIL
LVTTL input, VDD >= 2.7 V
–
–
0.8
V
–
SID64
VOH
Output voltage HIGH level
VDD –0.6
–
–
V
IOH = 4-mA at 3.3-V
VDD
SID65
VOH
Output voltage HIGH level
VDD –0.5
–
–
V
IOH = 1-mA at 1.8-V
VDD
SID66
VOL
Output voltage LOW level
–
–
0.6
V
IOL = 8-mA at 3.3-V
VDD
SID67
VOL
Output voltage LOW level
–
–
0.6
V
IOL = 4-mA at 1.8-V
VDD
SID68
VOL
Output voltage LOW level
–
–
0.4
V
IOL = 3-mA at 3.3-V
VDD
SID69
RPULLUP
Pull-up resistor
3.5
5.6
8.5
kΩ
–
SID70
RPULLDOWN
Pull-down resistor
3.5
5.6
8.5
kΩ
–
Note
3. VIH must not exceed VDD + 0.2 V.
Document Number: 001-95464 Rev. *G
Page 22 of 42
PRoC™ BLE: CYBL1XX7X
Family Datasheet
PRELIMINARY
Table 10. GPIO DC Specifications (continued)
Spec ID#
SID71
Parameter
Description
Min
Typ
Max
Units
IIL
Input leakage current (absolute value)
–
–
2
nA
Details/
Conditions
25 °C,
VDD = 3.3 V
SID72
IIL_CTBM
Input leakage on CTBm input pins
–
–
4
nA
–
SID73
CIN
Input capacitance
–
–
7
pF
–
SID74
VHYSTTL
Input hysteresis LVTTL
25
40
0.05 ×
VDD
–
–
mV
–
mV
VDD > 2.7 V
SID75
VHYSCMOS
Input hysteresis CMOS
SID76
IDIODE
Current through protection diode to
VDD/VSS
–
–
100
µA
–
SID77
ITOT_GPIO
Maximum total source or sink chip
current
–
–
200
mA
–
Details/
Conditions
Table 11. GPIO AC Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Units
SID78
TRISEF
Rise time in Fast-Strong mode
2
–
12
ns
3.3-V VDDD,
CLOAD = 25-pF
SID79
TFALLF
Fall time in Fast-Strong mode
2
–
12
ns
3.3-V VDDD,
CLOAD = 25-pF
SID80
TRISES
Rise time in Slow-Strong mode
10
–
60
ns
3.3-V VDDD,
CLOAD = 25-pF
SID81
TFALLS
Fall time in Slow-Strong mode
10
–
60
ns
3.3-V VDDD,
CLOAD = 25-pF
SID82
FGPIOUT1
GPIO Fout; 3.3 V VDD 5.5 V.
Fast-Strong mode
–
–
33
MHz
90/10%, 25-pF load,
60/40 duty cycle
SID83
FGPIOUT2
GPIO Fout; 1.7 VVDD 3.3 V.
Fast-Strong mode
–
–
16.7
MHz
90/10%, 25-pF load,
60/40 duty cycle
SID84
FGPIOUT3
GPIO Fout; 3.3 V VDD 5.5 V.
Slow-Strong mode
–
–
7
MHz
90/10%, 25-pF load,
60/40 duty cycle
SID85
FGPIOUT4
GPIO Fout; 1.7 V VDD 3.3 V.
Slow-Strong mode
–
–
3.5
MHz
90/10%, 25-pF load,
60/40 duty cycle
SID86
FGPIOIN
GPIO input operating frequency.
1.71 V VDD 5.5 V
–
–
48
MHz
90/10% VIO
Min
Typ
Max
Units
Table 12. OVT GPIO DC Specifications (P5_0 and P5_1 Only)
Spec ID#
Parameter
Description
Details/
Conditions
SID71A
IIL
Input leakage (absolute value).
VIH > VDD
–
–
10
µA
25°C, VDD = 0 V,
VIH = 3.0 V
SID66A
VOL
Output voltage LOW level
–
–
0.4
V
IOL = 20-mA,
VDD > 2.9 V
Document Number: 001-95464 Rev. *G
Page 23 of 42
PRoC™ BLE: CYBL1XX7X
Family Datasheet
PRELIMINARY
Table 13. OVT GPIO AC Specifications (P5_0 and P5_1 Only)
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details/
Conditions
SID78A
TRISE_OVFS
Output rise time in Fast-Strong mode
1.5
–
12
ns
25-pF load,
10%–90%,
VDD = 3.3-V
SID79A
TFALL_OVFS
Output fall time in Fast-Strong mode
1.5
–
12
ns
25-pF load,
10%–90%,
VDD = 3.3-V
SID80A
TRISESS
Output rise time in Slow-Strong mode
10
–
60
ns
25-pF load,
10%-90%,
VDD = 3.3-V
SID81A
TFALLSS
Output fall time in Slow-Strong mode
10
–
60
ns
25-pF load,
10%-90%,
VDD = 3.3-V
SID82A
FGPIOUT1
GPIO FOUT; 3.3 V ≤ VDD ≤ 5.5 V
Fast-Strong mode
–
–
24
MHz
90/10%, 25-pF
load, 60/40 duty
cycle
SID83A
FGPIOUT2
GPIO FOUT; 1.71 V ≤ VDD ≤ 3.3 V
Fast-Strong mode
–
–
16
MHz
90/10%, 25-pF
load, 60/40 duty
cycle
Min
Typ
Max
Units
0.7 ×
VDDD
–
–
V
CMOS input
–
–
0.3 × VDDD
V
CMOS input
3.5
5.6
8.5
kΩ
XRES
Table 14. XRES DC Specifications
Spec ID#
SID87
Parameter
Description
VIH
Input voltage HIGH threshold
Details/
Conditions
SID88
VIL
Input voltage LOW threshold
SID89
RPULLUP
Pull-up resistor
SID90
CIN
Input capacitance
–
3
–
pF
–
SID91
VHYSXRES
Input voltage hysteresis
–
100
–
mV
–
SID92
IDIODE
Current through protection diode to
VDD/VSS
–
–
100
µA
–
–
Table 15. XRES AC Specifications
Spec ID#
SID93
Parameter
TRESETWIDTH
Description
Reset pulse width
Document Number: 001-95464 Rev. *G
Min
Typ
Max
Units
1
–
–
µs
Details/
Conditions
–
Page 24 of 42
PRoC™ BLE: CYBL1XX7X
Family Datasheet
PRELIMINARY
Analog Peripherals
Temperature Sensor
Table 16. Temperature Sensor Specifications
Spec ID#
SID155
Parameter
TSENSACC
Description
Temperature sensor accuracy
Min
Typ
Max
Units
Details/Conditions
–5
±1
5
°C
–40 to +85 °C
SAR ADC
Table 17. SAR ADC DC Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID156
A_RES
Resolution
–
–
12
bits
SID157
A_CHNIS_S
Number of channels – single-ended
–
–
8
–
8 full-speed
–
SID158
A-CHNKS_D
Number of channels – differential
–
–
4
–
Differential inputs use
neighboring I/O
SID159
A-MONO
Monotonicity
–
–
–
–
Yes
SID160
A_GAINERR
Gain error
–
–
±0.1
%
With external
reference
SID161
A_OFFSET
Input offset voltage
–
–
2
mV
Measured with 1-V
VREF
SID162
A_ISAR
Current consumption
–
–
1
mA
–
SID163
A_VINS
Input voltage range – single-ended
VSS
–
VDDA
V
–
SID164
A_VIND
Input voltage range – differential
VSS
–
VDDA
V
–
SID165
A_INRES
Input resistance
–
–
2.2
kΩ
–
SID166
A_INCAP
Input capacitance
–
–
10
pF
SID312
VREFSAR
Trimmed internal reference to SAR
–1
–
1
%
Min
Typ
Max
Units
–
Percentage of Vbg
(1.024 V)
Table 18. SAR ADC AC Specifications
Spec ID#
Parameter
Description
Details/
Conditions
Measured at 1-V
reference
SID167
A_PSRR
Power supply rejection ratio
70
–
–
dB
SID168
A_CMRR
Common-mode rejection ratio
66
–
–
dB
–
SID169
A_SAMP
Sample rate
–
–
1
Msps
–
SID313
Fsarintref
SAR operating speed without external
reference bypass
–
–
100
Ksps
SID170
A_SNR
Signal-to-noise ratio (SNR)
65
–
–
dB
SID171
A_BW
Input bandwidth without aliasing
–
–
A_SAMP/2
kHz
SID172
A_INL
Integral nonlinearity (INL). VDD = 1.71 to
5.5 V, 1 Msps
–1.7
–
2
LSB
VREF = 1 V to VDD
SID173
A_INL
Integral nonlinearity. VDDD = 1.71 to
3.6 V, 1 Msps
–1.5
–
1.7
LSB
VREF = 1.71 V to VDD
SID174
A_INL
Integral nonlinearity. VDD = 1.71 to 5.5 V,
500 Ksps
–1.5
–
1.7
LSB
VREF = 1 V to VDD
SID175
A_DNL
Differential nonlinearity (DNL). VDD =
1.71 to 5.5 V, 1 Msps
–1
–
2.2
LSB
VREF = 1 V to VDD
Document Number: 001-95464 Rev. *G
12-bit resolution
FIN = 10 kHz
–
Page 25 of 42
PRoC™ BLE: CYBL1XX7X
Family Datasheet
PRELIMINARY
Table 18. SAR ADC AC Specifications (continued)
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details/
Conditions
SID176
A_DNL
Differential nonlinearity. VDD = 1.71 to
3.6 V, 1 Msps
–1
–
2
LSB
VREF = 1.71 V to VDD
SID177
A_DNL
Differential nonlinearity. VDD = 1.71 to
5.5 V, 500 Ksps
–1
–
2.2
LSB
VREF = 1 V to VDD
SID178
A_THD
Total harmonic distortion
–
–
–65
dB
Description
Min
Typ
Max
Units
Details/
Conditions
1.71
–
5.5
V
–
FIN = 10 kHz
CSD
Table 19. CSD Block Specifications
Spec ID#
Parameter
SID179
VCSD
Voltage range of operation
SID180
IDAC1
DNL for 8-bit resolution
–1
–
1
LSB
–
SID181
IDAC1
INL for 8-bit resolution
–3
–
3
LSB
–
SID182
IDAC2
DNL for 7-bit resolution
–1
–
1
LSB
–
SID183
IDAC2
INL for 7-bit resolution
–3
–
3
LSB
–
5
–
–
Rati
o
Capacitance range of
9-pF to 35-pF; 0.1-pF
sensitivity. Radio is not
operating during the scan.
Output current of IDAC1 (8-bits) in HIGH
IDAC1_CRT1 range
–
612
–
µA
–
SID186
Output current of IDAC1 (8-bits) in LOW
IDAC1_CRT2 range
–
306
–
µA
–
SID187
Output current of IDAC2 (7-bits) in HIGH
IDAC2_CRT1 range
–
305
–
µA
–
SID188
Output current of IDAC2 (7-bits) in LOW
IDAC2_CRT2 range
–
153
–
µA
–
SID184
SNR
SID185
Ratio of counts of finger to noise
Digital Peripherals
4x TCPWM
Table 20. Timer DC Specifications
Spec ID
SID189
SID190
SID191
Parameter
ITIM1
Description
Block current consumption at 3 MHz
Min
–
Typ
–
Max
43
Units
µA
Details/Conditions
16-bit timer
ITIM2
Block current consumption at 12 MHz
–
–
152
µA
16-bit timer
ITIM3
Block current consumption at 48 MHz
–
–
620
µA
16-bit timer
Table 21. Timer AC Specifications
Spec ID
SID192
Parameter
TTIMFREQ
Description
Operating frequency
Min
FCLK
Typ
–
Max
48
Units
MHz
Details/Conditions
–
SID193
TCAPWINT
SID194
TCAPWEXT
Capture pulse width (internal)
2 × TCLK
–
–
ns
–
Capture pulse width (external)
2 × TCLK
–
–
ns
–
SID195
TTIMRES
Timer resolution
SID196
TTENWIDINT
Enable pulse width (internal)
SID197
TTENWIDEXT
SID198
TTIMRESWINT
TCLK
–
–
ns
–
2 × TCLK
–
–
ns
–
Enable pulse width (external)
2 × TCLK
–
–
ns
–
Reset pulse width (internal)
2 × TCLK
–
–
ns
–
Document Number: 001-95464 Rev. *G
Page 26 of 42
PRoC™ BLE: CYBL1XX7X
Family Datasheet
PRELIMINARY
Table 21. Timer AC Specifications (continued)
Spec ID
SID199
Parameter
TTIMRESEXT
Description
Reset pulse width (external)
Min
2 × TCLK
Typ
–
Max
–
Units
ns
Details/Conditions
–
Units
Details/Conditions
µA
16-bit Counter
Counter
Table 22. Counter DC Specifications
Spec ID
SID200
Parameter
ICTR1
Description
Block current consumption at 3 MHz
Min
–
Typ
–
Max
43
SID201
ICTR2
Block current consumption at 12 MHz
–
–
152
µA
16-bit Counter
SID202
ICTR3
Block current consumption at 48 MHz
–
–
620
µA
16-bit Counter
Min
FCLK
Typ
–
Max
48
Units
MHz
Details/Conditions
–
Table 23. Counter AC Specifications
Spec ID
SID203
Parameter
TCTRFREQ
Description
Operating frequency
SID204
TCTRPWINT
Capture pulse width (internal)
2 × TCLK
–
–
ns
–
SID205
TCTRPWEXT
Capture pulse width (external)
2 × TCLK
–
–
ns
–
SID206
TCTRES
Counter resolution
TCLK
–
–
ns
–
SID207
TCENWIDINT
Enable pulse width (internal)
2 × TCLK
–
–
ns
–
SID208
TCENWIDEXT
Enable pulse width (external)
2 × TCLK
–
–
ns
–
SID209
TCTRRESWINT Reset pulse width (internal)
2 × TCLK
–
–
ns
–
SID210
TCTRRESWEXT Reset pulse width (external)
2 × TCLK
–
–
ns
–
Pulse Width Modulation (PWM)
Table 24. PWM DC Specifications
Min
Typ
Max
Units
SID211
Spec ID
IPWM1
Parameter
Block current consumption at 3 MHz
Description
–
–
43
µA
16-bit PWM
Details/Conditions
SID212
IPWM2
Block current consumption at 12 MHz
–
–
152
µA
16-bit PWM
SID213
IPWM3
Block current consumption at 48 MHz
–
–
620
µA
16-bit PWM
Table 25. PWM AC Specifications
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
FCLK
–
48
MHz
–
Pulse width (internal)
2 × TCLK
–
–
ns
–
Pulse width (external)
2 × TCLK
–
–
ns
–
TPWMKILLINT
Kill pulse width (internal)
2 × TCLK
–
–
ns
–
TPWMKILLEXT
Kill pulse width (external)
2 × TCLK
–
–
ns
–
SID219
TPWMEINT
Enable pulse width (internal)
2 × TCLK
–
–
ns
–
SID220
TPWMENEXT
Enable pulse width (external)
2 × TCLK
–
–
ns
–
SID221
TPWMRESWINT
Reset pulse width (internal)
2 × TCLK
–
–
ns
–
SID222
TPWMRESWEXT Reset pulse width (external)
2 × TCLK
–
–
ns
–
SID214
TPWMFREQ
Operating frequency
SID215
TPWMPWINT
SID216
TPWMEXT
SID217
SID218
Document Number: 001-95464 Rev. *G
Page 27 of 42
PRoC™ BLE: CYBL1XX7X
Family Datasheet
PRELIMINARY
I2C
Table 26. I2C DC Specifications
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID223
II2C1
Block current consumption at 100 kHz
–
–
50
µA
–
SID224
II2C2
Block current consumption at 400 kHz
–
–
155
µA
–
SID225
II2C3
Block current consumption at 1 Mbps
–
–
390
µA
–
–
–
1.4
µA
–
Min
–
Typ
–
Max
1
Units
Mbps
Details/Conditions
–
Min
Typ
Max
Units
–
17.5
–
µA
–
500
5000
pF
–
20
–
mV
–
2
–
mA
–
2
–
mA
Min
10
Typ
50
Max
150
Units
Hz
SID226
II2C4
2
I C enabled in Deep-Sleep mode
Table 27. Fixed I2C AC Specifications
Spec ID
SID227
Parameter
FI2C1
Description
Bit rate
LCD Direct Drive
Table 28. LCD Direct Drive DC Specifications
Spec ID
Parameter
SID228
ILCDLOW
SID229
CLCDCAP
SID230
LCDOFFSET
SID231
ILCDOP1
SID232
ILCDOP2
Description
Operating current in low-power mode
LCD capacitance per segment/common
driver
Long-term segment offset
LCD system operating current.
Vbias = 5 V
LCD system operating current.
Vbias = 3.3 V
Details/Conditions
16 × 4 small-segment
display at 50 Hz
32 × 4 segments.
50 Hz. 25 °C
32 × 4 segments.
50 Hz. 25 °C
Table 29. LCD Direct Drive AC Specifications
Spec ID
SID233
Parameter
FLCD
Description
LCD frame rate
Details/Conditions
–
Table 30. Fixed UART DC Specifications
Description
Min
Typ
Max
Units
Details/Conditions
SID234
Spec ID
IUART1
Parameter
Block current consumption at 100 kbps
–
–
55
µA
–
SID235
IUART2
Block current consumption at
1000 kbps
–
–
360
µA
–
Min
Typ
Max
Units
Details/Conditions
–
–
1
Mbps
–
Min
Typ
Max
Units
Details/Conditions
Table 31. Fixed UART AC Specifications
Spec ID
SID236
Parameter
FUART
Description
Bit rate
SPI Specifications
Table 32. Fixed SPI DC Specifications
Spec ID
Parameter
Description
SID237
ISPI1
Block current consumption at 1 Mbps
–
–
360
µA
–
SID238
ISPI2
Block current consumption at 4 Mbps
–
–
560
µA
–
SID239
ISPI3
Block current consumption at 8 Mbps
–
–
600
µA
–
Document Number: 001-95464 Rev. *G
Page 28 of 42
PRoC™ BLE: CYBL1XX7X
Family Datasheet
PRELIMINARY
Table 33. Fixed SPI AC Specifications
Spec ID
SID240
Parameter
Description
SPI operating frequency (master; 6x
oversampling)
FSPI
Min
Typ
Max
Units
Details/Conditions
–
–
8
MHz
–
Min
–
Typ
–
Max
18
Units
ns
Details/Conditions
–
20
–
–
ns
Full clock, late MISO
sampling
0
–
–
ns
Referred to Slave
capturing edge
Table 34. Fixed SPI Master Mode AC Specifications
Spec ID
SID241
Parameter
TDMO
SID242
TDSI
SID243
THMO
Description
MOSI valid after SCLK driving edge
MISO valid before SCLK capturing
edge. Full clock, late MISO sampling
used
Previous MOSI data hold time
Table 35. Fixed SPI Slave Mode AC Specifications
Spec ID
SID244
Parameter
TDMI
Description
MOSI valid before SCLK capturing edge
SID245
TDSO
SID246
TDSO_ext
SID247
THSO
MISO valid after SCLK driving edge
MISO Valid after SCLK driving edge in
external clock mode. VDD < 3.0 V
Previous MISO data hold time
SID248
TSSELSCK
SSEL valid to first SCK valid edge
Min
40
Typ
–
Max
–
Units
ns
–
–
42 + 3 × TCPU
ns
–
–
53
ns
0
–
–
ns
100
–
–
ns
Memory
Table 36. Flash DC Specifications
Spec ID
SID249
Parameter
VPE
Description
Erase and program voltage
Min
1.71
Typ
–
Max
5.5
Units
V
SID309
TWS48
SID310
SID311
Details/Conditions
–
CPU execution from
flash
CPU execution from
flash
CPU execution from
flash
Number of Wait states at 32–48 MHz
2
–
–
–
TWS32
Number of Wait states at 16–32 MHz
1
–
–
–
TWS16
Number of Wait states for 0–16 MHz
0
–
–
–
Min
Typ
Max
Units
–
–
20
ms
–
–
13
ms
Row program time after erase
–
–
7
ms
–
Bulk erase time (256 KB)
–
–
35
ms
–
Table 37. Flash AC Specifications
Spec ID
Parameter
SID250
TROWWRITE[4]
SID251
[4]
SID252
SID253
TROWERASE
TROWPROGRAM
TBULKERASE[4]
Description
Row (block) write time (erase and
program)
Row erase time
[4]
SID254
TDEVPROG[4]
Total device program time
SID255
FEND
SID256
FRET
SID257
FRET2
Flash endurance
Flash retention. TA 55 °C, 100 K P/E
cycles
Flash retention. TA 85 °C, 10 K P/E
cycles
Details/Conditions
Row (block) =
256 bytes
–
–
–
25
seconds
–
100 K
–
–
cycles
–
20
–
–
years
–
10
–
–
years
–
Note
4. It can take as much as 20 ms to write to flash. During this time, the device should not be reset, or flash operations will be interrupted and cannot be relied on to have
completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs. Make
certain that these are not inadvertently activated.
Document Number: 001-95464 Rev. *G
Page 29 of 42
PRoC™ BLE: CYBL1XX7X
Family Datasheet
PRELIMINARY
System Resources
Power-on-Reset (POR)
Table 38. POR DC Specifications
Min
Typ
Max
Units
Details/Conditions
SID258
Spec ID
VRISEIPOR
Parameter
Rising trip voltage
Description
0.80
–
1.45
V
–
SID259
VFALLIPOR
Falling trip voltage
0.75
–
1.40
V
–
SID260
VIPORHYST
Hysteresis
15
–
200
mV
–
Description
Min
Typ
Max
Units
Details/Conditions
Precision power-on reset (PPOR)
response time in Active and Sleep
modes
–
–
1
µs
–
Table 39. POR AC Specifications
Spec ID
SID264
Parameter
TPPOR_TR
Table 40. Brown-Out Detect
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details/
Conditions
SID261
VFALLPPOR
BOD trip voltage in Active and Sleep
modes
1.64
–
–
V
–
SID262
VFALLDPSLP
BOD trip voltage in Deep Sleep
1.4
–
–
V
–
Min
Typ
Max
Units
Details/
Conditions
1.1
–
–
V
–
Description
Min
Typ
Max
Units
Table 41. Hibernate Reset
Spec ID#
SID263
Parameter
VHBRTRIP
Description
BOD trip voltage in Hibernate
Voltage Monitors (LVD)
Table 42. Voltage Monitor DC Specifications
SID265
VLVI1
LVI_A/D_SEL[3:0] = 0000b
1.71
1.75
1.79
V
Details/
Conditions
–
SID266
VLVI2
LVI_A/D_SEL[3:0] = 0001b
1.76
1.80
1.85
V
–
SID267
VLVI3
LVI_A/D_SEL[3:0] = 0010b
1.85
1.90
1.95
V
–
Spec ID
Parameter
SID268
VLVI4
LVI_A/D_SEL[3:0] = 0011b
1.95
2.00
2.05
V
–
SID269
VLVI5
LVI_A/D_SEL[3:0] = 0100b
2.05
2.10
2.15
V
–
SID270
VLVI6
LVI_A/D_SEL[3:0] = 0101b
2.15
2.20
2.26
V
–
SID271
VLVI7
LVI_A/D_SEL[3:0] = 0110b
2.24
2.30
2.36
V
–
SID272
VLVI8
LVI_A/D_SEL[3:0] = 0111b
2.34
2.40
2.46
V
–
SID273
VLVI9
LVI_A/D_SEL[3:0] = 1000b
2.44
2.50
2.56
V
–
SID274
VLVI10
LVI_A/D_SEL[3:0] = 1001b
2.54
2.60
2.67
V
–
SID2705
VLVI11
LVI_A/D_SEL[3:0] = 1010b
2.63
2.70
2.77
V
–
SID276
VLVI12
LVI_A/D_SEL[3:0] = 1011b
2.73
2.80
2.87
V
–
SID277
VLVI13
LVI_A/D_SEL[3:0] = 1100b
2.83
2.90
2.97
V
–
SID278
VLVI14
LVI_A/D_SEL[3:0] = 1101b
2.93
3.00
3.08
V
–
SID279
VLVI15
LVI_A/D_SEL[3:0] = 1110b
3.12
3.20
3.28
V
–
Document Number: 001-95464 Rev. *G
Page 30 of 42
PRoC™ BLE: CYBL1XX7X
Family Datasheet
PRELIMINARY
Table 42. Voltage Monitor DC Specifications (continued)
Spec ID
Parameter
Description
Min
Typ
Max
4.39
4.50
4.61
V
Details/
Conditions
–
–
–
100
µA
–
Min
Typ
Max
Units
Details/
Conditions
–
–
1
µs
–
SID280
VLVI16
LVI_A/D_SEL[3:0] = 1111b
SID281
LVI_IDD
Block current
Units
Table 43. Voltage Monitor AC Specifications
Spec ID
SID282
Parameter
TMONTRIP
Description
Voltage monitor trip time
SWD Interface
Table 44. SWD Interface Specifications
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID283
F_SWDCLK1
3.3 V VDD 5.5 V
–
–
14
MHz
SWDCLK ≤ 1/3 CPU
clock frequency
SID284
F_SWDCLK2
1.71 V VDD 3.3 V
–
–
7
MHz
SWDCLK ≤ 1/3 CPU
clock frequency
SID285
T_SWDI_SETUP T = 1/f SWDCLK
0.25 × T
–
–
ns
–
SID286
T_SWDI_HOLD
0.25 × T
–
–
ns
–
SID287
T_SWDO_VALID T = 1/f SWDCLK
–
–
0.5 × T
ns
–
SID288
T_SWDO_HOLD T = 1/f SWDCLK
1
–
–
ns
–
Typ
Max
Units
Details/Conditions
T = 1/f SWDCLK
Internal Main Oscillator
Table 45. IMO DC Specifications
Spec ID
Parameter
Description
Min
SID289
IIMO1
IMO operating current at 48 MHz
–
–
1000
µA
–
SID290
IIMO2
IMO operating current at 24 MHz
–
–
325
µA
–
SID291
IIMO3
IMO operating current at 12 MHz
–
–
225
µA
–
SID292
IIMO4
IMO operating current at 6 MHz
–
–
180
µA
–
SID293
IIMO5
IMO operating current at 3 MHz
–
–
150
µA
–
Min
Typ
Max
Units
Table 46. IMO AC Specifications
Spec ID
Parameter
Description
Details/Conditions
SID296
FIMOTOL3
Frequency variation from 3 to
48 MHz
–
–
±2
%
With API-called
calibration
SID297
FIMOTOL3
IMO startup time
–
12
–
µs
–
Min
Typ
Max
Units
Details/Conditions
–
0.3
1.05
µA
–
Min
Typ
Internal Low-Speed Oscillator
Table 47. ILO DC Specifications
Spec ID
SID298
Parameter
IILO2
Description
ILO operating current at 32 kHz
Table 48. ILO AC Specifications
Spec ID
Parameter
Description
Max
Units
Details/Conditions
SID299
TSTARTILO1
ILO startup time
–
–
2
ms
–
SID300
FILOTRIM1
32-kHz trimmed frequency
15
32
50
kHz
–
Document Number: 001-95464 Rev. *G
Page 31 of 42
PRoC™ BLE: CYBL1XX7X
Family Datasheet
PRELIMINARY
Table 49. External Clock Specifications
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID301
ExtClkFreq
External clock input frequency
0
–
48
MHz
CMOS input level only.
TTL input is not
supported
SID302
ExtClkDuty
Duty cycle; measured at VDD/2
45
–
55
%
CMOS input level only.
TTL input is not
supported
Table 50. ECO Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details/
Conditions
–
24
–
MHz
–
SID389
FECO
Crystal frequency
SID390
FTOL
Frequency tolerance
–50
–
50
ppm
–
SID391
ESR
Equivalent series resistance
–
–
60
Ω
–
SID392
PD
Drive level
–
–
100
µW
–
SID393
TSTART1
Startup time (Fast Charge on)
–
–
850
µs
–
SID394
TSTART2
Startup time (Fast Charge off)
–
–
3
ms
–
SID395
CL
Load capacitance
–
8
–
pF
–
SID396
C0
Shunt capacitance
–
1.1
–
pF
–
SID397
IECO
Operating current
–
1400
–
µA
–
Min
Typ
Max
Units
Details/
Conditions
Table 51. WCO Specifications
Spec ID#
Parameter
Description
SID398
FWCO
Crystal frequency
–
32.768
–
kHz
–
SID399
FTOL
Frequency tolerance
–
50
–
ppm
–
SID400
ESR
Equivalent series resistance
–
50
–
kΩ
–
SID401
PD
Drive level
–
–
1
µW
–
SID402
TSTART
Startup time
–
–
500
ms
–
SID403
CL
Crystal load capacitance
6
–
12.5
pF
–
SID404
C0
Crystal shunt capacitance
–
1.35
–
pF
–
SID405
IWCO1
Operating current (high-power
mode)
–
–
8
µA
–
SID406
IWCO2
Operating current (low-power
mode)
–
–
2.6
µA
–
Document Number: 001-95464 Rev. *G
Page 32 of 42
PRoC™ BLE: CYBL1XX7X
Family Datasheet
PRELIMINARY
Ordering Information
The CYBL1XX7X part numbers and features are listed in the following table.
Part Number
Available at Available at
ES10
PR4
CPU
Speed
(MHz)
Flash
Size
(KB)
DMA
CapSense
SCB
TCPWM
12-bit
ADC
I2S
PWM
LCD
Package
Bluetooth
Version
CYBL10573-56LQXI
Yes
Yes
48
256
No
Yes
(Gestures)
2
4
1 Msps
Yes
1
Yes
56-QFN
4.1
CYBL10573-76FNXI
Yes
Yes
48
256
No
Yes
(Gestures)
2
4
1 Msps
Yes
1
Yes
76-WLCSP
4.1
CYBL11171-56LQXI
–
Yes
48
256
Yes
No
1
2
1 Msps
No
0
No
56-QFN
4.2
CYBL11172-56LQXI
–
Yes
48
256
Yes
No
2
4
1 Msps
No
4
No
56-QFN
4.2
CYBL11173-56LQXI
–
Yes
48
256
Yes
No
2
4
1 Msps
Yes
0
No
56-QFN
4.2
CYBL11471-56LQXI
–
Yes
48
256
Yes
Yes
2
4
1 Msps
No
0
No
56-QFN
4.2
CYBL11472-56LQXI
–
Yes
48
256
Yes
Yes
2
4
1 Msps
Yes
0
No
56-QFN
4.2
CYBL11473-56LQXI
–
Yes
48
256
Yes
Yes
2
4
1 Msps
No
0
Yes
56-QFN
4.2
CYBL11571-56LQXI
–
Yes
48
256
Yes
Yes
(Gestures)
2
4
1 Msps
No
0
No
56-QFN
4.2
CYBL11572-56LQXI
–
Yes
48
256
Yes
Yes
(Gestures)
2
4
1 Msps
Yes
1
No
56-QFN
4.2
CYBL11573-56LQXI
Yes
Yes
48
256
Yes
Yes
(Gestures)
2
4
1 Msps
Yes
1
Yes
56-QFN
4.2
CYBL11573-56LQXQ
–
Yes
48
256
Yes
Yes
(Gestures)
2
4
1 Msps
Yes
1
Yes
56-QFN
4.2
CYBL11573-76FNXI
–
Yes
48
256
Yes
Yes
(Gestures)
2
4
1 Msps
Yes
1
Yes
76-WLCSP
4.2
CYBL11573-76FNXQ
–
Yes
48
256
Yes
Yes
(Gestures)
2
4
1 Msps
Yes
1
Yes
76-WLCSP
4.2
Ordering Code Definitions
CY BL 1 X A B C - DE FG H I
Temperature Range: I = Industrial, Q = Extended Industrial
X = Pb-Free
Package Code: LQ = QFN, FN = WLCSP (0.38 mm Thickness)
Number of pins in the package
Device Identification Number that corresponds to the part feature set
Flash Capacity: 7 = 256 KB
Product Type: 1 = Embedded MCU, 4 = CapSense,
5 = CapSense with Gestures
Bluetooth Standard Supported: 0 = BLE4.1, 1 = BLE 4.2
st
Subfamily: 1 = 1 BLE family
Marketing Code: BL = BLE Product family
Company ID: CY = Cypress
Note
5. All part numbers support input voltage from 1.9 V to 5.5 V.
Document Number: 001-95464 Rev. *G
Page 33 of 42
PRoC™ BLE: CYBL1XX7X
Family Datasheet
PRELIMINARY
The Field Values are listed in the following table:
Field
Description
Values
CYBL
Cypress PRoC™ BLE Family
CYBL
1X
Subfamily
10, 11
1st Generation BLE 4.1, 4.2
1
Embedded Only
4
CapSense
5
Touch
7
256 KB
A
Product Type
B
Flash Capacity
C
Feature set
DE
Package Pins
FG
56
76
Package code
H
Pb
I
Meaning
LQ
QFN
FN
WLCSP
X
Pb-free
Q
Extended temp - 40 °C to 105 °C
I
Industrial –40 °C to 85 °C
X Absent (with Pb)
Temperature Range
Packaging
Table 52. Package Characteristics
Parameter
Description
Conditions
Min
Typ
Max
Units
TA
Operating ambient temperature
–
–40
25
105
°C
TJ
Operating junction temperature
–
–40
–
125
°C
TJA
Package JA (56-pin QFN)
–
–
16.9
–
°C/watt
TJC
Package JC (56-pin QFN)
–
–
9.7
–
°C/watt
TJA
Package JA (76-ball WLCSP)
–
–
20.1
–
°C/watt
TJC
Package JC (76-ball WLCSP)
–
–
0.19
–
°C/watt
Table 53. Solder Reflow Peak Temperature
Maximum Peak
Temperature
Maximum Time at Peak
Temperature
56-pin QFN
260 °C
30 seconds
76-ball WLCSP
260 °C
30 seconds
Package
Table 54. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2
Package
MSL
56-pin QFN
MSL 3
76-ball WLCSP
MSL 1
Table 55. Package Details
Spec ID
Package
Description
001-58740 Rev. *C
56-pin QFN
7 mm × 7 mm × 0.6 mm
001-96603 Rev. *A
76-ball WLCSP
4.04 mm × 3.87 mm × 0.55 mm
Document Number: 001-95464 Rev. *G
Page 34 of 42
PRELIMINARY
PRoC™ BLE: CYBL1XX7X
Family Datasheet
Figure 6. 56-Pin QFN 7 mm × 7 mm × 0.6 mm
TOP VIEW
SIDE VIEW
BOTTOM VIEW
NOTES:
1.
HATCH AREA IS SOLDERABLE EXPOSED PAD
2. BASED ON REF JEDEC # MO-248
3. ALL DIMENSIONS ARE IN MILLIMETERS
001-58740 *C
The center pad on the QFN package must be connected to ground (VSS) for the proper operation of the device.
Document Number: 001-95464 Rev. *G
Page 35 of 42
PRELIMINARY
PRoC™ BLE: CYBL1XX7X
Family Datasheet
WLCSP Compatibility
The PRoC BLE family has products with 128 KB (16KB SRAM) and 256 KB (32KB SRAM) Flash. Package pin-outs and sizes are
identical for the 56-pin QFN package but are different in one dimension for the 68-ball WLCSP.
The 256KB Flash product has an extra column of balls which are required for mechanical integrity purposes in the Chip-Scale package.
With consideration for this difference, the land pattern on the PCB may be designed such that either product may be used with no
change to the PCB design.
Figure 7 shows the 128KB and 256 KB Flash CSP Packages.
Figure 7. 128KB and 256 KB Flash CSP Packages
128K BLE
256K BLE
CONNECTED PADS
NC PADS
PACKAGE CENTER
PACK BOUNDARY
FIDUCIAL FOR128K
FIDUCIAL FOR256K
The rightmost column of (all NC, No Connect) balls in the 256K BLE WLCSP is for mechanical integrity purposes. The package is
thus wider (3.2 mm versus 2.8 mm). All other dimensions are identical. Cypress will provide layout symbols for PCB layout.
The scheme in Figure 7 is implemented to design the PCB for the 256K BLE package with the appropriate space requirements thus
allowing use of either package at a later time without redesigning the Printed Circuit Board.
Document Number: 001-95464 Rev. *G
Page 36 of 42
PRELIMINARY
PRoC™ BLE: CYBL1XX7X
Family Datasheet
Figure 8. 76-Ball WLCSP Package Outline
TOP VIEW
SIDE VIEW
BOTTOM VIEW
NOTES:
1. REFERENCE JEDEC PUBLICATION 95, DESIGN GUIDE 4.18
001-96603 *A
2. ALL DIMENSIONS ARE IN MILLIMETERS
Document Number: 001-95464 Rev. *G
Page 37 of 42
PRELIMINARY
PRoC™ BLE: CYBL1XX7X
Family Datasheet
Acronyms
Table 56. Acronyms Used in This Document
Acronym
Description
abus
analog local bus
ADC
analog-to-digital converter
AG
analog global
AHB
AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data
transfer bus
Table 56. Acronyms Used in This Document (continued)
Acronym
Description
ETM
embedded trace macrocell
FET
field-effect transistor
FIR
finite impulse response, see also IIR
FPB
flash patch and breakpoint
FS
full-speed
GPIO
general-purpose input/output, applies to a PSoC
pin
ALU
arithmetic logic unit
AMUXBUS
analog multiplexer bus
HCI
host controller interface
API
application programming interface
HVI
high-voltage interrupt, see also LVI, LVD
APSR
application program status register
IC
integrated circuit
ARM®
advanced RISC machine, a CPU architecture
IDAC
current DAC, see also DAC, VDAC
ATM
automatic thump mode
IDE
integrated development environment
Inter-Integrated Circuit, a communications
protocol
BW
bandwidth
I2C, or IIC
CAN
Controller Area Network, a communications
protocol
I2S
Inter-IC Sound
CMRR
common-mode rejection ratio
IIR
infinite impulse response, see also FIR
CPU
central processing unit
ILO
internal low-speed oscillator, see also IMO
CRC
cyclic redundancy check, an error-checking
protocol
IMO
internal main oscillator, see also ILO
INL
integral nonlinearity, see also DNL
DAC
digital-to-analog converter, see also IDAC, VDAC
I/O
input/output, see also GPIO, DIO, SIO, USBIO
DFB
digital filter block
IPOR
initial power-on reset
DIO
digital input/output, GPIO with only digital
capabilities, no analog. See GPIO.
IPSR
interrupt program status register
DMIPS
Dhrystone million instructions per second
DMA
direct memory access, see also TD
DNL
differential nonlinearity, see also INL
DNU
do not use
DR
DSI
IRQ
interrupt request
ITM
instrumentation trace macrocell
LCD
liquid crystal display
LIN
Local Interconnect Network, a communications
protocol.
port write data registers
LR
link register
digital system interconnect
LUT
lookup table
DWT
data watchpoint and trace
LVD
low-voltage detect, see also LVI
ECC
error correcting code
LVI
low-voltage interrupt, see also HVI
ECO
external crystal oscillator
LVTTL
low-voltage transistor-transistor logic
EEPROM
electrically erasable programmable read-only
memory
MAC
multiply-accumulate
EMI
electromagnetic interference
MCU
microcontroller unit
EMIF
external memory interface
MISO
master-in slave-out
EOC
end of conversion
NC
no connect
EOF
end of frame
NMI
nonmaskable interrupt
EPSR
execution program status register
ESD
electrostatic discharge
Document Number: 001-95464 Rev. *G
NRZ
non-return-to-zero
NVIC
nested vectored interrupt controller
Page 38 of 42
PRELIMINARY
Table 56. Acronyms Used in This Document (continued)
Acronym
Description
PRoC™ BLE: CYBL1XX7X
Family Datasheet
Table 56. Acronyms Used in This Document (continued)
Acronym
Description
NVL
nonvolatile latch, see also WOL
SRAM
static random access memory
opamp
operational amplifier
SRES
software reset
PAL
programmable array logic, see also PLD
STN
super twisted nematic
PC
program counter
SWD
serial wire debug, a test protocol
PCB
printed circuit board
SWV
single-wire viewer
PGA
programmable gain amplifier
TD
transaction descriptor, see also DMA
PHUB
peripheral hub
THD
total harmonic distortion
PHY
physical layer
TIA
transimpedance amplifier
PICU
port interrupt control unit
TN
twisted nematic
PLA
programmable logic array
TRM
technical reference manual
PLD
programmable logic device, see also PAL
TTL
transistor-transistor logic
PLL
phase-locked loop
TX
transmit
PMDD
package material declaration data sheet
UART
POR
power-on reset
Universal Asynchronous Transmitter Receiver, a
communications protocol
PRES
precise power-on reset
PRS
pseudo random sequence
PS
port read data register
PSoC®
Programmable System-on-Chip™
PSRR
power supply rejection ratio
PWM
pulse-width modulator
RAM
random-access memory
RISC
reduced-instruction-set computing
RMS
root-mean-square
RTC
real-time clock
RTL
register transfer language
RTR
remote transmission request
RX
receive
SAR
successive approximation register
SC/CT
switched capacitor/continuous time
SCL
I2C serial clock
SDA
I2C serial data
S/H
sample and hold
SINAD
signal to noise and distortion ratio
SIO
special input/output, GPIO with advanced
features. See GPIO.
SOC
start of conversion
SOF
start of frame
SPI
Serial Peripheral Interface, a communications
protocol
SR
slew rate
Document Number: 001-95464 Rev. *G
USB
Universal Serial Bus
USBIO
USB input/output, PSoC pins used to connect to
a USB port
VDAC
voltage DAC, see also DAC, IDAC
WDT
watchdog timer
WOL
write once latch, see also NVL
WRES
watchdog timer reset
XRES
external reset I/O pin
XTAL
crystal
Page 39 of 42
PRoC™ BLE: CYBL1XX7X
Family Datasheet
PRELIMINARY
Document Conventions
Units of Measure
Table 57. Units of Measure (continued)
Table 57. Units of Measure
Symbol
Symbol
Unit of Measure
Unit of Measure
µH
microhenry
microsecond
°C
degrees Celsius
µs
dB
decibel
µV
microvolt
dBm
decibel-milliwatts
µW
microwatt
fF
femtofarads
mA
milliampere
Hz
hertz
ms
millisecond
KB
1024 bytes
mV
millivolt
kbps
kilobits per second
nA
nanoampere
Khr
kilohour
ns
nanosecond
kHz
kilohertz
nV
nanovolt
k
kilo ohm
ohm
ksps
kilosamples per second
pF
picofarad
LSB
least significant bit
ppm
parts per million
Mbps
megabits per second
ps
picosecond
MHz
megahertz
s
second
M
mega-ohm
sps
samples per second
Msps
megasamples per second
sqrtHz
square root of hertz
µA
microampere
V
volt
µF
microfarad
W
watt
Document Number: 001-95464 Rev. *G
Page 40 of 42
PRELIMINARY
PRoC™ BLE: CYBL1XX7X
Family Datasheet
Revision History
Description Title: PRoC™ BLE: CYBL1XX7X Family Datasheet Programmable Radio-on-Chip With Bluetooth Low Energy
(PRoC™ BLE)
Document Number: 001-95464
Orig. of Submission
Revision
ECN
Description of Change
Change
Date
*D
4792956
CSAI
06/10/2015 Initial release
Updated Bluetooth version to 4.2.
Updated Link Layer features.
Updated max values for TCPWM DC specifications.
*E
4922509
SKAR
09/17/2015
Updated ordering code definitions.
Updated package temperature range to –40 °C to 105 °C.
Removed Errata.
Updated the following specs:
*F
4992761
KISB
*G
5007591
SASD/
SKUV
II2C1: From10.5 uA to 50 uA
II2C2: From 135 uA to 155 uA
II2C3: From 310 uA to 390uA
ILCDLOW: From 5 uA to 17.5uA
IUART1: From 9 uA to 55uA
10/29/2015
LVI_Idd: From 10 uA to 100 uA
RXS, IDLE (SID340): From -90 dBm to -89 dBm
RXS, IDLE (SID340A): From -92 dBm to -91 dBm
RXS, HIGHGAIN: From -92 dBm to -91 dBm
Iavg_4sec, 0 dBm: From 5.7 uA to 6.25 uA
IECO: From 600 uA to 1400 uA
IDD15: From1.5 uA to 1.6 uA
Updated Deep Sleep current to 1.5 uA
Updated Wakeup from Stop mode to 2.2 ms
Added DMA feature
12/02/2015 Added Bluetooth 4.2 features
Modified flash row write/erase size to 256 bytes
Modified ordering information table
Added extended temperature support
Document Number: 001-95464 Rev. *G
Page 41 of 42
PRELIMINARY
PRoC™ BLE: CYBL1XX7X
Family Datasheet
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
Memory
PSoC
Touch Sensing
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/memory
cypress.com/go/psoc
cypress.com/go/touch
USB Controllers
Wireless/RF
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Community | Forums | Blogs | Video | Training
Technical Support
cypress.com/go/support
cypress.com/go/usb
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2014-2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-95464 Rev. *G
Revised December 2, 2015
All products and company names mentioned in this document may be the trademarks of their respective holders.
Page 42 of 42