REVISIONS LTR DESCRIPTION DATE Prepared in accordance with ASME Y14.24 APPROVED Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 PMIC N/A PREPARED BY RICK OFFICER Original date of drawing YY-MM-DD CHECKED BY RAJESH PITHADIA 12-09-19 4 A REV 5 6 7 8 9 10 11 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 TITLE MICROCIRCUIT, LINEAR, OPERATIONAL AMPLIFIER, HIGH PRECISION, LOW NOISE, MONOLITHIC SILICON APPROVED BY CHARLES F. SAFFLE SIZE AMSC N/A 3 CODE IDENT. NO. DWG NO. V62/12610 16236 PAGE 1 OF 11 5962-V047-12 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high precision, low noise, operational amplifier microcircuit, with an operating temperature range of -55°C to +125°C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/12610 - Drawing number 01 X E Device type (See 1.2.1) Case outline (See 1.2.2) Lead finish (See 1.2.3) 1.2.1 Device type(s). Device type Generic 01 OPA2227 Circuit function High precision, low noise operational amplifier 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter Number of pins X 8 JEDEC PUB 95 Package style MS-012-AA Plastic small outline 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacture: Finish designator A B C D E Z DLA LAND AND MARITIME COLUMBUS, OHIO Material Hot solder dip Tin-lead plate Gold plate Palladium Gold flash palladium Other SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12610 PAGE 2 1.3 Absolute maximum ratings. 1/ Supply voltage range (VS) .......................................................................................... Signal input terminals: Voltage ................................................................................................................... Current ................................................................................................................... Output short circuit (to ground) ................................................................................... Junction temperature range (TJ) ................................................................................ ±18 V -VS – 0.7 V to +VS + 0.7 V 20 mA Continuous 2/ 150°C Storage temperature range (TSTG) ............................................................................ -65°C to +150°C Lead temperature (soldering, 10 seconds) ................................................................. 300°C 1.4 Recommended operating conditions. 3/ Supply voltage range (VS) .......................................................................................... ±5 V to ±15 V Operating free-air temperature range (TA) ................................................................. -55°C to +125°C 1.5 Thermal characteristics. Thermal metric Symbol Case X Unit θJA 91.9 °C/W θJC(TOP) 39.9 °C/W Thermal resistance, junction-to-board 6/ θJB 40.6 °C/W Characterization parameter, junction-to-top 7/ ψJT 3.9 °C/W Characterization parameter, junction-to-board 8/ ψJB 39.6 °C/W Thermal resistance, junction-to-ambient 4/ Thermal resistance, junction-to-case (top) 5/ 1/ 2/ 3/ 4/ 5/ 6/ 7/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. One channel per package. Use of this product beyond the manufacturers design rules or stated parameters is done at the user’s risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. The thermal resistance, junction-to-ambient under natural convection is obtained in a simulation on a JEDEC standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The thermal resistance, junction-to-case (top) is obtained by simulating a cold plate test on the package top. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The thermal resistance, junction-to-board is obtained by simulating in an environment with a ring cold plate fixture to control the printed circuit board (PCB) temperature, as described in JESD51-8. Characterization parameter, junction-to-top (ψJT ) estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). 8/ Characterization parameter, junction-to-board (ψJB ) estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12610 PAGE 3 2. APPLICABLE DOCUMENTS JEDEC Solid State Technology Association JEDEC PUB 95 EIA/JESD51-2a EIA/JEDEC 51-7 EIA/JESD51-8 - Registered and Standard Outlines for Semiconductor Devices Integrated Circuits Thermal Test Method Environment Conditions – Natural Convection (Still Air) High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages Integrated Circuits Thermal Test Method Environment Conditions – Junction-to-Board (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http://www.jedec.org) ANSI SEMI STANDARD G30-88 - Test Method for Junction-to-Case Thermal Resistance Measurements for Ceramic Packages (Applications for copies should be addressed to the American National Standards Institute, Semiconductor Equipment and Materials International, 1819 L Street, NW, 6 th floor, Washington, DC 20036 or online at http://www.ansi.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as follows: A. B. C. Manufacturer’s name, CAGE code, or logo Pin 1 identifier ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12610 PAGE 4 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions 2/ Temperature, TA Device type Limits Min Unit Max Offset voltage Input offset voltage +25°C VOS ±100 01 ±250 -55°C to +125°C Input offset voltage versus temperature ∆VOS / ∆T Input offset voltage versus power supply VS = ±2.5 V to ±18 V Input offset voltage versus time Channel separation (dual) CS f = 1 kHz, RL = 5 kΩ µV ±0.1 typical µV / °C +25°C 01 -55°C to +125°C 01 +25°C 01 0.2 typical µV / mo +25°C 01 110 typical dB ±2.1 µV/V Input bias current. Input bias current IIB +25°C 01 ±10 nA Input offset current IOS +25°C 01 ±10 nA +25°C 01 Noise. Input voltage noise Input voltage noise density Current noise density Vn en in f = 0.1 Hz to 10 Hz 90 typical nVp-p 15 typical nVrms 3.5 typical nV / f = 100 Hz 3 typical Hz f = 1 kHz 3 typical f = 10 Hz +25°C f = 1 kHz +25°C 01 01 0.4 typical pA / Hz Input voltage range section. Common mode voltage range VCM Common mode rejection ratio CMRR VCM = -VS + 2 V to +VS – 2 V -55°C to +125°C 01 -VS +2 +25°C 01 120 -55°C to +125°C V +VS -2 dB 108 See footnotes at end of table. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12610 PAGE 5 TABLE I. Electrical performance characteristics – Continued. 1/ Test Symbol Conditions 2/ Temperature, TA Device type Limits Min Unit Max Input impedance section. 7 Ω||pF 9 Ω||pF Differential 3/ Open loop voltage gain +25°C 01 10 ||12 typical Common mode 3/ VCM = -VS + 2 V to +VS – 2 V +25°C 01 10 || 3 typical VO = -VS + 2 V to +VS – 2 V +25°C 01 132 Open loop gain section. Open loop voltage gain AOL RL = 10 kΩ VO = -VS + 3.5 V to +VS – 3.5 V RL = 600 Ω -55°C to +125°C 112 +25°C 132 -55°C to +125°C 112 dB Frequency response section. Gain bandwidth product GBW +25°C 01 8 typical MHz Slew rate SR +25°C 01 2.3 typical V/µs Settling time tS +25°C 01 5 typical µs 0.1%, G = 1, 10 V step, CL = 100 pF 0.01%, G = 1, 10 V step, CL = 100 pF VIN x G = VS +25°C 01 1.3 typical µs (THD + N) f = 1 kHz, G = 1, VO = 3.5 Vrms +25°C 01 0.00005 typical % VO RL = 10 kΩ -55°C to +125°C 01 Overload recovery time Total harmonic distortion + noise 5.6 typical Output section. Voltage output RL = 600 Ω Short circuit current +25°C ISC -VS +2 +VS -2 -VS + 3.5 +VS - 3.5 ±45 typical 01 V mA See footnotes at end of table. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12610 PAGE 6 TABLE I. Electrical performance characteristics – Continued. 1/ Test Symbol Conditions 2/ Temperature, TA Device type Limits Unit Min Max Power supply section. Specified voltage range VS Operating voltage range Quiescent current (per amplifier) IQ IO = 0 A +25°C 01 ±5 ±15 V +25°C 01 ±2.5 ±18 V +25°C 01 ±3.95 mA -55°C to +125°C ±4.30 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ Unless otherwise specified, VS = ±5 V to ±15 V and RL = 10 kΩ. 3/ The || symbolizes that the input impedance is being represented as the resistance value is in parallel with the capacitance. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12610 PAGE 7 Case X FIGURE 1. Case outline. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12610 PAGE 8 Case X Dimensions Inches Symbol Millimeters Min Max Min Max A --- 0.069 --- 1.75 A1 0.004 0.010 0.10 0.25 b 0.012 0.020 0.31 0.51 c 0.005 0.010 0.13 0.25 D 0.189 0.197 4.80 5.00 E 0.150 0.157 3.80 4.00 E1 0.228 0.244 5.80 6.20 e 0.050 BSC L 0.016 n 1.27 BSC 0.050 0.40 8 1.27 8 NOTES: 1. Controlling dimensions are inch, millimeter dimensions are given for reference only. 2. For dimension D, body length does not include mold flash, protrusion, or gate burrs. Mold flash, protrusion, or gate burrs shall not exceed 0.006 inch (0.15 mm) per end. 3. For dimension E, body width does not include interlead flash. Interlead flash shall not exceed 0.017 inch (0.43 mm) per side. 4. Falls with JEDEC MS-012-AA. FIGURE 1. Case outline - Continued. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12610 PAGE 9 Device type 01 Case outline X Terminal number Terminal symbol 1 OUTPUT A 2 -INPUT A 3 +INPUT A 4 -VS 5 +INPUT B 6 -INPUT B 7 OUTPUT B 8 +VS FIGURE 2. Terminal connections. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12610 PAGE 10 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Top side marking Transport media Vendor part number 2/ 3/ V62/12610-01XE 01295 2227EP Tape and reel OPA2227MDREP Tube OPA2227MDEP 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. 2/ For the most current package and ordering information, see the package option addendum at the end of the manufacturer’s data sheet. 3/ Package drawings, standard packaging quantities, thermal data, symbolization, and printed circuit board (PCB) design guidelines are available from the manufacturer. CAGE code 01295 DLA LAND AND MARITIME COLUMBUS, OHIO Source of supply Texas Instruments, Inc. Semiconductor Group 8505 Forest Lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12610 PAGE 11