V6208603

REVISIONS
LTR
DESCRIPTION
A
Correct the JA limit from 120C/W to 162C/W
as specified under paragraph 1.3. Add a
DATE
APPROVED
09-10-06
C. SAFFLE
15-04-16
C. SAFFLE
sentence to SHDN description as specified
under Figure 1. - ro
B
Make changes to RTOTAL, INL, and Rpu tests
under Table I. Update document paragraphs to
current requirements. - ro
CURRENT DESIGN ACTIVITY CAGE CODE 16236
HAS CHANGED NAMES TO:
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
Prepared in accordance with ASME Y14.24
Vendor item drawing
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PMIC N/A
PREPARED BY
RICK OFFICER
Original date of drawing
YY-MM-DD
CHECKED BY
RAJESH PITHADIA
07-12-19
TITLE
MICROCIRCUIT, DIGITAL-LINEAR, SINGLE
DIGITAL CONTROLLED POTENTIOMETER,
MONOLITHIC SILICON
APPROVED BY
ROBERT M. HEBER
SIZE
A
REV
AMSC N/A
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
CODE IDENT. NO.
DWG NO.
V62/08603
16236
B
PAGE
1
OF
16
5962-V047-015
1. SCOPE
1.1 Scope. This drawing documents the general requirements of a high performance single digital controlled potentiometer
microcircuit, with an operating temperature range of -55C to +125C.
1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item
drawing establishes an administrative control number for identifying the item on the engineering documentation:
V62/08603
-
Drawing
number
01
X
E
Device type
(See 1.2.1)
Case outline
(See 1.2.2)
Lead finish
(See 1.2.3)
1.2.1 Device type(s).
Device type
Generic
01
ISL22316
Circuit function
Single digital controlled potentiometer (DCP)
1.2.2 Case outline(s). The case outline(s) are as specified herein.
Outline letter
Number of pins
X
10
JEDEC PUB 95
Package style
MO-187BA
Plastic surface mount
1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacture:
Finish designator
A
B
C
D
E
Z
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Material
Hot solder dip
Tin-lead plate
Gold plate
Palladium
Gold flash palladium
Other
SIZE
A
CODE IDENT NO.
16236
REV
B
DWG NO.
V62/08603
PAGE
2
1.3 Absolute maximum ratings.
1/
Supply voltage range (VCC) ....................................................................................... -0.3 V to +6 V
Voltage at any digital interface pin with respect to GND ............................................ -0.3 V to VCC + 0.3 V
Voltage at any digital controlled potentiometer (DCP) pin with respect to GND ......... -0.3 V to VCC
Wiper current (IW) (10 seconds) ................................................................................. 6 mA
Latchup ...................................................................................................................... Class II, level B at +125C 2/
Electrostatic discharge (ESD):
Human body model ................................................................................................ 5 kV
Charge device model ............................................................................................. 1 kV
Maximum junction temperature (TJ) ........................................................................... +150C
Storage temperature range ........................................................................................ -65C to +150C
Lead temperature (soldering, 10 seconds) ................................................................. +300C
Thermal resistance, junction-to-ambient (JA) ........................................................... 162C/W 3/
1.4 Recommended operating conditions. 4/
Supply voltage range (VCC) .......................................................................................
Power rating of each DCP ..........................................................................................
Wiper current of each DCP ........................................................................................
Operating free-air temperature range (TA) .................................................................
1/
2/
3/
4/
2.7 V to 5.5 V
5 mW
3.0 mA
-55C to +125C
Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated under
“recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may
affect device reliability.
JEDEC class II pulse conditions and failure criterion used. Level B exceptions are: using a maximum positive pulse of 6.5 V
on the shutdown (SHDN) pin, and using a maximum negative pulse of -1 V for all pins.
JA is measured with the component mounted on a high effective thermal conductivity test board in free air.
See manufacturer’s technical brief TB379 for details.
Use of this product beyond the manufacturers design rules or stated parameters is done at the user’s risk. The manufacturer
and/or distributor maintain no responsibility or liability for product used beyond the stated limits.
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PAGE
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2. APPLICABLE DOCUMENTS
JEDEC Solid State Technology Association
JEDEC PUB 95 –
Registered and Standard Outlines for Semiconductor Devices
(Copies of these documents are available online at http:/www.jedec.org or from JEDEC – Solid State Technology Association,
3103 North 10th Street, Suite 240–S, Arlington, VA 22201-2107).
3. REQUIREMENTS
3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as
follows:
A.
B.
C.
Manufacturer’s name, CAGE code, or logo
Pin 1 identifier
ESDS identification (optional)
3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable)
above.
3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are
as specified in 1.3, 1.4, and table I herein.
3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein.
3.5 Diagrams.
3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1.
3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2.
3.5.3 Block diagram. The block diagram shall be as shown in figure 3.
3.5.4 Timing waveforms. The timing waveforms shall be as shown in figure 4.
DEFENSE SUPPLY CENTER, COLUMBUS
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TABLE I. Electrical performance characteristics. 1/
Test
Symbol
Conditions
VCC = 2.7 V to 5.5 V,
unless otherwise specified
High terminal (RH) to
low terminal (RL)
resistance
RTOTAL
RH to RL resistance
tolerance
RTOTAL
End to end
temperature
coefficient
RTOTAL
W option, VCC = 3.3 V 2/
Wiper resistance
RW
VCC = 3.3 V at 25C,
Temperature,
TA
Device
type
Limits
Min
W option, VCC = 3.3 V
+25C
01
-55C to +125C
01
+25C
01
-55C to +125C
01
-55C to +125C
01
+25C
01
Unit
Max
10 typical
-20
k
+20
50 typical
%
ppm/C
200

VCC
V
wiper control = VCC / RTOTAL
VRH and VRL terminal
voltages
Potentiometer
capacitance
Leakage on DCP pins
VRH,
VRH and VRL to GND
0
VRL
10 typical
CH 2/
High terminal, VCC = 3.3 V
CL 2/
Low terminal, VCC = 3.3 V
10 typical
CW 2/
Wiper terminal, VCC = 3.3 V
25 typical
ILkgDCP
Voltage at pin from GND to VCC
Voltage divider mode section
01
-55C to +125C
pF
1
A
0 V at RL; VCC at RH; measured at RW, unloaded
Integral non linearity
INL 3/
Monotonic over all tap positions
-55C to +125C
01
-1
1
LSB 4/
Differential non linearity
DNL 5/
Monotonic over all tap positions
-55C to +125C
01
-1
+1
LSB 4/
Zero scale error
ZSerror
6/
W option
-55C to +125C
01
0
5
LSB 4/
Full scale error
FSerror
7/
W option
-55C to +125C
01
-5
0
LSB 4/
Ratiometric
temperature
coefficient
TCV
2/, 8/
DCP register set to 40 hex for W
option, VCC = 3.3 V
+25C
01
4 typical
ppm/C
See footnotes at end of table.
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TABLE I. Electrical performance characteristics – Continued. 1/
Test
Symbol
Conditions
VCC = 2.7 V to 5.5 V,
unless otherwise specified
Temperature,
TA
Device
type
Limits
Unit
Min
Max
Resistor mode section
Measurements between RW and RL with RH not connected, or between RW and RH with RL not connected.
Integral non-linearity
RINL
9/
DCP register set between 10 hex
and 70 hex; monotonic over all tap
positions; W option
-55C to +125C
01
-1
+1
MI
10/
Differential nonlinearity
RDNL
11/
W option
-55C to +125C
01
-1
+1
MI
10/
Offset
Roffset
12/
W option
-55C to +125C
01
0
5
MI
10/
-55C to +125C
01
0.5
mA
-55C to +125C
01
3
mA
-55C to +125C
01
7
A
Operating specifications section
VCC supply current
(volatile write / read)
ICC1
VCC supply current
(non-volatile write /
read)
ICC2
VCC current
(standby)
ISB
fSCL = 400 kHz; SDA = open;
2
(for inter-integrated circuit (I C),
active, read and write states)
fSCL = 400 kHz; SDA = open;
2
(for I C, active, read and write
states)
VCC = +5.5 V,
2
I C interface in standby state
5
VCC = +3.6 V,
2
I C interface in standby state
VCC current
(shutdown)
ISD
01
-55C to +125C
VCC = +5.5 V,
A
5
2
I C interface in standby state
4
VCC = +3.6 V,
2
I C interface in standby state
See footnotes at end of table.
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TABLE I. Electrical performance characteristics – Continued. 1/
Test
Symbol
Conditions
VCC = 2.7 V to 5.5 V,
unless otherwise specified
Temperature,
TA
Device
type
Limits
Unit
Min
Max
-1
1
A
Operating specifications section - continued.
Leakage current, at
-55C to +125C
01
SCL falling edge of last bit of DCP
data byte to wiper new position,
VCC = 3.3 V
+25C
01
1.5 typical
s
From rising edge of SHDN signal
to wiper stored position and RH
connection, VCC = 3.3 V
+25C
01
1.5 typical
s
ILkgDig
Voltage at pin from GND to VCC,
SDA is inactive
DCP wiper response
time
tDCP
2/
DCP recall time from
shutdown mode
tshdnrec
pins A0, A1, SHDN ,
SDA, and SCL
SCL falling edge of last bit of ACR
data byte to wiper stored position
and RH connection, VCC = 3.3 V
Power on recall
voltage
Vpor
VCC ramp rate
VCCRamp
Power up delay
tD
Minimum VCC at which memory
recall occurs
VCC above Vpor, to DCP initial
value register recall completed,
2
and inter-integrated circuit (I C)
interface in standby state
1.5 typical
-55C to +125C
01
2.6
-55C to +125C
01
-55C to +125C
01
-55C to +125C
01
1,000,
000
Cycles
 +55C
01
50
Years
0.2
V
V/ms
3
ms
EEPROM specification section
EEPROM endurance
EEPROM retention
Non-volatile write
cycle time
 +90C
15
 +125C
10
01
-55C to +125C
tWC
20
ms
13/
See footnotes at end of table.
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TABLE I. Electrical performance characteristics – Continued. 1/
Test
Symbol
Conditions
VCC = 2.7 V to 5.5 V,
unless otherwise specified
Temperature,
TA
Device
type
Limits
Unit
Min
Max
Serial interface specification section
A1, A0, SHDN , SDA,
and SCL input buffer
low voltage
VIL
-55C to +125C
01
-0.3
0.3 *
VCC
V
A1, A0, SHDN , SDA,
and SCL input buffer
high voltage
VIH
-55C to +125C
01
0.7 *
VCC
0.3 +
VCC
V
SDA and SCL input
buffer hysteresis
Hysteresis
-55C to +125C
01
0.05 x
VCC
SDA output buffer low
voltage, sinking 4 mA
VOL
-55C to +125C
01
0
A1, A0, SHDN , SDA,
and SCL pin
capacitance
Cpin 2/
+25C
01
SCL frequency
fSCL
-55C to +125C
01
400
kHz
Pulse width
suppression time at
SDA and SCL inputs
tsp
Any pulse narrower than the
maximum specification is
suppressed
-55C to +125C
01
50
ns
SCL falling edge to
SDA output data valid
tAA
SCL falling edge crossing 30% of
VCC, until SDA exits the 30% to
-55C to +125C
01
900
ns
VCC = 3.3 V
V
0.4
10 typical
V
pF
70% of VCC window
Time the bus must be
free before the start
of a new transmission
tBUF
SDA crossing 70% of VCC during
a STOP condition, to SDA
crossing 70% of VCC during the
following START condition
-55C to +125C
01
1300
ns
Clock low time
tLOW
Measured at the 30% of VCC
crossing
-55C to +125C
01
1300
ns
Clock high time
tHIGH
Measured at the 70% of VCC
crossing
-55C to +125C
01
600
ns
See footnotes at end of table.
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TABLE I. Electrical performance characteristics – Continued. 1/
Test
Symbol
Conditions
VCC = 2.7 V to 5.5 V,
unless otherwise specified
Temperature,
TA
Device
type
Limits
Min
Unit
Max
Serial interface specification section - continued.
START condition
setup time
tSU:STA
SCL rising edge to SDA falling
edge; both crossing 70% of VCC
-55C to +125C
01
600
ns
START condition
hold time
tHD:STA
From SDA falling edge crossing
30% of VCC to SCL falling edge
-55C to +125C
01
600
ns
-55C to +125C
01
100
ns
-55C to +125C
01
0
ns
-55C to +125C
01
600
ns
crossing 70% of VCC
Input data setup time
tSU:DAT
From SDA exiting the 30% to 70%
of VCC window, to SCL rising edge
crossing 30% of VCC
Input data hold time
tHD:DAT
From SCL rising edge crossing 70%
of VCC to SDA entering the 30% to
70% of VCC window
STOP condition setup
time
tSU:STO
From SCL rising edge crossing 70%
of VCC, to SDA rising edge crossing
30% of VCC
STOP condition hold
time for read, or
volatile only write
tHD:STO
From SDA rising edge to SCL falling
edge; both crossing 70% of VCC
-55C to +125C
01
1300
ns
Output data hold time
tDH
From SCL falling edge crossing
30% of VCC, until SDA enters the
-55C to +125C
01
0
ns
30% to 70% of VCC window
SDA to SCL rise time
tR
From 30% to 70% of VCC
-55C to +125C
01
20 +
0.1 *
Cb
250
ns
SDA to SCL fall time
tF
From 70% to 30% of VCC
-55C to +125C
01
20 +
0.1 *
Cb
250
ns
Capacitive loading of
SDA or SCL
Cb
Total on chip and off chip
-55C to +125C
01
10
400
pF
See footnotes at end of table.
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TABLE I. Electrical performance characteristics – Continued. 1/
Test
Symbol
Conditions
VCC = 2.7 V to 5.5 V,
unless otherwise specified
Temperature,
TA
Device
type
Limits
Min
Unit
Max
Serial interface specification section - continued.
SDA and SCL bus pull
up resistor off chip
Rpu
Maximum is determine by tR and tF,
For Cb = 400 pF, max is about
2 k  2.5 k,
For Cb = 40 pF, max is about
15 k  20 k
-55C to +125C
01
1
k
A1 and A0 setup time
tSU:A
Before START condition
-55C to +125C
01
600
ns
A1 and A0 hold time
tHD:A
After STOP condition
-55C to +125C
01
600
ns
1/
Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over
the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters
may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization
and/or design.
2/
This parameter is not 100 percent tested.
3/
INL = [ V(RW)i – (i  LSB) – V(RW)0 ] / LSB for i = 127.
4/
LSB: [ V(RW)127 – V(RW)0 ] / 127. V(RW)127 and V(RW)0 are V(RW) for the DCP register set to 7F hex and 00 hex respectively.
LSB is the incremental voltage when changing from one tap to an adjacent tap.
5/
DNL = [ V(RW)i – V(RW)i-1 ] / LSB – 1, for i =1 to 127, I is the DCP register setting.
6/
ZS error = V(RW)0 / LSB.
7/
FS error = [V(RW)127 – VCC ] / LSB.
8/
TCV = Max(V(RW)i) – Min(V(RW))i) / [Max(V(RW)i) + Min(V(RW)i) ] / 2 x ( 10 / 165C ) for i = 16 to 127 decimal,
T = -55C to +125C. Max ( ) is the maximum value of the wiper voltage and Min( ) is the minimum value of the wiper
voltage over temperature range.
9/
RINL = [ RWi – (MI  i) – RW0 ] / MI, for i = 16 to 127.
6
10/ MI = | RW127 – RW0 | / 127. MI is a minimum increment. RW127 and RW0 are the measured resistances for the DCP
register set to 7F hex and 00 hex respectively.
11/ RDNL = (RWi – RWi-1 ) / MI – 1, for i = 16 to 127.
12/ Roffset = RW0 / MI, when measuring between RW and RL.
Roffset = RW127 / MI, when measuring between RW and RH.
2
13/ tWC is the time from a valid STOP condition at the end of a write sequence of inter-integrated circuit (I C) serial interface,
to the end of the self timed internal non-volatile write cycle.
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Case X
FIGURE 1. Case outline.
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Case X - continued
Dimensions
Inches
Symbol
Millimeters
Notes
Min
Max
Min
Max
A
0.037
0.043
0.94
1.10
A1
0.002
0.006
0.05
0.15
A2
0.030
0.037
0.75
0.95
b
0.007
0.011
0.18
0.27
c
0.004
0.008
0.09
0.20
D
0.116
0.120
2.95
3.05
3
E
0.116
0.120
2.95
3.05
4
E1
0.187
0.199
4.75
5.05
e
L
L1
0.020 BSC
0.016
0.50 BSC
0.028
0.40
0.037 REF
0.70
6
0.95 REF
R
0.003
---
0.07
---
R1
0.003
---
0.07
---
n
8
10
7
NOTES:
1. Controlling dimensions are millimeter, inch dimensions are given for reference only.
2. Dimensioning and tolerances per ANSI Y14.5M-1994.
3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate
burrs shall not exceed 0.15 mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions and are measured at datum plane.
Interlead flash and protrusions shall not exceed 0.15 mm (0.006 inch) per side.
5. Formed leads shall be planar with respect to one another within 0.10 mm (0.004 inch) at seating plane.
6. “L” is the length of terminal for soldering to a substrate.
7. “n” is the number of terminal positions.
8. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08 mm (0.003 inch)
total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent
lead is 0.07 mm (0.0027 inch).
9. Falls within JEDEC MO-187-BA.
FIGURE 1. Case outline - Continued.
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Device type
01
Case outline
X
Terminal number
Terminal
symbol
Description
1
SCL
Open drain inter-integrated circuit (I C) interface clock input.
2
SDA
Open drain serial data I/O for the inter-integrated circuit (I C)
interface.
3
A1
Device address input for the inter-integrated circuit (I C)
interface.
4
A0
Device address input for the inter-integrated circuit (I C)
interface.
5
SHDN
6
GND
7
RL
“Low” terminal of digitally controlled potentiometer (DCP).
8
RW
“Wiper” terminal of digitally controlled potentiometer (DCP).
9
RH
“High” terminal digitally controlled potentiometer (DCP).
10
VCC
Power supply pin.
2
2
2
2
Shutdown active low input. This pin is logically ANDed with
the SHDN bit in the access control register (ACR).
Device ground pin.
FIGURE 2. Terminal connections.
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FIGURE 3. Block diagram.
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14
FIGURE 4. Timing waveforms.
DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
B
DWG NO.
V62/08603
PAGE
15
4. VERIFICATION
4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as
indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices,
classification, packaging, and labeling of moisture sensitive devices, as applicable.
5. PREPARATION FOR DELIVERY
5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial
practices for electrostatic discharge sensitive devices.
6. NOTES
6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum.
6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book.
The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided.
6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee
of present or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all
current sources of supply at http://www.landandmaritime.dla.mil/Programs/Smcr/.
Vendor item drawing
administrative control
number 1/
Device
manufacturer
CAGE code
Part marking
Vendor part number
V62/08603-01XB
34371
2316M
ISL22316WMUEP
1/ The vendor item drawing establishes an administrative control number for identifying the
item on the engineering documentation.
2/ Add –TK suffix to vendor part number for 1000 piece quantity with tape and reel packaging option.
CAGE code
34371
DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO
Source of supply
Intersil Corporation
1001 Murphy Ranch Road
Milpitas, CA 95035-6803
SIZE
A
CODE IDENT NO.
16236
REV
B
DWG NO.
V62/08603
PAGE
16