CY3688 MoBL-USB™ TX2UL Development Kit Guide Doc. # 001-46448 Rev. *C Cypress Semiconductor 198 Champion Court San Jose, CA 95134-1709 Phone (USA): 800.858.1810 Phone (Intnl): 408.943.2600 http://www.cypress.com Copyrights Copyright © 2008-2012 Cypress Semiconductor Corporation. All rights reserved. MoBL-USB™ is a trademark of Cypress Semiconductor Corporation. All other trademarks or registered trademarks referenced herein are the property of their respective owners. The information in this document is subject to change without notice and should not be construed as a commitment by Cypress. While reasonable precautions have been taken, Cypress assumes no responsibility for any errors that may appear in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Cypress. Made in the U.S.A. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Flash Code Protection Cypress products meet the specifications contained in their particular Cypress Data Sheets. Cypress believes that its family of products is one of the most secure families of its kind on the market today, regardless of how they are used. There may be methods, unknown to Cypress, that can breach the code protection features. Any of these methods, to our knowledge, would be dishonest and possibly illegal. Neither Cypress nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Cypress is willing to work with the customer who is concerned about the integrity of their code. Code protection is constantly evolving. We at Cypress are committed to continuously improving the code protection features of our products. 2 CY3688 MoBL-USB™ TX2UL Development Kit Guide, Doc. # 001-46448 Rev. *C Contents 1. Introduction 1.1 1.2 1.3 1.4 Kit Components ...........................................................................................................5 Development Board .....................................................................................................5 1.2.1 Connector and Jumper Definition on the Development Board.........................5 1.2.2 Power Supply ...................................................................................................6 1.2.3 ULPI Interface ..................................................................................................6 1.2.4 CS_N and RESET............................................................................................6 1.2.5 Testing and Accessibility ..................................................................................7 1.2.6 Specification .....................................................................................................7 Document Revision History ........................................................................................8 Documentation Conventions........................................................................................8 A. Appendix A.1 5 9 TX3 DVK Board Schematic .........................................................................................9 CY3688 MoBL-USB™ TX2UL Development Kit Guide, Doc. # 001-46448 Rev. *C 3 Contents 4 CY3688 MoBL-USB™ TX2UL Development Kit Guide, Doc. # 001-46448 Rev. *C 1. Introduction The CY3688 MoBL-USB™ TX2UL Development Kit (DVK) is a combination of hardware and documentation, which can be used to evaluate the MoBL-USB TX2UL device and to integrate it to existing development platforms with ULPI interface. The Cypress MoBL-USB TX2UL is a low-voltage high-speed and full-speed compatible USB 2.0 ULPI Transceiver. The TX2UL is specifically designed for mobile handset applications by offering tiny package options and low power consumption. Due to the requirement for backward compatibility in the USB 2.0 specification, the USB 2.0 ULPI PHY functions with either a Full-Speed (12 Mbits/sec) USB host or a High-Speed (480 Mbits/sec) USB host. 1.1 1.2 Kit Components ■ Development board ■ Quick start guide ■ CD ROM ■ Power supply ■ USB A to B cable Development Board The board can be used to interconnect to a development platform with ULPI Link. After the TX2UL device is configured, the link enumerates to the USB host PC and runs traffic. USB signal quality testing is done to confirm the quality of TX2UL eye diagram. Board schematic and layout are included in the CD ROM. 1.2.1 Connector and Jumper Definition on the Development Board J1:100-pin T&MT connector D3, D6, D8: Power indication U2: USB Type B connector J11: VBATT power supply selector J4: Jumper for CS_N inversion for links with active high operation J5: Jumper for RESET_N inversion for links with active high operation CY3688 MoBL-USB™ TX2UL Development Kit Guide, Doc. # 001-46448 Rev. *C 5 Introduction Figure 1-1. Block Diagram D6 VBATT VDD D8 D3 VIO J5 OSC1 CLK J4 RESET_N CS_N ULPI BUS J1 T&MT Connector VIO VBATT VBUS VDD U1 TX2UL RESET_N CS_N U2 USB Connector U5 Inverter J11 R12 J10 EXT PWR 1.2.2 U3 PWR REG R7 R13 VIO VDD Power Supply The TX2UL device VDD and VIO power supplies are expected to be supplied from the ULPI connector. VBATT power supply can be supplied from VBUS or the external power supply included with the kit. To power the board using VBUS, connect pin 2 and 3 of J11. Make sure the USB cable is connected to a host USB port. The other option is to use the included power supply and connect 1 and 2 of J11 (default configuration). The system is equipped with a method to check the power consumption of the TX2UL device. Measure the voltage drop across R7, R13, and R12, this is the current consumed by VDD, VIO, and VBATT consecutively. 1.2.3 ULPI Interface UTMI+ Low Pin Interface (ULPI) is a standard interface developed to interface a link to a USB 2.0 PHY. It supports an 8-bit wide SDR data path. The primary I/Os of this block support multirange LVCMOS signaling from 1.8 V to 3.3 V. The level used is automatically selected by the voltage applied to VIO and can be set at any voltage between 1.8 V and 3.3 V. The ULPI interface is mapped to J1 for interconnection to development platforms. The connector pinout is as specified by the ULPI specification, page 92. Use the schematic attached in the CD/DVD ROM as a reference. 1.2.4 CS_N and RESET The TX2UL device uses CS_N and RESET_N as active low inputs. In case this system is used with a link with active high GPIO operation, an option is available to invert these signals. The default is J4 and J5; connect 1 and 2 for direct connection from link. Connecting 2 and 3 will invert these signals. 6 CY3688 MoBL-USB™ TX2UL Development Kit Guide, Doc. # 001-46448 Rev. *C Introduction 1.2.5 Testing and Accessibility J2 and J14 shown in the following figure are test points for debugging purposes. It can be used to connect a logic analyzer to observe the ULPI bus timing. Figure 2. Testing and Accessibility VBATT J2 DATA0 DATA1 DATA2 DATA3 DATA4 1.2.6 J14 1 11 2 12 3 13 4 14 5 15 6 16 7 17 8 18 9 19 10 20 DATA5 RESET_N 1 11 CS_N 2 12 CLOCK 3 13 4 14 5 15 6 16 7 17 8 18 9 19 10 20 DATA6 STP DATA7 DIR NXT VDD VIO Specification The following specifications are useful when developing with the TX2UL USB 2.0 ULPI PHY. These specifications are also found at http://www.usb.org. ■ UTMI+ Low Pin Interface (ULPI) Specification, V1.1 ■ USB 2.0 Specification, USB Implementers Forum (USB-IF) CY3688 MoBL-USB™ TX2UL Development Kit Guide, Doc. # 001-46448 Rev. *C 7 Introduction 1.3 Document Revision History Rev. PDF Creation Date Origin of Change Description of Change ** 05/20/2008 AESA New Guide. *A 09/15/2009 AESA Changed Part Number to TX2UL. *B 05/05/2011 EYZ Added schematic *C 03/29/2012 HBM Updated Chapter Title in Cover page as “CY3688 MoBL-USB™ TX2UL Development Kit Guide”. Updated Chapter Title in Chapter 1 as “Introduction”. 1.4 Documentation Conventions Table 1. Documentation Conventions for User Guides Convention 8 Usage Courier New Displays file locations, user entered text, and source code: C:\ ...cd\icc\ Italics Displays file names and reference documentation: Read about the sourcefile.hex file in the PSoC Designer User Guide. [Bracketed, Bold] Displays keyboard commands in procedures: [Enter] or [Ctrl] [C] File > Open Represents menu paths: File > Open > New Project Bold Displays commands, menu paths, and icon names in procedures: Click the File icon and then click Open. Times New Roman Displays an equation: 2+2=4 No text, gray table cell Represents a reserved bit in register tables. CY3688 MoBL-USB™ TX2UL Development Kit Guide, Doc. # 001-46448 Rev. *C A. Appendix TX3 DVK Board Schematic EDGE CONN/ 24PIN_QFN CONN/ USB 4 3 2 CONNECTIONS VDD TP2 TP4 1 VIO VDDR TP5 R7 1 1 OHM VIOR TP6 F R13 2 1 1 OHM 2 1 5 1 F 6 1 7 8 1 A.1 VIOR VDD VIOR 2 2 J4 JUMP3_100MIL 2B5< 2D8< U1 BI 2B6< 2B1< BI 2D3< 2B6< BI 22 1 DATA4 DATA5 DATA6 DATA7 2 1 22 1 22 2 R20 R18 DATA4 DATA5 2 R19 2 DATA6 DATA7 IN IN 2E4< 2B5< IN CS_N STP RESET_N 7 17 DP 22 DM CS_N 16 STP 18 RESET_N XI XO VSSBATT0_2 2D1< 15 14 22 R22 22 R25 22 R23 2 1 2 1 2 1 DIR NXT CLOCK OUT 2C6< OUT 2C6< 2C3< OUT 2C6< 2B5< OUT VBUS_OUT 1 SOD-523 2C1< R21 J5 JUMP3_100MIL 2 2E4< 2B5< XIN XOUT 21 20 IN OUT RESET_N 2 1 2 2 4 6 8 10 12 3 3 U2 1 VBUS 3 DP 2 2C8> 2C6< 1Y 2Y 3Y 4Y 5Y 6Y 1 3 5 9 11 13 1A 2A 3A 4A 5A 6A 4 GND 5 S1 S2 TP7 2D8< 2B6< BI R1 1 2E8< 2B6< BI 2 1 1 1 R5 ZERO C1 NC GND 3 1 33 XIN 2 OUT J6 1 2 0.01UF 2 C 1 2 HEADER2 J7 HEADER2 1 2 2 18 20 22 25 RESERVED_25 27 GND_27 29 GPIO3 31 DATA7 33 DATA5 R26 HEADER2 VDDR J9 HEADER2 NXT VIOR J2 J14 VBATT 2E8< 2B1< IN DATA0 DATA1 2E8< 2D1< IN 2E8< 2B3< IN DATA2 IN DATA3 B 2E8< 2D1< 2E8< 2B3< IN DATA4 HEADER_10X2 1 1 11 11 2 2 12 12 3 3 13 13 4 4 14 14 5 5 15 15 6 6 16 16 7 7 17 17 8 8 18 18 9 19 19 10 20 20 9 10 DATA5 IN 2D3< 2E8< 2E4< 2D8< 2E4< 2D8< DATA6 IN DATA7 IN 2D3< 2D8< DIR IN 2C1< 2E6< NXT IN 2B1< 2D8< IN IN 2E6< 2B1< IN 2D8< 2B1< IN 2C3< 2E6< RESET_N CS_N CLOCK STP HEADER_10X2 1 1 11 11 2 2 12 12 3 3 13 13 4 4 14 14 5 5 15 15 6 6 16 16 7 7 17 17 8 8 18 18 9 9 19 19 10 20 20 10 2E8< 2B8< BI 2E8< 2B8< BI DATA4 DATA2 VDD VIO 2 7 6 5 4 3 24 GPIO1 26 VBUS_OUT 28 RESERVED_30 30 VBUS_OUT 34 DATA3 DATA1 36 DATA1 VIO_38 38 DATA3 GND_35 RESERVED_37 39 GND_39 RESERVED_40 40 41 RESERVED_41 RESERVED_42 42 43 GND_43 RESERVED_44 44 45 SPKR_MIC 47 VBUSIN 49 DCPSNT_N 51 GND_46 RESERVED_48 52 GND_51 SYS_CLK 53 GND_53 GND_54 55 RESERVED_55 GPIO6 57 VDD_57 GPIO8 59 RESERVED_59 61 GPIO1O 63 GPIO12 RESERVED_64 64 65 GND_65 RESERVED_66 66 67 RESERVED_67 69 VDD_69 71 NXT RESERVED_72 72 RESERVED_74 74 GND_68 DIR 58 62 GND_76 76 RESERVED_77 GPIO14 78 79 RESERVED_79 GND_80 80 81 VIO_81 83 DATA4 GND_84 85 DATA2 DATA0 87 VIO_87 89 RESERVED_89 91 RESERVED_91 93 RESERVED_93 95 GND_95 97 RESERVED_97 RESERVED_98 99 RESERVED_99 PSU_SHD_N STP DIR 70 RESERVED_75 CLOCK C 68 GND_73 GND_92 D 56 73 RESERVED_94 2B8< 2E8< 54 77 RESERVED_88 2B8< 2E8< BI 60 75 DATA6 BI 46 50 GND_62 2E6< 48 GPIO13 RESERVED_60 IN VIOR 32 35 THIS DOCUMENT CONTAINS INFORMATION PROPRIETARY TO CYPRESS SEMICONDUCTOR. USE OR DISCLOSURE WITHOUT THE WRITTEN PERMISSION OF AN OFFICER OF CYPRESS IS EXPRESSLY FORBIDDEN. COPYRIGHT (C) CYPRESS 2002 8 GND_24 37 CYPRESS SEMICONDUCTOR A 16 RESERVED_22 200 E 14 RESERVED_20 GND_32 VDDR 12 RESERVED_18 DATA7 DATA5 IN VDD_16 VDDR 10 RESERVED_23 3B2< 3B3< 4C2< 2E6< 2B6< GPIO11 RESERVED_14 GND_21 J8 1 2 RESERVED_10 2 RESERVED_19 VIO VCC1_103_OSC GPIO9 RESET 4.7 NF 250 V VDD GND_9 19 2D6< 2 9 11 17 2 1 R6 OUTPUT 8 SPKR_L VDDR VCC 6 VDD_8 21 VDDR OSC1 4 GPIO5 GPIO7 GND_2 23 1 4 GND_4 GPI04 7 GND_13 2 1M OUT GPI02 5 13 787780 GND_SHLD C3 3 15 DM 6 1 1 OUT 1 R24 USB_DP USB_DM 23 R28 U5 2 D4 2 D VBUS IN VIO 10 NXT CLOCK NC 3D7< VDD 25 2B5< 2B5< 2B1< 2E4< 3 19 DIR 13 2 24 VCC_3 VCC_19 VIO 12 VBATT VBATT0_2 14 DATA3 9 2 22 1 8 11 R11 R17 22 1 DATA2 VIOR GPIOO PROV BI 2B6< 6 R10 J1 EDGE CONNECTOR 1 1 BI 2B3< 2 24_PIN_QFN 3 SN74LV14APW 2B8< 2B8< DATA1 1 3 GND 2D1< 2D3< 22 1 DATA0 5 R16 2 1 BI 4 2 22 1 5K 2B3< R15 22 1 1 2B8< DATA0 DATA1 DATA2 DATA3 2 BI 10K BI 2B8< 1 2 VIOR 1 2B1< 2 VCC 2B8< 2D1< THERMAL_PAD E CS_N OUT PROV R27 0.01UF 1 1 C29 0.1UF 0.01UF 2 1 1 C13 2 1 2 C12 0.1UF 0.01UF 2 1 C11 2 1 1 2 C10 0.1UF 2 1 1 C25 0.01UF 0.1UF 2 2 C24 1 C28 C9 0.01UF 7 VIO C8 0.1UF 2 1 VBATT C27 2.2UF 82 IN 2B6< 2E6< DATA6 BI 2B6< 2D8< DATA0 BI 2B8< 2E8< 84 86 88 CLOCK 90 IN 92 B 94 STP 96 OUT 98 2B5< 2D8< 100 DRAWING TITLE TX3_DVK_BOARD SIZE CC REV. ENGINEER 2 1 A DATE. Thu Mar 27 17:21:28 2008 <ENGINEER> <ENGINEER2> PAGE 2 OF 3 1 [+] Feedbac CY3688 MoBL-USB™ TX2UL Development Kit Guide, Doc. # 001-46448 Rev. *C 9 10 CY3688 MoBL-USB™ TX2UL Development Kit Guide, Doc. # 001-46448 Rev. *C