BA7078AF/AS Multimedia ICs Synchronization signal processor for high definition displays BA7078AF/AS The BA7078AF is a synchronization signal processing LSI chip designed for multiscan high-definition displays. It generates a synchronization signal and clamp pulse for three types of input signals: separate synchronization, composite synchronization, and synchronization on video. !Application CRT displays !Features 1) Operates on a single 5V power supply, with low power consumption. 2) Synchronization signal existence and polarity detec-tion output. 3) Adjustable clamp pulse width, allowing for the selec-tion of front or back editing. 4) Vertical synchronization separation is based on hori-zontal frequency tracking, for separation starting at 1H. 5) Minimal attached components. !Absolute maximum ratings (Ta = 25°C) Parameter Symbol Limits Unit VCC 7.0 V Power supply voltage ∗1 Pd Power dissipation ∗2 450(BA7078AF) 600(BA7078AS) °C −25 to +75 Topr Operating temperature mW °C −55 to +125 Tstg Storage temperature ∗1 Reduced by 4.5mW for each increase in Ta of 1°C over 25°C. ∗2 Reduced by 6.0mW for each increase in Ta of 1°C over 25°C. !Recommended operating conditions (Ta = 25°C) Parameter Power supply voltage Symbol Min. Typ. Max. Unit VCC 4.5 5.0 5.5 V 1/12 BA7078AF/AS Multimedia ICs !Block diagram HSCTL 1 C / HSYNC IN 2 VIDEO IN 3 H SYNC DET. 18 POLH 17 EXIH 16 POLV 15 EXIV SYNC SEPA. VSEPA 4 VSYNC IN 5 14 Vcc CVPOL 6 13 HDRV 12 CLAMP 11 VDRV 10 CPWID HOR. SYNC CONTROL V SYNC SEPA. V SYNC DET. CVEXI 7 CPSEL 8 GND 9 CLAMP PULSE GEN. 2/12 BA7078AF/AS Multimedia ICs !Pin descriptions Pin No. Pin name 1 HSCTL 2 C / HSYNC IN 3 VIDEO IN Functions HDRV output Used to select whether to output the VDRV section of the HDRV output signal. High : VDRV section of HDRV is output Low : VDRV section of HDRV is not output Composite sync / H SYNC input Input either the composite synchronization signal or the horizontal synchronization signal. Input is clamped, and is initiated by capacitor coupling. SYNC ON VIDEO input Inputs the SYNC ON VIDEO signal(green). Input is sink chip clamped. Input is initiated by capacitor coupling. 4 VSEPA f-V conversion Converts the horizontal synchronization signal frequency into a voltage. The voltage generated is proportional to the frequency of the horizontal synchronization signal. Attach a 0.56µF capacitor between the ground pins. 5 VSYNC IN V SYNC input Inputs the vertical synchronization signal. 6 CVPOL Vertical polarity integration Integrates the vertical synchronization signal polarity detection circuit. Attach a 1.5µF capacitor between this pin and the ground. 7 CVEXI Vertical existence integration Integrates the vertical synchronization signal existence detection circuit. Attach a 1µF capacitor between this pin and the ground. Setting the clamp position Used to set the clamp pulse generation position to either the front or back edge of HSYNC High : The front edge is the generation position Open : Composite / H SYNC IN : The front edge is the generation position VIDEO IN : The back edge is the generation position Low : The back edge is the generation position 8 CPSEL 9 GND 10 CPWID Setting the clamp pulse width Sets the clamp pulse width according to the attached time constant. Attach a resistor between this pin and VCC and, a capacitor between this pin and GND. When R = 3.9kΩ and C = 100pF, pulse width is approximately 400 ns. Set the resistor to register an abnormality at 1kΩ. 11 VDRV VDRV output Outputs the vertical synchronization signal. The output signal has positive polarity. 12 CLAMP Clamp output Outputs the clamp pulse generated from the vertical synchronization signal. The output signal has a positive polarity. 13 HDRV HDRV output Outputs the clamp pulse generated from the horizontal synchronization signal. The output signal has positive polarity. 14 VCC Power supply 15 EXIV Vertical existence output Indecates whether the vertical synchronization signal exists. For the output logic, refer to the separate table. 16 POLV Vertical polarity output Indicates the polarity of the vertical synchronization signal. For the output logic, refer to the separate table. 17 EXIH Horizontal existence output Indicates whether the horizontal synchronization signal exists. For the output logic, refer to the separate table. 18 POLH Horizontal polarity output Indicates the polarity of the horizontal synchronization signal. For the output logic, refer to the separate table. Ground − − 3/12 BA7078AF/AS Multimedia ICs !Input / output circuits HSCTL VSEPA C / HSYNC IN VCC VCC VCC 670Ω 60kΩ 200Ω 1kΩ 51kΩ 2pin 4pin 1pin 30kΩ 10µA CVPOL VIDEO IN VSYNC IN VCC VCC VCC 2kΩ 200Ω 5pin 3pin CVEXI 200Ω 6pin CPSEL CPWID VCC VCC VCC 50kΩ 1kΩ 7pin 10pin 8pin 50kΩ 4/12 BA7078AF/AS Multimedia ICs GND VDRV CLAMP VCC VCC 9pin 12pin 11pin HDRV POLV VCC VCC VCC VCC 10kΩ 13pin EXIH POLH EXIV VCC 10kΩ 17pin 14pin 16pin 15pin VCC VCC 10kΩ 10kΩ 18pin 5/12 BA7078AF/AS Multimedia ICs !Electrical characteristics (unless otherwise noted, VCC = 5V, Ta = 25°C) Parameter Symbol Min. Typ. Max. Unit VCC 4.5 5.0 5.5 V Power supply voltage ICC 21 30 39 mA VDRV output voltage "H" V VDH 4.5 5.0 − V VDRV output voltage "L" V VDL − 0.2 0.5 V VDRV output current "L" I VDL 8 − − mA Quiescent current Conditions VDRV rising delay time trdVD − 280 450 ns HDRV output voltage "H" V HDH 4.5 5.0 − V HDRV output voltage "L" V HDL − 0.2 0.5 V HDRV output current "L" I HDL 8 − − mA HDRV rising delay time (1) trdHD1 − 65 115 ns C / HSYNC IN HDRV rising delay time (2) trdHD2 − 95 145 ns VIDEO IN CLAMP output voltage "H" V CPH 4.5 5.0 − V CLAMP output voltage "L" V CPL − 0.2 0.5 V CLAMP output current "L" I CPL 8 − − mA CLAMP rising delay time (1) trdCP1 − 75 125 ns front edge CLAMP rising delay time (2) trdCP2 − 95 145 ns back edge Synchronization detection output voltage "H" V DH 4.5 5.0 − V Synchronization detection output voltage "L" V DL − 0.2 0.5 V Synchronization detection output current "L" I DL 3 − − mA VSYNC IN Z oD 7 10 13 kΩ Minimum synchronization separation level V SMin. − − 0.2 VP-P HSCTL "H" level threshold voltage V tHSH 2.5 − − V HSCTL "L" level threshold voltage V tHSL − − 1.5 V CPSEL "H" level threshold voltage V tCPH 3.8 − − V CPSEL "L" level threshold voltage V tCPL − − 1.2 V Synchronization detection output impedance !Synchronization signal detection chart OUTPUT INPUT Composite / HSYNC H. COMP (Positive) H. COMP (Negative) No signal VSYNC EXIH EXIV POLH POLV No signal H L L L Positive H H L L Negative H H L H No signal H L H L Positive H H H L Negative H H H H No signal L L L L Positive L H L L Negative L H L H 6/12 BA7078AF/AS Multimedia ICs !Relationship between INPUT to OUTPUT OUTPUT INPUT Composite / HSYNC VSYNC − − VIDEO − − − VDRV CLAMP VIDEO VIDEO CS CS CS VIDEO VS VIDEO CS VS CS − − − − − − − CS CS CS − − VS − − CS VS CS − Explanation of symbol HDRV VIDEO − : No Signal : Signal Input !Input signal range Vert. separate sync Hor. separate sync Parameter Polarity Amplitude (Sync) : Vs Composite sync Sync on Video Posi. / Neg. Posi. / Neg. Posi. / Neg. Neg. 1.0 to 5.0VP-P 1.0 to 5.0VP-P 1.0 to 5.0VP-P 0.2 to 0.6VP-P (Video) : Vv 0 to 2.1VP-P Vert. sync frequency range : fV Vert. sync pulse width range : pwV 40 to 200Hz − 40 to 200Hz 40 to 200Hz 8.0µs to Duty35% − ∗ 1HMin. to 400µs ∗ 1HMin. Hor. sync frequency range : fH − 15k to 200kHz 15k to 200kHz 15k to 200kHz Hor. sync pulse width range : pwH − 94ns to Duty35% 94ns to Duty30% Duty30% Max. ∗ 1H = 1 / fH !Input signal waveform Vert. / Hor.separate sync T=1/f VS pw Duty=pw/T(%) Composite sync TH=1/fH VS pwV pwH Duty=pwH/TH(%) (ex.pwV=1H) Sync on Video VV VS pwH Duty=pwH/TH(%) pwV (ex.pwV=1H) TH=1/fH 7/12 BA7078AF/AS Multimedia ICs !Measurement circuit 1 POLH HSCTL 18 SW18 2 1 V1 V 3 4 A V 3mA Oscilloscope 2 SW2 1 EXIH C / HSYNC IN 17 3 2 SW17 2 1 3 4 4.7µF 4.7µF V V2 75Ω A V 3mA Oscilloscope 3 SW3 2 1 VIDEO IN POLV 16 3 SW16 2 1 3 4 1µF 1µF V3 75Ω V A V 3mA Oscilloscope 4 VSEPA EXIV 15 0.56µF SW15 2 1 V 3 4 A V 3mA Oscilloscope Vcc 5V 5 SW5 VCC VSYNC IN 14 A 47µF 0.01µF 2 1 3 4.7µF 75Ω V5 1MΩ 6 CVPOL HDRV 13 SW13 1.5µF 3 2 1 V V 8mA Oscilloscope 7 CVEXI CLAMP 12 SW12 1µF 3 2 1 V V 8mA Oscilloscope 8 VDRV CPSEL 11 SW11 3 2 1 V8 V 8mA V Oscilloscope 9 CPWID GND 10 VCC 3.9kΩ 100pF Fig.1 8/12 BA7078AF/AS Multimedia ICs !Conditions for measurement of electrical characteristics Switch condition Parameter 2 3 5 11 12 13 15 16 17 18 Quiescent current 1 1 1 1 1 1 1 1 1 1 VDRV output voltage "H" 1 1 3 1 1 1 1 1 1 1 VDRV output voltage "L" 1 1 3 1 1 1 1 1 1 1 VDRV output current "L" 1 1 3 2 1 1 1 1 1 1 VDRV rising delay time 1 1 2 3 1 1 1 1 1 1 HDRV output voltage "H" 3 1 1 1 1 1 1 1 1 1 HDRV output voltage "L" 3 1 1 1 1 1 1 1 1 1 HDRV output current "L" 3 1 1 1 1 2 1 1 1 1 HDRV rising delay time (1) 2 1 1 1 1 3 1 1 1 1 HDRV rising delay time (2) 1 2 1 1 1 3 1 1 1 1 CLAMP output voltage "H" 2 1 1 1 3 1 1 1 1 1 CLAMP output voltage "L" 2 1 1 1 3 1 1 1 1 1 CLAMP output current "L" 3 1 1 1 2 1 1 1 1 1 CLAMP rising delay time (1) 2 1 1 1 3 1 1 1 1 1 CLAMP rising delay time (2) 1 2 1 1 3 1 1 1 1 1 POLH output voltage "H" 2 1 1 1 1 1 1 1 1 1 POLH output voltage "L" 2 1 1 1 1 1 1 1 1 1 POLH output current "L" 3 1 1 1 1 1 1 1 1 2 POLH output impedance 3 1 1 1 1 1 1 1 1 4 EXIH output voltage "H" 2 1 1 1 1 1 1 1 1 1 EXIH output voltage "L" 1 1 1 1 1 1 1 1 1 1 EXIH output current "L" 3 1 1 1 1 1 1 1 2 1 EXIH output impedance 3 1 1 1 1 1 1 1 4 1 POLV output voltage "H" 1 1 2 1 1 1 1 1 1 1 POLV output voltage "L" 1 1 2 1 1 1 1 1 1 1 POLV output current "L" 1 1 3 1 1 1 1 2 1 1 POLV output impedance 1 1 3 1 1 1 1 4 1 1 EXIV output voltage "H" 1 1 2 1 1 1 1 1 1 1 EXIV output voltage "L" 1 1 1 1 1 1 1 1 1 1 EXIV output current "L" 1 1 3 1 1 1 2 1 1 1 EXIV output impedance 1 1 3 1 1 1 4 1 1 1 Minimum synchronization separation level 1 2 1 1 1 3 1 1 1 1 HSCTL "H" level threshold voltage 2 1 2 1 1 3 1 1 1 1 HSCTL "L" level threshold voltage 2 1 2 1 1 3 1 1 1 1 CPSEL "H" level threshold voltage 1 2 1 1 3 3 1 1 1 1 CPSEL "L" level threshold voltage 2 1 1 1 3 3 1 1 1 1 9/12 BA7078AF/AS Multimedia ICs !Application example HSCTL C / H SYNC IN 1 C1 2 H SYNC DET. 18 POLH 17 EXIST H 16 POLV 15 EXIST V 4.7µF VIDEO IN C2 3 SYNC SEPA. 1µF 4 C3 VSYNC IN 0.56µF 0.47µF C7 HOR. SYNC CONTROL 14 R2 1MΩ 1.5µF C5 1µF OPEN : AUTO H : Front L : Back 13 HDRV 12 CLAMP 11 VDRV V SYNC DET. 7 CPSEL 47µF 0.01µF 6 C4 Vcc 5V V SYNC SEPA. 5 8 CLAMP PULSE GEN. Vcc 10 9 R1 C6 3.9kΩ 100pF Fig.2 10/12 BA7078AF/AS Multimedia ICs !Attached components R: The resistor for limiting the LED current. Use the resistor of not less than 1W. R RPM-850 LED C1 : 47µF Coupling capacitor for C / H SYNC IN A low capacitance increases the size of the input pin waveform’s sag. C2 : 1µF Coupling capacitor for VIDEO IN A low capacitance increase the size of the input pin waveform’s sag. C3 : 0.56µF Conversion capacitor for f-V A low capacitance increase the size of the ripple of the f-V conversion voltage. A large capacitance is not a problem, but will delay the reaction speed. C4 : 1.5 µF Capacitor for POLH (detection of the vertical synchronization signal’s polarity) The minimum capacitance is determined as follows: The internal hysteresis comparator does not react when the duty of minimum frequency synchronization (fV = 40Hz, T = 25ms) is 50%. CMin. = 16µ × T [F] A large capacitance is not a probrem, built will deray the reaction speed. C5 : 1µF Capacitor for EXIH (detection of the vertical synchronization signal’s existance) The minimum capacitance is determined as follows: The internal hysteresis comparator does not react at the minimum frequency synchronization (fV = 40Hz, T = 25ms) CMin. = 16µ × T [F] A large capacitance is not a problem, but will deray the reaction speed. C6 : 100pF Constant for setting the clamp pulse width C7 : 0.47µF Coupling capacitor for VSYNC IN A low capacitance increases the size of the input pin waveform’s sag. R1 : 3.9kΩ A low resistance results in a narrow clamp pulse width. Set no lower than 1kΩ. R2 : 1MΩ Discharge current setting resistor for CLAMP IN 11/12 BA7078AF/AS Multimedia ICs 90 80 70 60 50 40 30 20 10 VCC=5.0V 0 −50 −25 0 25 50 75 100 TEMPERATURE : Ta(°C) 140 Output position : front edge 120 100 80 60 40 20 Vcc=5.0V 0 −50 100 80 60 40 20 Vcc=5.0V 25 50 75 25 50 75 100 140 120 100 80 60 40 20 Vcc=5.0V 0 −50 −25 100 TEMPERATURE : Ta (°C) 0 25 50 75 100 TEMPERATURE : Ta (°C) Fig.5 VIDEO IN−HDRV Rising delay time vs. temperature 3 260 240 2.5 PIN VOLTAGE : VS (V) 120 PROPAGATION DELAY OF RISE TIME : trdvd (ns) PROPAGATION DELAY OF RISE TIME : trdcl (ns) Output position back edge 0 0 160 Fig.4 C / HSYNC IN-CLAMP Rising delay time vs. temperature 140 −25 −25 TEMPERATURE : Ta (°C) Fig.3 C / HSYNC IN-HDRV Rising delay time vs. temperature 0 −50 PROPAGATION DELAY OF RISE TIME : trdhd (ns) 100 PROPAGATION DELAY OF RISE TIME : trdcl (ns) PROPAGATION DELAY OF RISE TIME : trdhd (ms) !Electrical characteristic curves 220 200 180 160 140 2 1.5 1 0.5 120 100 −50 Fig.6 VIDEO IN-CLAMP Rising delay time vs. temperature VCC=5.0V VCC=5.0V −25 0 25 50 75 0 0 100 20 40 60 80 100 120 140 160 180 200 TEMPERATURE : Ta (°C) HORIZONTAL FREQUENCY : fH (kHz) Fig.7 VSYNC IN-VDRV Rising delay time vs. temperature Fig.8 VSEPA horizontal frequency vs. pin voltage !External dimensions (Unit : mm) BA7078AF BA7078AS 11.2±0.2 19.4 ± 0.3 10 18 10 1 9 0.4±0.1 0.3Min. 0.51Min. 6.5 ± 0.3 1.27 3.95 ± 0.3 9 3.4 ± 0.2 0.11 1.8±0.1 1 0.15±0.1 5.4±0.2 7.8±0.3 18 7.62 0.3 ± 0.1 1.778 0.5 ± 0.1 0 ∼ 15 0.15 SOP18 SDIP18 12/12 Appendix Notes No technical content pages of this document may be reproduced in any form or transmitted by any means without prior permission of ROHM CO.,LTD. The contents described herein are subject to change without notice. The specifications for the product described in this document are for reference only. Upon actual use, therefore, please request that specifications to be separately delivered. Application circuit diagrams and circuit constants contained herein are shown as examples of standard use and operation. Please pay careful attention to the peripheral conditions when designing circuits and deciding upon circuit constants in the set. Any data, including, but not limited to application circuit diagrams information, described herein are intended only as illustrations of such devices and not as the specifications for such devices. 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In case of export from Japan, please confirm if it applies to "objective" criteria or an "informed" (by MITI clause) on the basis of "catch all controls for Non-Proliferation of Weapons of Mass Destruction. Appendix1-Rev1.0