ETC BA7078S

Multimedia ICs
Synchronization signal processor for
high definition displays
BA7078S
The BA7078S is a synchronization signal processing LSI chip designed for multiscan high-definition displays. It generates a synchronization signal and clamp pulse for three types of input signals: separate synchronization, composite
synchronization, and synchronization on video.
Applications
•CRT
displays
•1)Features
Operates on a single 5V power supply, with low
4) Vertical synchronization separation is based on horizontal frequency tracking, for separation starting at
1H.
5) Minimal attached components.
power consumption.
2) Synchronization signal existence and polarity detection output.
3) Adjustable clamp pulse width, allowing for the selection of front or back editing.
•Absolute maximum ratings (Ta = 25°C)
Parameter
Symbol
Limits
Unit
Power supply voltage
VCC
7.0
V
Power dissipation
Pd
600
mW
Operating temperature
Topr
– 25 ~ + 75
°C
Storage temperature
Tstg
– 55 ~ + 125
°C
∗ Reduced by 6mW for each increase in Ta of 1°C over 25°C.
•Recommended operating conditions (Ta = 25°C)
Parameter
Power supply voltage
Symbol
Min.
Typ.
Max.
Unit
VCC
4.5
5.0
5.5
V
1
Multimedia ICs
BA7078S
•Block diagram
HSCTL
1
C / HSYNC IN
2
VIDEO IN
3
VSEPA
4
VSYNC IN
5
CVPOL
6
H SYNC Det.
SYNC Sepa.
Hor. SYNC
Control
18
POLH
17
EXIH
16
POLV
15
EXIV
14
Vcc
13
HDRV
12
CLAMP
11
VDRV
10
CPWID
V SYNC Sepa.
V SYNC Det.
2
CVEXI
7
CPSEL
8
GND
9
Clamp Pulse Gen.
Multimedia ICs
BA7078S
•Pin descriptions
Pin No.
Pin name
Function
HDRV output
Used to select whether to output the VDRV section of the HDRV output
signal.
High: VDRV section of HDRV is output
Low: VDRV section of HDRV is not output
Composite sync / H SYNC input
Inputs either the composite synchronization signal or the horizontal
synchronization signal. Input is clamped, and is initiated by capacitor
coupling.
1
HSCTL
2
CHSYNC IN
3
VIDEO IN
4
VSEPA
f-V conversion
Converts the horizontal synchronization signal frequency into a voltage.
The voltage generated is proportional to the frequency of the horizontal
synchronization signal. Attach a 0.56µF capacitor between the ground pins.
5
VSYNC IN
V SYNC input
Inputs the vertical synchronization signal.
6
CVPOL
Vertical polarity integration
Integrates the vertical synchronization signal polarity detection circuit.
Attach a 1.5µF capacitor between this pin and the ground.
7
CVEXI
8
CPSEL
9
GND
SYNC ON VIDEO input
Vertical existence integration
Setting the clamp position
Ground
Inputs the SYNC ON VIDEO signal (green).
Input is sink chip clamped. Input is initiated by capacitor coupling.
Integrates the vertical synchronization signal existence detection circuit.
Attach a 1µF capacitor between this pin and the ground.
Used to set the clamp pulse generation position to either the front or back
edge of HSYNC
High: The front edge is the generation position
Open: Composite / H SYNC IN: The front edge is
the generation position
VIDEO IN: The back edge is
the generation position
Low: The back edge is the generation position
—
10
CPWID
Setting the clamp pulse width
Sets the clamp pulse width according to the attached time constant.
Attach a resistor between this pin and Vcc, and a capacitor between
this pin and GND. When R = 3.9kΩ and
C = 100pF, pulse width is approximately 400 ns. Set the
resistor to register an abnormality at 1kΩ.
11
VDRV
VDRV output
Outputs the vertical synchronization signal.
The output signal has positive polarity.
12
CLAMP
Clamp output
Outputs the clamp pulse generated from the vertical
synchronization signal. The output signal has a positive polarity.
13
HDRV
HDRVoutput
Outputs the clamp pulse generated from the horizontal
synchronization signal. The output signal has positive polarity.
14
VCC
Power supply
—
3
Multimedia ICs
BA7078S
Pin No.
Pin name
Function
15
EXIV
Vertical existence output
Indicates whether the vertical synchronization signal
exists. For the output logic, refer to the separate table.
16
POLV
Vertical polarity output
Indicates the polarity of the vertical synchronization
signal. For the output logic, refer to the separate table.
17
EXIH
Horizontal existence output
Indicates whether the horizontal synchronization signal
exists. For the output logic, refer to the separate table.
18
POLH
Horizontal polarity output
Indicates the polarity of the horizontal synchronization
signal. For the output logic, refer to the separate table.
•Input / output circuits
HSCTL
VSEPA
CHSYNC IN
VCC
VCC
VCC
670Ω
60kΩ
200Ω
1kΩ
51kΩ
2pin
4pin
1pin
30kΩ
10µA
CVPOL
VIDEO IN
VSYNC IN
VCC
200Ω 10kΩ
3pin
5pin
50kΩ
4
VCC
VCC
2kΩ
200Ω
6pin
200Ω
Multimedia ICs
BA7078S
CVEXI
CPSEL
CPWID
VCC
VCC
VCC
50kΩ
1kΩ
8pin
10pin
7pin
50kΩ
GND
VDRV
CLAMP
VCC
VCC
9pin
12pin
11pin
HDRV
POLV
VCC
VCC
VCC
VCC
10kΩ
14pin
13pin
16pin
5
Multimedia ICs
BA7078S
EXIV
EXIH
POLH
VCC
VCC
VCC
10kΩ
10kΩ
10kΩ
17pin
15pin
•Electrical characteristics (unless otherwise noted, V
Parameter
Power supply voltage
Quiescent current
CC
18pin
= 5V, Ta = 25°C)
Symbol
Min.
Typ.
Max.
Unit
VCC
4.5
5.0
5.5
V
ICC
21
30
39
mA
VDRV output voltage (high)
V VDH
4.5
5.0
—
V
VDRV output voltage (low)
V VDL
—
0.2
0.5
V
VDRV output current (low)
I VDL
8
—
—
mA
VDRV rising delay time
t rdVD
—
280
450
ns
HDRV output voltage (high)
V HDH
4.5
5.0
—
V
HDRV output voltage (low)
V HDL
—
0.2
0.5
V
HDRV output current (low)
I HDL
8
—
—
mA
Conditions
VSYNC IN
HDRV rising delay time (1)
trdHD1
—
65
115
ns
CHSYNC IN
HDRV rising delay time (2)
trdHD2
—
95
145
ns
VIDEO IN
CLAMP output voltage (high)
V CPH
4.5
5.0
—
V
CLAMP output voltage (low)
V CPL
—
0.2
0.5
V
CLAMP output current (low)
I CPL
8
—
—
mA
CLAMP rising delay time (1)
trdCP1
—
75
125
ns
front edge
CLAMP rising delay time (2)
trdCP2
—
95
145
ns
back edge
Synchronization detection output voltage (high)
V DH
4.5
5.0
—
V
Synchronization detection output voltage (low)
V DL
—
0.2
0.5
V
Synchronization detection output current (low)
I DL
3
—
—
mA
Synchronization detection output impedance
Z oD
7
10
13
kΩ
Minimum synchronization separation level
V SMin.
—
—
0.2
VP-P
HSCTL high level threshold voltage
V tHSH
2.5
—
—
V
HSCTL low level threshold voltage
V tHSL
—
—
1.5
V
CPSEL high level threshold voltage
V tCPH
3.8
—
—
V
CPSEL low level threshold voltage
V tCPL
—
—
1.2
V
6
Multimedia ICs
BA7078S
•Measurement circuit
1
POLH
HSCTL
18
SW18
2
1
V1
V
3
4
A
V
3mA
Oscilloscope
2
SW2
1
4.7µF
2
EXIH
CHSYNC IN
17
3
SW17
4.7µF
V
V2
75Ω
2
1
3
4
A
V
3mA
Oscilloscope
3
SW3
2
1
1µF
VIDEO IN
POLV
16
3
1µF
SW16
V
V3
75Ω
2
1
3
4
A
V
3mA
Oscilloscope
4
VSEPA
EXIV
15
0.56µF
SW15
2
1
V
3
A
V
3mA
4
Oscilloscope
5
SW5
VCC
VSYNC IN
14
Vcc 5V
A
47µF
0.01µF
2
1
3
V5
75Ω
6
CVPOL
HDRV
13
SW13
1.5µF
3
2
1
V
V
8mA
Oscilloscope
7
CLAMP
CVEXI
12
1µF
SW12
3
2
1
V
V
8mA
Oscilloscope
8
VDRV
CPSEL
11
SW11
V8
3
2
1
V
8mA
V
Oscilloscope
9
CPWID
GND
10
VCC
3.9kΩ
100pF
Fig. 1
7
Multimedia ICs
BA7078S
•Conditions for measurement of electrical characteristics
Parameter
Switch condition
2
3
5
11
12
13
15 16
17
18
Quiescent current
1
1
1
1
1
1
1
1
1
1
VDRV output voltage (high)
1
1
3
1
1
1
1
1
1
1
VDRV output voltage (low)
1
1
3
1
1
1
1
1
1
1
VDRV output current (low)
1
1
3
2
1
1
1
1
1
1
VDRV rising delay time
1
1
2
3
1
1
1
1
1
1
HDRV output voltage (high)
3
1
1
1
1
1
1
1
1
1
HDRV output voltage (low)
3
1
1
1
1
1
1
1
1
1
HDRV output current (low)
3
1
1
1
1
2
1
1
1
1
HDRV rising delay time (1)
2
1
1
1
1
3
1
1
1
1
HDRV rising delay time (2)
1
2
1
1
1
3
1
1
1
1
CLAMP output voltage (high)
2
1
1
1
3
1
1
1
1
1
CLAMP output voltage (low)
2
1
1
1
3
1
1
1
1
1
CLAMP output current (low)
3
1
1
1
2
1
1
1
1
1
CLAMP rising delay time (1)
2
1
1
1
3
1
1
1
1
1
CLAMP rising delay time (2)
1
2
1
1
3
1
1
1
1
1
POLH output voltage (high)
2
1
1
1
1
1
1
1
1
1
POLH output voltage (low)
2
1
1
1
1
1
1
1
1
1
POLH output current (low)
3
1
1
1
1
1
1
1
1
2
POLH output impedance
3
1
1
1
1
1
1
1
1
4
EXIH output voltage (high)
2
1
1
1
1
1
1
1
1
1
EXIH output voltage (low)
1
1
1
1
1
1
1
1
1
1
EXIH output current (low)
3
1
1
1
1
1
1
1
2
1
EXIH output impedance
3
1
1
1
1
1
1
1
4
1
POLV output voltage (high)
1
1
2
1
1
1
1
1
1
1
POLV output voltage (low)
1
1
2
1
1
1
1
1
1
1
POLV output current (low)
1
1
3
1
1
1
1
2
1
1
POLV output impedance
1
1
3
1
1
1
1
4
1
1
EXIV output voltage (high)
1
1
2
1
1
1
1
1
1
1
EXIV output voltage (low)
1
1
1
1
1
1
1
1
1
1
EXIV output current (low)
1
1
3
1
1
1
2
1
1
1
EXIV output impedance
1
1
3
1
1
1
4
1
1
1
Minimum synchronization separation level
1
2
1
1
1
3
1
1
1
1
HSCTL high level threshold voltage
2
1
2
1
1
3
1
1
1
1
HSCTL low level threshold voltage
2
1
2
1
1
3
1
1
1
1
CPSEL high level threshold voltage
1
2
1
1
3
3
1
1
1
1
CPSEL low level threshold voltage
2
1
1
1
3
3
1
1
1
1
8
Multimedia ICs
BA7078S
•Application example
HSCTL
C / H SYNC IN
1
C1
2
H SYNC Det.
18
POL H
17
EXIST H
16
POL V
15
EXIST V
4.7µF
VIDEO IN
C2
3
1µF
SYNC Sepa.
4
C3
0.56µF
V SYNC Sepa
5
V SYNC IN
Hor. SYNC
Control
Vcc 5V
14
47µF
0.01µF
6
C4
1.5µF
C5
1µF
OPEN: AUTO
H: Front
L : Back
H DRV
12
CLAMP
11
V DRV
V SYNC Det.
7
CP SEL
13
8
Clamp Pulse Gen.
Vcc
10
9
R1
C6
3.9kΩ
100pF
Fig. 2
9
Multimedia ICs
BA7078S
•Attached components
C1: 47µF
Coupling capacitor for C / H SYNC IN
A low capacitance increases the size of the input pin waveform's sag.
C2: 1µF
Coupling capacitor for VIDEO IN
A low capacitance increases the size of the input pin waveform's sag.
C3: 0.56µF
Conversion capacitor for f-V
A low capacitance increases the size of the ripple of the f-V conversion voltage. A large capacitance is
not a problem, but will delay the reaction speed.
C4: 1.5µF
Capacitor for POLH (detection of the vertical synchronization signal's polarity)
The minimum capacotance is determined as follows:
The internal hysteresis comparator does not react when the duty of minimum frequency synchronization (fV = 40Hz, T = 25ms) is 50%.
CMin. = 30µ ∗ T[F]
A large capacitance is not a probrem, buit will deray the reaction speed.
C5: 1µF
Capacitor for EXIH (detection of the vertical synchronization signal's existence)
The minimum capacitance is determined as follows:
The internal hysteresis comparator does not react at the minimum frequency synchronization (fV =
40Hz, T = 25ms)
CMin. = 16µ ∗ T[F]
A large capacitance is not a probrem, but will deray the reaction speed.
C6: 100pF
Constant for setting the clamp pulse width
R1: 3.9kΩ
A low resistance results in a narrow clamp pulse width. Set no lower than 1kΩ.
10
BA7078S
100
PROPAGATION DELAY OF RISE TIME: trdcl (ns)
90
80
70
60
50
40
30
20
10
0
– 50
Vcc = 5.0V
– 25
0
25
50
75
100
TEMPERATURE: Ta (°C)
140
Output position: front edge
120
100
80
60
40
20
Vcc = 5.0V
0
– 50
PROPAGATION DELAY OF RISE TIME: trdvd (ns)
PROPAGATION DELAY OF RISE TIME: trdcl (ns)
Output position back edge
120
100
80
60
40
20
Vcc = 5.0V
0
25
50
75
25
50
75
100
160
140
120
100
80
60
40
20
Vcc = 5.0V
0
– 50
100
TEMPERATURE: Ta (°C)
Fig. 6 VIDEO IN-CLAMP
Rising delay time vs.
temperature
– 25
0
25
50
75
100
TEMPERATURE: Ta (°C)
Fig. 4 C / HSYNC IN-CLAMP
Rising delay time vs.
temperature
140
– 25
0
TEMPERATURE: Ta(°C)
Fig. 3 C / HSYNC IN-HDRV
Rising delay time vs.
temperature
0
– 50
– 25
Fig. 5 VIDEO IN-HDRV
Rising delay time vs.
temperature
3
260
240
2.5
PIN VOLTAGE: VS (V)
PROPAGATION DELAY OF RISE TIME: trdhd (ms)
•Electrical characteristic curves
PROPAGATION DELAY OF RISE TIME: trdhd (ns)
Multimedia ICs
220
200
180
160
140
2
1.5
1
0.5
120
Vcc = 5.0V
Vcc = 5.0V
100
– 50
– 25
0
25
50
75
100
0
0
20 40 60 80 100 120 140 160 180 200
TEMPERATURE: Ta (°C)
HORIZONTAL FREQUENCY: fH (kHz)
Fig. 7 VSYNC IN-HDRV
Rising delay time vs.
temperature
Fig. 8 VSEPA horizontal
frequency vs.
pin voltage
•External dimensions (Units: mm)
19.4 ± 0.3
10
1
9
3.4 ± 0.2
0.51Min.
3.95 ± 0.3
6.5 ± 0.3
18
7.62
0.3 ± 0.1
1.778
0.5 ± 0.1
0°~15°
SDIP18
11