PHILIPS N74F8966A

Philips Semiconductors FAST Products
Product specification
9-Bit address/data Futurebus transceiver, ADT
FEATURES
• 9–bit transceiver (both directions)
• Drives heavily loaded backplanes with
equivalent load impedances down to
10 ohms
• High drive (100mA) open collector
drivers on B port
• Reduced voltage swing (1V to 2V)
produces less noise and reduces
power consumption
• High speed operation enhances
performance of backplane buses and
facilitates incident wave switching
• Compatible with IEEE 896 futurebus
standards and IEEE 1194 BTL standard
• Built–in precision band–gap reference
provides accurate receiver thresholds
and improved noise immunity
• Controlled output ramp and multiple
GND pins minimize ground bounce
• Glitch–free power up/power down
operation
74F8965/74F8966
• Guaranteed skew of less than 2ns
DESCRIPTION
The 74F8965 and 74F8966 are 9–bit
bidirectional latchable transceivers and are
intended to provide the electrical interface to
a high performance wired–OR bus. The B
port inverting drivers are low–capacitance
open collector with controlled ramp and are
designed to sink 100mA from 2 volts. The B
port inverting receivers have a precision band
gap references for improved noise margins.
The B port interfaces to ’Backplane
Transceiver Logic’ (BTL). BTL features a
reduced (1V to 2V) voltage swing for lower
power consumption and a series diode on
the drivers to reduce capacitive loading.
Incident wave switching is employed, therefore BTL propagation delays are short. Although the voltage swing is much less for
BTL, so is its receiver threshold region,
therefore noise margins are excellent.
BTL offers low power consumption, low
ground bounce, EMI and crosstalk, low
capacitive loading, superior noise margin and
low propagation delays. This results in a high
bandwidth, reliable backplane.
The 74F8965 and 74F8966 A ports have TTL
3–state drivers and TTL receivers.
The B ports have standard BTL I/O with
100mA current sink capability. The B–to–A
path is a simple inverted buffered path. When
going from A–to–B the user may choose between a buffered path or a latching function.
The 74F8966 also has an idle arbitrator/multiple competitors output. The IAMC output
compares, using a wired–OR configuration,
the data on the bus to the latched data presented to the bus. If the bus data matches the
data presented by the 74F8966 then IAMC is
high. If the data doesn’t match then IAMC
goes low.
TYPICAL PROPAGATION DELAY
TYPICAL SUPPLY CURRENT( TOTAL)
74F8965
3.5ns
80mA
74F8966
3.5ns
80mA
TYPE
ORDERING INFORMATION
DESCRIPTION
ORDER CODE
COMMERCIAL RANGE
VCC = 5V ±10%, Tamb = 0°C to +70°C
44–pin PLCC
N74F8965A, N74F8966A
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
74F (U.L.)
HIGH/LOW
DESCRIPTION
LOAD VALUE
HIGH/LOW
A0 – A8
TTL data inputs
1.0/0.033
20µA/20µA
B0 – B8
Data inputs with threshold circuitry
5.0/0.167
100µA/100µA
Output enable inputs
1.0/0.167
20µA/100µA
Latch select (active low) (’F8965)
1.0/0.167
20µA/100µA
Idle arbitration request (active low) (’F8965)
1.0/0.167
20µA/100µA
Latch enable input (active low)
1.0/0.167
20µA/100µA
150/40
3mA/24mA
OC/166.7
OC/100mA
OC/80
OC/48mA
OEA, OEB0, OEB1
LS
IAREQ
LE
A0 – A8
3–state TTL outputs
B0 – B8
Open collector BTL outputs
IAMC
Idle arbitration/multiple competitors output (’F8966)
Notes to input and output loading and fan out table
1. One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
2. OC = Open collector.
December 19, 1990
1
853 1526 01320
Philips Semiconductors FAST Products
Product specification
9-Bit address/data Futurebus transceiver, ADT
PIN CONFIGURATION PLCC
74F8965/74F8966
IEC/IEEE SYMBOL
74F8965
74F8965
LOGIC
BUS BUS
LOGIC
A1 GND A0 VCC OEA OEB0 OEB1 VCC GND
B0
BUS
GND
6
41
40
5
4
3
2
1
44
43
42
23
LOGIC GND
7
39 B1
A2
8
38 BUS GND
LOGIC GND
9
44
22
2
37 B2
A3 10
&
EN3
2
C4
EN5
4
36 BUS GND
LOGIC GND 11
G1/V2
1
1
35 B3
1
1
34 BUS GND
A4 12
33 B4
A5 13
LOGIC GND 14
32 BUS GND
A6 15
31 B5
LOGIC GND 16
30 BUS GND
29 B6
A7 17
18
19
20
21
22
LOGIC A8 LOGIC LOGIC LE
GND
GND V
CC
23
24
25
LS
BUS
VCC
B8
26
27
BUS B7
GND
39
8
37
10
35
12
33
13
31
15
29
17
27
19
25
28
IEC/IEEE SYMBOL
74F8966
74F8966
BUS BUS
LOGIC
LOGIC
A1 GND A0 VCC OEA OEB0 OEB1 VCC GND
5
4
3
3
6
BUS
GND
PIN CONFIGURATION PLCC
6
41
1 MUX
4D
2
1
44
43
42
B0
BUS
GND
41
40
LOGIC GND
7
39 B1
A2
8
38 BUS GND
LOGIC GND
9
37 B2
23
1
A3 10
44
22
2
1
10
11
G1/V2/EN6 12
13
&
EN3 14
15
2
16
C4
17
18
EN5
20
36 BUS GND
41
1
4
LOGIC GND 11
35 B3
A4 12
34 BUS GND
A5 13
33 B4
LOGIC GND 14
A6 15
LOGIC GND 16
18
19
December 19, 1990
20
21
22
23
24
IAMC LOGIC LE IREQ BUS
VCC
VCC
25
B8
26
27
BUS B7
GND
28
BUS
GND
2
1 N7 1
MUX
3
39
8
37
32 BUS GND
10
35
31 B5
12
33
13
31
15
29
17
27
19
25
29 B6
LOGIC A8
GND
1
6
30 BUS GND
A7 17
7 Z10
4D
Philips Semiconductors FAST Products
Product specification
9-Bit address/data Futurebus transceiver, ADT
74F8965/74F8966
LOGIC SYMBOL
74F8965
4
6
8
74F8966
10 12 13 15 17 19
4
A0 A1 A2 A3 A4 A5 A6 A7 A8
OEB0
1
OEB0
44
OEB1
44
OEB1
23
LS
23
IAREQ
22
LE
22
LE
OEA
8
10 12 13 15 17 19
A0 A1 A2 A3 A4 A5 A6 A7 A8
1
2
6
B0 B1 B2 B3 B4 B5 B6 B7 B8
2
OEA
20
IAMC
B0 B1 B2 B3 B4 B5 B6 B7 B8
41 39 37 35 33 31 29 27 25
41 39 37 35 33 31 29 27 25
Logic VCC = Pin 3, 21
Logic GND = Pin 5, 7, 9, 11, 14, 16, 18
Logic VCC = Pin 3, 21
Logic GND = Pin 5, 7, 9, 11, 14, 16, 18, 20
PIN DESCRIPTION
SYMBOL
PINS
TYPE
A0 – A8
4, 6, 8, 10, 12, 13, 15, 17, 19
I/O
Data inputs/TTL 3–state outputs
B0 – B8
41, 39, 37, 35, 33, 31, 29, 27, 25
I/O
Data inputs / open collector outputs, high current drives.
OEB0
1
Input
Output enable input. Enables the B outputs when high.
OEB1
44
Input
Output enable input. Enables the B outputs when low.
OEA
2
Input
Output enable input. Enables the A outputs when high.
LE
22
Input
Latch enable input. Enables latch when low.
LS
23
Input
Latch select input. Selects latch when low (74F8965).
IAREQ
23
Input
Idle arbitration request input (74F8966).
IAMC
20
Output
Idle arbitration/multiple competitors output (open collector output) (74F8966).
Bus GND
26, 28, 30, 32, 34, 36, 38, 40, 42
Ground
Bus ground (0V)
Logic GND
5, 7, 9, 11, 14, 16, 18, 20 (74F8965)
Ground
Logic ground (0V)
Bus VCC
24, 43
Power
Positive supply voltages
Logic VCC
3, 21
Power
Positive supply voltages
December 19, 1990
NAME AND FUNCTION
3
Philips Semiconductors FAST Products
Product specification
9-Bit address/data Futurebus transceiver, ADT
74F8965/74F8966
LOGIC DIAGRAM FOR 74F8965
OEB0
1
OEB1
44
LS
23
LE
22
OEA
2
D Q
41
E
A0
B0
4
D Q
39
E
A1
B1
6
D Q
37
E
A2
B2
8
D Q
35
E
A3
B3
10
D Q
33
E
TTL levels
A4
B4
12
D Q
31
E
A5
B5
13
D Q
29
E
A6
B6
15
D Q
27
E
A7
B7
17
D Q
25
E
A8
B8
19
Logic VCC = Pin 3, 21
Logic GND = Pin 5, 7, 9, 11, 14, 16, 18, 20
December 19, 1990
4
BTL levels
Philips Semiconductors FAST Products
Product specification
9-Bit address/data Futurebus transceiver, ADT
74F8965/74F8966
LOGIC DIAGRAM FOR 74F8966
OEB0
OEB1
IAREQ
LE
OEA
1
44
48mA
open
collector
23
20
IAMC
TTL level
22
2
D Q
41
E
4
B0
A0
D Q
6
39
E
B1
A1
D Q
8
37
E
B2
A2
D Q
10
35
E
B3
A3
D Q
TTL levels
12
33
E
B4
A4
D Q
13
31
E
B5
A5
D Q
15
29
E
B6
A6
D Q
17
27
E
B7
A7
D Q
19
25
E
A8
Logic VCC = Pin 3, 21
Logic GND = Pin 5, 7, 9, 11, 14, 16, 18
December 19, 1990
5
B8
BTL levels
Philips Semiconductors FAST Products
Product specification
9-Bit address/data Futurebus transceiver, ADT
74F8965/74F8966
FUNCTION TABLE FOR 74F8965
INPUTS
LATCH
OUTPUTS
AIn
Bn*
OEB0
OEB1
LS
OEA
LE
STATE
An
Bn
L
–
H
L
H
L
X
X
input
H**
H
–
H
L
H
L
X
X
input
L
L
–
H
L
L
L
L
H
input
H**
H
–
H
L
L
L
L
L
input
L
OPERATING MODE
An to Bn bypass latch
An to Bn transparent latch
l
–
H
L
L
L
↑
H
input
H**
h
–
H
L
L
L
↑
L
input
L
–
–
H
L
L
H
H
H
L
H**
–
–
H
L
L
H
H
L
H
L
(preconditioned latch)
X
–
H
L
L
L
H
NC
input
L
An to Bn hold
X
X
L
X
X
X
X
X
X
H**
X
X
X
H
H
X
X
X
X
H**
–
L
L
H
H
H
X
X
H
input
–
H
L
H
H
H
X
X
L
input
–
X
X
X
X
L
X
X
Z
X
An to Bn latch and read
An to Bn outputs latched and read
Disable Bn outputs
Bn to An
Disable An outputs
Notes to function table for 74F8965
1. H = High voltage level
2. h = High voltage level one setup time prior to the low–to–high LE transition
3. L = Low voltage level
4. l = Low voltage level one setup time prior to the low–to–high LE transition
5. NC= No change
6. X = Don’t care
7. Z = High impedance ”off’ state
8. – = Input not externally driven
9. ↑ = Low–to–high transition
10.H**= Goes to level of pullup voltage.
11. B* = Precaution should be taken to insure B inputs do not float. If they do they are equal to low state.
FUNCTION TABLE FOR 74F8966
INPUTS
LATCH
OUTPUTS
OPERATING MODE
AIn
Bn*
OEB0
OEB1
IAREQ
LS
OEA
LE
STATE
An
Bn
IAMC
L
–
H
L
L
H
L
X
X
input
H**
H**
H
–
H
L
L
H
L
X
X
input
L
H**
L
–
H
L
L
L
L
L
H
input
H**
H**
H
–
H
L
L
L
L
L
L
input
L
H**
An to Bn bypass latch
An to Bn transparent latch
l
–
H
L
L
L
L
↑
H
input
H**
H**
h
–
H
L
L
L
L
↑
L
input
L
H**
–
–
H
L
L
L
H
H
H
L
H**
H**
An to Bn outputs latched and read
–
–
H
L
L
L
H
H
L
H
L
H**
(preconditioned latch)
X
–
H
L
L
L
L
H
NC
input
NC
H**
An to Bn hold
X
X
L
X
X
X
X
X
X
X
H**
H**
Disable Bn outputs
X
X
X
H
H
H
X
X
X
X
H**
H**
–
L
L
H
H
H
H
X
X
H
input
H**
–
H
L
H
H
H
H
X
X
L
input
H**
–
Bn
L
H
H
↓*
H
H
Bn
Z
Bn
L
–
Bn
L
H
H
↓*
H
H
Bn
Z
Bn
H**
–
X
X
X
X
X
L
X
X
Z
X
X
December 19, 1990
6
An to Bn latch and read
Bn to An
Latch Bn data idle arbitration request
(preconditioned latch)
Disable An outputs
Philips Semiconductors FAST Products
Product specification
9-Bit address/data Futurebus transceiver, ADT
74F8965/74F8966
Notes to function table for 74F8966
1. H = High voltage level
2. h = High voltage level one setup time prior to the low–to–high LE transition
3. L = Low voltage level
4. l = Low voltage level one setup time prior to the low–to–high LE transition
5. NC= No change
6. X = Don’t care
7. Z = High impedance ”off’ state
8. – = Input not externally driven
9. ↑ = Low–to–high transition
10.↓* = High–to–low transition, latch must be preconditioned before IAREQ
11. H**= Goes to level of pullup voltage.
12.B* = Precaution should be taken to insure B inputs do not float. If they do they are equal to low state.
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free air temperature range.)
SYMBOL
PARAMETER
VCC
Supply voltage
VIN
Input voltage
IIN
Input current
VOUT
Voltage applied to output in high output state
IOUT
Current applied to output in low output
state
Tamb
Operating free air temperature range
Tstg
Storage temperature range
RATING
UNIT
–0.5 to +7.0
V
OEB0, OEB1, LEA, LE
–0.5 to +7.0
V
A0 – A8, B0 – B8
–0.5 to +5.5
V
–40 to +5
mA
–0.5 to VCC
V
A0 – A8
48
mA
IAMC (74F8966 only)
96
mA
B0 – B8
200
mA
0 to +70
°C
–65 to +150
°C
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
VCC
Supply voltage
VIH
High–level input voltage
VIL
Low–level input voltage
MIN
NOM
MAX
UNIT
4.5
5.0
5.5
V
Except B0 – B8
2.0
B0 – B8
1.625
V
1.55
V
Except B0 – B8
0.8
V
B0 – B8
1.475
V
–18
mA
–3
mA
IIk
Input clamp current
IOH
High–level output current
A0 – A8
VOH
High–level output voltage
IAMC (74F8966 only)
A0 – A8
24
mA
IOL
Low–level output current
IAMC (74F8966 only)
48
mA
B0 – B8
100
mA
+70
°C
Tamb
Operating free air temperature
range
December 19, 1990
4.5
0
7
V
Philips Semiconductors FAST Products
Product specification
9-Bit address/data Futurebus transceiver, ADT
74F8965/74F8966
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
PARAMETER
SYMBOL
TEST
LIMITS
CONDITIONS1
IOH
High–level output current
IOFF
Power–off output current
VOH
VOL
VIK
II
IIH
IIL
High-level output voltage
Low-level output voltage
MIN
TYP2
UNIT
MAX
B0 – B8
VCC = MAX, VIL = MAX, VIH = MIN, VOH = 2.1V
100
µA
IAMC (74F8966)
VCC = MAX, VIL = MAX, VIH = MIN, VOH = 4.5V
100
µA
B0 – B8
VCC = 0.0V, VIL = MAX, VIH = MIN, VOH = 2.1V
100
µA
IAMC (74F8966)
VCC = 0.0V, VIL = MAX, VIH = MIN, VOH = 4.5V
100
µA
A0 –
A84
VCC = MAX, VIL = MAX, VIH = MIN, IOH = –3mA
VCC
V
0.50
V
0.50
V
1.10
V
VCC = MIN, II = IIK
-1.2
V
VCC = MAX, VI = 7.0V
100
µA
VCC = MAX, VI = 5.5V
1
mA
VCC = MAX, VI = 2.7V
20
µA
A0 – A84
VCC = MIN,
IAMC (74F8966)
VIL = MAX
IOL = 48mA
B0 – B8
VIH = MIN
IOL = 100mA
Input clamp voltage
2.4
IOL = 24mA
0.75
1.0
Input current at
maximum input voltage
OEB0, OEB1,
OEA, LE, LS,
IAREQ
High–level input current
A0 – A8, B0 –
B8
OEB0, OEB1,
OEA, LE, LS,
IAREQ
B0 – B8
VCC = MAX, VI = 2.1V
100
µA
VCC = MAX, VI = 0.5V
–100
µA
Low–level input current
OEB0, OEB1,
OEA, LE, LS,
IAREQ
B0 – B8
VCC = MAX, VI = 0.3V
–100
µA
A0 – A8
VCC = MAX, VO = 2.7V
50
µA
VCC = MAX, VI = 0.5V
–50
µA
-150
mA
IIH + IOZH
Off–state output current,
high–level voltage applied
IIL + IOZL
Off–state output current,
low–level voltage applied
IOS
Short circuit output
current3
ICC
Supply current (total)
A0 – A8 only
AO8
ICCH
ICCL
VCC = MAX
-60
VCC = MAX
80
140
mA
VCC = MAX, VIL = 0.5V
85
145
mA
75
100
mA
ICCZ
Notes to DC electrical characteristics
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at VCC = 5V, Tamb = 25°C.
3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a
high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence
of parameter tests, IOS tests should be performed last.
4. Due to test equipment limitations, actual test conditions are for VIH =1.8V and VIL = 1.3V.
December 19, 1990
8
Philips Semiconductors FAST Products
Product specification
9-Bit address/data Futurebus transceiver, ADT
74F8965/74F8966
AC ELECTRICAL CHARACTERISTICS
A PORT LIMITS
Tamb = +25°C
SYMBOL
PARAMETER
TEST
CONDITION
Tamb = 0°C to +70°C
VCC = +5.0V
CL = 50pF, RL = 500Ω
VCC = +5.0V ± 10%
UNIT
CL = 50pF, RL = 500Ω
MIN
TYP
MAX
MIN
MAX
Waveform 2
3.0
2.5
5.0
4.5
8.0
7.5
2.5
2.5
8.5
8.0
ns
Output enable time to high or low,
OEA to An
Waveform 5, 6
7.5
9.0
9.0
11.0
12.0
13.5
6.0
7.5
14.0
16.0
ns
tPHZ
tPLZ
Output disable from high or low,
OEA to An
Waveform 5, 6
3.0
4.0
5.0
6.0
8.0
9.0
2.5
4.0
9.0
10.0
ns
tsk(o)
Skew between receivers in same package
1.0
ns
tPLH
tPHL
Propagation delay
Bn to An
tPZH
tPZL
Waveform 4
0.5
1.0
B PORT LIMITS
Tamb = +25°C
SYMBOL
PARAMETER
TEST
CONDITION
Tamb = 0°C to +70°C
VCC = +5.0V
CD = 30pF, RU = 9Ω
VCC = +5.0V ± 10%
UNIT
CD = 30pF, RU = 9Ω
MIN
TYP
MAX
MIN
MAX
Waveform 2
2.5
3.0
4.0
5.0
7.0
7.5
2.0
2.5
8.0
9.0
ns
Waveform 2
1.0
1.5
3.0
3.0
5.5
5.5
1.0
1.0
6.0
6.5
ns
Waveform 1, 2
3.0
4.0
5.0
5.5
8.0
8.5
3.0
3.5
8.5
9.5
ns
Output enable/disable time,
OEB0 to Bn
Waveform 2
4.0
5.0
6.0
6.5
8.5
9.5
3.5
3.5
10.0
11.5
ns
tPLH
tPHL
Output enable/disable time,
OEB1 to Bn
Waveform 1
5.5
3.0
7.5
5.0
10.0
8.0
5.0
2.5
11.0
8.5
ns
tPLH
tPHL
Propagation delay
IAREQ or LS to Bn
Waveform 1, 2
4.5
2.0
7.5
6.5
10.0
9.5
4.0
2.0
11.0
11.0
ns
tTLH
tTHL
Transition time, Bn port
10% to 90%, 90% to 10%
Test circuit and
waveforms
2.0
2.0
1.0
1.0
3.0
3.0
ns
tsk(o)
Skew between drivers in same package
Waveform 4
1.0
2.0
ns
tPLH
tPHL
Propagation delay
An to Bn (transparent latch)
tPLH
tPHL
Propagation delay
An to Bn (bypass latch)
tPLH
tPHL
Propagation delay
LE to Bn
tPLH
tPHL
2.0
IAMC PORT LIMITS (74F8966 only)
Tamb = +25°C
SYMBOL
PARAMETER
tPLH
tPHL
Propagation delay
An to IAMC (latches preset)
tPLH
tPHL
Propagation delay
IAREQ to IAMC
December 19, 1990
TEST
CONDITION
Tamb = 0°C to +70°C
VCC = +5.0V
CL = 50pF, RL = 500Ω
VCC = +5.0V ± 10%
UNIT
CL = 50pF, RL = 500Ω
MIN
TYP
MAX
MIN
MAX
Waveform 2
10.5
7.0
14.5
12.0
18.0
15.0
9.5
6.0
20.0
17.5
ns
Waveform 2
6.5
2.5
8.0
4.5
11.0
7.0
6.0
2.0
11.5
8.0
ns
9
Philips Semiconductors FAST Products
Product specification
9-Bit address/data Futurebus transceiver, ADT
74F8965/74F8966
AC SETUP REQUIREMENTS
LIMITS
Tamb = +25°C
SYMBOL
PARAMETER
TEST
CONDITION
VCC = +5.0V
CL = 50pF, RL = 500Ω
MIN
tsu(H)
tsu(L)
Setup time, high or low
An to LE
th(H)
th(L)
tw(L)
Tamb = 0°C to +70°C
TYP
VCC = +5.0V ± 10%
UNIT
CL = 50pF, RL = 500Ω
MAX
MIN
MAX
Waveform 3
2.5
0.0
3.0
0.0
ns
Hold time, high or low
An to LE
Waveform 3
4.0
2.5
5.0
3.0
ns
LE pulse width, low
Waveform 3
4.0
4.5
ns
AC WAVEFORMS
Bn, LS, LE,
OEB1, IAREQ
VM
tPLH
Bn, IAMC
An, Bn, LS, LE,
OEB0, IAREQ
VM
VM
VM
VM
th(L)
tsk(o)
th(H)
tsu(H)
tw(L)
VM
VM
VM
tPHZ
VM
An, Bn
VM
VM
tPZH
An
VM
VM
Waveform 4. Output skew
Waveform 3. Data setup and hold times and LE pulse width
OEA
VM
Waveform 2. Propagation delay for data or
output enable to output
tsu(L)
LE
tPLH
VM
An, Bn. IAMC
VM
An, Bn
VM
VM
tPHL
tPHL
Waveform 1. Propagation delay for data or
output enable to output
An, Bn
VM
OEA
VOH -0.3V
VM
VM
tPZL
VM
An
tPLZ
VM
0V
VOL +0.3V
Waveform 5. 3–state output enable time to high level
and output disable time from high level
Waveform 6. 3-state output enable time to low level
and output disable time from low level
Notes to AC waveforms
1. For all waveforms, VM = 1.5V.
2. The shaded areas indicate when the input is permitted to change for predictable output performance.
December 19, 1990
10
Philips Semiconductors FAST Products
Product specification
9-Bit address/data Futurebus transceiver, ADT
74F8965/74F8966
TEST CIRCUITS AND WAVEFORMS
SWITCH POSITION
TEST
SWITCH
tPLZ, tPZL
closed
All other
open
tw
90%
NEGATIVE
PULSE
VCC
10%
VIN
RL
VOUT
AMP (V)
VM
VM
7.0V
PULSE
GENERATOR
90%
10%
tTHL (tf )
tTLH (tr )
tTLH (tr )
tTHL (tf )
Low V
D.U.T.
RT
CL
AMP (V)
RL
90%
POSITIVE
PULSE
VM
VM
10%
Test circuit for 3–state outputs on A port
VCC
90%
10%
tw
Low V
7.0V
Input pulse definition
VIN
RU
VOUT
PULSE
GENERATOR
D.U.T.
RT
CD
INPUT PULSE REQUIREMENTS
family
tTLH
tw
74F amplitude Low V VM rep. rate
A port
3.0V
0.0V
1.5V
1MHz
500ns
2.5ns
2.5ns
B port
3.0V
1.0V
1.5V
1MHz
500ns
4.0ns
4.0ns
Test circuit for outputs on B port
DEFINITIONS:
RL = Load resistor; see AC electrical characteristics for value.
CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value.
RU = Pull up resistor; see AC electrical characteristics for value.
CD = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value.
RT = Termination resistance should be equal to ZOUT of pulse generators.
December 19, 1990
tTHL
11