PHILIPS N74F8961A

Philips Semiconductors FAST Products
Product specification
Octal latched bidirectional Futurebus transceivers
(3-State + open-collector)
FEATURES
• Octal latched transceiver
• Drives heavily loaded backplanes with
equivalent load impedances down to 10Ω
• High drive (100mA) open collector drivers
on B port
• Reduced voltage swing (1 volt) produces
less noise and reduces power consumption
• High speed operation enhances
performance of backplane buses and
facilitates incident wave switching
• Compatible with IEEE futurebus standards
• Built-in precision band-gap reference
provides accurate receiver thresholds and
improved noise immunity
74F8960/74F8961
voltage swing is much less for BTL, so is its
receiver threshold region, therefore noise
margins are excellent.
DESCRIPTION
The 74F8960 and 74F8961 are octal
bidirectional latched transceivers and are
intended to provide the electrical interface to
a high performance wired–OR bus. The B
port inverting drivers are low–capacitance
open collector with controlled ramp and are
designed to sink 100mA from 2 volts. The B
port inverting receivers have a 100 mV
threshold region and a 4ns glitch filter.
BTL offers low power consumption, low
ground bounce, EMI and crosstalk, low
capacitive loading, superior noise margin and
low propagation delays. This results in a high
bandwidth, reliable backplane.
The 74F8960 and 74F8961 A ports have TTL
3–state drivers and TTL receivers with a latch
function. A separate High–level control input
(VX) is provided to limit the A side output
level to a given voltage level (such as 3.3V).
For 5.0V systems, VX is simply tied to VCC.
The B port interfaces to ‘Backplane
Transceiver Logic’ (BTL). BTL features a
reduced (1V to 2V) voltage swing for lower
power consumption and a series diode on
the drivers to reduce capacitive loading.
Incident switching is employed, therefore BTL
propagation delays are short. Although the
The 74F8961 is the non–inverting version of
74F8960.
• Controlled output ramp and multiple GND
pins minimize ground bounce
• Glitch-free power up/down operation
TYPE
TYPICAL PROPAGATION DELAY
TYPICAL SUPPLY CURRENT( TOTAL)
74F8960
6.5ns
80mA
74F8961
6.5ns
80mA
ORDERING INFORMATION
ORDER CODE
COMMERCIAL RANGE
VCC = 5V ±10%, Tamb = 0°C to +70°C
DESCRIPTION
28–pin plastic DIP (300 mil)1
N74F8960N, N748961N
28–pin PLCC1
N74F8960A, N74F8961A
NOTE: Thermal mounting techiques are recommended.
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
74F (U.L.)
HIGH/LOW
DESCRIPTION
LOAD VALUE
HIGH/LOW
A0 – A8
PNP latched inputs
3.5/0.117
70µA/70µA
B0 – B8
Data inputs with threshold circuitry
5.0/0.167
100µA/100µA
OEA
A output enable input (active high)
1.0/0.033
20µA/20µA
OEB0, OEB1
B output enable inputs (active low)
1.0/0.033
20µA/20µA
Latch enable input (active low)
1.0/0.033
20µA/20µA
150/40
3mA/24mA
OC/166.7
OC/100mA
LE
A0 – A7
3–state outputs
B0 – B7
Open collector outputs
NOTES:
1. One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
2. OC = Open collector.
December 19, 1990
1
853-1120 01322
Philips Semiconductors FAST Products
Product specification
Octal latched bidirectional Futurebus transceivers
(3-State + open-collector)
PIN CONFIGURATION
PIN CONFIGURATION PLCC
74F8960
VCC 1
28 LE
27 B0
A0 3
26 B1
25 GND
A1 5
24 B2
A2 6
23 B3
A3 7
22 GND
GND 8
4
24 B2
15
OEB0
A3
23 B3
2
OEA
GND
8
GND 11
VX
PLCC
22 GND
9
18 GND
17 B7
6
7
9
10
12 13
26
7
A5 10
5
B0 B1
27
25 GND
20 B5
16 OEB1
28
6
19 B6
15 OEB0
1
A2
A5 10
14
2
5
A4 9
A7 13
3
A1
A4
A6 12
74F8960
3
GND A0 OEA VCC LE
21 B4
GND 11
LOGIC SYMBOL
74F8960
OEA 2
GND 4
74F8960/74F8961
A0 A1 A2
28
LE
16
OEB1
A3 A4 A5
A6 A7
21 B4
B0 B1 B2 B3 B4 B5
B6 B7
27
19 17
20 B5
19 B6
12
13
14
15
16
17
A6
A7 VX OEB2 OEB1 B7 GND
18
26 24
23
21 20
VCC = Pin 1, VX = Pin 14
GND = Pin 4, 8, 11, 18, 22, 25
PIN CONFIGURATION
PIN CONFIGURATION PLCC
74F8961
74F8961
VCC 1
28 LE
OEA 2
27 B0
A0 3
26 B1
GND 4
74F8961
3
25 GND
A1 5
24 B2
A2 6
23 B3
A3 7
LOGIC SYMBOL
22 GND
GND A0 OEA VCC LE
4
3
2
1
28
27
5
25 GND
A2
6
24 B2
15
OEB0
A3 7
23 B3
2
OEA
A4
8
PLCC
22 GND
GND 8
21 B4
A4 9
20 B5
A5 10
20 B5
A5 10
19 B6
GND 11
19 B6
GND 11
9
7
9
10
12 13
A0 A1 A2 A3 A4 A5
28
LE
16
OEB1
A6 A7
21 B4
18 GND
12
13
A6 12
17 B7
A6
A7 VX OEB2 OEB1 B7 GND
A7 13
16 OEB1
VX 14
15 OEB0
December 19, 1990
6
26
A1
GND
5
B0 B1
14
15
16
17
18
B0 B1 B2
27
26 24
VCC = Pin 1, VX = Pin 14
GND = Pin 4, 8, 11, 18, 22, 25
2
B3 B4 B5
B6 B7
23
19 17
21 20
Philips Semiconductors FAST Products
Product specification
Octal latched bidirectional Futurebus transceivers
(3-State + open-collector)
IEC/IEEE SYMBOL FOR 74F8960
74F8960/74F8961
IEC/IEEE SYMBOL FOR 74F8961
74F8960
74F8961
&
15
15
EN2
28
C1
2
2
EN3
3
2
1D
EN2
16
16
28
&
27
3
C1
EN3
2
1D
27
3
3
5
5
26
6
6
24
7
7
23
9
9
21
10
10
20
11
19
13
17
26
24
23
21
20
11
19
13
17
PIN DESCRIPTION
SYMBOL
PINS
TYPE
A0 – A7
3, 5, 6, 7, 9, 10, 12, 13
I/O
PNP latched input/3–state output (with VX control option)
B0 – B7
27, 26, 24, 23, 21, 20, 19, 17
I/O
Data input with special threshold circuitry to reject noise/ open collector output, high
current drive
OEB0
15
Input
Enables the B outputs when both pins are low
OEB1
16
Input
Enables the A outputs when high
LE
28
Input
Latched when high (a special feature is buillt in for proper enabling times)
VX
14
Input
Clamping voltage keeping VOH from rising above VX (VX = Vcc for normal use)
December 19, 1990
NAME AND FUNCTION
3
Philips Semiconductors FAST Products
Product specification
Octal latched bidirectional Futurebus transceivers
(3-State + open-collector)
74F8960/74F8961
LOGIC DIAGRAM
74F9861
74F9860
OEB0
OEB1
15
OEB0
16
OEB1
16
OEA 2
OEA 2
LE 28
LE 28
A0
15
3
Data
Q
A0
27 B0
3
A1
5
Data
Q
A1
26 B1
5
6
Data
Q
A2
24 B2
6
7
Data
Q
A3
23 B3
7
9
Data
Q
A4
21 B4
9
Data
Q
A5 10
20 B5
Data
Q
A6 12
19 B6
Data
Q
A7 13
17 B7
Data
Data
Data
Data
Data
LE
LE
VCC = Pin 1, VX = Pin 14,
GND = Pin 4, 8, 11, 18, 22, 25
December 19, 1990
Data
Q
24 B2
Q
23 B3
Q
21 B4
Q
20 B5
Q
19 B6
Q
17 B7
LE
LE
A7 13
26 B1
LE
LE
A6 12
Q
LE
LE
A5 10
Data
LE
LE
A4
27 B0
LE
LE
A3
Q
LE
LE
A2
Data
LE
LE
4
Philips Semiconductors FAST Products
Product specification
Octal latched bidirectional Futurebus transceivers
(3-State + open-collector)
74F8960/74F8961
FUNCTION TABLE FOR 74F8960
INPUTS
LATCH
OUTPUTS
OPERATING MODE
An
Bn*
LE
OEA
Bn
L
L
OEB
1
L
An
X
OEB
0
L
STATE
H
H
Z
L
L
X
L
L
L
L
L
Z
H**
X
X
H
L
L
L
Qn
Z
Qn
A 3–state, latched data to B
–
–
L
H
L
L
(1)
(1)
(1)
Feedback: A to B, B to A
–
H
H
H
L
L
H (2)
H
Z(2)
–
L
H
H
L
L
H (2)
L
Z(2)
–
–
H
H
L
L
Qn
Qn
Qn
H
X
L
L
H
X
H
Z
Z
l
X
L
L
H
X
l
Z
Z
X
X
H
L
H
X
Qn
Z
Z
–
H
L
H
H
X
H
H
Z
–
L
L
H
H
H
L
L
Z
–
H
H
H
H
H
Qn
H
Z
–
L
H
H
H
H
Qn
L
Z
H
X
L
L
X
H
H
Z
Z
l
X
L
L
X
H
l
Z
Z
X
X
H
L
X
H
Qn
Z
Z
–
H
L
H
X
H
H
H
Z
–
L
L
H
X
H
L
L
Z
–
H
H
H
X
H
Qn
H
Z
–
L
H
H
X
H
Qn
L
Z
NOTES:
1. H =
2. L =
3. X =
4. – =
5. Z =
6. Qn =
7. (1) =
8. (2) =
9. H**=
10. B* =
A 3–state, data from A to B
Preconditioned latch enabling data transfer from B to A
Latch state to A and B
B and A 3–state
B 3–state, data from B to A
B and A 3–state
B 3–state, data from B to A
High–voltage level
Low–voltage level
Don’t care
Input not externally driven
High impedance (off) state
High or low voltage level one setup time prior to the low–to–high LE transition.
Condition will cause a feedback loop path: A to B and B to A.
The latch must be preconmditioned such that B inputs may assume a high or low level while OEB0 and OEB1 are low and LE is high.
Goes to level of pullup voltage.
Precaution should be taken to insure the B inputs do not float. If they do they are equal to low state.
December 19, 1990
5
Philips Semiconductors FAST Products
Product specification
Octal latched bidirectional Futurebus transceivers
(3-State + open-collector)
74F8960/74F8961
FUNCTION TABLE FOR 74F8961
INPUTS
LATCH
OUTPUTS
OPERATING MODE
An
Bn*
LE
OEA
Bn
L
L
OEB
1
L
An
X
OEB
0
L
STATE
H
H
Z
H**
L
X
L
L
L
L
L
Z
L
X
X
H
L
L
L
Qn
Z
Qn
A 3–state, latched data to B
–
–
L
H
L
L
(1)
(1)
(1)
Feedback: A to B, B to A
–
H
H
H
L
L
H (2)
H
Z(2)
–
L
H
H
L
L
H (2)
L
Z(2)
–
–
H
H
L
L
Qn
Qn
Qn
H
X
L
L
H
X
H
Z
Z
l
X
L
L
H
X
l
Z
Z
X
X
H
L
H
X
Qn
Z
Z
–
H
L
H
H
X
H
H
Z
–
L
L
H
H
H
L
L
Z
–
H
H
H
H
H
Qn
H
Z
–
L
H
H
H
H
Qn
L
Z
H
X
L
L
X
H
H
Z
Z
l
X
L
L
X
H
l
Z
Z
X
X
H
L
X
H
Qn
Z
Z
–
H
L
H
X
H
H
H
Z
–
L
L
H
X
H
L
L
Z
–
H
H
H
X
H
Qn
H
Z
–
L
H
H
X
H
Qn
L
Z
NOTES:
1. H =
2. L =
3. X =
4. – =
5. Z =
6. Qn =
7. (1) =
8. (2) =
9. H**=
10. B* =
A 3–state, data from A to B
Preconditioned latch enabling data transfer from B to A
Latch state to A and B
B and A 3–state
B 3–state, data from B to A
B and A 3–state
B 3–state, data from B to A
High–voltage level
Low–voltage level
Don’t care
Input not externally driven
High impedance (off) state
High or low–voltage level one setup time prior to the low–to–high LE transition.
Condition will cause a feedback loop path: A to B and B to A.
The latch must be preconmditioned such that B inputs may assume a high or low level while OEB0 and OEB1 are low and LE is high.
Goes to level of pullup voltage.
Precaution should be taken to insure the B inputs do not float. If they do they are equal to low state.
December 19, 1990
6
Philips Semiconductors FAST Products
Product specification
Octal latched bidirectional Futurebus transceivers
(3-State + open-collector)
74F8960/74F8961
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free air temperature range.)
SYMBOL
PARAMETER
RATING
UNIT
VCC
Supply voltage
–0.5 to +7.0
V
VX
Threshold control
–0.5 to +7.0
V
VIN
Input voltage
OEB, OEA, LE
–0.5 to +7.0
V
A0 – A7, B0 – B7
–0.5 to +5.5
V
–40 to +5
mA
–0.5 to VCC
V
A0 – A7
48
mA
B0 – B7
200
mA
0 to +70
°C
–65 to +150
°C
IIN
Input current
VOUT
Voltage applied to output in high output state
IOUT
Current applied to output in low output state
Tamb
Operating free air temperature range
Tstg
Storage temperature range
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
MIN
NOM
MAX
UNIT
4.5
5.0
5.5
V
VCC
Supply voltage
VIH
High–level input voltage
Except B0 – B7
2.0
B0 – B7
1.6
VIL
Low–level input voltage
Except B0 – B7
0.8
B0 – B7
1.475
V
IIk
Input clamp current
Except A0 – A7
–18
mA
A0 – A7
–40
mA
V
V
V
IOH
High–level output current
A0 – A7
–3
mA
IOL
Low–level output current
A0 – A7
24
mA
B0 – B7
100
mA
+70
°C
Tamb
Operating free air temperature
range
December 19, 1990
0
7
Philips Semiconductors FAST Products
Product specification
Octal latched bidirectional Futurebus transceivers
(3-State + open-collector)
74F8960/74F8961
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST
LIMITS
CONDITIONS1
UNIT
TYP.
MIN.
2
MAX.
IOH
High–level output current
B0 – B7
VCC = MAX, VIL = MAX, VIH = MIN, VOH = 2.1V
100
µA
IOFF
Power–off output current
B0 – B7
VCC = 0.0V, VIL = MAX, VIH = MIN, VOH = 2.1V
100
µA
VCC
V
High-level output voltage
A74
VCC = MIN,
VOH
VOL
VIK
Low-level output voltage
VIL = MAX, VIH = MIN
IOH = –4mA,
VX =3.13V and 3.47V
A0 – A74
VCC = MIN,
IOL = 20mA, VX = VCC
B0 – B78
VIL = MAX
IOL = 100mA
VIH = MIN
IOL = 4mA
2.5
2.5
V
0.50
V
1.15
V
0.40
V
A0 – A7
VCC = MIN, II = IIK
-0.5
V
Except A0 – A7
VCC = MIN, II = IIK
-1.2
V
Input current at
maximum input voltage
OEBn, OEA, LE
A0–A7, B0 – B7
VCC = MAX, VI = 7.0V
VCC = MAX, VI = 5.5V
100
1
mA
IIH
High–level input current
OEBn, OEA, LE
VCC = MAX, VI = 2.7V
20
VCC = MAX, VI = 2.1V, Bn – An = 0V
100
IIL
Low–level input current
OEBn, OEA, LE
VCC = MAX, VI = 0.5V
–20
B0 – B7
VCC = MAX, VI = 0.3V
–100
µA
µA
µA
µA
II
Input clamp voltage
A0 –
IOH = –3mA, VX =VCC
B0–B7
µA
IOZH + IIH
Off–state output current,
high–level current applied
A0 – A7
VCC = MAX, VO = 2.7V
70
µA
IOZL + IIL
Off–state output current,
low–level voltage applied
A0 – A7
VCC = MAX, VI = 0.5V
–70
µA
IX
High–level control current
IOS
Short circuit output
current3
ICC
Supply current (total)
VCC = MAX, VX = VCC, LE = OEA = OEBn =
2.7V, A0 – A7 = 2.7V, B0 – B7 = 2.0V,
–100
100
µA
VCC = MAX, VX = 3.13 & 3.47V, LE = OEA =
OEBn = A0 – A7 = 2.7V, B0 – B7 = 2.0V,
–10
10
µA
-60
-150
mA
V = MAX, Bn = 1.3V, OEA = 2.0V, OEBn =
74F8960 CC
2.7V
A0–A7
’F8960
only
V = MAX, Bn = 1.8V, OEA = 2.0V, OEBn =
only 74F8961 CC
2.7V
ICCH
VCC = MAX
65
100
mA
ICCL
VCC = MAX, VIL = 0.5V
100
145
mA
75
100
mA
ICCZ
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type
and function table for operating mode.
2. All typical values are at VCC = 5V, Tamb = 25°C.
3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, IOS tests should be performed last.
4. Due to test equipment limitations, actual test conditions are for VIH =1.8v and VIL = 1.3V.
December 19, 1990
8
Philips Semiconductors FAST Products
Product specification
Octal latched bidirectional Futurebus transceivers
(3-State + open-collector)
74F8960/74F8961
AC ELECTRICAL CHARACTERISTICS FOR 74F8960
A PORT LIMITS
Tamb = +25°C
SYMBOL
PARAMETER
TEST
CONDITION
Tamb = 0°C to +70°C
VCC = +5.0V
CL = 50pF, RL = 500Ω
VCC = +5.0V ± 10%
UNIT
CL = 50p, RL = 500Ω
MIN
TYP
MAX
MIN
MAX
Waveform 1, 2
4.5
6.0
6.0
10.0
8.5
13.5
3.5
7.5
9.5
14.5
ns
tPLH
tPHL
Propagation delay
Bn to An
tPZH
tPZL
Output enable time to high or low, OEA
to An
Waveform 4
Waveform 5
8.0
8.5
10.5
11.0
13.5
13.5
7.5
8.5
15.0
16.0
ns
tPHZ
tPLZ
Output enable time from high or low,
OEA to An
Waveform 4
Waveform 5
2.0
2.0
3.5
4.5
6.5
7.0
2.0
2.0
7.0
7.5
ns
B PORT LIMITS
Tamb = +25°C
SYMBOL
PARAMETER
TEST
CONDITION
Tamb = 0°C to +70°C
VCC = +5.0V
CD = 50pF, RU = 9Ω
VCC = +5.0V ± 10%
UNIT
CD = 50pF, RL = 9Ω
MIN
TYP
MAX
MIN
MAX
Waveform 1, 2
3.5
3.5
5.5
5.0
8.0
8.0
2.0
3.0
9.5
9.0
ns
Propagation delay
LE to Bn
Waveform 1, 2
3.5
4.0
5.5
6.5
8.5
9.0
2.5
3.0
9.5
10.5
ns
tPLH
tPHL
Output enable/disable time
OEBn to Bn
Waveform 1, 2
2.5
3.5
4.5
5.5
7.5
8.5
1.5
3.5
8.0
9.0
ns
tTLH
tTHL
Transition time, Bn port
1.3V to 1.7V, 1.7V to 1.3V
Test circuit and
waveforms
0.5
0.5
2.0
2.0
4.5
4.5
0.5
0.5
5.0
6.0
ns
tPLH
tPHL
Propagation delay
An to Bn
tPLH
tPHL
AC SETUP REQUIREMENTS FOR 74F8960
LIMITS
Tamb = +25°C
SYMBOL
PARAMETER
TEST
CONDITION
VCC = +5.0V
CL = 50pF, RL = 500Ω
MIN
TYP
MAX
Tamb = 0°C to +70°C
VCC = +5.0V ± 10%
UNIT
CL = 50pF, RL = 500Ω
MIN
MAX
tsu(H)
tsu(L)
Setup time, high or low
An to LE
Waveform 3
5.0
3.0
5.0
5.0
ns
th(H)
th(L)
Hold time, high or low
An to LE
Waveform 3
0.0
0.0
0.0
0.0
ns
tw(L)
LE pulse width, low
Waveform 3
4.5
5.0
ns
December 19, 1990
9
Philips Semiconductors FAST Products
Product specification
Octal latched bidirectional Futurebus transceivers
(3-State + open-collector)
74F8960/74F8961
AC ELECTRICAL CHARACTERISTICS FOR 74F8961
A PORT LIMITS
Tamb = +25°C
SYMBOL
PARAMETER
TEST
CONDITION
Tamb = 0°C to +70°C
VCC = +5.0V
CL = 50pF, RL = 500Ω
VCC = +5.0V ± 10%
UNIT
CL = 50p, RL = 500Ω
MIN
TYP
MAX
MIN
MAX
Waveform 1, 2
5.5
4.5
8.0
6.0
12.0
9.0
5.5
4.5
12.0
9.0
ns
tPLH
tPHL
Propagation delay
Bn to An
tPZH
tPZL
Output enable time to high or low, OEA
to An
Waveform 4
Waveform 5
8.0
8.5
10.5
11.0
13.5
13.5
7.5
8.0
15.0
15.5
ns
tPHZ
tPLZ
Output enable time from high or low,
OEA to An
Waveform 4
Waveform 5
2.0
2.0
3.5
4.5
6.0
7.0
1.5
2.0
6.5
7.5
ns
B PORT LIMITS
Tamb = +25°C
SYMBOL
PARAMETER
TEST
CONDITION
Tamb = 0°C to +70°C
VCC = +5.0V
CD = 50pF, RU = 9Ω
VCC = +5.0V ± 10%
UNIT
CD = 50pF, RU = 9Ω
MIN
TYP
MAX
MIN
MAX
Waveform 1, 2
3.0
3.0
5.0
4.5
7.0
7.5
2.5
2.5
8.0
8.5
ns
Propagation delay
LE to Bn
Waveform 1, 2
3.5
3.5
5.0
5.0
8.0
8.0
3.0
2.5
9.0
9.0
ns
tPLH
tPHL
Output enable/disable time
OEBn to Bn
Waveform 1, 2
3.0
3.5
4.5
5.5
7.0
9.0
2.5
3.5
8.0
10.0
ns
tTLH
tTHL
Transition time, Bn port
1.3V to 1.7V, 1.7V to 1.3V
Test circuit and
waveforms
0.5
0.5
2.0
2.0
4.5
4.5
0.5
0.5
5.0
4.5
ns
tPLH
tPHL
Propagation delay
An to Bn
tPLH
tPHL
AC SETUP REQUIREMENTS FOR 74F8961
LIMITS
Tamb = +25°C
SYMBOL
PARAMETER
TEST
CONDITION
VCC = +5.0V
CL = 50pF, RL = 500Ω
MIN
TYP
MAX
Tamb = 0°C to +70°C
VCC = +5.0V ± 10%
UNIT
CL = 50pF, RL = 500Ω
MIN
MAX
tsu(H)
tsu(L)
Setup time, high or low
An to LE
Waveform 3
3.5
4.5
4.5
5.0
ns
th(H)
th(L)
Hold time, high or low
An to LE
Waveform 3
0.0
0.0
0.0
0.0
ns
tw(L)
LE pulse width, low
Waveform 3
4.0
5.0
ns
December 19, 1990
10
Philips Semiconductors FAST Products
Product specification
Octal latched bidirectional Futurebus transceivers
(3-State + open-collector)
74F8960/74F8961
AC WAVEFORMS
An, Bn, OEBn
An, Bn, OEBn
VM
tPLH
An, Bn
VM
VM
tPHL
tPHL
VM
VM
VM
VM
Waveform 2. Propagation delay for data to output
VM
VM
VM
th(L)
th(H)
ts(L)
ts(H)
VM
LE
tPLH
VM
An, Bn
Waveform 1. Propagation delay for data to output
An
VM
tw(L)
VM
VM
Waveform 3. Data setup and hold times and LE pulse width
OEA
VM
OEA
VM
tPZH
VOH -0.3V
tPHZ
An
VM
VM
tPZL
VM
tPLZ
VM
An
0V
VOL +0.3V
Waveform 4. 3–state output enable time to high level
and output disable time from high level
Waveform 5. 3-state output enable time to low level
and output disable time from low level
NOTES:
1. For all waveforms, VM = 1.5V.
2. The shaded areas indicate when the input is permitted to change for predictable output performance.
TEST CIRCUITS AND WAVEFORMS
SWITCH POSITION
TEST
SWITCH
tPLZ, tPZL
closed
All other
open
tw
90%
NEGATIVE
PULSE
VCC
10%
VIN
RL
VOUT
AMP (V)
VM
VM
7.0V
PULSE
GENERATOR
90%
10%
tTHL (tf )
tTLH (tr )
tTLH (tr )
tTHL (tf )
Low V
D.U.T.
RT
CL
AMP (V)
RL
VM
VM
10%
Test circuit for 3–state outputs on A port
VCC
90%
90%
POSITIVE
PULSE
10%
tw
Low V
7.0V
Input pulse definition
VIN
RU
VOUT
PULSE
GENERATOR
D.U.T.
RT
CD
INPUT PULSE REQUIREMENTS
family
tTLH
tw
74F amplitude Low V VM rep. rate
A port
3.0V
0.0V
1.5V
1MHz
500ns
2.5ns
2.5ns
B port
3.0V
1.0V
1.5V
1MHz
500ns
4.0ns
4.0ns
Test circuit for outputs on B port
DEFINITIONS:
RL = Load resistor; see AC electrical characteristics for value.
CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value.
RU = Pull up resistor; see AC electrical characteristics for value.
CD = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value.
RT = Termination resistance should be equal to ZOUT of pulse generators.
December 19, 1990
tTHL
11