Download Ultra37000 CPLD Family Datasheet

Ultra37000 CPLD Family
5 V and 3.3 V ISR™
High Performance CPLDs
5 V and 3.3 V ISR™ High Performance CPLDs
General Description
■
In-System Reprogrammable™ (ISR™) CMOS CPLDs
❐ JTAG interface for reconfigurability
❐ Design changes do not cause pinout changes
❐ Design changes do not cause timing changes
■
High Density
❐ 32 to 512 macrocells
❐ 32 to 264 I/O pins
❐ 5 dedicated inputs including 4 clock pins
■
Simple Timing Model
❐ No fanout delays
❐ No expander delays
❐ No dedicated vs. I/O pin delays
❐ No additional delay through PIM
❐ No penalty for using full 16 product terms
❐ No delay for steering or sharing product terms
■
3.3 V and 5 V Versions
■
PCI Compatible [1]
■
Programmable Bus-hold Capabilities on All I/Os
■
Intelligent Product Term Allocator Provides
❐ 0 to 16 product terms to any macrocell
❐ Product term steering on an individual basis
❐ Product term sharing among local macrocells
■
Flexible Clocking
❐ 4 synchronous clocks per device
❐ Product term clocking
❐ Clock polarity control per logic block
■
Consistent Package and Pinout Offering across All Densities
❐ Simplifies design migration
❐ Same pinout for 3.3 V and 5 V devices
■
Packages
❐ 44 to 256 pins in PLCC, PQFP, TQFP, and Fine-Pitch BGA
Packages
❐ Pb-free packages available
The Ultra37000™ family of CMOS CPLDs provides a range of
high density programmable logic solutions with unparalleled
system performance. The Ultra37000 family is designed to bring
the flexibility, ease of use, and performance of the 22 V10 to high
density CPLDs. The architecture is based on a number of logic
blocks that are connected by a Programmable Interconnect
Matrix (PIM). Each logic block features its own product term
array, product term allocator, and 16 macrocells. The PIM
distributes signals from the logic block outputs and all input pins
to the logic block inputs.
All the Ultra37000 devices are electrically erasable and
In-System Reprogrammable (ISR), which simplifies both design
and manufacturing flows, thereby reducing costs. The ISR
feature provides the ability to reconfigure the devices without
having design changes cause pinout or timing changes. The
Cypress ISR function is implemented through a JTAG-compliant
serial interface. Data is shifted in and out through the TDI and
TDO pins, respectively. Because of the superior routability and
simple timing model of the Ultra37000 devices, ISR allows users
to change existing logic designs while simultaneously fixing
pinout assignments and maintaining system performance.
The entire family features JTAG for ISR and boundary scan, and
is compatible with the PCI Local Bus specification, meeting the
electrical and timing requirements. The Ultra37000 family
features user programmable bus-hold capabilities on all I/Os.
Ultra37000 5 V Devices
The Ultra37000 devices operate with a 5 V supply and can
support 5 V or 3.3 V I/O levels. VCCO connections provide the
capability of interfacing to either a 5 V or 3.3 V bus. By
connecting the VCCO pins to 5 V the user insures 5V TTL levels
on the outputs. If VCCO is connected to 3.3 V the output levels
meet 3.3 V JEDEC standard CMOS levels and are 5 V tolerant.
These devices require 5 V ISR programming.
Ultra37000V 3.3 V Devices
Devices operating with a 3.3 V supply require 3.3 V on all VCCO
pins, reducing the device’s power consumption. These devices
support 3.3 V JEDEC standard CMOS output levels, and are
5V-tolerant. These devices allow 3.3 V ISR programming.
Note
1. Due to the 5 V tolerant nature of 3.3 V device I/Os, the I/Os are not clamped to VCC, PCI VIH = 2 V.
Cypress Semiconductor Corporation
Document Number: 38-03007 Rev. *I
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 23, 2012
"Not Recommended for New Design"
Features
Ultra37000 CPLD Family
Logic Block Diagrams ...................................................... 3
Selection Guide ................................................................ 6
5 V Selection Guide ..................................................... 6
3.3 V Selection Guide .................................................. 7
Pin Configurations ........................................................... 8
Architecture Overview of Ultra37000 Family ............... 13
Programmable Interconnect Matrix ........................... 13
Logic Block ................................................................ 13
Product Term Allocator .............................................. 14
Ultra37000 Macrocell ................................................ 14
Clocking ..................................................................... 16
Timing Model ............................................................. 16
JTAG and PCI Standards ............................................... 17
PCI Compliance ........................................................ 17
IEEE 1149.1-compliant JTAG ................................... 17
Development Software Support .................................... 17
Warp .......................................................................... 17
Warp Professional™ ................................................. 17
Warp Enterprise™ ..................................................... 17
Third-Party Software ................................................. 17
Programming ............................................................. 17
Third-Party Programmers .......................................... 18
5 V Device Maximum Ratings ........................................ 19
Operating Range ............................................................. 19
5 V Device Electrical Characteristics ............................ 19
Inductance ....................................................................... 20
Capacitance .................................................................... 20
Document Number: 38-03007 Rev. *I
Endurance Characteristics ............................................ 20
3.3 V Device Maximum Ratings ..................................... 21
Operating Range ............................................................. 21
3.3 V Device Electrical Characteristics ......................... 21
Inductance ....................................................................... 22
Capacitance .................................................................... 22
Endurance Characteristics ............................................ 22
AC Test Loads and Waveforms ..................................... 23
Switching Characteristics .............................................. 25
Switching Characteristics .............................................. 27
Switching Waveforms .................................................... 30
Power Consumption ....................................................... 34
Typical 5 V Power Consumption ............................... 34
Typical 3.3 V Power Consumption ............................ 37
Ordering Information ...................................................... 40
5 V Ordering Information ........................................... 40
3.3 V Ordering Information ........................................ 40
Ordering Code Definitions ......................................... 41
Package Diagrams .......................................................... 42
Acronyms ........................................................................ 45
Document Conventions ................................................. 45
Units of Measure ....................................................... 45
Document History Page ................................................. 46
Sales, Solutions, and Legal Information ...................... 50
Worldwide Sales and Design Support ....................... 50
Products .................................................................... 50
PSoC Solutions ......................................................... 50
Page 2 of 50
"Not Recommended for New Design"
Contents
Ultra37000 CPLD Family
Logic Block Diagrams
CY37032/CY37032V
Clock/
Input Input
TDI
TCK
TMS
4
1
36
LOGIC
BLOCK
A
I/O0I/O15
36
PIM
16
16
16
LOGIC
BLOCK
B
16
CY37064/CY37064V
Input
Clock/
Input
4
1
4
4
I/O0-I/O15
LOGIC
BLOCK
A
16 I/Os
LOGIC
BLOCK
B
I/O16-I/O31
32
TDI
TCK
TMS
JTAG Tap
Controller
36
36
16
16
36
16 I/Os
16 I/Os
I/O16I/O31
"Not Recommended for New Design"
16 I/Os
TDO
JTAGEN
4
4
JTAG Tap
Controller
16
PIM
LOGIC
BLOCK
D
16 I/Os
LOGIC
BLOCK
C
16 I/Os
I/O48-I/O63
36
16
I/O32-I/O47
32
TDO
Document Number: 38-03007 Rev. *I
Page 3 of 50
Ultra37000 CPLD Family
Logic Block Diagrams (continued)
TDI
CLOCK
INPUTS INPUTS
1
4
I/O16–I/O31
I/O32–I/O47
I/O28–I/O63
16 I/Os
LOGIC
BLOCK
36
A
16 I/Os
LOGIC
BLOCK
B
16 I/Os
LOGIC
BLOCK
C
16 I/Os
36
PIM
16
LOGIC
BLOCK
D
36
36
16
16
36
36
16
16
36
36
16
16
16 I/Os
LOGIC
BLOCK
16 I/Os
LOGIC
BLOCK
16 I/Os
LOGIC
BLOCK
16 I/Os
G
I/O112–I/O127
I/O96–I/O111
I/O80–I/O95
F
I/O64–I/O79
64
CY37192/CY37192V
Input
1
Clock/
Input
4
4
4
JTAG Tap
Controller
LOGIC
BLOCK
E
TDO
JTAGEN
H
16
64
TDI
TCK
TMS
Controller
TMS
4
INPUT/CLOCK
MACROCELLS
4
INPUT
MACROCELL
I/O0–I/O15
JTAG Tap
TCK
"Not Recommended for New Design"
CY37128/CY37128V
10 I/Os
I/O0–I/O9
LOGIC
BLOCK
A
10 I/Os
I/O10–I/O19
LOGIC
BLOCK
B
10 I/Os
I/O20–I/O29
LOGIC
BLOCK
C
10 I/Os
I/O30–I/O39
LOGIC
BLOCK
D
10 I/Os
I/O40–I/O49
LOGIC
BLOCK
E
10 I/Os
I/O50–I/O59
LOGIC
BLOCK
F
60
36
36
16
16
36
36
16
16
36
36
16
16
36
16
PIM
36
16
36
36
16
16
36
36
16
16
LOGIC
BLOCK
L
10 I/Os
I/O110–I/O119
LOGIC
BLOCK
K
10 I/Os
I/O100–I/O109
LOGIC
BLOCK
J
10 I/Os
I/O90–I/O99
LOGIC
BLOCK
I
10 I/Os
I/O80–I/O89
LOGIC
BLOCK
H
10 I/Os
I/O70–I/O79
LOGIC
BLOCK
G
10 I/Os
I/O60–I/O69
60
TDO
Document Number: 38-03007 Rev. *I
Page 4 of 50
Ultra37000 CPLD Family
Logic Block Diagrams (continued)
Clock/
Input Input
CY37256/CY37256V
1
4
12 I/Os
I/O0I/O11
12 I/Os
I/O12I/O23
LOGIC
BLOCK
B
12 I/Os
I/O24I/O35
LOGIC
BLOCK
C
12 I/Os
I/O36I/O47
LOGIC
BLOCK
D
12 I/Os
I/O48I/O59
LOGIC
BLOCK
E
12 I/Os
I/O60I/O71
LOGIC
BLOCK
F
12 I/Os
I/O72I/O83
LOGIC
BLOCK
G
12 I/Os
LOGIC
BLOCK
H
I/O84I/O95
TDI
TCK
TMS
JTAG Tap
Controller
TDO
Document Number: 38-03007 Rev. *I
96
36
36
16
16
36
36
16
16
36
36
16
16
36
36
16
16
36
PIM
36
16
16
36
36
16
16
36
36
16
16
36
36
16
16
LOGIC
BLOCK
P
12 I/Os
I/O180I/O191
LOGIC
BLOCK
O
12 I/Os
I/O168I/O179
LOGIC
BLOCK
N
12 I/Os
I/O156I/O167
LOGIC
BLOCK
M
12 I/Os
I/O144I/O155
LOGIC
BLOCK
L
12 I/Os
I/O132I/O143
LOGIC
BLOCK
K
12 I/Os
I/O120I/O131
LOGIC
BLOCK
J
12 I/Os
I/O108I/O119
LOGIC
BLOCK
I
12 I/Os
I/O96I/O107
"Not Recommended for New Design"
4
4
LOGIC
BLOCK
A
96
Page 5 of 50
Ultra37000 CPLD Family
Selection Guide
5 V Selection Guide
Table 1. General Information
Device
Macrocells
Dedicated
Inputs
I/O Pins
Speed (tPD)
Speed (fMAX)
CY37032
32
5
32
6
200
CY37064
64
5
32/64
6
200
CY37128
128
5
64/128
6.5
167
CY37192
192
5
120
7.5
154
CY37256
256
5
128/160/192
7.5
154
200
167
154
125
100
X
X
X
X
Table 2. Speed Bins
CY37064
X
CY37128
X
X
83
X
CY37192
X
X
CY37256
X
X
Table 3. Device-Package Offering and I/O Count
Device
44-pin TQFP
44-pin PLCC
CY37032
37
37
CY37064
37
37
CY37128
100-pin TQFP
160-pin TQFP
69
69
133
CY37192
125
CY37256
133
Document Number: 38-03007 Rev. *I
Page 6 of 50
"Not Recommended for New Design"
Device
CY37032
Ultra37000 CPLD Family
3.3 V Selection Guide
Table 4. General Information
Device
Macrocells
Dedicated
Inputs
CY37032V
32
5
32
8.5
143
CY37064V
64
5
32/64
8.5
143
I/O Pins
Speed (tPD)
Speed (fMAX)
CY37128V
128
5
64/80/128
10
125
CY37192V
192
5
120
12
100
CY37256V
256
5
128/160/192
12
100
125
100
83
66
Table 5. Speed Bins
143
X
CY37064V
X
CY37128V
X
X
X
X
CY37192V
X
X
CY37256V
X
X
"Not Recommended for New Design"
Device
CY37032V
Table 6. Device-Package Offering and I/O Count
Device
44-pin TQFP
CY37032V
37
CY37064V
37
CY37128V
100-pin TQFP
160-pin TQFP
69
69
133
CY37192V
125
CY37256V
133
Document Number: 38-03007 Rev. *I
256-ball FBGA
197
Page 7 of 50
Ultra37000 CPLD Family
Pin Configurations
The Pin Configurations are as follows. [2]
I/O29
I/O28
44 43 42 41 40 39 38 37 36 35 34
33
32
2
3
31
4
30
5
29
6
28
27
7
1
I/O5/TCK
I/O6
I/O 7
CLK2/I0
JTAGEN
GND
CLK0/I 1
I/O8
I/O9
I/O10
CLK3/I2
I/O23
I/O22
I/O21
I/O19 /TDO
I/O20
I/O12
I/O13 /TMS
I/O14
I/O15
I/O11
VCC
GND
I/O16
I/O17
I/O18
26
8
9
25
10
24
11
23
12 13 14 15 16 17 18 19 20 21 22
I/O27 /TDI
I/O26
I/O25
I/O24
CLK1/I 4
GND
I3
"Not Recommended for New Design"
I/O31
I/O30
I/O1
I/O 0
GND
VCCO
I/O2
I/O4
I/O3
Figure 1. 44-pin TQFP pinout (Top View)
I/O28
I/O29
I/O31
I/O30
I/O 1
I/O 0
GND
VCCO
I/O 2
I/O 4
I/O 3
Figure 2. 44-pin PLCC pinout (Top View)
6 5 4 3 2 1 44 43 42 41 40
I/O27 /TDI
I/O26
I/O25
I/O24
CLK1/I 4
GND
I3
CLK3/I2
I/O23
I/O22
I/O21
I/O19 /TDO
I/O20
39
38
37
36
35
34
33
32
31
30
29
18 19 20 21 22 23 24 25 26 27 28
VCC
GND
I/O16
I/O17
I/O18
7
8
9
10
11
12
13
14
15
16
17
I/O12
I/O /TMS
13
I/O14
I/O15
I/O 5/TCK
I/O6
I/O7
CLK2/I0
JTAGEN
GND
CLK0/I 1
I/O8
I/O9
I/O10
I/O 11
Note
2. For 3.3 V versions (Ultra37000V), VCCO = VCC.
Document Number: 38-03007 Rev. *I
Page 8 of 50
Ultra37000 CPLD Family
Pin Configurations (continued)
The Pin Configurations are as follows. [2]
NC
56
GND
57
I/O
58
I/O
59
I/O
I/O
61
I/O 60
62
I/O
I/O 63
I/O
VCC
N/C
GND
NC
2
1
I/O 0
VCCO
I/O
I/O
5
6
7
4
3
I/O
I/O
I/O
I/O
I/O
VCCO
NC
Figure 3. 100-pin TQFP pinout (Top View)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
GND
I/O 8
I/O 9
I/O 10
1
75
TDI
2
74
VCCO
3
73
I/O 55
4
72
I/O 54
5
71
I/O 53
I/O 11
6
70
I/O 52
I/O 12
7
69
I/O 51
I/O 13
8
68
I/O 50
I/O 14
9
I/O 15
67
10
66
CLK0 /I 0
11
VCCO
65
12
N/C
64
13
63
14
62
GND
CLK 1 /I 1
I/O 49
I/O 48
CLK 3 /I 4
GND
NC
VCCO
CLK 2 /I 3
15
I/O16
61
16
60
I/ O47
I/O17
17
59
I/O 46
I/O18
18
58
I/O 45
I/O19
19
I/O20
57
I/O 44
20
I/O21
56
21
55
I/O22
22
54
I/O23
23
53
VCCO
24
52
NC
25
51
"Not Recommended for New Design"
TCK
I/O 43
I/O 42
I/O 41
I/O 40
GND
NC
TDO
VCCO
I/O 38
I/O 39
I/O 35
I/O 36
I/O 37
I/O 33
I/O 34
GND
VCC [3 ]
I/O 32
NC
I2
VCCO
I/O 30
I/O 31
I/O 28
I/O 29
I/O 26
I/O 27
I/O 24
I/O 25
TMS
GND
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Note
3. This pin is a N/C, but Cypress recommends that you connect it to VCC to ensure future compatibility.
Document Number: 38-03007 Rev. *I
Page 9 of 50
Ultra37000 CPLD Family
Pin Configurations (continued)
The Pin Configurations are as follows. [2]
Figure 4. 160-pin TQFP pinout (Top View)
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
VCCO
I/O15
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
I/O8
GND
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
VCCO
GND
VCC
JTAGEN
I/O127
I/O126
I/O125
I/O124
I/O123
I/O122
I/O121
I/O120
GND
I/O119
I/O118
I/O117
I/O116
I/O115
I/O114
I/O113
I/O112
GND
For CY37128(V) and CY37256(V)
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
VCCO
I/O111
I/O110
I/O109
I/O108 /TDI
I/O107
I/O106
I/O105
I/O104
GND
I/O103
I/O102
I/O101
I/O100
I/O99
I/O98
I/O97
I/O96
CLK3/I4
GND
VCCO
CLK2/I3
I/O95
I/O94
I/O93
I/O92
I/O91
I/O90
I/O89
I/O88
GND
I/O87
I/O86
I/O85
I/O84
I/O83
I/O82
I/O81
I/O80
GND
GND
I/O48
I/O49
I/O50
I/O51
I/O52/TMS
I/O53
I/O54
I/O55
GND
I/O56
I/O57
I/O58
I/O59
I/O60
I/O61
I/O62
I/O63
I2
VCCO
GND
VCC
I/O64
I/O65
I/O66
I/O67
I/O68
I/O69
I/O70
I/O71
GND
I/O72
I/O73
I/O74
I/O75
I/O76/TDO
I/O77
I/O78
I/O79
VCCO
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
I/O18
I/O19
I/O20/TCK
I/O21
I/O22
I/O23
GND
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
CLK0/I0
VCCO
GND
CLK1/I1
I/O32
I/O33
I/O34
I/O35
I/O36
I/O37
I/O38
I/O39
GND
I/O40
I/O41
I/O42
I/O43
I/O44
I/O45
I/O46
I/O47
VCCO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Document Number: 38-03007 Rev. *I
Page 10 of 50
"Not Recommended for New Design"
GND
I/O16
I/O17
Ultra37000 CPLD Family
Pin Configurations (continued)
The Pin Configurations are as follows. [2]
Figure 5. 160-pin TQFP pinout (Top View)
GND
NC
I/O16
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
VCCO
I/O104
83
82
81
I/O75
NC
GND
I/O103
I/O102
TDI
I/O101
I/O100
I/O99
I/O98
GND
I/O97
I/O96
I/O95
I/O94
I/O93
I/O92
I/O91
I/O90
CLK3/I4
GND
VCCO
CLK2/I3
I/O89
I/O88
I/O87
I/O86
I/O85
I/O84
I/O83
I/O82
GND
I/O81
I/O80
I/O79
I/O78
I/O77
I/O76
Document Number: 38-03007 Rev. *I
TDO
I/O72
I/O73
I/O74
VCCO
TMS
I/O49
I/O50
I/O51
GND
I/O52
I/O53
I/O54
I/O55
I/O56
I/O57
I/O58
I/O59
I2
VCCO
GND
VCC
I/O60
I/O61
I/O62
I/O63
I/O64
I/O65
I/O66
I/O67
GND
I/O68
I/O69
I/O70
I/O71
GND
NC
I/O46
I/O47
I/O48
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
I/O17
I/O18
TCK
I/O19
I/O20
I/O21
GND
I/O22
I/O23
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
CLK0/I0
VCCO
GND
CLK1/I1
I/O30
I/O31
I/O32
I/O33
I/O34
I/O35
I/O36
I/O37
GND
I/O38
I/O39
I/O40
I/O41
I/O42
I/O43
I/O44
I/O45
VCCO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Page 11 of 50
"Not Recommended for New Design"
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
VCCO
I/O15
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
I/O8
GND
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
VCCO
GND
VCC
NC
I/O119
I/O118
I/O117
I/O116
I/O115
I/O114
I/O113
I/O112
GND
I/O111
I/O110
I/O109
I/O108
I/O107
I/O106
I/O105
NC
GND
For CY37192(V)
Ultra37000 CPLD Family
Pin Configurations (continued)
The Pin Configurations are as follows. [2]
Figure 6. 256-ball FBGA pinout (Top View)
2
3
4
5
6
8
9
10
11
12
13
14
15
16
A
GND GND I/O26 I/O24 I/O20
B
GND I/O27 I/O25 I/O23 I/O19 I/O15 I/O10 GND GND I/O185 I/O181 I/O176 I/O171 I/O166 I/O165 GND
C
I/O29 I/O28
D
I/O32 I/O31 I/O30
NC
VCC
7
I/O22 I/O18 I/O14
I/O11 GND GND I/O186 VCC I/O177 I/O172 I/O167 GND GND
I/O9
I/O4 I/O191 I/O184 I/O180 I/O175 I/O170
I/O17 I/O13
I/O8
I/O3 I/O190 I/O183 I/O179 I/O174 I/O169 I/O160 I/O161 I/O162
E
I/O35 I/O34 I/O33 I/O21 I/O16 I/O12
I/O7
I/O2 I/O189 VCC I/O178 I/O173 I/O168 I/O157 I/O158 I/O159
F
VCC
I/O38 I/O37 I/O36
TCK
VCC
I/O6
I/O1 I/O188 I/O182 VCC
G
I/O43 I/O42 I/O41 I/O40
VCC
I/O39
I/O5
I/O0 I/O187 I/O148 I/O149 CLK3 I/O150 I/O151 I/O152 I/O153
/ I4
H
GND GND I/O47 I/O46 CLK0 I/O45 I/O44 GND GND I/O144 I/O145 CLK2 I/O146 I/O147 GND GND
/ I0
/ I3
J
GND GND I/O51 I/O50
K
I/O57 I/O56 I/O55 I/O54 CLK1 I/O53 I/O52 I/O91 I/O96 I/O101 I/O135 VCC I/O136 I/O137 I/O138 I/O139
/ I1
L
VCC
M
I/O63 I/O62 I/O61 I/O72 I/O77 I/O82
N
I/O66 I/O65 I/O64 I/O73 I/O78 I/O83 I/O87 I/O94 I/O99 I/O104 I/O109 I/O113
P
I/O68 I/O67
R
GND I/O69 I/O70 I/O75 I/O80 I/O85 I/O89 GND GND I/O106 I/O111 I/O115 I/O119 I/O121 I/O123 GND
T
GND GND I/O71 I/O76 I/O81
NC
NC
I/O60 I/O59 I/O58 TMS
NC
I/O49 I/O48 GND GND I/O140 I/O141
VCC
I/O86 I/O92 I/O97 I/O102 VCC
VCC
Document Number: 38-03007 Rev. *I
I/O163 I/O164
TDI I/O154 I/O155 I/O156 VCC
I2
I/O142 I/O143 GND GND
TDO I/O132 I/O133 I/O134 VCC
I/O93 I/O98 I/O103 I/O108 I/O112 I/O117 I/O129 I/O130 I/O131
NC
I/O74 I/O79 I/O84 I/O88 I/O95 I/O100 I/O105 I/O110 I/O114 I/O118
VCC
NC
I/O126 I/O127 I/O128
NC
I/O124 I/O125
I/O90 GND GND I/O107 VCC I/O116 I/O120 I/O122 GND GND
Page 12 of 50
"Not Recommended for New Design"
1
Ultra37000 CPLD Family
Programmable Interconnect Matrix
The PIM consists of a completely global routing matrix for signals
from I/O pins and feedbacks from the logic blocks. The PIM
provides extremely robust interconnection to avoid fitting and
density limitations.
The inputs to the PIM consist of all I/O and dedicated input pins
and all macrocell feedbacks from within the logic blocks. The
number of PIM inputs increases with pin count and the number
of logic blocks. The outputs from the PIM are signals routed to
the appropriate logic blocks. Each logic block receives 36 inputs
from the PIM and their complements, allowing for 32-bit
operations to be implemented in a single pass through the
device. The wide number of inputs to the logic block also
improves the routing capacity of the Ultra37000 family.
An important feature of the PIM is its simple timing. The
propagation delay through the PIM is accounted for in the timing
specifications for each device. There is no additional delay for
traveling through the PIM. In fact, all inputs travel through the
PIM. As a result, there are no route-dependent timing
parameters on the Ultra37000 devices. The worst-case PIM
delays are incorporated in all appropriate Ultra37000
specifications.
Routing signals through the PIM is completely invisible to the
user. All routing is accomplished by software — no hand routing
is necessary. Warp and third-party development packages
automatically route designs for the Ultra37000 family in a matter
of minutes. Finally, the rich routing resources of the Ultra37000
family accommodate last minute logic changes while maintaining
fixed pin assignments.
Logic Block
The logic block is the basic building block of the Ultra37000
architecture. It consists of a product term array, an intelligent
product-term allocator, 16 macrocells, and a number of I/O cells.
The number of I/O cells varies depending on the device used.
Refer to Figure 7 for the block diagram.
Product Term Array
Each logic block features a 72 × 87 programmable product term
array. This array accepts 36 inputs from the PIM, which originate
from macrocell feedbacks and device pins. Active LOW and
active HIGH versions of each of these inputs are generated to
create the full 72-input field. The 87 product terms in the array
can be created from any of the 72 inputs.
Of the 87 product terms, 80 are for general-purpose use for the
16 macrocells in the logic block. Four of the remaining seven
product terms in the logic block are output enable (OE) product
terms. Each of the OE product terms controls up to eight of the
16 macrocells and is selectable on an individual macrocell basis.
In other words, each I/O cell can select between one of two OE
product terms to control the output buffer. The first two of these
four OE product terms are available to the upper half of the I/O
macrocells in a logic block. The other two OE product terms are
available to the lower half of the I/O macrocells in a logic block.
The next two product terms in each logic block are dedicated
asynchronous set and asynchronous reset product terms. The
final product term is the product term clock. The set, reset, OE
and product term clock have polarity control to realize OR
functions in a single pass through the array.
Figure 7. Logic Block with 50% Buried Macrocells
2
3
016
PRODUCT
TERMS
7
016
PRODUCT
TERMS
FROM
PIM
36
72 x 87
PRODUCT TERM
ARRAY
80
PRODUCT
TERMS
016
16
MACROCELL
1
I/O
CELL
0
to cells
2, 4, 6 8, 10, 12
PRODUCT
TERM
ALLOCATOR
016
TO
PIM
MACROCELL
0
2
PRODUCT
TERMS
MACROCELL
14
I/O
CELL
14
MACROCELL
15
8
Document Number: 38-03007 Rev. *I
Page 13 of 50
"Not Recommended for New Design"
Architecture Overview of Ultra37000 Family
Ultra37000 CPLD Family
Each logic block can operate in high speed mode for critical path
performance, or in low power mode for power conservation. The
logic block mode is set by the user on a logic block by logic block
basis.
Product Term Allocator
Through the product term allocator, software automatically
distributes product terms among the 16 macrocells in the logic
block as needed. A total of 80 product terms are available from
the local product term array. The product term allocator provides
two important capabilities without affecting performance: product
term steering and product term sharing.
Product Term Steering
Product term steering is the process of assigning product terms
to macrocells as needed. For example, if one macrocell requires
ten product terms while another needs just three, the product
term allocator will “steer” ten product terms to one macrocell and
three to the other. On Ultra37000 devices, product terms are
steered on an individual basis. Any number between 0 and 16
product terms can be steered to any macrocell. Note that 0
product terms is useful in cases where a particular macrocell is
unused or used as an input register.
Product Term Sharing
Product term sharing is the process of using the same product
term among multiple macrocells. For example, if more than one
output has one or more product terms in its equation that are
common to other outputs, those product terms are only
programmed once. The Ultra37000 product term allocator allows
sharing across groups of four output macrocells in a variable
fashion. The software automatically takes advantage of this
capability—the user does not have to intervene.
Note that neither product term sharing nor product term steering
have any effect on the speed of the product. All worst-case
steering and sharing configurations are incorporated in the
timing specifications for the Ultra37000 devices.
Ultra37000 Macrocell
Within each logic block there are 16 macrocells. Macrocells can
either be I/O Macrocells, which include an I/O Cell which is
associated with an I/O pin, or buried Macrocells, which do not
connect to an I/O. The combination of I/O Macrocells and buried
Macrocells varies from device to device.
Buried Macrocell
Figure 8 displays the architecture of buried macrocells. The
buried macrocell features a register that can be configured as
combinatorial, a D flip-flop, a T flip-flop, or a level-triggered latch.
Document Number: 38-03007 Rev. *I
The register can be asynchronously set or asynchronously reset
at the logic block level with the separate set and reset product
terms. Each of these product terms features programmable
polarity. This allows the registers to be set or reset based on an
AND expression or an OR expression.
Clocking of the register is very flexible. Four global synchronous
clocks and a product term clock are available to clock the
register. Furthermore, each clock features programmable
polarity so that registers can be triggered on falling and rising
edges (see Clocking on page 16). Clock polarity is chosen at the
logic block level.
The buried macrocell also supports input register capability. The
buried macrocell can be configured to act as an input register
(D-type or latch) whose input comes from the I/O pin associated
with the neighboring macrocell. The output of all buried
macrocells is sent directly to the PIM regardless of its
configuration.
I/O Macrocell
Figure 8 on page 15 illustrates the architecture of the I/O
macrocell. The I/O macrocell supports the same functions as the
buried macrocell with the addition of I/O capability. At the output
of the macrocell, a polarity control mux is available to select
active LOW or active HIGH signals. This has the added
advantage of allowing significant logic reduction to occur in many
applications.
The Ultra37000 macrocell features a feedback path to the PIM
separate from the I/O pin input path. This means that if the
macrocell is buried (fed back internally only), the associated I/O
pin can still be used as an input.
Bus Hold Capabilities on all I/Os
Bus-hold, which is an improved version of the popular internal
pull-up resistor, is a weak latch connected to the pin that does
not degrade the device’s performance. As a latch, bus-hold
maintains the last state of a pin when the pin is placed in a high
impedance state, thus reducing system noise in bus-interface
applications. Bus-hold additionally allows unused device pins to
remain unconnected on the board, which is particularly useful
during prototyping as designers can route new signals to the
device without cutting trace connections to VCC or GND. For
more information, see the application note Understanding
Bus-Hold — A Feature of Cypress CPLDs.
Programmable Slew Rate Control
Each output has a programmable configuration bit, which sets
the output slew rate to fast or slow. For designs concerned with
meeting FCC emissions standards the slow edge provides for
lower system noise. For designs requiring very high performance
the fast edge rate provides maximum system performance.
Page 14 of 50
"Not Recommended for New Design"
Low Power Option
Ultra37000 CPLD Family
Figure 8. I/O and Buried Macrocells
I/O MACROCELL
FROM PTM
FAST
0
1
016
PRODUCT
TERMS
SLEW
SLOW
C25
0
1
2
3
C26
0
P
D/T/L
O
O
1
Q
1
R
C4
4
“0”
“1”
DECODE
C0 C1 C24
I/O CELL
O
0
0
1
2
3
O
C6 C5
1
0
C2 C3
BURIED MACROCELL
FROM PTM
016
PRODUCT
TERMS
"Not Recommended for New Design"
0
1
C25
0
0
O
1
0
1
2
3
P
D/T/L
O
1
Q
C7
Q
R
4
DECODE
C0 C1 C24
1
0
C2 C3
FEEDBACK TO PIM
FEEDBACK TO PIM
FEEDBACK TO PIM
ASYNCHRONOUS
BLOCK RESET
4 SYNCHRONOUS CLOCKS (CLK0,CLK1,CLK2,CLK3)
ASYNCHRONOUS
1 ASYNCHRONOUS CLOCK(PTCLK)
BLOCK PRESET
OE0 OE1
Figure 9. Input Macrocell
INPUT PIN
FROM CLOCK
POLARITY MUXES
0
1
2
3
D
Q
D
Q
0
1
2
3
O
TO PIM
O
C12 C13
C10 C11
D
Q
LE
Document Number: 38-03007 Rev. *I
Page 15 of 50
Ultra37000 CPLD Family
Figure 10. Input/Clock Macrocell
0
TO CLOCK MUX ON
ALL INPUT MACROCELLS
O
1
INPUT/CLOCK PIN
C12
0
O
1
FROM CLOCK
POLARITY INPUT
CLOCK PINS
D
0
1
2
3
Q
D
C13, C14, C15
0
1
2
3
Q
TO CLOCK MUX
IN EACH
LOGIC BLOCK
O
TO PIM
OR C16
CLOCK POLARITY MUX
ONE PER LOGIC BLOCK
FOR EACH CLOCK INPUT
O
C10C11
C8 C9
D
Q
Clocking
Each I/O and buried macrocell has access to four synchronous
clocks (CLK0, CLK1, CLK2 and CLK3) and an asynchronous
product term clock PTCLK. Each input macrocell has access to
all four synchronous clocks.
Dedicated Inputs/Clocks
Five pins on each member of the Ultra37000 family are
designated as input-only. There are two types of dedicated
inputs on Ultra37000 devices: input pins and input/clock pins.
Figure 9 on page 15 illustrates the architecture for input pins.
Four input options are available for the user: combinatorial,
registered, double-registered, or latched. If a registered or
latched option is selected, any one of the input clocks can be
selected for control.
Figure 10 illustrates the architecture for the input/clock pins.
Similar to the input pins, input/clock pins can be combinatorial,
registered, double-registered, or latched. In addition, these pins
feed the clocking structures throughout the device. The clock
path at the input has user-configurable polarity.
time is also 4.0 ns. These measurements are for any output and
synchronous clock, regardless of the logic used.
The Ultra37000 features:
■
No fanout delays
■
No expander delays
■
No dedicated vs. I/O pin delays
■
No additional delay through PIM
■
No penalty for using 0–16 product terms
■
No added delay for steering product terms
■
No added delay for sharing product terms
■
No routing delays
■
No output bypass delays
The simple timing model of the Ultra37000 family eliminates
unexpected performance penalties.
Figure 11. Timing Model for CY37128
Product Term Clocking
In addition to the four synchronous clocks, the Ultra37000 family
also has a product term clock for asynchronous clocking. Each
logic block has an independent product term clock which is
available to all 16 macrocells. Each product term clock also
supports user configurable polarity selection.
Timing Model
One of the most important features of the Ultra37000 family is
the simplicity of its timing. All delays are worst case and system
performance is unaffected by the features used. Figure 11
illustrates the true timing model for the 167-MHz devices in high
speed mode. For combinatorial paths, any input to any output
incurs a 6.5 ns worst-case delay regardless of the amount of
logic used. For synchronous systems, the input setup time to the
output macrocells for any input is 3.5 ns and the clock to output
Document Number: 38-03007 Rev. *I
COMBINATORIAL SIGNAL
tPD = 6.5 ns
INPUT
OUTPUT
REGISTERED SIGNAL
tS = 3.5 ns
INPUT
D,T,L
O
tCO = 4.5 ns
OUTPUT
CLOCK
Page 16 of 50
"Not Recommended for New Design"
LE
Ultra37000 CPLD Family
JTAG and PCI Standards
Development Software Support
PCI Compliance
Warp
5V operation of the Ultra37000 is fully compliant with the PCI
Local Bus Specification published by the PCI Special Interest
Group. The 3.3V products meet all PCI requirements except for
the output 3.3V clamp, which is in direct conflict with 5V
tolerance. The Ultra37000 family’s simple and predictable timing
model ensures compliance with the PCI AC specifications
independent of the design.
Warp is a state-of-the-art compiler and complete CPLD design
tool. For design entry, Warp provides an IEEE-STD-1076/1164
VHDL text editor, an IEEE-STD-1364 Verilog text editor, and a
graphical finite state machine editor. It provides optimized
synthesis and fitting by replacing basic circuits with ones
pre-optimized for the target device, by implementing logic in
unused memory and by perfect communication between fitting
and synthesis. To facilitate design and debugging, Warp
provides graphical timing simulation and analysis.
The Ultra37000 family has an IEEE 1149.1 JTAG interface for
both Boundary Scan and ISR.
Boundary Scan
The Ultra37000 family supports Bypass, Sample/Preload,
Extest, Idcode, and Usercode boundary scan instructions. The
JTAG interface is shown in Figure 12.
Instruction Register
TMS
TCK
TDO
JTAG
TAP
CONTROLLER
Warp Professional contains several additional features. It
provides an extra method of design entry with its graphical block
diagram editor. It allows up to 5 ms timing simulation instead of
only 2 ms. It allows comparison of waveforms before and after
design changes.
Warp Enterprise™
Figure 12. JTAG Interface
TDI
Warp Professional™
Bypass Reg.
Boundary Scan
Warp Enterprise provides even more features. It provides
unlimited timing simulation and source-level behavioral
simulation as well as a debugger. It has the ability to generate
graphical HDL blocks from HDL text. It can even generate
testbenches.
Warp is available for PC and UNIX platforms. Some features are
not available in the UNIX version. For further information see the
Warp for PC, Warp for UNIX, Warp Professional and Warp
Enterprise data sheets on Cypress’s web site.
idcode
Third-Party Software
Usercode
Although Warp is a complete CPLD development tool on its own,
it interfaces with nearly every third party EDA tool. All major
third-party software vendors provide support for the Ultra37000
family of devices. Refer to the third-party software data sheet or
contact your local sales office for a list of currently supported
third-party vendors.
ISR Prog.
Data Registers
Programming
In-System Reprogramming (ISR)
In-System Reprogramming is the combination of the capability
to program or reprogram a device on-board, and the ability to
support design changes without changing the system timing or
device pinout. This combination means design changes during
debug or field upgrades do not cause board respins. The
Ultra37000 family implements ISR by providing a JTAG
compliant interface for on-board programming, robust routing
resources for pinout flexibility, and a simple timing model for
consistent system performance.
Document Number: 38-03007 Rev. *I
There are four programming options available for Ultra37000
devices. The first method is to use a PC with the 37000 UltraISR
programming cable and software. With this method, the ISR pins
of the Ultra37000 devices are routed to a connector at the edge
of the printed circuit board. The 37000 UltraISR programming
cable is then connected between the parallel port of the PC and
this connector. A simple configuration file instructs the ISR
software of the programming operations to be performed on
each of the Ultra37000 devices in the system. The ISR software
then automatically completes all of the necessary data
manipulations required to accomplish the programming, reading,
verifying, and other ISR functions. For more information on the
Cypress ISR Interface, see the CYUSBISRPC Programming
Cable User’s Guide.
Page 17 of 50
"Not Recommended for New Design"
IEEE 1149.1-compliant JTAG
Ultra37000 CPLD Family
The second method for programming Ultra37000 devices is on
automatic test equipment (ATE). This is accomplished through a
file created by the ISR software. Check the Cypress website for
the latest ISR software download information.
For all pinout, electrical, and timing requirements, refer to device
data sheets. For ISR cable and software specifications, refer to
the UltraISR kit data sheet (CY3700i).
Third-Party Programmers
As with development software, Cypress support is available on
a wide variety of third-party programmers. All major third-party
programmers (including BP Micro, Data I/O, and SMS) support
the Ultra37000 family.
"Not Recommended for New Design"
The third programming option for Ultra37000 devices is to utilize
the embedded controller or processor that already exists in the
system. The Ultra37000 ISR software assists in this method by
converting the device JEDEC maps into the ISR serial stream
that contains the ISR instruction information and the addresses
and data of locations to be programmed. The embedded
controller then simply directs this ISR stream to the chain of
Ultra37000 devices to complete the desired reconfiguring or
diagnostic operations. Contact your local sales office for
information on availability of this option.
The fourth method for programming Ultra37000 devices is to use
the same programmer that is currently being used to program
FLASH370i devices.
Document Number: 38-03007 Rev. *I
Page 18 of 50
Ultra37000 CPLD Family
5 V Device Maximum Ratings
DC Voltage Applied to Outputs
in High-Z State .............................................–0.5 V to +7.0 V
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
DC Input Voltage .........................................–0.5 V to +7.0 V
Storage Temperature ............................... –65 °C to +150 °C
Ambient Temperature with
Power Applied ......................................... –55 °C to +125 °C
Supply Voltage to Ground Potential .............–0.5 V to +7.0 V
DC Program Voltage ........................................... 4.5 to 5.5 V
Current into Outputs ................................................... 16 mA
Static Discharge Voltage
(per MIL-STD-883, Method 3015) .......................... > 2001 V
Latch-up Current .................................................... > 200 mA
Operating Range
Range
Commercial
Industrial
Ambient Temperature [4]
Junction Temperature
Output Condition
VCC
VCCO
0 °C to +70 °C
0 °C to +90 °C
5V
5 V  0.25 V
5 V  0.25 V
3.3 V
5 V  0.25 V
3.3 V  0.3 V
–40 °C to +85 °C
–40 °C to +105 °C
5V
5 V  0.5 V
5 V  0.5 V
3.3 V
5 V  0.5 V
3.3 V  0.3 V
5 V Device Electrical Characteristics
Over the Operating Range
Parameter
VOH
VOHZ
Description
Output HIGH Voltage
Test Conditions
Min
Typ
Max
Unit
VCC = Min IOH = –3.2 mA
(Commercial / Industrial) [6]
2.4
–
–
V
IOH = –2.0 mA (Military) [6]
2.4
–
–
V
–
–
4.2
V
–
–
4.5
V
–
–
3.6
V
–
–
3.6
V
–
–
0.5
V
–
–
0.5
V
[8]
Output HIGH Voltage with Output VCC = Max IOH = 0 A (Commercial)
Disabled [7]
IOH = 0 A (Industrial / Military) [8]
IOH = –100 A (Commercial)
[8]
IOH = –150 A
(Industrial / Military) [8]
VOL
Output LOW Voltage
VCC = Min IOL = 16 mA
(Commercial / Industrial) [6]
IOL = 12 mA (Military) [6]
VIH
Input HIGH Voltage
Guaranteed Input Logical HIGH Voltage for all
Inputs [9]
2.0
–
VCCmax
V
VIL
Input LOW Voltage
Guaranteed Input Logical LOW Voltage for all
Inputs [9]
–0.5
–
0.8
V
IIX
Input Load Current
VI = GND or VCC, Bus-Hold Disabled
–10
–
10
A
IOZ
Output Leakage Current
VO = GND or VCC, Output Disabled, Bus-Hold
Disabled
–50
–
50
A
IOS
Output Short Circuit Current [7, 10]
VCC = Max, VOUT = 0.5 V
–30
–
–160
mA
Notes
4. Normal Programming Conditions apply across Ambient Temperature Range for specified programming methods. For more information on programming the Ultra37000
Family devices, refer to the Application Note titled An Introduction to In System Reprogramming with the Ultra37000.
5. TA is the “Instant On” case temperature.
6. IOH = –2 mA, IOL = 2 mA for TDO.
7. Tested initially and after any design or process changes that may affect these parameters.
8. When the I/O is output disabled, the bus-hold circuit can weakly pull the I/O to above 3.6V if no leakage current is allowed. Note that all I/Os are output disabled during
ISR programming. Refer to the application note “Understanding Bus-Hold” for additional information.
9. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
10. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. VOUT = 0.5 V is chosen to avoid test problems caused
b t t
dd
d ti
Document Number: 38-03007 Rev. *I
Page 19 of 50
"Not Recommended for New Design"
The Operating Range is described as follows. [4]
Ultra37000 CPLD Family
5 V Device Electrical Characteristics (continued)
Over the Operating Range
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
IBHL
Input Bus-Hold LOW Sustaining VCC = Min, VIL = 0.8 V
Current
+75
–
–
A
IBHH
Input Bus-Hold HIGH Sustaining VCC = Min, VIH = 2.0 V
Current
–75
–
–
A
IBHLO
Input Bus-Hold LOW Overdrive
Current
VCC = Max
–
–
+500
A
IBHHO
Input Bus-Hold HIGH Overdrive
Current
VCC = Max
–
–
–500
A
Parameter [11]
L
Description
Maximum Pin Inductance
Test
Conditions
44-pin TQFP
44-pin PLCC
100-pin TQFP
160-pin TQFP
Unit
VIN = 5 V at
f = 1 MHz
2
5
8
9
nH
Max
Unit
Capacitance
Parameter [11]
Description
Test Conditions
CI/O
Input/Output Capacitance
VIN = 5 V at f = 1 MHz at TA = 25 °C
10
pF
CCLK
Clock Signal Capacitance
VIN = 5 V at f = 1 MHz at TA = 25 °C
12
pF
VIN = 5 V at f = 1 MHz at TA = 25 °C
16
pF
CDP
Dual-Function Pins
[12]
Endurance Characteristics
Parameter [11]
N
Description
Minimum Reprogramming
Cycles
Test Conditions
Normal Programming Conditions [13]
Min
Typ
Unit
1,000
10,000
Cycles
Notes
11. Tested initially and after any design or process changes that may affect these parameters.
12. Dual pins are I/O with JTAG pins.
13. Normal Programming Conditions apply across Ambient Temperature Range for specified programming methods. For more information on programming the Ultra37000
Family devices, refer to the Application Note titled An Introduction to In System Reprogramming with the Ultra37000.
Document Number: 38-03007 Rev. *I
Page 20 of 50
"Not Recommended for New Design"
Inductance
Ultra37000 CPLD Family
3.3 V Device Maximum Ratings
DC Voltage Applied to Outputs
in High-Z State .............................................–0.5 V to +7.0 V
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
DC Input Voltage .........................................–0.5 V to +7.0 V
Storage Temperature ............................... –65 C to +150 C
Ambient Temperature with
Power Applied ......................................... –55 C to +125 C
Supply Voltage to Ground Potential .............–0.5 V to +4.6 V
DC Program Voltage ........................................... 3.0 to 3.6 V
Current into Outputs ..................................................... 8 mA
Static Discharge Voltage
(per MIL-STD-883, Method 3015) .......................... > 2001 V
Latch-up Current .................................................... > 200 mA
Operating Range
Range
Commercial
Industrial
Ambient Temperature [14]
Junction Temperature
VCC [15]
0 °C to +70 °C
0 °C to +90 °C
3.3 V ± 0.3 V
–40 °C to +85 °C
–40 °C to +105 °C
3.3 V ± 0.3 V
3.3 V Device Electrical Characteristics
Over the Operating Range
Parameter
VOH
Description
Output HIGH Voltage
Test Conditions
VCC = Min IOH = –4 mA (Commercial)
[16]
Min
Max
Unit
2.4
–
V
–
0.5
V
IOH = –3 mA (Military) [16]
VOL
Output LOW Voltage
VCC = Min IOL = 8 mA (Commercial) [16]
IOL = 6 mA (Military)
[16]
VIH
Input HIGH Voltage
Guaranteed Input Logical HIGH Voltage for all
Inputs [17]
2.0
5.5
V
VIL
Input LOW Voltage
Guaranteed Input Logical LOW Voltage for all
Inputs [17]
–0.5
0.8
V
IIX
Input Load Current
VI = GND or VCC, Bus-Hold Disabled
–10
10
A
IOZ
Output Leakage Current
VO = GND or VCC, Output Disabled, Bus-Hold
Disabled
–50
50
A
IOS
Output Short Circuit
Current [18, 19]
VCC = Max, VOUT = 0.5 V
–30
–160
mA
IBHL
Input Bus-Hold LOW Sustaining VCC = Min, VIL = 0.8 V
Current
+75
–
A
IBHH
Input Bus-Hold HIGH Sustaining VCC = Min, VIH = 2.0 V
Current
–75
–
A
IBHLO
Input Bus-Hold LOW Overdrive
Current
VCC = Max
–
+500
A
IBHHO
Input Bus-Hold HIGH Overdrive
Current
VCC = Max
–
–500
A
Notes
14. Normal Programming Conditions apply across Ambient Temperature Range for specified programming methods. For more information on programming the Ultra37000
Family devices, refer to the Application Note titled An Introduction to In System Reprogramming with the Ultra37000.
15. For CY37064VP100-143AXC, CY37064VP44-143AXC; Operating Range: VCC is 3.3 V ± 0.16 V.
16. IOH = –2 mA, IOL = 2 mA for TDO.
17. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
18. Tested initially and after any design or process changes that may affect these parameters.
19. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. VOUT = 0.5 V is chosen to avoid test problems caused
Document Number: 38-03007 Rev. *I
Page 21 of 50
"Not Recommended for New Design"
The Operating Range is described as follows. [14]
Ultra37000 CPLD Family
Inductance
Description
Test
Conditions
44- pin TQFP
Maximum Pin Inductance
VIN = 3.3 V at
f = 1 MHz
2
Parameter [20]
L
44-pin PLCC 100- pin TQFP 160-pin TQFP Unit
5
8
9
nH
Max
Unit
Parameter [20]
Description
Test Conditions
CI/O
Input/Output Capacitance
VIN = 3.3 V at f = 1 MHz at TA = 25 °C
8
pF
CCLK
Clock Signal Capacitance
VIN = 3.3 V at f = 1 MHz at TA = 25 °C
12
pF
VIN = 3.3 V at f = 1 MHz at TA = 25 °C
16
pF
CDP
Dual Functional Pins
[21]
Endurance Characteristics
Parameter [20]
N
Description
Minimum Reprogramming
Cycles
Test Conditions
Normal Programming Conditions [22]
Min
Typ
Unit
1,000
10,000
Cycles
Notes
20. Tested initially and after any design or process changes that may affect these parameters.
21. Dual pins are I/O with JTAG pins.
22. Normal Programming Conditions apply across Ambient Temperature Range for specified programming methods. For more information on programming the Ultra37000
Family devices, refer to the Application Note titled An Introduction to In System Reprogramming with the Ultra37000.
Document Number: 38-03007 Rev. *I
Page 22 of 50
"Not Recommended for New Design"
Capacitance
Ultra37000 CPLD Family
AC Test Loads and Waveforms
Figure 13. 5 V AC Test Loads and Waveforms
238 (COM'L)
319 (MIL)
238 (COM'L)
319 (MIL)
5V
OUTPUT
170 (COM'L)
236 (MIL)
35 pF
INCLUDING
JIG AND
SCOPE
5V
3.0V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(b)
(a)
170 (COM'L)
GND
236 (MIL)
<2 ns
ALL INPUT PULSES
90%
90%
10%
10%
<2 ns
(c)
Equivalent to:
THÉVENIN EQUIVALENT
99 (COM'L)
136 (MIL) 2.08V (COM'L)
OUTPUT
2.13V (MIL)
Figure 14. 3.3 V AC Test Loads and Waveforms
3.3V
295 (COM'L)
393 (MIL)
OUTPUT
35 pF
INCLUDING
JIG AND
SCOPE
(a)
Equivalent to:
OUTPUT
340 (COM'L)
453 (MIL)
295 (COM'L)
393 (MIL)
3.3V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(b)
3.0V
340 (COM'L)
GND
453 (MIL)
<2 ns
ALL INPUT PULSES
90%
90%
10%
10%
<2 ns
(c)
THÉVENIN EQUIVALENT
158 (COM’L)
270 (MIL)
1.77V (COM'L)
1.77V (MIL)
5 OR 35 pF
Document Number: 38-03007 Rev. *I
Page 23 of 50
"Not Recommended for New Design"
5 OR 35 pF
Ultra37000 CPLD Family
Parameter [23]
VX
tER(–)
1.5 V
Output Waveform — Measurement Level
VOH
VX
0.5V
VOH
0.5V
VOL
1.5 V
VX
tEA(–)
0.5V
2.6 V
VOL
tEA(+)
VX
Vthe
VX
"Not Recommended for New Design"
tER(+)
0.5V
(d) Test Waveforms
Note
23. tER measured with 5 pF AC Test Load and tEA measured with 35 pF AC Test Load.
Document Number: 38-03007 Rev. *I
Page 24 of 50
Ultra37000 CPLD Family
Switching Characteristics
Over the Operating Range
Parameter [24]
Description
Unit
Combinatorial Mode Parameters
tPD[25, 26, 27]
Input to Combinatorial Output
tPDL[25, 26, 27]
tPDLL[25, 26, 27]
tEA[25, 26, 27]
tER[25, 28]
Input to Output Through Transparent Input or Output Latch
ns
Input to Output Through Transparent Input and Output Latches
ns
Input to Output Enable
ns
Input to Output Disable
ns
ns
Input Register Parameters
tWL
Clock or Latch Enable Input LOW Time[10]
ns
tWH
Clock or Latch Enable Input HIGH
Time[10]
ns
tIS
Input Register or Latch Set-up Time
tIH
Input Register or Latch Hold Time
ns
tICO[25, 26, 27]
Input Register Clock or Latch Enable to Combinatorial Output
ns
tICOL[25, 26, 27]
Input Register Clock or Latch Enable to Output Through Transparent Output Latch
ns
Synchronous Clocking Parameters
tCO[26, 27]
Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable to Output
ns
tS[25]
Set-Up Time from Input to Sync. Clk (CLK0, CLK1, CLK2, or CLK3) or Latch Enable
ns
tH
Register or Latch Data Hold Time
ns
tCO2[25, 26, 27]
Output Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable to Combinatorial Output Delay
(Through Logic Array)
ns
tSCS[25]
Output Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable to Output Synchronous Clock
(CLK0, CLK1, CLK2, or CLK3) or Latch Enable (Through Logic Array)
ns
tSL[25]
Set-Up Time from Input Through Transparent Latch to Output Register Synchronous Clock (CLK0 CLK1,
CLK2, or CLK3) or Latch Enable
ns
tHL
Hold Time for Input Through Transparent Latch from Output Register Synchronous Clock (CLK0, CLK1,
CLK2, or CLK3) or Latch Enable
ns
Notes
24. All AC parameters are measured with two outputs switching and 35 pF AC Test Load.
25. Logic blocks operating in low power mode, add tLP to this specification.
26. Outputs using Slow Output Slew Rate, add tSLEW to this specification.
27. When VCCO = 3.3V, add t3.3IO to this specification.
28. tER measured with 5 pF AC Test Load and tEA measured with 35 pF AC Test Load.
Document Number: 38-03007 Rev. *I
Page 25 of 50
"Not Recommended for New Design"
ns
Ultra37000 CPLD Family
Switching Characteristics (continued)
Over the Operating Range
Parameter [24]
Description
Unit
Product Term Clocking Parameters
tCOPT[30, 31, 32]
Product Term Clock or Latch Enable (PTCLK) to Output
ns
tSPT
Set-Up Time from Input to Product Term Clock or Latch Enable (PTCLK)
ns
tHPT
Register or Latch Data Hold Time
ns
tISPT[30]
Set-Up Time for Buried Register used as an Input Register from Input to Product Term Clock or Latch
Enable (PTCLK)
ns
tIHPT
Buried Register Used as an Input Register or Latch Data Hold Time
ns
Product Term Clock or Latch Enable (PTCLK) to Output Delay (Through Logic Array)
ns
tCO2PT
[30, 31, 32]
Pipelined Mode Parameters
tICS[30]
Input Register Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) to Output Register Synchronous Clock
(CLK0, CLK1, CLK2, or CLK3)
ns
fMAX1
Maximum Frequency with Internal Feedback (Lesser of 1/tSCS, 1/(tS + tH), or 1/tCO) [33]
MHz
fMAX2
Maximum Frequency Data Path in Output Registered/Latched Mode (Lesser of 1/(tWL + tWH), 1/(tS + tH),
or 1/tCO) [33]
MHz
fMAX3
Maximum Frequency with External Feedback (Lesser of 1/(tCO + tS) or 1/(tWL + tWH) [33]
MHz
fMAX4
Maximum Frequency in Pipelined Mode (Lesser of 1/(tCO + tIS), 1/tICS, 1/(tWL + tWH), 1/(tIS + tIH), or
1/tSCS) [33]
MHz
Reset/Preset Parameters
tRW
Asynchronous Reset Width [33]
ns
tRR[30]
tRO[30, 31, 32]
Asynchronous Reset Recovery Time [33]
ns
Asynchronous Reset to Output
ns
tPW
Asynchronous Preset Width [33]
tPR
[30]
tPO[30, 31, 32]
Asynchronous Preset Recovery Time
ns
[33]
ns
Asynchronous Preset to Output
ns
User Option Parameters
tLP
Low Power Adder
ns
tSLEW
Slow Output Slew Rate Adder
ns
t3.3IO
3.3 V I/O Mode Timing Adder [33]
ns
JTAG Timing Parameters
tS JTAG
Set-up Time from TDI and TMS to TCK [33]
[33]
tH JTAG
Hold Time on TDI and TMS
tCO JTAG
Falling Edge of TCK to TDO [33]
fJTAG
Maximum JTAG Tap Controller Frequency
ns
ns
ns
[33]
ns
Notes
29. All AC parameters are measured with two outputs switching and 35 pF AC Test Load.
30. Logic blocks operating in low power mode, add tLP to this specification.
31. Outputs using Slow Output Slew Rate, add tSLEW to this specification.
32. When VCCO = 3.3V, add t3.3IO to this specification.
33. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 38-03007 Rev. *I
Page 26 of 50
"Not Recommended for New Design"
Operating Frequency Parameters
Ultra37000 CPLD Family
Over the Operating Range
Max
Min
Max
Min
Max
7.5
66 MHz
Min
–
83 MHz
Max
6.5
100 MHz
Min
–
125 MHz
Max
Max
6
143 MHz
Min
Min
154 MHz
Max
167 MHz
Min
Max
Min
200 MHz
Parameter [34]
Unit
–
8.5
–
10
–
12
–
15
–
20
ns
Combinatorial Mode Parameters
tPD [35, 36, 37]
tPDL
[35, 36, 37]
–
"Not Recommended for New Design"
Switching Characteristics
–
11
–
12.5
–
14.5
–
16
–
16.5
–
17
–
19
–
22
ns
tPDLL [35, 36, 37]
–
12
–
13.5
–
15.5
–
17
–
17.5
–
18
–
20
–
24
ns
tEA [35, 36, 37]
–
8
–
8.5
–
11
–
13
–
14
–
16
–
19
–
24
ns
tER[35, 38]
–
8
–
8.5
–
11
–
13
–
14
–
16
–
19
–
24
ns
–
2.5
–
2.5
–
3
–
3
–
4
–
5
–
ns
Input Register Parameters
tWL
2.5
–
2.5
tWH
2.5
–
2.5
–
2.5
–
2.5
–
3
–
3
–
4
–
5
tIS
2
–
2
–
2
–
2
–
2
–
2.5
–
3
–
4
tIH
2
–
2
–
2
–
2
–
2
–
2.5
–
3
–
4
–
ns
tICO [35, 36, 37]
–
11
–
11
–
11
–
12.5
–
12.5
–
16
–
19
–
24
ns
tICOL [35, 36, 37]
–
12
–
12
–
12
–
14
–
16
–
18
–
21
–
26
ns
–
4
–
4.5
–
6
–
6.5 [39]
–
6.5 [40]
–
8 [41]
–
10
ns
–
10
–
ns
–
ns
–
ns
Synchronous Clocking Parameters
tCO [36, 37]
[35]
–
4
tH
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
ns
tCO2[35, 36, 37]
–
9.5
–
10
–
11
–
12
–
14
–
16
–
19
–
24
ns
tSCS[35]
5
–
6
–
6.5
–
7
–
8 [39]
–
10
–
12
–
15
–
ns
7.5
–
7.5
–
8.5
–
9
–
10
–
12
–
15
–
15
–
ns
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
ns
tHL
–
5
–
5
–
5.5
–
6
–
8
[41]
4
tSL
4
[40]
tS
[35]
–
[39]
Notes
34. All AC parameters are measured with two outputs switching and 35 pF AC Test Load.
35. Logic blocks operating in low power mode, add tLP to this specification.
36. Outputs using Slow Output Slew Rate, add tSLEW to this specification.
37. When VCCO = 3.3V, add t3.3IO to this specification.
38. tER measured with 5 pF AC Test Load and tEA measured with 35 pF AC Test Load.
39. For reference only, the following values correspond to the obsolete CY37512 devices: tCO = 5 ns, tS = 6.5 ns, tSCS = 8.5 ns, tICS = 8.5 ns, fMAX1 = 118 MHz.
40. The following values correspond to the CY37192V and CY37256V devices: tCO = 6 ns, tS = 7 ns, fMAX2 = 143 MHz, fMAX3 = 77 MHz, and fMAX4 = 100 MHz; and for the CY37512 devices: tS = 7 ns.
41. For reference only, the following values correspond to the obsolete CY37512V devices: tCO = 6.5 ns, tS = 9.5 ns, and fMAX2 = 105 MHz.
Document Number: 38-03007 Rev. *I
Page 27 of 50
Ultra37000 CPLD Family
Switching Characteristics (continued)
Over the Operating Range
167 MHz
154 MHz
143 MHz
125 MHz
100 MHz
83 MHz
66 MHz
–
200
–
200
–
167
–
154
–
–
–
100
–
MHz
fMAX3
125
–
125
–
105
–
91
–
83
–
80 [46]
–
62.5
–
50
–
MHz
fMAX4
167
–
167
–
154
–
125
–
118
–
100
–
83
–
66
–
MHz
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
–
7
–
10
–
10
–
13
–
13
–
13
–
15
–
20
ns
2.5
–
2.5
–
2.5
–
3
–
5
–
5.5
–
6
–
7
–
ns
tHPT
–
ns
–
ns
Min
Min
Unit
tSPT
Min
Max
200
125[47]
Parameter
Max
fMAX2
153[46]
"Not Recommended for New Design"
200 MHz
[34]
Product Term Clocking Parameters
tCOPT [42, 43, 44]
2.5
–
2.5
–
2.5
–
3
–
5
–
5.5
–
6
–
7
tISPT[42]
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
tIHPT
6
–
6.5
–
6.5
–
7.5
–
9
–
11
–
14
tCO2PT [42, 43, 44]
–
12
–
14
6
–
6
–
7
–
8 [45]
–
10
–
167
–
154
–
143
–
125[45]
–
100
15
19
19
–
19
–
ns
24
–
30
ns
12
–
15
–
ns
–
83
–
66
–
MHz
21
Pipelined Mode Parameters
tICS[42]
5
–
Operating Frequency Parameters
fMAX1
200
–
Reset/Preset Parameters
tRW
8
–
8
–
8
–
8
–
10
–
12
–
15
–
20
–
ns
tRR[42]
10
–
10
–
10
–
10
–
12
–
14
–
17
–
22
–
ns
Notes
42. Logic blocks operating in low power mode, add tLP to this specification.
43. Outputs using Slow Output Slew Rate, add tSLEW to this specification.
44. When VCCO = 3.3V, add t3.3IO to this specification.
45. For reference only, the following values correspond to the obsolete CY37512 devices: tCO = 5 ns, tS = 6.5 ns, tSCS = 8.5 ns, tICS = 8.5 ns, fMAX1 = 118 MHz.
46. The following values correspond to the CY37192V and CY37256V devices: tCO = 6 ns, tS = 7 ns, fMAX2 = 143 MHz, fMAX3 = 77 MHz, and fMAX4 = 100 MHz; and for the CY37512 devices: tS = 7 ns.
47. For reference only, the following values correspond to the obsolete CY37512V devices: tCO = 6.5 ns, tS = 9.5 ns, and fMAX2 = 105 MHz.
Document Number: 38-03007 Rev. *I
Page 28 of 50
Ultra37000 CPLD Family
Switching Characteristics (continued)
Over the Operating Range
Max
Min
Max
Min
Max
"Not Recommended for New Design"
Min
12
Max
10
66 MHz
Min
8
–
83 MHz
Max
–
tPO
[48, 49, 50]
–
100 MHz
Min
10
125 MHz
Max
8
tPR[48]
–
143 MHz
Unit
13
–
14
–
15
–
18
–
21
–
26
ns
–
8
–
10
–
12
–
15
–
20
–
ns
–
10
–
12
–
14
–
17
–
22
–
ns
–
13
–
14
–
15
–
18
–
21
–
26
ns
Min
tPW
12
154 MHz
Max
–
tRO [48, 49, 50]
Min
Min
Parameter
167 MHz
Max
200 MHz
[34]
13
–
–
8
–
10
–
13
User Option Parameters
tLP
–
2.5
–
2.5
–
2.5
–
2.5
–
2.5
–
2.5
–
2.5
–
2.5
ns
tSLEW
–
3
–
3
–
3
–
3
–
3
–
3
–
3
–
3
ns
t3.3IO[51]
–
0.3
–
0.3
–
0.3
–
0.3
–
0.3
–
0.3
–
0.3
–
0.3
ns
JTAG Timing Parameters
tS JTAG
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
tH JTAG
20
–
20
–
20
–
20
–
20
–
20
–
20
–
20
tCO JTAG
–
20
–
20
–
20
–
20
–
20
–
20
–
20
–
20
ns
fJTAG
–
20
–
20
–
20
–
20
–
20
–
20
–
20
–
20
MHz
–
ns
–
ns
Notes
48. Logic blocks operating in low power mode, add tLP to this specification.
49. Outputs using Slow Output Slew Rate, add tSLEW to this specification.
50. When VCCO = 3.3V, add t3.3IO to this specification.
51. Only applicable to the 5 V devices.
Document Number: 38-03007 Rev. *I
Page 29 of 50
Ultra37000 CPLD Family
Switching Waveforms
Figure 15. Combinatorial Output
INPUT
tPD
COMBINATORIAL
OUTPUT
Figure 16. Registered Output with Synchronous Clocking
INPUT
tS
tH
"Not Recommended for New Design"
SYNCHRONOUS
CLOCK
tCO
REGISTERED
OUTPUT
tCO2
REGISTERED
OUTPUT
tWL
tWH
SYNCHRONOUS
CLOCK
Figure 17. Registered Output with Product Term Clocking Input Going Through the Array
INPUT
tSPT
tHPT
PRODUCT TERM
CLOCK
tCOPT
REGISTERED
OUTPUT
Document Number: 38-03007 Rev. *I
Page 30 of 50
Ultra37000 CPLD Family
Switching Waveforms (continued)
Figure 18. Registered Output with Product Term Clocking Input Coming From Adjacent Buried Register
INPUT
tIHPT
tISPT
PRODUCT TERM
CLOCK
tCO2PT
REGISTERED
OUTPUT
Figure 19. Latched Output
tSL
"Not Recommended for New Design"
INPUT
tHL
LATCH ENABLE
tPDL
tCO
LATCHED
OUTPUT
Figure 20. Registered Input
REGISTERED
INPUT
tIH
tIS
INPUT REGISTER
CLOCK
tICO
COMBINATORIAL
OUTPUT
tWH
tWL
CLOCK
Figure 21. Clock to Clock
INPUT REGISTER
CLOCK
tICS
tSCS
OUTPUT
REGISTER CLOCK
Document Number: 38-03007 Rev. *I
Page 31 of 50
Ultra37000 CPLD Family
Switching Waveforms (continued)
Figure 22. Latched Input
LATCHED INPUT
tIH
tIS
LATCH ENABLE
tPDL
tICO
COMBINATORIAL
OUTPUT
tWH
tWL
"Not Recommended for New Design"
LATCH ENABLE
Figure 23. Latched Input and Output
LATCHED INPUT
tPDLL
LATCHED
OUTPUT
tICOL
tSL
INPUT LATCH
ENABLE
tHL
tICS
OUTPUT LATCH
ENABLE
tWH
tWL
LATCH ENABLE
Figure 24. Asynchronous Reset
tRW
INPUT
tRO
REGISTERED
OUTPUT
tRR
CLOCK
Document Number: 38-03007 Rev. *I
Page 32 of 50
Ultra37000 CPLD Family
Switching Waveforms (continued)
Figure 25. Asynchronous Preset
tPW
INPUT
tPO
REGISTERED
OUTPUT
tPR
CLOCK
Figure 26. Output Enable/Disable
tER
"Not Recommended for New Design"
INPUT
tEA
OUTPUTS
Document Number: 38-03007 Rev. *I
Page 33 of 50
Ultra37000 CPLD Family
Power Consumption
Typical 5 V Power Consumption
CY37032
60
H ig h S p e e d
50
40
Icc (mA)
Low Power
30
"Not Recommended for New Design"
20
10
0
0
50
100
150
200
250
F re q u e n c y (M H z )
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 5V, TA = Room Temperature
CY37064
90
80
H ig h S p e e d
70
Icc (mA)
60
50
Low Power
40
30
20
10
0
0
20
40
60
80
100
120
140
160
180
F re q u e n c y (M H z )
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 5V, TA = Room Temperature
Document Number: 38-03007 Rev. *I
Page 34 of 50
Ultra37000 CPLD Family
Typical 5 V Power Consumption (continued)
CY37128
160
H ig h S p e e d
140
120
Icc (mA)
100
Low Power
80
60
40
"Not Recommended for New Design"
20
0
0
20
40
60
80
100
120
140
160
180
F re q u e n c y (M H z )
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 5V, TA = Room Temperature
CY37192
300
250
H ig h S p e e d
Icc (mA)
200
Low Power
150
100
50
0
0
20
40
60
80
100
120
140
160
180
F re q u e n c y (M H z )
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 5V, TA = Room Temperature
Document Number: 38-03007 Rev. *I
Page 35 of 50
Ultra37000 CPLD Family
Typical 5 V Power Consumption (continued)
CY37256
300
H ig h S p e e d
250
200
Icc (mA)
Low Power
150
100
"Not Recommended for New Design"
50
0
0
20
40
60
80
100
120
140
160
180
F re q u e n c y (M H z )
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 5V, TA = Room Temperature
Document Number: 38-03007 Rev. *I
Page 36 of 50
Ultra37000 CPLD Family
Typical 3.3 V Power Consumption
CY37032V
30
H igh S p ee d
25
L ow P o w er
Icc (mA)
20
15
10
"Not Recommended for New Design"
5
0
0
20
40
60
80
100
120
140
160
F re qu e n cy (M H z)
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 3.3V, TA = Room Temperature
CY37064V
45
H ig h S p e e d
40
35
Low Power
Icc (mA)
30
25
20
15
10
5
0
0
20
40
60
80
1 00
120
14 0
F re q u e n c y (M H z)
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 3.3V, TA = Room Temperature
Document Number: 38-03007 Rev. *I
Page 37 of 50
Ultra37000 CPLD Family
Typical 3.3 V Power Consumption (continued)
CY37128V
80
H ig h S p e e d
70
60
Low Power
Icc (mA)
50
40
30
20
"Not Recommended for New Design"
10
0
0
20
40
60
80
100
120
140
F r e q u e n c y (M H z )
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 3.3V, TA = Room Temperature
CY37192V
120
H ig h S p e e d
100
80
Icc (mA)
Low Power
60
40
20
0
0
20
40
60
80
100
120
F re q u e n c y (M H z )
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 3.3V, TA = Room Temperature
Document Number: 38-03007 Rev. *I
Page 38 of 50
Ultra37000 CPLD Family
Typical 3.3 V Power Consumption (continued)
CY37256V
140
120
H ig h S p e e d
100
Icc (mA)
Low Power
80
60
40
20
0
20
40
60
80
100
"Not Recommended for New Design"
0
120
F re q u e n c y (M H z )
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 3.3V, TA = Room Temperature
Document Number: 38-03007 Rev. *I
Page 39 of 50
Ultra37000 CPLD Family
Ordering Information
5 V Ordering Information
Macrocells
Speed
(MHz)
32
154
CY37032P44-154AXI
A44
44-pin TQFP (Pb-free)
Industrial
125
CY37032P44-125AXC
A44
44-pin TQFP (Pb-free)
Commercial
CY37032P44-125JXC
J67
44-pin PLCC (Pb-free)
CY37064P44-125AXC
A44
44-pin TQFP (Pb-free)
CY37064P44-125JXC
J67
44-pin PLCC (Pb-free)
A100
100-pin TQFP (Pb-free)
CY37064P44-125AXI
A44
44-pin TQFP (Pb-free)
CY37064P100-125AXI
A100
100-pin TQFP (Pb-free)
CY37128P100-125AXC
A100
100-pin TQFP (Pb-free)
CY37128P160-125AXC
A160
160-pin TQFP (Pb-free)
125
CY37064P100-125AXC
128
125
Package
Name
Package Type
Operating
Range
Commercial
Industrial
Commercial
CY37128P100-125AXI
A100
100-pin TQFP (Pb-free)
CY37128P160-125AXI
A160
160-pin TQFP (Pb-free)
100
CY37128P160-100AXC
A160
160-pin TQFP (Pb-free)
Commercial
192
83
CY37192P160-83AXC
A160
160-pin TQFP (Pb-free)
Commercial
256
125
83
Industrial
CY37192P160-83AXI
A160
160-pin TQFP (Pb-free)
Industrial
CY37256P160-125AXC
A160
160-pin TQFP (Pb-free)
Commercial
CY37256P160-125AXI
A160
160-pin TQFP (Pb-free)
Industrial
CY37256P160-83AXC
A160
160-pin TQFP (Pb-free)
Commercial
CY37256P160-83AXI
A160
160-pin TQFP (Pb-free)
Industrial
3.3 V Ordering Information
Macrocells
Speed
(MHz)
32
143
CY37032VP44-143AXC
A44
44-pin TQFP (Pb-free)
100
CY37032VP44-100AXC
A44
44-pin TQFP (Pb-free)
64
100
CY37064VP44-100AXC
A44
44-pin TQFP (Pb-free)
Commercial
128
125
CY37128VP100-125AXC
A100
100-pin TQFP (Pb-free)
Commercial
83
CY37128VP160-83AXI
A160
160-pin TQFP (Pb-free)
Industrial
Ordering Code
Document Number: 38-03007 Rev. *I
Package
Name
Package Type
Operating
Range
Commercial
Page 40 of 50
"Not Recommended for New Design"
64
Ordering Code
Ultra37000 CPLD Family
Ordering Code Definitions
C Y 3 7 128 V P 100 - 125 A X C
Family Type
37 = Ultra37000 Family
Macrocell Density
32 = 32 Macrocells 192 = 192 Macrocells
64 = 64 Macrocells
256 = 256 Macrocells
128 = 128 Macrocells
Operating Reference Voltage
V = 3.3V Supply Voltage
(5.0V if not specified)
Pin Count
P44 = 44 Pins
P100 = 100 Pins
P160 = 160 Pins
P256 = 256 Pins
Document Number: 38-03007 Rev. *I
Operating Conditions
Commercial
0°C to +70°C
Industrial
-40°C to +85°C
Lead Free
X = Pb free
Package Type
A = Thin Quad Flat Pack (TQFP)
J = Plastic Leaded Chip Carrier (PLCC)
BB = Fine-Pitch Ball Grid Array (FBGA)
1.0 mm Lead Pitch
Speed
200 = 200 MHz
154 = 154 MHz
125 = 125 MHz
83 = 83 MHz
167 = 167 MHz
143 = 143 MHz
100 = 100 MHz
66 = 66 MHz
"Not Recommended for New Design"
Cypress Semiconductor ID
Page 41 of 50
Ultra37000 CPLD Family
Package Diagrams
"Not Recommended for New Design"
Figure 27. 44-pin TQFP (10 × 10 × 1.4 mm) A44S Package Outline, 51-85064
51-85064 *E
Figure 28. 44-pin PLCC J44 Package Outline, 51-85003
51-85003 *C
Document Number: 38-03007 Rev. *I
Page 42 of 50
Ultra37000 CPLD Family
Package Diagrams (continued)
"Not Recommended for New Design"
Figure 29. 100-pin TQFP (14 × 14 × 1.4 mm) A100SA Package Outline, 51-85048
51-85048 *G
Figure 30. 160-pin TQFP (24 × 24 × 1.4 mm) A160SA Package Outline, 51-85049
51-85049 *D
Document Number: 38-03007 Rev. *I
Page 43 of 50
Ultra37000 CPLD Family
Package Diagrams (continued)
"Not Recommended for New Design"
Figure 31. 256-ball FBGA (17 × 17 × 1.7 mm) BB256/BW0BD Package Outline, 51-85108
51-85108 *I
Document Number: 38-03007 Rev. *I
Page 44 of 50
Ultra37000 CPLD Family
Acronym
Document Conventions
Description
Units of Measure
ATE
automatic test equipment
CMOS
complementary metal oxide semiconductor
°C
degree Celsius
CPLD
complex programmable logic device
MHz
megahertz
FBGA
fine-pitch ball grid array
µA
microampere
I/O
input/output
mm
millimeter
ISR
in-system reprogrammable
ms
millisecond
JEDEC
joint electron devices engineering council
nH
nanohenry
JTAG
joint test action group
ns
nanosecond
OE
output enable

ohm
PC
personal computer
%
percent
PCI
peripheral component interconnect
pF
picofarad
PIM
programmable interconnect matrix
V
volt
PLCC
plastic leaded chip carrier
W
watt
TDI
test data-in
TDO
test data-out
TQFP
thin quad flat pack
TTL
transistor-transistor logic
Document Number: 38-03007 Rev. *I
Symbol
Unit of Measure
"Not Recommended for New Design"
Acronyms
Page 45 of 50
Ultra37000 CPLD Family
Document History Page
Document Title: Ultra37000 CPLD Family, 5 V and 3.3 V ISR™ High Performance CPLDs
Document Number: 38-03007
ECN No.
Submission
Date
Orig. of
Change
Description of Change
**
106272
04/18/01
SZV
Change from Spec number: 38-00475 to 38-03007
*A
124942
03/21/03
OOR
Updated 3.3V VCC requirements for –144 speeds
Added an Addendum
*B
126262
05/09/03
TEH
Changed pinout for CY37128V BB100 package
*C
128125
07/16/03
HOM
Obsoleted following 3.3V PLCC packaged devices:
CY37032VP44-143JC
CY37032VP44-100JC
CY37032VP44-100JI
CY37064VP44-143JC
CY37064VP84-143JC
CY37064VP44-100JC
CY37064VP84-100JC
CY37064VP44-100JI
CY37064VP84-100JI
CY37128VP84-125JC
CY37128VP84-83JC
CY37128VP84-83JI
*D
282709
11/08/04
YDT
Changed package diagrams and labels for consistency
Added Pb-free logo on first page, and a note in Features
Added Pb-free package diagram labels
Added Pb-free Parts to Ordering Information
CY37032P44-200AXC, CY37032P44-200JXC, CY37032P44-154AXI,
CY37032P44-154JXI, CY37032P44-125AXC, CY37032P44-125JXC,
CY37064P44-200AXC, CY37064P44-200JXC, CY37064P100-200AXC,
CY37064P44-154AXI, CY37064P44-154JXI, CY37064P44-125AXC,
CY37064P44-125JXC, CY37064P100-125AXC, CY37064P44-125AXI,
CY37064P100-125AXI, CY37128P84-167JXC, CY37128P100-167AXC,
CY37128P160-167AXC, CY37128P84-125JXC, CY37128P100-125AXC,
CY37128P160-125AXC, CY37128P84-125JXI, CY37128P100-125AXI,
CY37128P160-125AXI, CY37128P84-100JXC, CY37128P100-100AXC,
CY37128P160-100AXC, CY37128P100-100AXI, CY37192P160-154AXC,
CY37192P160-125AXC, CY37192P160-125AXI, CY37192P160-83AXC,
CY37192P160-83AXI, CY37256P160-154AXC, CY37256P160-125AXC,
CY37256P160-125AXI, CY37256P160-83AXC, CY37256P160-83AXI,
CY37032VP44-143AXC, CY37032VP44-100AXC, CY37032VP44-100AXI,
CY37032VP44-100JXI, CY37064VP44-143AXC, CY37064VP100-143AXC,
CY37064VP44-100AXC, CY37064VP100-100AXC, CY37064VP44-100AXI,
CY37064VP100-100AXI, CY37128VP100-125AXC,
CY37128VP160-125AXC, CY37128VP160-125AXI, CY37128VP100-83AXC,
CY37128VP160-83AXC, CY37128VP100-83AXI, CY37128VP160-83AXI,
CY37192VP160-100AXC, CY37192VP160-66AXC,
CY37256VP160-100AXC, CY37256VP160-100AXI, CY37256VP160-66AXC
*E
321635
03/14/05
PCX
Added Package Diagram BG292
Updated all PBGA package type information (BG292 & BG388)
Document Number: 38-03007 Rev. *I
Page 46 of 50
"Not Recommended for New Design"
Rev.
Ultra37000 CPLD Family
Document History Page (continued)
Rev.
ECN No.
Submission
Date
Orig. of
Change
Description of Change
*F
2813051
12/04/09
AAE
a.In the features section, reduced the maximum number of pins from 400 to
256 in reference to current package pin count in production.
b. 5V Selection Guide: Removed CY37384 and CY37512 options from the
general information table, removed CY37384 and CY37512 options from the
Speed Bins table, removed all in-active speed bin options, removed all in-active
device-package offering and I/O count options.
c. 3.3V Selection Guide: Removed CY37384V and CY37512V options from
the general information table, removed CY37384V and CY37512V options
from the Speed Bins table, removed all in-active speed bin options, removed
all in-active device-package offering and I/O count options.
d. Updated the development software support specific to Programming in
which the CY3700i (ISR Programming Kit) reference had been replaced with
the CYUSBISRPC Programming Cable User’s Guide.
e. Logic diagrams: Removed references to CY37384/ CY37384V and
CY37512/ CY37512V.
f. 5V Device Electrical Characteristics specific to the Inductance table:
Removed 44 pin CLCC, 84 pin PLCC, 84 pin CLCC and 208 pin PQFP from
the table.
g. 3.3V Device Electrical Characteristics specific to the Inductance table:
Removed 44 pin CLCC, 84 pin PLCC, 84 pin CLCC and 208 pin PQFP from
the table.
h. Note 10: Updated CY37064VP100-AC to CY37064VP100-AXC and
CY37064VP44-143AC to CY37064VP44-143AXC. Removed references to
CY37064VP100-143BBC and CY37064VP48-143BAC because these are
obsolete device-package options.
i. Note 16: Removed CY37384 device as a reference.
j. Note 18: Removed CY37384V device as a reference.
k. Power Consumption graphs: Removed reference graphs for CY37384,
CY37512, CY37384V and CY37512V.
l. Pin Configurations: Removed reference pin-outs for 44 Pin CLCC, 48B
FBGA, 84 Pin PLCC, 84 Pin CLCC, 100B FBGA, 160 pin CQFP, 208 pin CQFP,
208 pin PQFP, 292B PBGA, 388B PBGA, and 400B FBGA.
Document Number: 38-03007 Rev. *I
Page 47 of 50
"Not Recommended for New Design"
Document Title: Ultra37000 CPLD Family, 5 V and 3.3 V ISR™ High Performance CPLDs
Document Number: 38-03007
Ultra37000 CPLD Family
Document History Page (continued)
Rev.
ECN No.
Submission
Date
Orig. of
Change
Description of Change
*F (cont)
2813051
12/04/09
AAE
m. Updated the 5 V Ordering Information: Removed the following obsolete part
numbers: CY37032P44-200AC, CY37032P44-200AXC,
CY37032P44-200JC, CY37032P44-200JXC, CY37032P44-154AC,
CY37032P44-154JC, CY37032P44-154AI, CY37032P44-154JI,
CY37032P44-154JXI, CY37032P44-125AC, CY37032P44-125JC,
CY37032P44-125AI, CY37032P44-125JI, CY37064P44-200AC,
CY37064P44-200AXC, CY37064P44-200JC, CY37064P44-200JXC,
CY37064P84-200JC, CY37064P100-200AC, CY37064P44-154AC,
CY37064P44-154JC, CY37064P84-154JC, CY37064P100-154AC,
CY37064P44-154AI, CY37064P44-154JI, CY37064P100-154AI,
CY37064P44-125AC, CY37064P44-125JC, CY37064P84-125JC,
CY37064P100-125AC, CY37064P44-125AI, CY37064P44-125JI,
CY37064P84-125JI, CY37064P100-125AI, 5962-9951901QYA,
CY37128P84-167JC, CY37128P84-167JXC, CY37128P100-167AC,
CY37128P100-167AXC, CY37128P160-167AC, CY37128P84-125JC,
CY37128P84-125JXC, CY37128P100-125AC, CY37128P160-125AC,
CY37128P84-125JI, CY37128P84-125JXI, CY37128P100-125AI,
CY37128P160-125AI, 5962-9952102QYA, CY37128P84-100JC,
CY37128P84-100JXC, CY37128P100-100AC, CY37128P160-100AC,
CY37128P84-100JI, CY37128P100-100AI, CY37128P100-100AXI,
CY37128P160-100AI, 5962-9952101QYA, CY37192P160-154AC,
CY37192P160-154AXC, CY37192P160-125AC, CY37192P160-125AI,
CY37192P160-83AC, CY37192P160-83AI, CY37256P160-154AC,
CY37256P160-154AXC, CY37256P208-154NC, CY37256P256-154BGC,
CY37256P160-125AC, CY37256P208-125NC, CY37256P256-125BGC,
CY37256P160-125AI, CY37256P208-125NI, CY37256P256-125BGI,
5962-9952302QZC, CY37256P160-83AC, CY37256P208-83NC,
CY37256P256-83BGC, CY37256P160-83AI, CY37256P208-83NI,
CY37256P256-83BGI, CY37384P208-125NC, CY37384P256-125BGC,
CY37384P208-83NC, CY37384P256-83BGC, CY37384P208-83NI,
5962-9952301QZC, CY37384P256-83BG, CY37512P208-125NC,
CY37512P256-125BGC, CY37512P208-100NC, CY37512P256-100BGC,
CY37512P352-100BGC, CY37512P208-100NI, CY37512P256-100BGI,
CY37512P352-100BGI, 5962-9952502QZC, CY37512P208-83NC,
CY37512P256-83BGC, CY37512P352-83BGC, CY37512P208-83NI,
CY37512P256-83BGI, CY37512P352-83BGI, 5962-9952501QZC.
Document Number: 38-03007 Rev. *I
Page 48 of 50
"Not Recommended for New Design"
Document Title: Ultra37000 CPLD Family, 5 V and 3.3 V ISR™ High Performance CPLDs
Document Number: 38-03007
Ultra37000 CPLD Family
Document History Page (continued)
Rev.
ECN No.
Submission
Date
Orig. of
Change
Description of Change
*F (cont)
2813051
12/04/09
AAE
n. Updated the 3.3V Ordering Information: Removed the following obsolete
part numbers: CY37032VP44-143AC, CY37032VP48-143BAC,
CY37032VP44-100AC, CY37032VP48-100BAC, CY37032VP44-100AI,
CY37032VP44-100AXI, CY37032VP48-100BAI, CY37032VP44-100JI,
CY37032VP44-100JXI, CY37064VP44-143AC, CY37064VP48-143BAC,
CY37064VP100-143AC, CY37064VP100-143BBC, CY37064VP44-100AC,
CY37064VP48-100BAC, CY37064VP100-100AC, CY37064VP100-100BBC,
CY37064VP44-100AI, CY37064VP44-100AXI, CY37064VP48-100BAI,
CY37064VP100-100BBI, CY37064VP100-100AI, 5962-9952001QYA,
CY37128VP100-125AC, CY37128VP100-125BBC, CY37128VP160-125AC,
CY37128VP160-125AI, CY37128VP100-83AC, CY37128VP100-83BBC,
CY37128VP160-83AC, CY37128VP100-83AI, CY37128VP100-83BBI,
CY37128VP160-83AI, 5962-9952201QYA, CY37192VP160-100AC,
CY37192VP160-66AC, CY37192VP160-66AI, CY37256VP160-100AC,
CY37256VP208-100NC, CY37256VP256-100BGC,
CY37256VP256-100BBC, CY37256VP160-100AI, CY37256VP160-66AC,
CY37256VP208-66NC, CY37256VP256-66BGC, CY37256VP160-66AI,
CY37256VP256-66BGI, 5962-9952401QZC, CY37384VP208-83NC,
CY37384VP256-83BGC, CY37384VP208-66NC, CY37384VP256-66BGC,
CY37384VP208-66NI, CY37384VP256-66BGI, CY37512VP208-83NC,
CY37512VP256-83BGC, CY37512VP352-83BGC, CY37512VP400-83BBC,
CY37512VP208-66NC, CY37512VP256-66BGC, CY37512VP352-66BGC,
CY37512VP400-66BBC, CY37512VP208-66NI, CY37512VP256-66BGI,
CY37512VP352-66BGI, CY37512VP400-66BBI, 5962-9952601QZC.
*F (cont)
2813051
12/04/09
AAE
o. Updated package diagram drawing revisions on the following: 51-85064,
51-85003, 51-85048.
p. Removed package diagram drawing references for obsoleted part numbers:
44 pin CLCC (51-80014), 48FBGA (51-85109), 84 pin CLCC (51-80095), 100B
FBGA (51-85107), 160 pin CQFP (51-80106), 208 pin PQFP (51-85069), 208
pin CQFP (51-80105), 292B PBGA (51-85097), 388B PBGA (51-85103), 400B
FBGA (51-85111).
q. Addendum for 3.3V Operating Range: Updated CY37064VP100-AC to
CY37064VP100-AXC and CY37064VP44-143AC to CY37064VP44-143AXC.
Removed references to CY37064VP100-143BBC and
CY37064VP48-143BAC because these are obsolete device-package options.
r. Removed Military Operating Range because all Military Part numbers have
been obsoleted.
*G
2896152
03/19/2010
AAE
Removed inactive parts from Ordering Information.
Updated Table of Contents.
Updated Packaging Information.
Updated links in Sales, Solutions, and Legal Information.
*H
3081920
11/09/2010
AAE
Updated Ordering Information and Ordering Code Definitions.
Minor edits.
*I
3721588
08/23/2012
AAE
Updated Package Diagrams (spec 51-85064 (Changed revision from *D to *E),
spec 51-85003 (Changed revision from *B to *C), spec 51-85048 (Changed
revision from *D to *G), spec 51-85049 (Changed revision from *C to *D), spec
51-85108 (Changed revision from *H to *I)).
Added Acronyms and Units of Measure.
Updated in new template.
Document Number: 38-03007 Rev. *I
Page 49 of 50
"Not Recommended for New Design"
Document Title: Ultra37000 CPLD Family, 5 V and 3.3 V ISR™ High Performance CPLDs
Document Number: 38-03007
Ultra37000 CPLD Family
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
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"Not Recommended for New Design"
Memory
© Cypress Semiconductor Corporation, 2001-2012. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-03007 Rev. *I
Revised August 23, 2012
Page 50 of 50
ViewDraw and SpeedWave are trademarks of ViewLogic. Windows is a registered trademark of Microsoft Corporation. Warp is a registered trademark, and In-System Reprogrammable, ISR, Warp
Professional, Warp Enterprise, and Ultra37000 are trademarks, of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their
respective holders.