Freescale Semiconductor Application Note AN3100 Rev. 3, 3/2011 General Purpose Amplifier and MMIC Biasing INTRODUCTION Freescale Semiconductor’s GaAs MMICs and General Purpose Amplifier (GPA) devices are all designed to operate from a single positive voltage supply. The GPAs have output powers ranging from 15 to 33 dBm. They are currently designed with five different circuit techniques: • • • • • Darlington Pair Darlington Pair with Active Bias Discrete with Diode Active Bias Discrete with integrated current mirror Field Effect Transistor (FET) operating at self bias and use three different device technologies: • Indium Gallium Phosphide Heterostructure Bipolar Transistors (InGaP HBT) • GaAs Heterostructure Field Effect Transistor (HFET) • GaAs Enhancement Mode Pseudomorphic High Electron Mobility Transistors (E--pHEMT) HBT devices are current--driven; therefore, Freescale recommends that designers use a constant current source to minimize the impact of shifts in supply voltage and shifts in the temperature of the operating environment. Deviations from the optimal current can impact both power and linearity performance. A series resistor between the voltage supply and collectors of the Darlington is the easiest way to emulate a constant current source (R6 in Fig. 1). Because the RF output of the Darlington Pair is also used for the DC bias, an RF choke is required (L1) to connect the voltage supply to the output. RF coupling capacitors may also be required on the RF input and RF output because the input and output of the devices are DC coupled. Freescale has developed a method to eliminate the need for an external resistor and to enable the devices to operate directly from a positive 5 Volt supply. This approach has exceptional current stability over temperature (Fig. 2). VSUPPLY The required biasing methods for the different circuit schemes are described in this application note. VCC GPA CIRCUIT DESIGN METHODS Freescale’s InGaP HBTs are designed using one of two different primary circuit methods. The low power GPAs (P1dB from 15 to 25 dBm) are designed using a Darlington Pair (Fig. 1). The Darlington Pair is biased when voltage is applied to the collector of discrete devices Q1 and Q2. Resistor R1 is used for negative feedback of the amplifier but is also part of the voltage divider with R2 to establish the base bias on Q1. VSUPPLY R6 RF INPUT RF OUTPUT R1 Q1 C1 R2 R3 R4 C2 Q2 R5 PACKAGED DEVICE Figure 2. Improved Darlington Pair InGaP HBT Bias Scheme without External Bias Resistor VCC C3 L1 RF INPUT C3 L1 RF OUTPUT R1 Q1 C1 R2 R3 R4 C2 Q2 R5 PACKAGED DEVICE Figure 1. Darlington Pair InGaP HBT Bias Scheme © Freescale Semiconductor, Inc., 2005, 2007--2008, 2011. All rights reserved. RF Application Information Freescale Semiconductor AN3100 1 Freescale has continued to improve bias and performance stability over temperature as well as reducing sensitivity to supply voltage variations by introducing Darlington Pair devices with an integrated active bias (Fig. 3). The second design approach that uses this method is the MMIC with a discrete RF device and current mirror (Fig. 5). VCC R6 VSUPPLY C6 L1 Vref C5 VCC L1 RF INPUT R5 C3 RF OUTPUT R1 C2 Q1 C1 Q2 R4 R2 R3 Q2 R4 Q3 C2 R3 RF INPUT R5 RF OUTPUT R2 R1 C4 Q1 C3 PACKAGED DEVICE Figure 3. Active Bias Darlington Pair InGaP HBT and E--pHEMT Bias Scheme The second circuit method is used on the intermediate power amplifiers (P1dB ranging from 21 to 33 dBm). These are designed with a MMIC that contains a discrete device, Q1, with an integrated active bias. This approach is used for devices based on E--pHEMT technology as well. This active bias approach means that the bias current has minimal shift with normal supply voltage deviations over the specified operating temperature range. One design approach that utilizes this method is the discrete MMIC with diode bias (Fig. 4). VSUPPLY C3 L1 RF OUTPUT VCC RF INPUT C2 R1 C1 PACKAGED DEVICE Figure 5. Intermediate Power Discrete with Integrated Current Mirror InGaP HBT Bias Scheme R6 in Fig. 5 is an external dropping resistor that is required to establish the reference voltage on the current mirror that drives the bias of Q1. The reference voltage (Vref) is different for each device based on its size. The data sheets for each device list the specific reference voltage required for optimal bias current. L1 is required to prevent the DC supply line from improperly loading the RF output. RF coupling capacitors (C3 and C4 in Fig. 5) are also required. The third circuit approach in GPAs is used for the HFET devices. The bias of this type of device is very similar to the Darlington circuit technology. The HFETs are discrete devices that operate directly from a 5 Volt supply voltage (Fig. 5). The DC blocking capacitor that is integrated in the feedback loop prevents the gate voltage from being established with R1 and R2; therefore, the HFET devices operate at 0 Volts on the gate when 5 Volts are applied to the drain. R3 is used to provide negative feedback and to reduce VGS to reduce the quiescent current via self bias. L1 is again required as an RF choke as well as the RF coupling capacitors, C2 and C3. VSUPPLY Q1 C1 R2 C4 R3 PACKAGED DEVICE Figure 4. Discrete Device with Active Bias L1 RF INPUT R1 C1 Q1 C2 R2 RF OUTPUT C3 R3 PACKAGED DEVICE Figure 6. HFET Bias Scheme AN3100 2 RF Application Information Freescale Semiconductor SUMMARY The GPA lineup from Freescale is designed to operate from a single positive voltage supply, which makes them easy to use. Designers using these devices should be careful to bias the devices correctly using the appropriate method for the type of device used. If the current is set too low, linearity and power will degrade. If the current is set too high, there is some risk of compromising reliability. The techniques outlined here are a guide to the bias approaches for the different technologies and products available from Freescale. The data sheets for each device should be followed to achieve optimal performance from all GPAs. AN3100 RF Application Information Freescale Semiconductor 3 REVISION HISTORY The following table summarizes revisions to this document. Revision Date 1 Sept. 2007 Description • Added connection nodes to VCC and Q1 collector, Fig. 3, Intermediate Power InGaP HBT Bias Scheme, p. 2 • Added Revision History, p. 3 2 July 2008 • Application note updated to reflect changes in device portfolio and addition of technology. 3 Mar. 2011 • Application note updated to reflect changes in device portfolio and E--pHEMT technology references. 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