Freescale Semiconductor Engineering Bulletin Document Number: EB740 Rev. 0, 04/2011 Detailed Information for Erratum SECF196 This engineering bulletin provides additional detail and clarification on erratum SECF196 affecting the ColdFire MCF532x and MCF537x devices. The objective of this document is to explain the cause and effects of the issue in greater detail and provide information on how systems might be impacted. Contents 1 2 3 1 Description During a power-on reset (POR), some power ramp and clock startup sequences can cause some pins to drive undefined values for a period of time during the reset sequence. Undefined signal states can be driven on FlexBus, SDRAMC, and BDM pins if the device exits POR with no internal clock present. Initially the pins are tri-stated while IVDD and EVDD/SDVDD are not fully powered. As the voltage rails ramp to the operating levels, the processor releases the pins from tri-state and the pin states are determined by digital control logic. However, the digital logic needs © Freescale Semiconductor, Inc., 2011. All rights reserved. Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Affected signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . System impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 FlexBus impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 SDRAM impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 BDM impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Workarounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Workaround step 1: Generate a qualifier signal . . . 3.2 Workaround step 2: Qualify signals. . . . . . . . . . . . . 1 2 2 3 3 4 5 5 5 6 Description several clock cycles to initialize, so the pins can be driven by uninitialized logic for a period of time while the digital logic initializes to the reset state. 1.1 Timing diagram Figure 1 shows an example of power-on reset (POR) timing that causes undefined signal states on FlexBus, SDRAM, and BDM pins. For clarity the diagram includes POR and pad enable signals. These are internal signals of the processor, so they are not visible externally. The undefined pin state can be driven out starting when EVDD/SDVDD and IVDD ramp to the point where the internal POR is released. EVDD/SDVDD FlexBus, SDRAM, and BDM reach a known state after several internal clocks, which ends the undefined pin state. If the clocks startup before the POR is released, then the undefined pin signal states could be eliminated. IVDD POR Pad Enable FB_CSn Undefined /RSTO Clock Figure 1. Power-on reset sequence causing undefined signal states 1.2 Affected signals Table 1 lists the FlexBus, SDRAMC, and BDM signals and describes how they are impacted. Detailed Information for Erratum SECF196, Rev. 0 2 Freescale Semiconductor System impact Table 1. MCF532x and MCF537x signals that can have undefined states during POR Module Signals Undefined? Description FlexBus Yes A[23:0], D[31:0], BE/BWE[3:0], OE, R/W, TS, FB_CS[5:0] Most FlexBus signals are in an undefined state any time between the release of the internal POR signal and clock startup. FlexBus TA The TA signal is always an input and it will be configured as an input at POR; therefore, this signal is in a defined state. SDRAMC Yes SD_A10, SD_CLK, SD_CS[1:0], SD_DQS[3:2], SD_SCAS, SD_SRAS, SD_SDR_DQS, SD_WE Most SDRAMC signals are in an undefined state any time between the release of the internal POR signal and clock startup. SDRAMC SD_CKE As part of the fix for an earlier erratum (SECF045) on any 3M29B and later devices, the SD_CKE signal is forced to drive high when the internal POR is released. No No Note: On 2M29B and earlier parts the state of SD_CKE can be undefined. SDRAMC SD_CLK No As part of the fix for an earlier erratum (SECF045) on any 3M29B and later devices, the SD_CLK signal is driven with a digital version of the input clock on EXTAL when the internal POR is released. BDM/JTAG PSTCLK, DSO, DDATA[3:0], Depends on If JTAG functions are selected (JTAG_EN = 1), then pin states are PST[3:0], ALLPST JTAG_EN defined. If BDM functions are selected (JTAG_EN = 0), the BDM outputs are undefined until clock start. BDM/JTAG DSI, BKPT No These signals are inputs in both BDM and JTAG mode, and they will default to inputs when the internal POR is released. BDM/JTAG JTAG_EN No This input signal is used to select between BDM and JTAG functions. It is configured as an input and sampled when the internal POR is released. 2 System impact Depending on how the processor signals are used in the rest of the system, an undefined pin state could cause unexpected behavior for a device external to the processor. Because the undefined pin states are temporary (pins will enter a defined state before the processor exits reset), in many cases the undefined pin states will not cause a functional issue for the system. 2.1 FlexBus impact The possibility of impact to devices on the FlexBus depends on the types of memory used in the system. Table 2 lists some common devices that might be used in a system and how they could be impacted by undefined signal states. Detailed Information for Erratum SECF196, Rev. 0 Freescale Semiconductor 3 System impact Table 2. Potential impact of undefined signal states on common FlexBus devices Device type Impacted? Comments NOR flash No Because NOR flash devices require a specific sequence with multiple steps to erase or write memory, the undefined signal states cannot corrupt NOR flash contents. SRAM No Because SRAM contents are undefined at power-on reset, any accidental writes to RAM caused by the undefined signal states should not impact the system. Note: If the SRAM has a battery backup or is powered independently of the processor such that its contents are defined at the time the processor goes through a power-on reset, then data corruption is possible. MRAM/FRAM Yes Any nonvolatile memory device with an asynchronous bus interface could be impacted. Because the memory contents are retained, accidental writes to the memory caused by the undefined signal states could corrupt the non-volatile data. CPLDs, FPGAs, and external peripherals Depends Because the use of these devices can vary and in some cases is user-defined, we are unable to make an accurate assessment of how these types of devices could be impacted. 2.2 SDRAM impact The SDRAMC on the MCF537x/MCF532x family is a special case. To fix an earlier erratum (SECF045), the SD_CLK signal is driven as soon as clocks are detected and SD_CKE is driven high. Because of this fix, there will be a short overlap between undefined pin states on the SDRAM control signals and SD_CLK starting up. This can allow an SDRAM to latch an erroneous SDRAM command. During initial startup, the SDRAM doesn’t allow any commands except NOP and COMMAND INHIBIT. Undefined signal states on the SDRAMC signals could potentially be recognized as other commands and cause undefined operation of the SDRAM. If the undefined operation of the SDRAM causes the SDRAM to drive the data bus, it could potentially cause interference with chip configuration and code fetches. 2.2.1 Non-split bus configurations If a non-split bus configuration is used, then the SDRAM shares data lines with the FlexBus. Data line contention between the SDRAM, FlexBus devices, and/or the MCU is possible. If a 32-bit wide SDRAM is used, then it could potentially cause interference with latching of chip configuration values on the FB_D[9:1]/RCON[9:1] signals. Contention while latching chip configuration values and/or boot code could result in boot failures. 2.2.2 Split bus configuration If a split bus configuration is used, then the SDRAM bus has a 16-bit wide dedicated data bus. Because the data lines are not shared with the FlexBus or chip configuration pins in this configuration, no issues are expected as a result of the undefined signal states on the SDRAMC signals. Detailed Information for Erratum SECF196, Rev. 0 4 Freescale Semiconductor Workarounds 2.3 BDM impact If the BDM signals are enabled (JTAG_EN = 0), then BDM outputs could also drive undefined signal states during reset. Because the BDM signals are not multiplexed with any module pins, in most systems these signals would route only to a BDM/JTAG header. Therefore, undefined pin states on BDM signals are not expected to cause functional problems for systems. 3 Workarounds The undefined pin states occur only during a power-on reset (POR) — the /RESET and/or /RSTOUT signals can be used to qualify FlexBus and SDRAMC signals. In most cases, the only signals that will need to be qualified are the FlexBus chip select and SDRAM chip select signals. By using qualified versions of the chip selects to connect to external devices, you can prevent those external devices from sampling the undefined pin states on address, data, and other control signals. 3.1 Workaround step 1: Generate a qualifier signal The first step to the workaround is to generate a signal that can be used to qualify or mask the undefined signal states on the chip select signals (or other control signals as needed). Determining the qualifier to use can require some characterization of power and reset signal operation in the system. The idea is to find a signal or combination of signals that remains high throughout the time when the undefined signal states can occur. Theoretically the RSTOUT signal could be used to qualify signals; however, because RSTOUT asserts low at the same time that the undefined signal states start to drive on other pins, if this signal were used as a qualifier alone, there could be small glitches while waiting for RSTOUT to propagate through logic. For this reason Freescale doesn’t recommend using RSTOUT on its own as a qualifier. If the system keeps the RESET input signal to the processor asserted during system power-up and through the start of clocks, then the RESET signal could be used to generate the qualifier signal as shown in Figure 2. /RESET Chip Select Qualifier Figure 2. Generating a qualifier signal using RESET If the system is not guaranteed to keep the RESET input signal asserted through the start of clocks, then a combination of the RESET and RSTOUT signals could be used instead as shown in Figure 3. It is important that there be a period of time during which RESET and RSTOUT are asserted simultaneously, to avoid possible glitches. Detailed Information for Erratum SECF196, Rev. 0 Freescale Semiconductor 5 Workarounds /RESET /RSTO UT Chip Select Q ualifier Figure 3. Generating a qualifier signal Using RESET and RSTOUT 3.2 Workaround step 2: Qualify signals For many systems there might be only a small number of chip selects or other control signals that need to be qualified to prevent the undefined signal states from reaching external devices. If there are only a small number of signals that need to be qualified, then adding discrete logic gates might be the best solution. Figure 4 shows an example of how a chip select signal could be qualified using an OR gate. Chip Select Qualifier Chip Select to External Device /FB_CSn Figure 4. Qualifying a chip select using an OR gate There are up to eight chip select signals available on the MCF532x/7x family devices — six FlexBus chip selects and two SDRAM chip selects. This means that all of the chip select signals on the processor could be qualified using a single 8-bit tri-statable buffer as shown in Figure 5. C h ip S e le c t Q u a lifie r /O E /F B _ C S 0 D0 O0 /M E M _ F B _C S0 /F B _ C S 1 D1 O1 /M E M _ F B _C S1 /F B _ C S 2 D2 O2 /M E M _ F B _C S2 /F B _ C S 3 D3 O3 /M E M _ F B _C S3 /F B _ C S 4 D4 O4 /M E M _ F B _C S4 /F B _ C S 5 D5 O5 /M E M _ F B _C S5 /S D _ C S 0 D6 O6 /M E M _ S D _C S0 /S D _ C S 1 D7 O7 /M E M _ S D _C S1 Figure 5. Qualifying all chip selects using a buffer In Figure 5, “MEM_” is used to differentiate the chip select signals from the processor and the qualified versions that would be connected to external memories. Each of the “MEM_” signals should include a pullup resistor to force the signal high while the buffer is disabled. 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