UM10409 120 V high power factor CFL reference board using the UBA2014T Rev. 1 — 12 October 2010 User manual Document information Info Content Keywords UBA2014T, half-bridge CFL driver, high PF, triac dimmable Abstract This user manual describes the 120 V mains dimmable Compact Fluorescent Lamp (CFL) reference board with high power factor based on the UBA2014T UM10409 NXP Semiconductors 120 V high power factor CFL reference board Revision history Rev Date Description v.1 20101012 initial version Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] UM10409 User manual All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 October 2010 © NXP B.V. 2010. All rights reserved. 2 of 25 UM10409 NXP Semiconductors 120 V high power factor CFL reference board 1. Introduction WARNING Lethal voltage and fire ignition hazard The non-insulated high voltages that are present when operating this product, constitute a risk of electric shock, personal injury, death and/or ignition of fire. This product is intended for evaluation purposes only. It shall be operated in a designated test area by personnel qualified according to local requirements and labor laws to work with non-insulated mains voltages and high-voltage circuits. This product shall never be operated unattended. Remark: Galvanic isolation of the mains phase using a variable transformer is always recommended. These devices can be recognized by the symbols shown in Figure 1. 019aaa691 019aaa690 a. Isolated Fig 1. b. Not isolated Variac isolation symbols The UBA2014T is a half-bridge driver IC used for electronically ballasted fluorescent lamps. In this application, it provides the drive function for two external MOSFETs and these supply power to the resonant tank circuit and Philips PL-C 4P 18 W CFL. The mains input is 120 V (RMS) ± 10 %. The bus voltage is generated with a Power Factor Correction (PFC) or boost circuit which utilizes the same external MOSFETs. This PFC circuit, also known as a combined free running PFC, has a Power Factor (PF) greater than 95 %. Dimming down to 10 % of lamp current (< 10 % lumens) is possible using a triac dimmer. A 120 V Lutron dimmer was used. The application can be used with lamps in a laboratory environment and a protection circuit is included (outside the circular PCB). This protection circuit disables the operation of the UBA2014T when a lamp is not attached to the circuit. This circuit is not necessary when the application is included in a CFL housing. Other protective circuits include: • OverVoltage Protection (OVP) on bus voltage • UnderVoltage LockOut (UVLO) which is not necessary in this application during deep dimming UM10409 User manual All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 October 2010 © NXP B.V. 2010. All rights reserved. 3 of 25 UM10409 NXP Semiconductors 120 V high power factor CFL reference board 2. Schematic Diagram DIM CONTROL R2 220 kΩ D7 D8 PMLL4148L 5.1 V DIM D5 V1 PESD15VL1BA C4 4.7 μF R4 33 kΩ Vbus 1N4937 OUTSIDE CIRCULAR PCB R1 P2 D2 L1 2.75 mH D1 C2 100 nF D6 Lboost D3 1N4007 4.7 mH P1 10 Ω X1 D4 OVERVOLTAGE PROTECTION R6 220 kΩ 1N4937 C3 100 nF R13 220 kΩ R45 NM 120 V (RMS) R9 D9 D10 PMLL4148L 5.1 V 10 Ω S1 PGND Vbus GND 5 R12 33 kΩ C12 220 nF IREF CT C13 100 pF CF R15 C15 1 kΩ C16 220 nF CSW PCS S2 10 nF R47 NM 150 Ω PGND LVS VREF 10 9 13 11 4 D11 PMLL4148L 10 Ω FVDD C17 100 nF SH UBA2014T 2 8 12 6 ACM 4 2.75 mH C20 2 P6 R31 6 P4 X2 P3 PL-C 4P 18 W 68 nF X3 T22 SPS04N60C3 PMLL4148L 10 Ω DIM P5 OUTSIDE CIRCULAR PCB D30 R24 3.3 Ω 16 15 CSP CSN 5 Lb 10 μH 220 pF NM Cres 4.7 nF R22 GL 14 C31 1 nF Lres C19 1 nF D12 12 V C21 La 10 μH 1 Cb 33 nF UVLO 3 R21 47 kΩ C18 PL-C 4P 18 W 470 pF 3 Ca 33 nF T20 SPS04N60C3 R20 GH 1 S3 R46 NM 47 Ω 7 T9 BC849 PGND NLP VDD U1 OVP 10 kΩ R8 10 kΩ R11 220 kΩ C8 220 nF C44 R7 5.6 kΩ R10 220 kΩ C7 10 μF PGND C5 4.7 μF R5 10 kΩ R25 4.7 Ω R23 47 kΩ R26 1.8 Ω R30 30 Ω R27 1.8 Ω R32 30 Ω C30 470 nF D31 1N4937 LAMP CURRENT SENSING PGND 1 kΩ OVP OUTSIDE CIRCULAR PCB R44 D40 PMLL4148L Default settings: S1 shorted S2 shorted S3 open C43 10 nF PGND R43 10 kΩ NLP T41 BC857 R41 3 kΩ R42 3.3 kΩ 47 Ω C42 2.2 nF T40 BC849 NO-LAMP PROTECTION 019aaa348 Fig 2. Schematic diagram high PF dimmable CFL using the UBA2014T UM10409 User manual All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 October 2010 © NXP B.V. 2010. All rights reserved. 4 of 25 UM10409 NXP Semiconductors 120 V high power factor CFL reference board 3. Specifications This section describes the specifications used in the application; see Figure 2. 019aaa692 a. Top view 019aaa693 b. Bottom view Fig 3. UM10409 User manual High power factor 18 W CFL reference board using the UBA2014T All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 October 2010 © NXP B.V. 2010. All rights reserved. 5 of 25 UM10409 NXP Semiconductors 120 V high power factor CFL reference board 3.1 General The UBA2014T high PF reference board powers a Philips PL-C 4P 18 W CFL. The reference board specifications are: • • • • • • • Input voltage range: 120 V (RMS); ± 10 %; 50 Hz or 60 Hz Input power: 24 W at 120 V (RMS) Input current: 200 mA (RMS) for 120 V (RMS) mains input Dimmable to 10 % lamp current (< 10 % lumens) using triac dimmer Power factor > 0.95, efficiency (η) > 75 % Operating frequency 45 Hz; frequency range between 40 kHz and 100 kHz Preheat time: 1200 ms; preheat frequency can be set to fmax or variable using current sensing on the Low-Side (LS) MOSFET for Preheat Current Sensor (PCS) pin • Rectangular board with connectors for mains and CFL and the possibility to break out the circular board (form factor = 45.5 mm) with additional connector pins for mains input and CFL on circular breakout board • Board mounted fused resistor • Complies with safety standards, EMI, RoHS, UL 1993 and UL 94V0 3.2 Protection circuits • • • • No-lamp protection by voltage sensing at LS MOSFET OverVoltage Protection (OVP) on the bus voltage (Vbus) Optional UnderVoltage LockOut (UVLO) Capacitive mode protection 3.3 CFLs tested • • • • • Philips PL-C 4P 18 W Philips PL-C 4P 23 W TCP 18 W Megaman 18 W Baishi 18 W 4. Reference board connections and bill of materials 4.1 Reference board connections Direct board connections: connect 120 V (RMS) to terminal X1 and connect PL-C 4P 18 W CFL filaments to terminals X2 and X3, respectively. Connection to the CFL’s circular board is also possible: 120 V (RMS) is connected between P1 and P2. The CFL filaments are connected between P3/P4 and P5/P6, respectively. If R45 is not needed, it must be short circuited to the mains return line using the solder connection S1. The default is with R45 as NM and S1 short circuited. UM10409 User manual All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 October 2010 © NXP B.V. 2010. All rights reserved. 6 of 25 UM10409 NXP Semiconductors 120 V high power factor CFL reference board The preheat selection can be chosen as follows: • When the PCS pin is set to VREF = 3 V using the solder connection S2, the preheat frequency is fmax (the default setting) • The preheat frequency is set using the current sensing resistors R26/R27 which are connected between the LS MOSFET (T22) and ground. The voltage across the sensing resistor is attenuated by R46/R47 and supplied to the Preheat Current Sensor (PCS) pin using solder connection S3 4.2 Bill Of Materials (BOM) including the PL-C 4P 18 W CFL Table 1. Reference board BOM including the PL-C 4P 18 W CFL Reference Description Remarks Value R1 flameproof power metal film resistor fused resistor; radial 10 Ω; 5 %; 2 W R2 thick film resistor; 1206 SMD 220 kΩ; 1 %; 0.25 W R4 thick film resistor; 0603 SMD 33 kΩ; 5 %; 0.1 W R5 thick film resistor; 0603 SMD 10 kΩ; 5 %; 0.1 W R6 thick film resistor; 1206 SMD 220 kΩ; 1 %; 0.25 W R7 thick film resistor; 0603 SMD 5.6 kΩ; 5 %; 0.1 W R8 thick film resistor; 0603 SMD 10 kΩ; 5 %; 0.1 W R9 thick film resistor; 0603 SMD 10 kΩ; 5 %; 0.1 W R10 thick film resistor; 1206 SMD 220 kΩ; 1 %; 0.25 W R11 thick film resistor; 1206 SMD 220 kΩ; 1 %; 0.25 W R12 thick film resistor; 0603 SMD 33 kΩ; 5 %; 0.1 W R13 thick film resistor; 1206 SMD 220 kΩ; 1 %; 0.25 W R15 thick film resistor; 0603 SMD 1 kΩ; 5 %; 0.1 W R20 thick film resistor; 0603 SMD 10 Ω; 5 %; 0.1 W R21 thick film resistor; 0603 SMD 47 kΩ; 5 %; 0.1 W R22 thick film resistor; 0603 SMD 10 Ω; 5 %; 0.1 W R23 thick film resistor; 0603 SMD 47 kΩ; 5 %; 0.1 W R24 thick film resistor; 0805 SMD 3.3 Ω; 1 %; 0.25 W R25 thick film resistor; 0805 SMD 4.7 Ω; 1 %; 0.25 W R26 thick film resistor; 0805 SMD 1.8 Ω; 1 %; 0.25 W R27 thick film resistor; 0805 SMD 1.8 Ω; 1 %; 0.25 W R30 thick film resistor; 1206 SMD 30 Ω; 1 %; 0.25 W R31 thick film resistor; 0603 SMD 1 kΩ; 5 %; 0.1 W R32 thick film resistor; 1206 SMD 30 Ω; 1 %; 0.25 W R41 thick film resistor; 0603 SMD 3 kΩ; 5 %; 0.1 W R42 thick film resistor; 0603 SMD 3.3 kΩ; 5 %; 0.1 W R43 thick film resistor; 0603 SMD 10 kΩ; 5 %; 0.1 W R44 thick film resistor; 0603 SMD 47 Ω; 5 %; 0.1 W R45 flameproof power metal film resistor fused, radial (NM) 10 Ω; 5 %; 2 W Resistors R46 thick film resistor; 0603 SMD (NM) 47 Ω; 5 %; 0.1 W R47 thick film resistor; 0603 SMD (NM) 150 Ω; 5 %; 0.1 W UM10409 User manual All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 October 2010 © NXP B.V. 2010. All rights reserved. 7 of 25 UM10409 NXP Semiconductors 120 V high power factor CFL reference board Table 1. Reference board BOM including the PL-C 4P 18 W CFL …continued Reference Description Remarks Value C2 polypropylene capacitor; class X2; lead spacing 10 mm interference suppression capacitor; radial 100 nF; 20 %; 310 V (AC) C3 metallized polyester film capacitor; lead spacing 5 mm radial 100 nF; 5 %; 250 V C4, C5 ceramic capacitor; X5R dielectric; 0805 SMD 4.7 μF; 10 %; 25 V C7 aluminium electrolytic capacitor; lead spacing 5 mm bus capacitor; radial 10 μF; 20 %; 450 V Capacitors C8 ceramic capacitor; X7R dielectric; 0805 SMD 220 nF; 5 %; 25 V C12 ceramic capacitor; X7R dielectric; 0603 SMD 220 nF; 10 %; 10 V C13 ceramic capacitor; NP0 dielectric; 0402 SMD 100 pF; 5 %; 50 V C15 ceramic capacitor; X7R dielectric; 0603 SMD 220 nF; 10 %; 10 V C16 ceramic capacitor; X7R dielectric; 0603 SMD 10 nF; 10 %; 50 V C17 ceramic capacitor; X7R dielectric; 0603 SMD 100 nF; 10 %; 50 V C18 ceramic capacitor; lead spacing 5 mm dV/dt; radial 470 pF; 10 %; 1000 V C19 ceramic capacitor; X7R dielectric; 0603 SMD 1 nF; 10 %; 50 V C20 polyester capacitor; lead spacing 10 mm DC blocking capacitor; radial 68 nF; 20 %; 400 V C21 ceramic capacitor; lead spacing 5 mm UVLO; radial (NM) 220 pF; 10 %; 1000 V C30 ceramic capacitor; X5R dielectric; 0603 SMD 470 nF; 10 %; 16 V C31 ceramic capacitor; X7R dielectric; 0603 SMD 1 nF; 10 %; 50 V C42 ceramic capacitor; X7R dielectric; 0603 SMD 2.2 nF; 10 %; 50 V C43 ceramic capacitor; X7R dielectric; 0603 SMD 10 nF; 10 %; 50 V C44 ceramic capacitor; NP0 dielectric; 0402 SMD; shorted - Ca ceramic capacitor; X7R dielectric; 1206 SMD 33 nF; 10 %; 50 V Cb ceramic capacitor; X7R dielectric; 1206 SMD 33 nF; 10 %; 50 V Cres metallized polypropylene film; lead spacing 10 mm resonant capacitor; radial 4.7 nF; 5 %; 1000 V Discrete, integrated components D1, D2, D3, diode; standard; 1 KV; 1 A; DO-41 D4 mains rectifier diode; radial; 1N4007 D5, D6 diode; fast recovery; 1 A; 600 V; DO-41 radial; 1N4937 - D7 diode; high speed; SOD80C SMD; PMLL4148L - D8 diode; 5.1 V Zener; SOD80C SMD; BZV55-C5V1 - D9 diode; high speed; SOD80C SMD; PMLL4148L - D10 diode; 5.1 V Zener; SOD80C SMD; BZV55-C5V1 - D11 diode; high speed; SOD80C SMD; PMLL4148L - D12 diode; 12 V Zener; SOD80C SMD; BZV55-C12V - D30, D31 diode; fast recovery; 1 A; 600 V; DO-41 Radial; 1N4937 - D40 diode; high speed; SOD80C SMD; PMLL4148L - V1 bidirectional diode; SOD323 SMD, transient suppression; PESD15VL1BA - T9 NPN transistor; SOT23 SMD; BC849BL - UM10409 User manual All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 October 2010 © NXP B.V. 2010. All rights reserved. 8 of 25 UM10409 NXP Semiconductors 120 V high power factor CFL reference board Table 1. Reference board BOM including the PL-C 4P 18 W CFL …continued Reference Description Remarks Value T20, T22 half-bridge MOSFETs; PG-TO251-3-11 SPS04N60C3 - T40 NPN transistor; SOT23 SMD; BC849BL - T41 PNP transistor; SOT23 SMD; BC857 - U1 half-bridge controller IC; SO16 UBA2014T - L1 ferrite inductor; 4.7 mH; 5R2; lead spacing 5 mm filter inductor; radial 4.7 mH; 0.26 A; 10 % Lres ferrite inductor; EE20 core; bobbin UL-V0; TP4 core material resonant inductor; Würth part nr. 76080098 - Inductors primary inductance 2.75 mH; 10 % secondary inductance for inductive mode heating - 10 μH; 25 % Lboost ferrite inductor; EE20 core; bobbin UL-V0; TP4 core material; primary inductance boost inductor; Würth 2.75 mH; 10 % part No. 76080098 X1 mains terminal connection outside circular PCB 5 mm; 2-way - X2 CFL filament 1 terminal connection outside circular PCB 5 mm, 2-way - X3 CFL filament 2 terminal connection outside circular PCB 5 mm, 2-way - P1, P2 isolated test pins for mains inputs inside circular PCB PK100 - P3, P4 isolated test pins for CFL filament 1 connection inside circular PCB PK100 - P5, P6 isolated test pins for CFL filament 2 connection inside circular PCB PK100 - UM10409 User manual All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 October 2010 © NXP B.V. 2010. All rights reserved. 9 of 25 UM10409 NXP Semiconductors 120 V high power factor CFL reference board 5. Measurements 5.1 Preheat and Sum of Squares (SoS) The hot to cold filament ratio (Rratio) for the Philips PL-C 4P 18 W CFL was initially measured using a variable DC voltage source across the filament. Preheat is sufficient when Rratio is approximately 5 : 1 (which is equivalent to a Vfilament of ±7.5 V). 019aaa694 6 Rratio 4 2 0 0 2 4 6 8 10 Vfilament (V) Fig 4. Ratio of hot to cold filament resistance against filament voltage for the PL-C 4P 18 W CFL The preheat waveforms for the reference board are shown in Figure 5. Vfilament of 7.4 V (RMS) and Ifilament of 235 mA (RMS) are measured at the end of the preheat timer period giving a power supply to the filament of approximately 1.7 W. UM10409 User manual All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 October 2010 © NXP B.V. 2010. All rights reserved. 10 of 25 UM10409 NXP Semiconductors 120 V high power factor CFL reference board tph Vfilament Ifilament 019aaa695 Fig 5. Preheat waveforms at end of preheat timer period for PL-C 4P 18 W CFL The preheat frequency is set at 100 kHz by connecting pin VREF = 3 V to the PCS pin. The preheat time is set to 1.2 s using: ⎛ C CT ⎞ ⎛ R IREF ⎞ -⎟ ⎜ ------------------⎟ t ph = 1.8 × ⎜ ----------------------⎝ 330 ⋅ 10 –9⎠ ⎝ 33 ⋅ 10 3⎠ (1) where CCT = 220 nF and RIREF = 33 kΩ. The preheat frequency can also be set by the current sensing resistors (see R26/R27 on Figure 2 on page 4) which are connected between the LS MOSFET and ground. The voltage across the sensing resistors is attenuated (R46/R47) and then supplied to the Preheat Current Sensor (PCS) pin using solder connection S3. As an example, with R26/R27 = 1.8 Ω, R46 = 47 Ω and R47 open, the preheat frequency is approximately 70 kHz and the measured power supplied to the filaments is 3.2 W (Vfilament = 10 V (RMS) and Ifilament = 320 mA (RMS)) which is too high. In addition, the Vbus voltage exceeds 400 V (DC) (the rating of bus voltage) during the preheat time period. The preheat frequency could be set higher by changing R26/R27 and the power to the filaments could be reduced by decreasing the preheat time. However, a preheat time of less than 0.4 s is not recommended. Setting the preheat frequency to the maximum frequency for this application with the PL-C 4P 18 W CFL, is the default (and optimum) setting. UM10409 User manual All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 October 2010 © NXP B.V. 2010. All rights reserved. 11 of 25 UM10409 NXP Semiconductors 120 V high power factor CFL reference board The Sum of Squares (SoS) gives a measure of the amount of heat that should be generated in the filaments to maintain the correct operating temperature. SoS is expressed by Equation 2: 2 2 (2) SoS = I LH + I LL where ILH is the lead-high current or total current supplied to the filament and ILL is the lead-low or filament heating current (see Figure 6). ILH ILH Ilamp ILL Rfilament ILL Rfilament 019aaa696 Fig 6. CFL electrode currents The SoS curve shown in Figure 7 was measured over a dimming range of 20 mA to 180 mA lamp current. 019aaa697 0.12 (1) SoS 0.08 (2) (3) (4) 0.04 0 0 0.05 0.10 0.15 0.20 llamp (mA) (1) SoS maximum. (2) SoS target. (3) SoS measured. (4) SoS minimum. Fig 7. SoS for PL-C 4P 18 W In Figure 8 and Figure 9, the waveforms for ILH and ILL are shown for both 180 mA and 20 mA lamp currents, measured with a current probe around the lead in wires. Ilamp is measured by taking both lead in wires through the current probe. UM10409 User manual All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 October 2010 © NXP B.V. 2010. All rights reserved. 12 of 25 UM10409 NXP Semiconductors 120 V high power factor CFL reference board ILL Ilamp ILH 019aaa698 Fig 8. ILL, Ilamp and ILH for Ilamp = 180 mA ILL Ilamp ILH 019aaa699 Fig 9. UM10409 User manual ILL, Ilamp and ILH for Ilamp = 20 mA All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 October 2010 © NXP B.V. 2010. All rights reserved. 13 of 25 UM10409 NXP Semiconductors 120 V high power factor CFL reference board 5.2 Preheat and lamp ignition After the preheat timer period of 1.2 s, the frequency sweeps down from fmax to fmin where fmin and fmax are calculated using Equation 3 and Equation 4, respectively. Ignition occurs when the minimum lamp ignition voltage is exceeded. – 12 3 33 × 10 3 100 × 10 f min = 40.5 × 10 × ---------------------------- × -------------------C CF R IREF (3) f max = 2.5 × f min (4) where CCF = 100 pF and RIREF = 33 kΩ The maximum preheat voltage must be less than the minimum lamp ignition voltage. In this application, the preheat frequency is set to maximum (100 kHz) during the preheat timer period which avoids overlapping of the maximum preheat voltage and minimum lamp ignition voltage will not occur. The maximum lamp ignition voltage must be reached before fmin is reached. The measured ignition voltage at 25 °C is shown in Figure 10. Vbus Vlamp tph 019aaa700 Fig 10. Preheat and lamp ignition waveforms 5.3 Efficiency, Power Factor (PF) Using a mains input voltage of 120 V (RMS), the input current is 200 mA (RMS) and the input power is 24 W. The losses are: • Fused resistor 10 Ω is 0.4 W UM10409 User manual All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 October 2010 © NXP B.V. 2010. All rights reserved. 14 of 25 UM10409 NXP Semiconductors 120 V high power factor CFL reference board • • • • 4.7 mH EMI coil (RDC = 5.2 Ω) is 0.5 W Lboost (RDC = 9 Ω, Iboost = 260 mA (RMS)) is 0.6 W Lres (RDC = 9 Ω, ILres = 275 mA (RMS)) is 0.7 W High-Side (HS) MOSFET (RDS(on) = 2.3 Ω, II = 275 mA (RMS)) is 0.2 W and Low-Side (LS) MOSFET (RDS(on) = 2.3 Ω, II = 360 mA (RMS)) is 0.3 W. The dissipation is 0.5 W for both MOSFETs. The waveforms shown in Figure 11 and Figure 12 • Each filament (Rfilament = 35 Ω, Ifilament = 175 mA) is 1.1 W, both filaments is 2.2 W Po Total losses are approximately 5 W. The efficiency is ------- = 80 %. P in Table 2. Parameter Extra measurements for 120 V (±10%) for 50 Hz and 60Hz 120 V (RMS)/50 Hz −10 (%) nominal 120 V (RMS)/60 Hz +10% (%) −10 (%) nominal +10% (%) Pin (W) 21.5 26.5 30 21.5 25.5 30 Plamp (W) 17.5 20.5 22.5 17.5 20.5 23 PF 0.99 0.99 0.99 0.99 0.99 0.99 CF 1.7 1.65 1.7 1.65 1.6 1.65 THD (%) 11 10.5 11 11.5 10 10.5 η (%) 81 77 75 81 80 77 5.4 MOSFET, boost and resonant inductor currents HS MOSFET current 019aaa701 Fig 11. HS MOSFET current UM10409 User manual All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 October 2010 © NXP B.V. 2010. All rights reserved. 15 of 25 UM10409 NXP Semiconductors 120 V high power factor CFL reference board LS MOSFET current 019aaa702 Fig 12. LS MOSFET current The current in the HS MOSFET is the sum of the boost inductor and resonant inductor currents when the HS MOSFET is conducting. Similarly, the current in the LS MOSFET is the sum of the boost inductor current and resonant inductor current when the LS MOSFET is conducting as shown in Figure 11 and Figure 12. The sum of boost inductor and resonant inductor current which is Iboost + ILres is shown in Figure 13 and amounts to 460 mA (RMS) when measured over one cycle of the mains input. UM10409 User manual All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 October 2010 © NXP B.V. 2010. All rights reserved. 16 of 25 UM10409 NXP Semiconductors 120 V high power factor CFL reference board Iboost + ILres 019aaa703 Fig 13. Iboost + ILres 5.5 Overvoltage protection circuit It is necessary to have OverVoltage Protection (OVP) to protect the bus capacitance and MOSFETs from voltage transients greater than their rated values. The steady state voltage on the bus capacitance C7 = 10 μF (see Figure 2) is described by Equation 5: 120 2 V P = ---------------1–δ (5) where Pboost = Plamp and δ is a 50 % duty cycle. If Pboost > Plamp, as is in the case of deep dimming when there is a small load, the bus voltage can rise above the rated bus capacitance value. The OVP circuit is designed to start operating when the bus voltage is greater than an OVP level of approximately 400 V. The OVP circuit then reduces the CSN pin voltage by 10 % (set by R9 in Figure 2) and the half-bridge frequency decreases implying that Plamp increases and the bus voltage decreases under the OVP level. When testing with different dimmers and for fast transient steps in the triac dimmer, the bus voltage did not rise above 400 V (DC). However, the OVP circuit was tested by supplying an external step on the bus voltage to the OVP circuit from 0 V (DC) to 410 V (DC) and at approximately 400 V (DC) the voltage on the CSN pin decreased by 10 %. The waveforms of the bus voltage to the OVP circuit and voltage at the CSN pin are shown in Figure 14. UM10409 User manual All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 October 2010 © NXP B.V. 2010. All rights reserved. 17 of 25 UM10409 NXP Semiconductors 120 V high power factor CFL reference board Vbus VCSN 019aaa704 Fig 14. OVP circuit test with bus voltage and voltage at CSP pin 5.6 No-lamp detection When a lamp is not connected, the voltage across the resonant capacitor continues to rise as the frequency sweeps down after preheat. The current in the MOSFETs can become excessive causing eventual damage to the internal drivers in the UBA2014T and external MOSFETs. The no-lamp detection/latch circuit monitors the voltage (VSENSE) across the sense resistor (parallel combination of R26/R27 which is 0.9 Ω) and thus, the current through the LS MOSFET. The resistors R26 and R27 are connected between the LS MOSFET source and ground as shown in Figure 2. When no-lamp is connected this voltage rises as the frequency sweeps down after the preheat time. The no-lamp detection/latch circuit is designed (using R41, R42 and R26, R27 in Figure 2) to trigger the latch and pull VDD to ground when the voltage across the lamp terminals exceeds approximately 2.5 times the ignition voltage. The relevant waveforms are shown in Figure 15. The no-lamp protection circuit is reset by removing the mains voltage. UM10409 User manual All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 October 2010 © NXP B.V. 2010. All rights reserved. 18 of 25 UM10409 NXP Semiconductors 120 V high power factor CFL reference board Vlamp VDD tph VSENSE 019aaa705 Fig 15. Waveforms for Vlamp, VDD, preheat time (tph) and VSENSE (across sense resistors R26, R27) UM10409 User manual All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 October 2010 © NXP B.V. 2010. All rights reserved. 19 of 25 UM10409 NXP Semiconductors 120 V high power factor CFL reference board 5.7 EMI prescan measurements 019aaa706 Fig 16. EN55015Q and EN55015A conducted EMI measurements, 120 V, 60 Hz mains input UM10409 User manual All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 October 2010 © NXP B.V. 2010. All rights reserved. 20 of 25 UM10409 NXP Semiconductors 120 V high power factor CFL reference board 6. Inductor specification 3 La 4 2 6 Lres, Lboost 1 Lb 5 019aaa728 Fig 17. Inductor schematic Table 3. Electrical characteristics Parameter Inductance (mH) Resistance Rated current (Ω) (A) Saturation current (A) Lres 2.75 ±10 % 9 0.35 1.1 La, Lb 0.010 ±25 % 0.495 - - Lboost 2.7 5 ±10 % 9 0.35 1.1 7. PCB layout The following should be taken into account for the PCB layout: • Separate ground of bridge rectifier back to bus capacitance (C7) ground (PGND in Figure 2) • Components on pins 1 to 4 close to the UBA2014T and their grounding should be closely routed back to pin 5 of the UBA2014T (GND in Figure 2) • Pin 5 (GND) of the UBA2014T should be routed back separately to C7 ground to minimize influence of PGND on GND • Inductors Lboost, Lres and L1 should not be placed near the UBA2014T to minimize the magnetic field interference to the IC • The grounding of both the lamp current sensing circuit and dim control should be connected closely together with separate routing back to bus capacitance (C7) ground (PGND) • External MOSFETs close to Lres, Lboost and bus capacitance so as to have small current loops • The half-bridge node tracks to Lres, Lboost and pin 11 of UBA2014T should be short to minimize interference from the half-bridge dV/dt voltage • Sense resistors (R26/R27) ground routed back separately to C7 ground (PGND) • ACM sense resistors (R24/R25) close to pin 12 (ACM) of UBA2014T and their grounding routed back separately to C7 ground (PGND) UM10409 User manual All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 October 2010 © NXP B.V. 2010. All rights reserved. 21 of 25 UM10409 NXP Semiconductors 120 V high power factor CFL reference board 019aaa710 Fig 18. PCB bottom layer 019aaa709 Fig 19. PCB top layer UM10409 User manual All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 October 2010 © NXP B.V. 2010. All rights reserved. 22 of 25 UM10409 NXP Semiconductors 120 V high power factor CFL reference board 8. Legal information 8.1 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 8.2 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product UM10409 User manual design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Evaluation products — This product is provided on an “as is” and “with all faults” basis for evaluation purposes only. NXP Semiconductors, its affiliates and their suppliers expressly disclaim all warranties, whether express, implied or statutory, including but not limited to the implied warranties of non-infringement, merchantability and fitness for a particular purpose. The entire risk as to the quality, or arising out of the use or performance, of this product remains with customer. In no event shall NXP Semiconductors, its affiliates or their suppliers be liable to customer for any special, indirect, consequential, punitive or incidental damages (including without limitation damages for loss of business, business interruption, loss of use, loss of data or information, and the like) arising out the use of or inability to use the product, whether or not based on tort (including negligence), strict liability, breach of contract, breach of warranty or any other theory, even if advised of the possibility of such damages. Notwithstanding any damages that customer might incur for any reason whatsoever (including without limitation, all damages referenced above and all direct or general damages), the entire liability of NXP Semiconductors, its affiliates and their suppliers and customer’s exclusive remedy for all of the foregoing shall be limited to actual damages incurred by customer based on reasonable reliance up to the greater of the amount actually paid by customer for the product or five dollars (US$5.00). The foregoing limitations, exclusions and disclaimers shall apply to the maximum extent permitted by applicable law, even if any remedy fails of its essential purpose. 8.3 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 October 2010 © NXP B.V. 2010. All rights reserved. 23 of 25 UM10409 NXP Semiconductors 120 V high power factor CFL reference board 9. Figures Fig 1. Fig 2. Fig 3. Fig 4. Fig 5. Fig 6. Fig 7. Fig 8. Fig 9. Fig 10. Fig 11. Fig 12. Fig 13. Fig 14. Fig 15. Fig 16. Fig 17. Fig 18. Fig 19. Variac isolation symbols. . . . . . . . . . . . . . . . . . . . .3 Schematic diagram high PF dimmable CFL using the UBA2014T . . . . . . . . . . . . . . . . . . .4 High power factor 18 W CFL reference board using the UBA2014T . . . . . . . . . . . . . . . . . . . . . . .5 Ratio of hot to cold filament resistance against filament voltage for the PL-C 4P 18 W CFL. . . . .10 Preheat waveforms at end of preheat timer period for PL-C 4P 18 W CFL . . . . . . . . . . . . . . . 11 CFL electrode currents . . . . . . . . . . . . . . . . . . . .12 SoS for PL-C 4P 18 W . . . . . . . . . . . . . . . . . . . . .12 ILL, Ilamp and ILH for Ilamp = 180 mA . . . . . . . . . . .13 ILL, Ilamp and ILH for Ilamp = 20 mA . . . . . . . . . . . .13 Preheat and lamp ignition waveforms . . . . . . . . .14 HS MOSFET current . . . . . . . . . . . . . . . . . . . . . .15 LS MOSFET current . . . . . . . . . . . . . . . . . . . . . .16 Iboost + ILres . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 OVP circuit test with bus voltage and voltage at CSP pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Waveforms for Vlamp, VDD, preheat time (tph) and VSENSE (across sense resistors R26, R27) . .19 EN55015Q and EN55015A conducted EMI measurements, 120 V, 60 Hz mains input . . . . . .20 Inductor schematic. . . . . . . . . . . . . . . . . . . . . . . .21 PCB bottom layer. . . . . . . . . . . . . . . . . . . . . . . . .22 PCB top layer . . . . . . . . . . . . . . . . . . . . . . . . . . .22 UM10409 User manual All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 October 2010 © NXP B.V. 2010. All rights reserved. 24 of 25 UM10409 NXP Semiconductors 120 V high power factor CFL reference board 10. Contents 1 2 3 3.1 3.2 3.3 4 4.1 4.2 5 5.1 5.2 5.3 5.4 5.5 5.6 5.7 6 7 8 8.1 8.2 8.3 9 10 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . 4 Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . 5 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Protection circuits . . . . . . . . . . . . . . . . . . . . . . . 6 CFLs tested . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Reference board connections and bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Reference board connections. . . . . . . . . . . . . . 6 Bill Of Materials (BOM) including the PL-C 4P 18 W CFL . . . . . . . . . . . . . . . . . . . . . . 7 Measurements . . . . . . . . . . . . . . . . . . . . . . . . . 10 Preheat and Sum of Squares (SoS) . . . . . . . . 10 Preheat and lamp ignition . . . . . . . . . . . . . . . . 14 Efficiency, Power Factor (PF) . . . . . . . . . . . . . 14 MOSFET, boost and resonant inductor currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Overvoltage protection circuit . . . . . . . . . . . . . 17 No-lamp detection . . . . . . . . . . . . . . . . . . . . . 18 EMI prescan measurements. . . . . . . . . . . . . . 20 Inductor specification . . . . . . . . . . . . . . . . . . . 21 PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Legal information. . . . . . . . . . . . . . . . . . . . . . . 23 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 12 October 2010 Document identifier: UM10409