DF N 20 20 MD -6 PMPB40SNA 60 V N-channel Trench MOSFET 29 October 2013 Product data sheet 1. General description N-channel enhancement mode Field-Effect Transistor (FET) in a leadless medium power DFN2020MD-6 (SOT1220) Surface-Mounted Device (SMD) plastic package using Trench MOSFET technology. 2. Features and benefits • • • • • Trench MOSFET technology Small and leadless ultra thin SMD plastic package: 2 x 2 x 0.65 mm Exposed drain pad for excellent thermal conduction Tin-plated 100 % solderable side pads for optical solder inspection AEC-Q101 qualified 3. Applications • • • • Relay driver High-speed line driver Low-side load switch Switching circuits 4. Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage Tj = 25 °C - - 60 V VGS gate-source voltage -20 - 20 V ID drain current VGS = 10 V; Tsp = 25 °C - - 12.9 A VGS = 10 V; ID = 4.8 A; Tj = 25 °C - 34 43 mΩ Static characteristics RDSon drain-source on-state resistance Scan or click this QR code to view the latest information for this product PMPB40SNA NXP Semiconductors 60 V N-channel Trench MOSFET 5. Pinning information Table 2. Pinning information Pin Symbol Description 1 D drain 2 D drain 3 G gate 4 S source 5 D drain 6 D drain 7 D drain 8 S source Simplified outline 1 Graphic symbol D 6 7 2 3 8 5 G 4 S 017aaa253 Transparent top view DFN2020MD-6 (SOT1220) 6. Ordering information Table 3. Ordering information Type number Package Name PMPB40SNA Description Version DFN2020MD-6 DFN2020MD-6: plastic thermal enhanced ultra thin small outline package; no leads; 6 terminals SOT1220 7. Marking Table 4. Marking codes Type number Marking code PMPB40SNA 1E 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage Tj = 25 °C - 60 V VGS gate-source voltage -20 20 V ID drain current - 12.9 A IDM peak drain current PMPB40SNA Product data sheet VGS = 10 V; Tsp = 25 °C VGS = 10 V; Tamb = 25 °C; t ≤ 5 s [1] - 6.8 A VGS = 10 V; Tamb = 100 °C [1] - 3 A - 23 A Tamb = 25 °C; single pulse; tp ≤ 10 µs All information provided in this document is subject to legal disclaimers. 29 October 2013 © NXP N.V. 2013. All rights reserved 2 / 15 PMPB40SNA NXP Semiconductors 60 V N-channel Trench MOSFET Symbol Parameter Conditions Min Max Unit EDS(AL)S non-repetitive drain-source avalanche energy Tj(init) = 25 °C; ID = 0.6 A; DUT in - 19 mJ total power dissipation Tamb = 25 °C [1] - 1.7 W Tamb = 25 °C; t ≤ 5 s [1] - 3.5 W - 12.5 W Ptot avalanche (unclamped) Tsp = 25 °C Tj junction temperature -55 150 °C Tamb ambient temperature -55 150 °C Tstg storage temperature -65 150 °C - 1.7 A Source-drain diode IS source current [1] Tamb = 25 °C [1] Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated, mounting pad for 2 drain 6 cm . 017aaa123 120 Pder (%) Ider (%) 80 80 40 40 0 - 75 Fig. 1. 017aaa124 120 - 25 25 75 125 Tj (°C) Normalized total power dissipation as a function of junction temperature PMPB40SNA Product data sheet 0 - 75 175 Fig. 2. - 25 75 125 Tj (°C) 175 Normalized continuous drain current as a function of junction temperature All information provided in this document is subject to legal disclaimers. 29 October 2013 25 © NXP N.V. 2013. All rights reserved 3 / 15 PMPB40SNA NXP Semiconductors 60 V N-channel Trench MOSFET aaa-005311 102 ID (A) Limit RDSon = VDS/ID 10 tp = 100 µs tp = 1 ms 1 tp = 10 ms DC; Tsp = 25 °C 10-1 DC; Tamb = 25 °C; drain mounting pad 6 cm2 10-2 10-2 10-1 1 tp = 100 ms 102 10 103 VDS (V) IDM = single pulse Fig. 3. Safe operating area; junction to ambient; continuous and peak drain currents as a function of drainsource voltage 9. Thermal characteristics Table 6. Thermal characteristics Symbol Parameter Conditions Rth(j-a) thermal resistance from junction to ambient in free air Rth(j-sp) thermal resistance from junction to solder point PMPB40SNA Product data sheet Min Typ Max Unit [1] - 235 270 K/W [2] - 67 74 K/W [3] - 33 36 K/W - 5 10 K/W [1] [2] Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint. [3] Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for drain 6 cm , t ≤ 5 s 2 Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for drain 6 cm . 2 All information provided in this document is subject to legal disclaimers. 29 October 2013 © NXP N.V. 2013. All rights reserved 4 / 15 PMPB40SNA NXP Semiconductors 60 V N-channel Trench MOSFET 017aaa542 103 Zth(j-a) (K/W) duty cycle = 1 0.75 102 0.5 0.33 0.25 0.2 0.1 10 0.05 0.02 0.01 0 1 10-3 10-2 10-1 1 102 10 103 tp (s) FR4 PCB, standard footprint Fig. 4. Transient thermal impedance from junction to ambient as a function of pulse duration; typical values 017aaa543 103 Zth(j-a) (K/W) 102 duty cycle = 1 0.75 0.5 0.33 10 0.25 0.2 0.1 0.05 0.02 0.01 0 1 10-3 10-2 10-1 FR4 PCB, mounting pad for drain 6 cm Fig. 5. 1 102 10 103 tp (s) 2 Transient thermal impedance from junction to ambient as a function of pulse duration; typical values 10. Characteristics Table 7. Characteristics Symbol Parameter Conditions Min Typ Max Unit Static characteristics V(BR)DSS drain-source breakdown voltage ID = 250 µA; VGS = 0 V; Tj = 25 °C 60 - - V VGSth gate-source threshold voltage ID = 250 µA; VDS = VGS; Tj = 25 °C 1 1.7 3 V IDSS drain leakage current VDS = 60 V; VGS = 0 V; Tj = 25 °C - - 1 µA VDS = 60 V; VGS = 0 V; Tj = 150 °C - - 20 µA PMPB40SNA Product data sheet All information provided in this document is subject to legal disclaimers. 29 October 2013 © NXP N.V. 2013. All rights reserved 5 / 15 PMPB40SNA NXP Semiconductors 60 V N-channel Trench MOSFET Symbol Parameter Conditions Min Typ Max Unit IGSS gate leakage current VGS = 20 V; VDS = 0 V; Tj = 25 °C - - 100 nA VGS = -20 V; VDS = 0 V; Tj = 25 °C - - -100 nA VGS = 10 V; ID = 4.8 A; Tj = 25 °C - 34 43 mΩ VGS = 10 V; ID = 4.8 A; Tj = 150 °C - 60 75 mΩ VGS = 4.5 V; ID = 3.2 A; Tj = 25 °C - 40 50 mΩ RDSon drain-source on-state resistance gfs forward transconductance VDS = 5 V; ID = 4.8 A; Tj = 25 °C - 19 - S RG gate resistance f = 1 MHz - 1.1 - Ω Dynamic characteristics QG(tot) total gate charge VDS = 30 V; ID = 4.8 A; VGS = 10 V; - 12.1 24 nC QGS gate-source charge Tj = 25 °C - 1.4 - nC QGD gate-drain charge - 2.1 - nC Ciss input capacitance VDS = 30 V; f = 1 MHz; VGS = 0 V; - 612 - pF Coss output capacitance Tj = 25 °C - 78 - pF Crss reverse transfer capacitance - 52 - pF td(on) turn-on delay time VDS = 30 V; ID = 4.8 A; VGS = 4.5 V; - 9 - ns tr rise time RG(ext) = 6 Ω; Tj = 25 °C - 23 - ns td(off) turn-off delay time - 12 - ns tf fall time - 12 - ns - 0.9 1.2 V Source-drain diode VSD source-drain voltage IS = 1.7 A; VGS = 0 V; Tj = 25 °C aaa-005312 25 10 V ID (A) 3.4 V 3.6 V ID (A) 4.5 V 20 aaa-005313 10-3 3.2 V 10-4 15 10 2.8 V 5 0 Fig. 6. min typ max 3V 10-5 VGS = 2.6 V 0 1 2 3 4 VDS (V) 5 10-6 0 1 2 VGS (V) 3 Tj = 25 °C Tj = 25 °C; VDS = 5 V Output characteristics: drain current as a Fig. 7. function of drain-source voltage; typical values Subthreshold drain current as a function of gate-source voltage PMPB40SNA Product data sheet All information provided in this document is subject to legal disclaimers. 29 October 2013 © NXP N.V. 2013. All rights reserved 6 / 15 PMPB40SNA NXP Semiconductors 60 V N-channel Trench MOSFET aaa-005314 100 RDSon (mΩ) 2.7 V 80 2.9 V 2.8 V 3.1 V 3V aaa-005315 120 RDSon (mΩ) 3.3 V 3.2 V 80 60 Tj = 150 °C 4.5 V 40 40 VGS = 10 V Tj = 25 °C 20 0 0 5 10 15 20 ID (A) 0 25 Tj = 25 °C Fig. 8. 0 4 8 12 16 20 VGS (V) ID = 5 A Drain-source on-state resistance as a function of drain current; typical values Fig. 9. aaa-005316 25 Drain-source on-state resistance as a function of gate-source voltage; typical values aaa-005317 2.0 ID (A) a 20 1.5 15 1.0 10 0.5 5 0 Tj = 150 °C 0 1 2 Tj = 25 °C 3 VGS (V) 0.0 -60 4 VDS > ID × RDSon Fig. 10. Transfer characteristics: drain current as a function of gate-source voltage; typical values PMPB40SNA Product data sheet 0 60 120 Tj (°C) 180 Fig. 11. Normalized drain-source on-state resistance as a function of junction temperature; typical values All information provided in this document is subject to legal disclaimers. 29 October 2013 © NXP N.V. 2013. All rights reserved 7 / 15 PMPB40SNA NXP Semiconductors 60 V N-channel Trench MOSFET aaa-005318 4 aaa-005319 103 Ciss VGS(th) (V) 3 C (pF) max Coss 102 2 typ Crss 1 min 0 -60 0 60 120 Tj (°C) 10 10-1 180 ID = 0.25 mA; VDS = VGS 1 10 VDS (V) 102 f = 1 MHz; VGS = 0 V Fig. 12. Gate-source threshold voltage as a function of junction temperature Fig. 13. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values aaa-005320 10 VDS VGS (V) ID 8 VGS(pl) 6 VGS(th) VGS 4 QGS1 QGS2 QGS 2 QGD QG(tot) 017aaa137 0 0 5 10 QG (nC) 15 Fig. 15. Gate charge waveform definitions ID = 5 A; VDS = 30 V; Tamb = 25 °C Fig. 14. Gate-source voltage as a function of gate charge; typical values PMPB40SNA Product data sheet All information provided in this document is subject to legal disclaimers. 29 October 2013 © NXP N.V. 2013. All rights reserved 8 / 15 PMPB40SNA NXP Semiconductors 60 V N-channel Trench MOSFET aaa-005321 20 IS (A) 16 12 Tj = 150 °C 8 Tj = 25 °C 4 0 0.0 0.4 0.8 VDS (V) 1.2 VGS = 0 V Fig. 16. Source current as a function of source-drain voltage; typical values 11. Test information P t2 duty cycle δ = t1 t2 t1 t 006aaa812 Fig. 17. Duty cycle definition 11.1 Quality information This product has been qualified in accordance with the Automotive Electronics Council (AEC) standard Q101 - Stress test qualification for discrete semiconductors, and is suitable for use in automotive applications. PMPB40SNA Product data sheet All information provided in this document is subject to legal disclaimers. 29 October 2013 © NXP N.V. 2013. All rights reserved 9 / 15 PMPB40SNA NXP Semiconductors 60 V N-channel Trench MOSFET 12. Package outline DFN2020MD-6: plastic thermal enhanced ultra thin small outline package; no leads; 6 terminals; body 2 x 2 x 0.65 mm SOT1220 (8×) pin 1 index area B E A X D A A1 detail X solderable lead end protrusion max. 0.02 mm (6×) C Lp E2 J1 D2 3 4 2 5 e J bp (6×) D1 e 1 v E1 0 2 mm scale Dimensions (mm are the original dimensions) Unit A A1 bp min 0.25 nom max 0.65 0.04 0.35 D D1 D2 E E1 E2 1.9 1.0 0.2 1.9 1.1 0.51 2.1 1.2 0.3 2.1 1.3 0.61 e J J1 0.65 0.27 0.64 Lp 0.2 0.3 v y y1 0.1 0.05 0.1 Note 1. Dimension A is including plating thickness. Outline version A B 6 pin 1 index area mm y y1 C sot1220_po References IEC JEDEC JEITA European projection Issue date 12-04-23 12-04-30 SOT1220 Fig. 18. Package outline DFN2020MD-6 (SOT1220) PMPB40SNA Product data sheet All information provided in this document is subject to legal disclaimers. 29 October 2013 © NXP N.V. 2013. All rights reserved 10 / 15 PMPB40SNA NXP Semiconductors 60 V N-channel Trench MOSFET 13. Soldering Footprint information for reflow soldering of DFN2020MD-6 package 0.33 (6×) SOT1220 0.76 0.43 (6×) 0.66 0.53 (6×) 0.56 0.25 0.35 0.45 0.775 0.65 2.06 0.285 1.25 1.35 0.35 (6×) 1.05 0.25 (6×) 0.65 0.45 (6×) 0.9 1.1 1.2 0.935 0.935 2.5 solder land solder land plus solder paste solder paste deposit solder resist occupied area Dimensions in mm sot1220_fr Fig. 19. Reflow soldering footprint for DFN2020MD-6 (SOT1220) PMPB40SNA Product data sheet All information provided in this document is subject to legal disclaimers. 29 October 2013 © NXP N.V. 2013. All rights reserved 11 / 15 PMPB40SNA NXP Semiconductors 60 V N-channel Trench MOSFET 14. Revision history Table 8. Revision history Data sheet ID Release date Data sheet status Change notice Supersedes PMPB40SNA v.3 20131029 Product data sheet - PMPB40SNA v.2 Modifications: • PMPB40SNA v.2 20130702 Product data sheet - PMPB40SNA v.1 PMPB40SNA v.1 20120928 Product data sheet - - PMPB40SNA Product data sheet Figure 8 corrected All information provided in this document is subject to legal disclaimers. 29 October 2013 © NXP N.V. 2013. All rights reserved 12 / 15 PMPB40SNA NXP Semiconductors 60 V N-channel Trench MOSFET In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. 15. 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Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. All information provided in this document is subject to legal disclaimers. 29 October 2013 © NXP N.V. 2013. All rights reserved 13 / 15 PMPB40SNA NXP Semiconductors 60 V N-channel Trench MOSFET No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Adelante, Bitport, Bitsound, CoolFlux, CoReUse, DESFire, EZ-HV, FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE, ITEC, Labelution, MIFARE, MIFARE Plus, MIFARE Ultralight, MoReUse, QLPAK, Silicon Tuner, SiliconMAX, SmartXA, STARplug, TOPFET, TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V. HD Radio and HD Radio logo — are trademarks of iBiquity Digital Corporation. PMPB40SNA Product data sheet All information provided in this document is subject to legal disclaimers. 29 October 2013 © NXP N.V. 2013. All rights reserved 14 / 15 PMPB40SNA NXP Semiconductors 60 V N-channel Trench MOSFET 16. Contents 1 General description ............................................... 1 2 Features and benefits ............................................1 3 Applications ........................................................... 1 4 Quick reference data ............................................. 1 5 Pinning information ............................................... 2 6 Ordering information ............................................. 2 7 Marking ................................................................... 2 8 Limiting values .......................................................2 9 Thermal characteristics .........................................4 10 Characteristics ....................................................... 5 11 11.1 Test information ..................................................... 9 Quality information ............................................... 9 12 Package outline ................................................... 10 13 Soldering .............................................................. 11 14 Revision history ................................................... 12 15 15.1 15.2 15.3 15.4 Legal information .................................................13 Data sheet status ............................................... 13 Definitions ...........................................................13 Disclaimers .........................................................13 Trademarks ........................................................ 14 © NXP N.V. 2013. All rights reserved For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 29 October 2013 PMPB40SNA Product data sheet All information provided in this document is subject to legal disclaimers. 29 October 2013 © NXP N.V. 2013. All rights reserved 15 / 15