Power Management Texas Instruments Incorporated LDO noise examined in detail By Masashi Nogawa Senior Systems Engineer, Linear Regulators Introduction Requirements and expectations for telecommunication systems continue to evolve as complexity and reliability of the communication channels continue to increase. These communication systems rely heavily on high-performance, high-speed clocking and data-converter devices. The perform ance of these devices is highly dependent on the quality of system power rails. A clock or converter IC simply cannot achieve top performance when powered by a dirty power supply. Just a small amount of noise on the power supply can cause dramatic negative effects on the performance. This article examines a basic LDO topology to find its dominant noise sources and suggests ways to minimize its output noise. A key parameter indicating the quality of a power supply is its noise output, which is commonly referred by the RMS noise measurement or by the spectral noise density. For the lowest RMS noise or the best spectral noise characteristics, a linear voltage regulator like a low-dropout voltage regulator (LDO) always has an advantage over a switching regulator. This makes it the power supply of choice for noise-critical applications. Figure 1. Negative-feedback loop of LDO VIN + Error Amp – NFET VGATE + VREF OUT Node ( VOUT) – COUT R1 FB Node (VFB ) R2 Figure 2. Reference-voltage buffering of LDO Basic LDO topology VIN A simple linear voltage regulator consists of a basic control loop where a negative feedback is compared to an internal reference in order to provide a constant voltage—regardless of changes or perturbations in the input voltage, temperature, or + load current. – Figure 1 shows a basic block diagram of an LDO regulator. The red arrow indicates the negativefeedback signal path. The output voltage, VOUT, is divided by feedback resistors R1 and R2 to provide the feedback voltage, VFB. VFB is compared to the reference voltage, VREF, at the negative input of the error amplifier to supply the gate-drive voltage, VGATE. Finally, the error signal drives the output transistor, NFET, to regulate VOUT. A simplified analysis of noise begins with Figure 2. The blue arrow traces a subset of the loop represented by a common amplifier variation known as a voltage follower or power buffer. This voltage-follower circuit forces VOUT to follow VREF. VFB is the error signal referring to VREF. In steady state, VOUT is bigger than VREF, as described in Equation 1: + Error Amp – NFET VGATE VREF OUT Node ( VOUT) COUT R1 FB Node (VFB ) R2 R1 VOUT = 1 + × VREF , R2 (1) where 1 + R1/R2 is the gain that the error amplifier must have to obtain the steady-state output voltage (VOUT). 14 High-Performance Analog Products www.ti.com/aaj 4Q 2012 Analog Applications Journal Power Management Texas Instruments Incorporated Suppose the voltage reference is not ideal and has an effective noise factor, VN(REF), on its DC output voltage (VREF). Assuming all circuit blocks in Figure 2 are ideal, VOUT becomes a function of the noise source. Equation 1 can be easily modified to account for the noise source, as described in Equation 2: Figure 3. LDO topology with equivalent-noise sources VIN VN(REF) R1 × (VREF + VN(REF) ), (2) VOUT + VN(OUT) = 1 + R2 VN(OUT) VN(FET ) OUT Node (VOUT) – R1 FB Node (VFB ) COUT VN(R1) VN(R2) R2 Figure 4. LDO topology with a consolidated noise source VIN Dominant sources of LDO outputvoltage noise For most typical LDO devices, a dominant source of output noise is the amplified reference noise in Equation 3. This is generally true even though the total output noise is device-dependent. Figure 3 is a complete block diagram showing each equivalentnoise source corresponding to its respective circuit element. Since any device with current flowing through it is a potential noise source, every single component in Figure 1 and Figure 2 is a noise source. Figure 4 is redrawn from Figure 3 to include all equivalent-noise sources referenced at the OUT node. The complete noise equation is NFET VGATE VREF (3) From Equations 2 and 3, it’s clear that a higher output voltage generates higher output noise. The feedback resistors, R1 and R2, set (or adjust) the output voltage, thereby setting the output noise voltage. For this reason, many LDO devices characterize the noise performance as a function of output voltage. For example, VN = 16 µVRMS × VOUT illustrates a standard form describing the output noise. VN(AMP ) + where VN(OUT) is the independent noise contribution to the output, expressed by Equation 3: R1 = 1 + × VN(REF) R2 + Error Amp – + Error Amp – NFET VGATE VN(OUT ) + VREF OUT Node (VOUT) – R1 COUT FB Node (VFB ) R2 R1 VN(OUT) = VN(AMP) + VN(FET) + 1 + R2 (4) ×(VN(REF) + VN(R1) + VN(R2) ). In most cases, because the reference-voltage block, or bandgap circuit, consists of many resistors, transistors, and capacitors, VN(REF) tends to dominate the last three noise sources in this equation where VN(REF) >> VN(R1) or VN(REF) >> VN(R2). Thus, Equation 4 can be simplified to R1 VN(OUT) = VN(AMP) + VN(FET) + 1 + × VN(REF). (5) R2 15 Analog Applications Journal 4Q 2012 www.ti.com/aaj High-Performance Analog Products Power Management Texas Instruments Incorporated For higher-performance LDO devices, it is common to add a noise-reduction (NR) pin to shunt reference noise to ground. Figure 5 illustrates how the NR pin works to reduce noise. Since it is known that VN(REF) is the dominant output-noise source, an RC filter capacitor, CNR, is inserted between the reference-voltage block (VREF) and the error amplifier to reduce this noise. This RC filter reduces the noise by an attenuation function of G RC ( f ) = 1 ( ) 1 + f fp 2 < 1, (6) Figure 5. LDO topology with reference-noise filter VIN RNR VREF1 VN(REF) VN(AMP ) + Error Amp – VN(FET ) + VREF OUT Node ( VOUT) – R1 where fp = In the real world, all control signal levels are frequency-dependent, including the noise signal. If the error amplifier has limited bandwidth, the high-frequency reference noise (VN(REF)) is filtered by the error amplifier in a way similar to using an RC filter. But in reality an error amplifier tends to have a very wide bandwidth, so the LDO device has very good power-supply ripple rejection (PSRR), which is another key performance param eter of high-performance LDOs. To satisfy this conflicting requirement, IC vendors settle on having a wide-bandwidth error amplifier for the best PSRR over less noise. This decision leads to using an NR pin function if low noise is also mandatory. R2 C NR Figure 6. RMS noise versus output voltage 100 CNR = 1 pF CFF = 10 pF 100 Hz to 100 kHz 90 80 RMS Noise (µVRMS ) VN(R2) NR Pin The amplified reference noise is therefore reduced to (1 + R1/R2) × VN(REF) × GRC, and Equation 5 then becomes COUT VN(R1) FB Node (VFB ) 1 . 2π × R NR × CNR R1 VN(OUT) = VN(AMP) + VN(FET) + 1 + R2 (7) × VN(REF) × G RC . NFET VGATE 70 60 Measurement 50 40 Curve Fitting 30 20 10 0 0.0 Controlling reference noise in a typical circuit 0.5 1.0 1.5 2.0 2.5 3.0 3.5 Output Voltage, VOUT (V) Amplified reference noise The Texas Instruments (TI) TPS74401 LDO was used for testing and measurements. The common setup parameters are shown in Table 1. Please note that a soft-start capacitor, CSS, in the TPS74401 datasheet1 is referred to as a noisereduction capacitor, CNR, in this article for easier reading. First, the effect of the amplifier gain was examined with a negligibly small CNR. Figure 6 shows RMS noise versus output-voltage settings. As discussed earlier, the dominant noise source, VN(REF), is amplified by the ratio of the feedback resistors R1 and R2. Equation 7 can be modified into the form of Equation 8: R1 VN(OUT) = VN(Other) + 1 + × VN(REF) × G RC , (8) R2 where VN(Other) is the sum of all other noise sources. Table 1. Setup parameters VIN = VOUT(Target) + 0.3 V IOUT = 0.5 A COUT = 10 µF VOUT(Target) R1 R2 1 + R1/R2 3.3 V 31.25 kΩ 10 kΩ 4.125 1.8 V 12.5 kΩ 10 kΩ 2.25 1.2 V 5 kΩ 10 kΩ 1.5 0.8 V 0 Ω (short OUT node to FB node) Open circuit 1 If Equation 8 is fitted to a linear curve of the form y = ax + b as shown by the red dotted line in Figure 6, VN(REF) (the slope term) can be estimated as 19 µVRMS, and VN(Other) (the y-intercept term) as 10.5 µVRMS. As explained 16 High-Performance Analog Products www.ti.com/aaj 4Q 2012 Analog Applications Journal Power Management Texas Instruments Incorporated later under “Effect of the noise-reduction (NR) pin,” the value of CNR was chosen as 1 pF to minimize the RC-filter effect to a negligible level, and GRC is treated as being equal to 1. In this situation, the basic assumption is that VN(REF) is the dominant noise source. Note that the minimum noise occurs when the OUT node is shorted to the FB node, making the amplifier gain (1 + R1/R2) equal to 1 (R1 = 0) in Equation 8. Figure 6 shows this minimum-noise point to be approximately 30 µVRMS. Figure 7. LDO topology with feedforward capacitor (CFF) for minimizing noise VIN VREF1 VN(OUT ) VREF R1 FB Node (VFB ) NR Pin 1 . 2π × R1 × CFF 1 R1 2π × f × CFF + 1 + R2 COUT CFF R2 C NR the entire given bandwidth of interest for the circuit conditions described. As expected, all curves converge toward the minimum output noise of approximately 30 µVRMS; in other words, the noise converges to VN(REF) + VN(Other) due to the effect of CFF. Figure 8 illustrates that, for a CFF value greater than 100 nF, the amplifier gain of 1 + R1/R2 in Equation 8 is canceled. This is true only because the low-frequency noise does not contribute significantly to the overall statistical mean of the RMS calculation, even though that lowfrequency noise is not completely canceled by CFF . In order to see the actual effect of CFF, it is necessary to look The output noise becomes OUT Node (VOUT) – This section explains a very effective technique for achieving a configuration with minimum output noise. A feedforward capacitor, CFF, forwards (bypasses) output noise around R1 as illustrated in Figure 7. This bypass or shorting action prevents the reference noise from being increased by the gain of the error amplifier at frequencies higher than the resonant frequency, fResonant, of R1 and CFF, where VN(OUT ) = VN(Other ) NFET VGATE + Canceling amplified reference noise fResonant = + Error Amp – (9) × G RC × VN( REF ). Figure 8 shows the changes in RMS noise relative to feed forward capacitance (CFF) and different output-voltage settings. Note that each point along each RMS plot represents the statistical mean of the integrated noise across Figure 8. Effects of feedforward capacitance on noise 100 90 VOUT = 3.3 V RMS Noise (µVRMS ) 80 70 60 VOUT = 1.8 V 50 40 30 VOUT = 1.2 V X X X X VOUT = 0.8 V 20 CNR = 1 pF 100 Hz to 100 kHz 10 0 1p 10 p 100 p 1n 10 n 100 n 1µ 10 µ Feedforward Capacitance, CFF (F) 17 Analog Applications Journal 4Q 2012 www.ti.com/aaj High-Performance Analog Products Power Management Texas Instruments Incorporated Figure 9. Output spectral noise density for various CFF values 10 Table 2. Calculated resonant frequencies CFF = 10 pF CFF = 1 nF CFF = 100 nF CFF = 10 µF fResonant 504 kHz 5.04 kHz 50.4 Hz 0.504 Hz Figure 9 shows that the curve of CFF = 100 nF rolls off around 50 Hz. The curve for CFF = 1 nF rolls off around 5 kHz, but the resonant frequency for when CFF = 10 pF is obscured by the overall internal effects on the LDO noise. Given these observations of Figure 9, it is assumed for the rest of this discussion that CFF = 10 µF to minimize noise. GRC decreases when the RC filter capacitor (CNR ) is used between the NR pin and ground. Figure 10 shows RMS noise as a function of CNR (see Figure 5). The difference between the two curves is examined later in the third paragraph under “Other technical considerations.” A wider integration range of 10 Hz to 100 kHz is used in Figure 10 to capture the performance difference in the low-frequency region. With CNR = 1 pF, both curves show very high RMS noise values. Although not shown in Figure 10, there is no RMS noise difference whether CNR = 1 pF or not. This is why GRC is treated as being equal to 1 in the earlier section, “Amplified reference noise.” As expected, RMS noise gets lower as CNR increases, and converges toward the minimum output noise of approximately 12.5 µVRMS when CNR = 1 µF. For a CFF of 10 µF, the amplifier gain (1 + R1/R2) can be ignored. Thus, Equation 8 can be simplified to VN(OUT) = VN(Other) + VN(REF) × G RC . 1 CFF = 10 pF CFF = 100 nF CFF = 1 nF CFF = 10 µF 0.1 0.01 10 100 1k 10 k 100 k 1M 10 M Frequency (Hz) Figure 10. RMS noise versus noise-reduction capacitance 50 45 40 RMS Noise (µVRMS ) Effect of the noise-reduction (NR) pin VOUT = 3.3 V CNR = 1 pF Output Spectral Noise Density (µV/ Hz) at the actual spectral-density plot of the noise voltage (Figure 9). Figure 9 shows that there is minimum noise at the curve of CFF = 10 µF but that all curves approach this minimum noise curve above certain frequencies. Those certain frequencies correspond to the resonant pole frequencies determined by the R1 and CFF values. See Table 2 for the calculated CFF values with an R1 value of 31.6 kΩ. 35 30 VOUT = 0.8 V 25 20 15 VOUT = 3.3 V with CFF = 10 µF 10 5 10 Hz to 100 kHz 0 1p 10 p 100 p 1n 10 n 100 n 1µ Noise-Reduction Capacitance, CNR (F) (10) As seen, VN(Other) is not affected by CNR. Therefore CNR remains 10.5 µVRMS as was determined by the data-curve fit in Figure 6. Equation 10 can be expressed as VN(OUT) = VN(REF) × G RC + 10.5 µV. Next, it is important to determine the effect of noisereduction capacitance on GRC . The minimum measured noise along the curve in Figure 10 allows Equation 10 to be rewritten as VN(OUT) = 12.5 µV = VN(REF) × G RC + 10.5 µV, (11) where VN(REF) × GRC is solved to equal 2 µVRMS. Adding CNR decreases the reference noise from 19.5 µVRMS to 2 µVRMS, which is to say that GRC has decreased from unity to an average of 0.1 (2/19.5) over the frequency range of 10 Hz to 100 kHz. 18 High-Performance Analog Products www.ti.com/aaj 4Q 2012 Analog Applications Journal Power Management Texas Instruments Incorporated Figure 11 shows how CNR reduces noise in the frequency domain. Just like the smaller CFF values in Figure 9, a smaller CNR starts working at a higher frequency. Note that the biggest CNR value, 1 µF, shows the lowest noise. Though the curve for CNR = 10 nF shows almost minimum noise close to the curve for CNR = 1 µF, the 10-nF curve shows a small hump between 30 and 100 Hz. The curves in Figure 8, where CNR = 1 pF, can be improved to those in Figure 12, where CNR = 1 µF. Figure 8 shows little difference in RMS noise between CFF = 100 nF and CFF = 10 µF, but Figure 12 clearly shows a difference. In Figure 12, regardless of the output voltage, values of CFF = 10 µF and CNR = 1 µF bring the lowest noise, 12.5 µVRMS, which is to say that the minimum GRC value (in other words, the maximum effect of the RC filter) is 0.1. This value of 12.5 µVRMS is the noise floor of the TI device TPS74401. When a new LDO device is used for noise-sensitive applications, it is good practice to figure out a noise floor unique to the device by using large CFF and CNR capacitors. Figure 12 indicates that an RMS-noise curve converges at the noise-floor value. Figure 11. Output spectral noise density versus frequency for various CNR values 10 Output Spectral Noise Density (µV/ Hz) VOUT = 3.3 V CFF = 10 µF CNR = 1 pF CNR = 100 pF CNR = 10 nF CNR = 1 µF 1 0.1 0.01 10 100 1k 10 k 100 k 1M 10 M Frequency (Hz) Figure 12. RMS noise versus feedforward capacitance after noise optimization 50 VOUT = 3.3 V CNR = 1 µF 10 Hz to 100 kHz 45 RMS Noise (µVRMS ) 40 35 VOUT = 1.8 V 30 25 VOUT = 1.2 V 20 15 X VOUT = 0.8 V 10 X X X 5 0 1p 10 p 100 p 1n 10 n 100 n 1µ 10 µ Feedforward Capacitance, CFF (F) 19 Analog Applications Journal 4Q 2012 www.ti.com/aaj High-Performance Analog Products Power Management Texas Instruments Incorporated Other technical considerations • How to cancel the amplified reference noise • How an NR function works Slow-start effect of noise-reduction capacitor Besides its ability to reduce noise, an RC filter is also known to work as an RC delay circuit. Therefore, a big CNR value causes a big delay of the regulator’s reference voltage. Slow-start effect of feedforward capacitor The same mechanism whereby CFF bypasses the AC signal across the R1 feedback resistor also bypasses the outputvoltage feedback information when VOUT is ramping up after an enable event. Until CFF is fully charged, an error amplifier takes a bigger negative feedback signal, resulting in a slow start. Why a higher VOUT value results in less RMS noise In Figures 8 and 10, the curve for VOUT = 3.3 V shows less noise than that for VOUT = 0.8 V. Since it is known that a higher voltage setting can increase the reference noise, this looks odd. The explanation is that, because CFF is connected to the OUT node, CFF has the effect of increasing the output-capacitor value in addition to bypassing the noise signal across resistor R1. Figure 12 shows that, as the reference noise gets minimized, this phenomenon can’t be observed. RMS-noise value Because the noise floor of the TPS74401 is 12.5 µVRMS, this device is one of the lowest-noise LDOs on the market. This absolute value of 12.5 µVRMS can be a good reference to use in designing a regulator with very low noise. Conclusion The basic noise of an LDO device and how to minimize it have been examined, including: • How each circuit block contributes to output noise • How the reference voltage is the dominant source of noise, amplified by an error amplifier Careful selection of a noise-reduction capacitor (CNR ) and a feedforward capacitor (CFF) can minimize LDO output noise to a noise-floor level unique to the device. With this noise-minimized configuration, an LDO device keeps the noise-floor value regardless of the parameters that usually affect noise in non-optimized configurations. Due to the expected side effect of a slow start when CNR and CFF are added to the circuit, values for these capacitors must be chosen that will provide a fast enough ramp-up. The method described in this article is already being used to optimize the noise of TI’s TPS7A8101 LDO. On page 10 of the TPS7A8101 datasheet,2 the device shows a constant noise value no matter what parameter is changed. References For more information related to this article, you can down load an Acrobat® Reader® file at www.ti.com/lit/litnumber and replace “litnumber” with the TI Lit. # for the materials listed below. Document Title TI Lit. # 1. “3.0A ultra-LDO with programmable softstart,” TPS74xx Datasheet . . . . . . . . . . . . . . . SBVS066M 2. “Low-noise, wide-bandwidth, high PSRR, low-dropout 1-A linear regulator,” TPS7A8101 Datasheet . . . . . . . . . . . . . . . . . . SBVS179A Related Web sites power.ti.com www.ti.com /ldo-ca www.ti.com /product/TPS7A8101 www.ti.com /product/TPS74401 20 High-Performance Analog Products www.ti.com/aaj 4Q 2012 Analog Applications Journal TI Worldwide Technical Support Internet TI Semiconductor Product Information Center Home Page support.ti.com TI E2E™ Community Home Page e2e.ti.com Product Information Centers Americas Phone +1(972) 644-5580 Brazil Phone 0800-891-2616 Mexico Phone 0800-670-7544 Fax Internet/Email +1(972) 927-6377 support.ti.com/sc/pic/americas.htm Europe, Middle East, and Africa Phone European Free Call International Russian Support 00800-ASK-TEXAS (00800 275 83927) +49 (0) 8161 80 2121 +7 (4) 95 98 10 701 Note: The European Free Call (Toll Free) number is not active in all countries. If you have technical difficulty calling the free call number, please use the international number above. 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