Product Folder Sample & Buy Technical Documents Support & Community Tools & Software DRV8711 www.ti.com SLVSC40 – JUNE 2013 STEPPER MOTOR CONTROLLER IC FEATURES 1 • Pulse Width Modulation (PWM) Microstepping Motor Driver – Built-In 1/256-Step Microstepping Indexer – Drives External N-Channel MOSFETs – Optional STEP/DIR Pins – Optional PWM Control Interface for DC Motors Flexible Decay Modes, Including Automatic Mixed Decay Mode Stall Detection With Optional BEMF Output Highly cConfigurable Va SPI Serial Interface Internal Reference and Torque DAC 8-V to 52-V Operating Supply Voltage Range Scalable Output Current Thermally Enhanced Surface Mount Package 5-V Regulator Capable of 10-mA Load 2 • • • • • • • • • Protection and Diagnostic Features – Overcurrent Protection (OCP) – Overtemperature Shutdown (OTS) – Undervoltage Lockout (UVLO) – Individual Fault Condition Indication Bits – Fault Condition Indication Pin APPLICATIONS • • • • Office Automation Machines Factory Automation Textile Machines Robotics DESCRIPTION The DRV8711 is a stepper motor controller that uses external N-channel MOSFETs to drive a bipolar stepper motor or two brushed DC motors. A microstepping indexer is integrated, which is capable of step modes from full step to 1/256-step. An ultra-smooth motion profile can be achieved using adaptive blanking time and various current decay modes, including an auto-mixed decay mode. Motor stall is reported with an optional back-EMF output. A simple step/direction or PWM interface allows easy interfacing to controller circuits. A SPI serial interface is used to program the device operation. Output current (torque), step mode, decay mode, and stall detection functions are all programmable via a SPI serial interface. Internal shutdown functions are provided for over current protection, short circuit protection, under voltage lockout and overtemperature. Fault conditions are indicated via a FAULTn pin, and each fault condition is reported via a dedicated bit through SPI. The DRV8811 is packaged in a PowerPAD™ 38-pin HTSSOP package with thermal pad (Eco-friendly: RoHS and no Sb/Br). ORDERING INFORMATION (1) TA –40°C to 85°C (1) (2) PACKAGE (2) PowerPAD™ (HTSSOP) – PWP ORDERABLE PART NUMBER Reel of 2000 Tube of 40 DRV8711DCPR DRV8711DCP TOP-SIDE MARKING DRV8711 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013, Texas Instruments Incorporated DRV8711 SLVSC40 – JUNE 2013 www.ti.com FUNCTIONAL BLOCK DIAGRAM VM 0.1µF + 1µF 0.01µF 100µF CP2 CP1 VM VCP VM 5V OUT VM Charge Pump V5 Gate Drive & OCP Regs VINT A1LS PWM logic 1µ F RESET UVLO PUC VM DCM Step Motor AOUT2 A2LS + Comp + - DIR/AIN2 AISENP ISEN amp - STEP/AIN1 A2HS Gate Drive & OCP OverTemp SLEEPn VM AOUT1 + 0.1µF A1HS HS Gate Drive AISENN + Comp - BIN1 SIN DAC BIN2 VM X B1HS Gate Drive & OCP Torque DAC SCS BOUT1 B1LS Logic PWM logic SCLK SDATI B2HS Gate Drive & OCP Reference SDATO VM DCM BOUT2 B2LS + Comp + BISENP ISEN amp - + - - FAULTn BISENN + Comp SIN DAC STALLn / BEMFVn X Torque DAC Stall detect BEMF 1nF GND 2 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DRV8711 DRV8711 www.ti.com SLVSC40 – JUNE 2013 TERMINAL FUNCTIONS NO. I/O (1) 5, 29, 38, PPAD - Device ground All pins must be connected to ground VM 4 - Bridge A power supply Connect to motor supply voltage. Bypass to GND with a 0.01-μF ceramic capacitor plus a 100-μF electrolytic capacitor. VINT 7 - Internal logic supply voltage Logic supply voltage. Bypass to GND with a 1-μF 6.3-V X7R ceramic capacitor. V5 6 O 5-V regulator output 5-V linear regulator output. Bypass to GND with a 0.1-μF 10-V X7R ceramic capacitor. CP1 1 IO Charge pump flying capacitor CP2 2 IO Charge pump flying capacitor Connect a 0.1-μF X7R capacitor between CP1 and CP2. Voltage rating must be greater than applied VM voltage. VCP 3 IO High-side gate drive voltage NAME DESCRIPTION EXTERNAL COMPONENTS OR CONNECTIONS POWER AND GROUND GND Connect a 1-μF 16-V X7R ceramic capacitor to VM CONTROL SLEEPn 8 I Sleep mode input Logic high to enable device, logic low to enter low-power sleep mode STEP/AIN1 10 I Step input/Bridge A IN1 Indexer mode: Rising edge causes the indexer to move one step. External PWM mode: controls bridge A OUT1 Internal pulldown. DIR/AIN2 11 I Direction input/Bridge A IN2 Indexer mode: Level sets the direction of stepping. External PWM mode: controls bridge A OUT2 Internal pulldown. BIN1 12 I Bridge B IN1 Indexer mode: No function External PWM mode: controls bridge B OUT1 Internal pulldown. BIN2 13 I Bridge B IN2 Indexer mode: No function External PWM mode: controls bridge B OUT2 Internal pulldown. RESET 9 I Reset input Active-high reset input initializes all internal logic and disables the Hbridge outputs. Internal pulldown. SCS 16 I Serial chip select input Active high to enable serial data transfer. Internal pulldown. SCLK 14 I Serial clock input Rising edge clocks data into part for write operations. Falling edge clocks data out of part for read operations. Internal pulldown. SDATI 15 I Serial data input Serial data input from controller. Internal pulldown. SDATO 17 O Serial data output Serial data output to controller. Open-drain output requires external pull-up. STALLn/ BEMFVn 19 OD Stall/Back EMF valid Internal stall detect mode: logic low when motor stall detected. External stall detect mode: Active low when valid back EMF measurement is ready. Open-drain output requires external pullup. FAULTn 18 OD Fault Logic low when in fault condition. Open-drain output requires external pullup. Faults: OCP, PDF, OTS, UVLO BEMF 20 O Back EMF Analog output voltage represents motor back EMF. Place a 1-nF lowleakage capacitor to ground on this pin. SERIAL INTERFACE STATUS OUTPUTS A1HS 36 O Bridge A out 1 HS gate Connect to gate of HS FET for bridge A out 1 AOUT1 37 I Bridge A output 1 Connect to output node of external FETs of bridge A out 1 A1LS 35 O Bridge A out 1 LS gate Connect to gate of LS FET for bridge A out 1 A2HS 31 O Bridge A out 2 HS gate Connect to gate of HS FET for bridge A out 2 AOUT2 30 I Bridge A output 2 Connect to output node of external FETs of bridge A out 2 A2LS 32 O Bridge A out 2 LS gate Connect to gate of LS FET for bridge A out 2 AISENP 34 I Bridge A Isense + in Connect to current sense resistor for bridge A AISENN 33 I Bridge A Isense - in Connect to ground at current sense resistor for bridge A B1HS 27 O Bridge B out 1 HS gate Connect to gate of HS FET for bridge B out 1 (1) Directions: I = input, O = output, OZ = 3-state output, OD = open-drain output, IO = input/output Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DRV8711 3 DRV8711 SLVSC40 – JUNE 2013 www.ti.com TERMINAL FUNCTIONS (continued) NAME NO. I/O (1) DESCRIPTION EXTERNAL COMPONENTS OR CONNECTIONS BOUT1 28 I Bridge B output 1 Connect to output node of external FETs of bridge B out 1 B1LS 26 O Bridge B out 1 LS gate Connect to gate of LS FET for bridge B out 1 B2HS 22 O Bridge B out 2 HS gate Connect to gate of HS FET for bridge B out 2 BOUT2 21 I Bridge B output 2 Connect to output node of external FETs of bridge B out 2 B2LS 23 O Bridge B out 2 LS gate Connect to gate of LS FET for bridge B out 2 BISENP 25 I Bridge B Isense + in Connect to current sense resistor for bridge B BISENN 24 I Bridge B Isense - in Connect to ground at current sense resistor for bridge B CRITICAL COMPONENTS PIN NAME COMPONENT 4 VM 100-µF electrolytic rated for VM voltage to GND 0.01-µF ceramic rated for VM voltage to GND 1-µF ceramic X7R rated 16 V to VCP 3 VCP 1, 2 CP1, CP2 6 V5 7 VINT 1-µF ceramic X7R rated 6.3 V to GND 17 SDATO Requires external pullup to logic supply 18 FAULTn Requires external pullup to logic supply 19 STALLn/BEMFVn Requires external pullup to logic supply 20 BEMF 0.1-µF rated for VM + 12 V between these pins 0.1-µF ceramic X7R rated 6.3 V to GND 1-nF low-leakage capacitor to GND DCP (HTSSOP) PACKAGE CP1 CP2 VCP VM GND V5 VINT SLEEPn RESET STEP / AIN1 DIR / AIN2 BIN1 BIN2 SCLK SDATI SCS SDATO FAULTn STALLn / BEMFVn 4 1 2 3 38 37 36 4 5 35 34 6 7 33 32 31 8 9 10 11 GND (PPAD) 30 29 28 12 27 13 26 14 25 15 24 16 23 17 22 18 21 19 20 Submit Documentation Feedback GND AOUT1 A1HS A1LS AISENP AISENN A2LS A2HS AOUT2 GND BOUT1 B1HS B1LS BISENP BISENN B2LS B2HS BOUT2 BEMF Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DRV8711 DRV8711 www.ti.com SLVSC40 – JUNE 2013 ABSOLUTE MAXIMUM RATINGS (1) (2) (3) over operating free-air temperature range (unless otherwise noted) Power supply voltage range DRV8711 UNIT -0.6 to 60 V -0.6 to VM + 12 V 5V regulator voltage (V5) -0.6 to 5.5 V Internal regulator voltage (VINT) -0.6 to 2.0 V Digital pin voltage range (SLEEPn, RESET, STEP/AIN1, DIR/AIN2, BIN1, BIN2, SCS, SCLK, SDATI, SDATO, FAULTn, STALLn/BEMFVn) -0.6 to 5.5 V -0.6 to VM + 12 V Low-side gate drive pin voltage range (A1LS, A2LS, B1LS, B2LS) -0.6 to 12 V Phase node pin voltage range (AOUT1, AOUT2, BOUT1, BOUT2) -0.6 to VM V ISENSEx pin voltage (AISENP, AISENN, BISENP, BISENN) -0.7 to +0.7 V BEMF pin voltage range (BEMF) -0.6 to VM V Operating virtual junction temperature range, TJ -40 to 150 °C Storage temperature range, Tstg -60 to 150 °C Charge pump voltage range (CP1, CP2, VCP) High-side gate drive pin voltage range (A1HS, A2HS, B1HS, B2HS) (1) (2) (3) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. Power dissipation and thermal limits must be observed. THERMAL INFORMATION DRV8711 THERMAL METRIC (1) DCP UNITS 38 PINS θJA Junction-to-ambient thermal resistance (2) 32.7 θJCtop Junction-to-case (top) thermal resistance (3) 17.2 (4) θJB Junction-to-board thermal resistance ψJT Junction-to-top characterization parameter (5) ψJB Junction-to-board characterization parameter (6) θJCbot (1) (2) (3) (4) (5) (6) (7) Junction-to-case (bottom) thermal resistance 14.3 °C/W 0.5 14.1 (7) 0.9 For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Spacer RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VM Motor power supply voltage range 8 52 V IVS V5 external load current 0 10 mA TA Operating ambient temperature range -40 85 °C Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DRV8711 5 DRV8711 SLVSC40 – JUNE 2013 www.ti.com ELECTRICAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Power Supplies IVM VM operating supply current VM = 24 V 17 20 mA IVMQ VM sleep mode supply current VM = 24 V, SLEEPn = 0 65 98 μA VM rising 7.1 8 VM falling 6.3 VUVLO VM undervoltage lockout voltage V Internal Linear Regulators V5 V5 output voltage VM ≥ 12 V, IOUT = 1 mA - 10 mA 4.8 5 5.2 V VINT VINT voltage No external load – reference only 1.7 1.8 1.9 V 0.8 V Logic-Level Inputs VIL Input low voltage VIH Input high voltage VHYS Input hysteresis voltage IIL Input low current VIN = 0 V -5 IIH Input high current VIN = 5 V 30 1.5 V 300 50 mV 5 μA 70 μA SDATAO, STALLn, FAULTn OUTPUTS (Open-Drain Outputs) VOL Output low voltage IO = 5 mA IOH Output high leakage current VO = 3.3 V 0.5 V 1 µA MOSFET Drivers VOUTH High-side gate drive output voltage VM = 24 V, IO = 100 μA VM+10 V VOUTL Low-side gate drive output voltage VM = 24 V, IO = 100 μA 10 V tDEAD Output dead time digital delay (dead time is enforced in analog circuits) IOUTH IOUTl tDRIVE tDRIVE Peak output current gate drive (source) Peak output current gate drive (sink) Peak current drive time (source) Peak current drive time (sink) DTIME = 00 400 DTIME = 01 450 DTIME = 10 650 DTIME = 11 850 IDRIVEP = 00 50 IDRIVEP = 01 100 IDRIVEP = 10 150 IDRIVEP = 11 200 IDRIVEN = 00 100 IDRIVEN = 01 150 IDRIVEN = 10 200 IDRIVEN = 11 400 TDRIVEP = 00 250 TDRIVEP = 01 500 TDRIVEP = 10 1000 TDRIVEP = 11 2000 TDRIVEN = 00 250 TDRIVEN = 01 500 TDRIVEN = 10 1000 TDRIVEN = 11 2000 ns mA mA ns ns Motor Driver tOFF PWM off time adjustment range Set by TOFF register 0.5 128 μs tBLANK Current sense blanking time Set by TBLANK register 0.5 5.12 μs 6 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DRV8711 DRV8711 www.ti.com SLVSC40 – JUNE 2013 ELECTRICAL CHARACTERISTICS (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX OCPTH = 00 160 250 320 OCPTH = 01 380 500 580 OCPTH = 10 620 750 850 OCPTH = 11 840 1000 1200 Die temperature 150 160 180 UNIT Protection Circuits VOCP Overcurrent protection trip level (Voltage drop across external FET) tTSD Thermal shutdown temperature (1) tHYS Thermal shutdown hysteresis 20 mV °C °C Current Sense Amplifiers AV Gain ISGAIN = 00 5 ISGAIN = 01 10 ISGAIN = 10 20 ISGAIN = 11 tSET Settling time (to ±1%) VOFS Offset voltage VIN Input differential voltage range V/V 40 ISGAIN = 00, ΔVIN = 400 mV 150 ISGAIN = 01, ΔVIN = 200 mV 300 ISGAIN = 10, ΔVIN = 100 mV 600 ISGAIN = 11, ΔVIN = 50 mV 1.2 ISGAIN = 00, input shorted -300 ns µs 4 mV 300 mV Current Control DACs Resolution Full-scale step response VREF (1) 256 10% to 90% Full-scale (reference) voltage 2.50 2.75 steps 5 µs 3 V Not tested in production - guaranteed by design. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DRV8711 7 DRV8711 SLVSC40 – JUNE 2013 www.ti.com SPI INTERFACE TIMING REQUIREMENTS over operating free-air temperature range (unless otherwise noted) No. PARAMETER CONDITIONS MIN MAX UNIT 1 tCYC Clock cycle time 250 ns 2 tCLKH Clock high time 25 ns 3 tCLKL Clock low time 25 ns 4 tSU(SDATI) Setup time, SDATI to SCLK 5 ns 5 tH(SDATI) Hold time, SDATI to SCLK 1 ns 6 tSU(SCS) Setup time, SCS to SCLK 5 ns 7 tH(SCS) Hold time, SCS to SCLK 1 ns 8 tL(SCS) Inactive time, SCS (between writes) 9 tD(SDATO) Delay time, SCLK to SDATO (during read) tSLEEP Wake time (SLEEPn inactive to high-side gate drive enabled) tRESET Delay from power-up or RESETn high until serial interface functional 7 6 100 ns 10 ns 1 ms 10 μs 8 SCS 1 SCLK 2 3 SDATI X X 4 5 9 SDATO valid SDATO 8 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DRV8711 DRV8711 www.ti.com SLVSC40 – JUNE 2013 INDEXER TIMING REQUIREMENTS over operating free-air temperature range (unless otherwise noted) No. PARAMETER CONDITIONS MIN MAX UNIT 250 kHz 1 fSTEP Step frequency 2 tWH(STEP) Pulse duration, STEP high 1.9 μs 3 tWL(STEP) Pulse duration, STEP low 1.9 μs 4 tSU(STEP) Setup time, command to STEP rising 200 ns 5 tH(STEP) Hold time, command to STEP rising 200 ns 1 2 3 STEP DIR, MODE 4 5 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DRV8711 9 DRV8711 SLVSC40 – JUNE 2013 www.ti.com FUNCTIONAL DESCRIPTION PWM Motor Drivers The DRV8711 contains two H-bridge motor pre-drivers with current-control PWM circuitry. More detailed descriptions of the sub-blocks are described in the following sections. Direct PWM Input Mode Direct PWM mode is selected by setting the PWMMODE bit in the OFF register. In direct PWM input mode, the AIN1, AIN2, BIN1, and BIN2 directly control the state of the output drivers. This allows for driving up to two brushed DC motors. The logic is shown below: Table 1. Direct PWM Input Mode Logic xIN1 xIN2 xOUT1 xOUT2 OPERATION 0 0 0 1 Z Z Asynchronous Fast Decay L H 1 Reverse Drive 0 H L Forward Drive 1 1 L L Slow Decay Note that if mixed or auto mixed decay modes are used, they will apply to every cycle, since current change information is not available. In direct PWM mode, the current control circuitry is still active. The full-scale VREF is set to 2.75 V. The TORQUE register may be used to scale this value, and the ISEN sense amp gain may still be set using the ISGAIN bits of the CTRL register. x1HS Gate Drive & OCP xIN1 VM xOUT1 x1LS xIN2 PWM logic x2HS Gate Drive & OCP VM xOUT2 x2LS + RISENSE Comp xISENP + ISEN amp xISENN - + - + Comp VREF X ISGAIN 1V TORQUE Torque DAC Figure 1. Direct PWM Input Mode 10 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DRV8711 DRV8711 www.ti.com SLVSC40 – JUNE 2013 The current through the motor windings is regulated by an adjustable fixed-off-time PWM current regulation circuit. When an H-bridge is enabled, current rises through the winding at a rate dependent on the DC voltage and inductance of the winding and the magnitude of the back EMF present. Once the current hits the current chopping threshold, the bridge disables the current for a fixed period of time, which is programmable between 500 nS and 128 µS by writing to the TOFF bits in the OFF register. After the off time expires, the bridge is reenabled, starting another PWM cycle. The chopping current is set by a comparator which compares the voltage across a current sense resistor connected to the xISENx pins, multiplied by the gain of the current sense amplifier, with a reference voltage. The current sense amplifier is programmable in the CTRL register. When driving in PWM mode, the chopping current is calculated as follows: 2.75V · TORQUE ICHOP = 256 · ISGAIN · RISENSE (1) Where TORQUE is the setting of the TORQUE bits, and ISGAIN is the programmed gain of the ISENSE amplifiers (5, 10, 20, or 40). Microstepping Indexer Built-in indexer logic in the DRV8711 allows a number of different stepping configurations. The MODE bits in the CTRL register are used to configure the stepping format as shown in the table below: Table 2. Microstepping Indexer Logic MODE3 MODE2 MODE1 MODE0 STEP MODE 0 0 0 0 Full step (2-phase excitation) with 71% current 0 0 0 1 1/2 step 0 0 1 0 1/4 step 0 0 1 1 1/8 step 0 1 0 0 1/16 step 0 1 0 1 1/32 step 0 1 1 0 1/64 step 0 1 1 1 1/128 step 1 0 0 0 1/256 step Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DRV8711 11 DRV8711 SLVSC40 – JUNE 2013 www.ti.com Table 3 shows the relative current and step directions for full-step through 1/8-step operation. Higher microstepping resolutions follow the same pattern. The AOUT current is the sine of the electrical angle; BOUT current is the cosine of the electrical angle. The reset state is 45°. This state is entered at power-up or application of RESETn. This is shown in the table below by cells shaded in yellow. Table 3. Step Directions FULL STEP 1/8 STEP 1 1 1 0 100 0 2 20 98 11.325 3 38 92 22.5 4 56 83 33.75 5 71 71 45 (home state) 6 83 56 56.25 7 92 38 67.5 8 98 20 78.75 9 100 0 90 10 98 -20 101.25 11 92 -38 112.5 12 83 -56 123.75 13 71 -71 135 14 56 -83 146.25 15 38 -92 157.5 16 20 -98 168.75 17 0 -100 180 18 -20 -98 191.25 19 -38 -92 202.5 20 -56 -83 213.75 21 -71 -71 225 22 -83 -56 236.25 23 -92 -38 247.5 24 -98 -20 258.75 25 -100 0 270 26 -98 20 281.25 27 -92 38 292.5 28 -83 56 303.75 29 -71 71 315 30 -56 83 326.25 31 -38 92 337.5 32 -20 98 348.75 2 3 4 3 5 6 2 4 7 8 5 9 10 3 6 11 12 7 13 14 4 ELECTRICAL ANGLE (DEGREES) 1/4 STEP 2 1 AOUT CURRENT BOUT CURRENT (% FULL-SCALE) (% FULL-SCALE) 1/2 STEP 8 15 16 At each rising edge of the STEP input, or each time a '1' is written to the RSTEP bit in the CTRL register, the indexer travels to the next state in the table. The direction is shown with the DIR pin high and the RDIR bit in the CTRL register set to '0', or the DIR pin low and the RDIR bit set to '1'. If the DIR pin is low with the RDIR bit '0', or the DIR pin is high with the RDIR bit '1', the sequence is reversed. Positive current is defined as xOUT1 = positive with respect to xOUT2. Note that if the step mode is changed while stepping, the indexer will advance to the next valid state for the new MODE setting at the rising edge of STEP. 12 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DRV8711 DRV8711 www.ti.com SLVSC40 – JUNE 2013 Current Regulation The current through the motor windings is regulated by an adjustable fixed-off-time PWM current regulation circuit. When an H-bridge is enabled, current rises through the winding at a rate dependent on the DC voltage and inductance of the winding and the magnitude of the back EMF present. Once the current hits the current chopping threshold, the bridge disables the current for a fixed period of time, which is programmable between 500 nS and 128 µS by writing to the TOFF bits in the OFF register. After the off time expires, the bridge is reenabled, starting another PWM cycle. In stepping motors, current regulation is used to vary the current in the two windings in a sinusoidal fashion to provide smooth motion. The PWM chopping current is set by a comparator which compares the voltage across a current sense resistor connected to the xISENx pins, multiplied by the gain of the current sense amplifier, with a reference voltage. The current sense amplifier is programmable in the CTRL register. VM x1HS Gate Drive & OCP Registers xOUT1 x1LS PWM logic VM x2HS Gate Drive & OCP xOUT2 x2LS + Comp xISENP RISENSE + ISEN amp xISENN - + - + Comp 2.75 V SIN DAC Indexer X ISGAIN 1V TORQUE Torque DAC Figure 2. PWM Chopping Current To generate the reference voltage for the current chopping comparator, the output of a sine lookup table is multiplied by the value of the bits in the TORQUE register. This result is applied to a sine-weighted DAC, whose full-scale output voltage is 2.75 V. Therefore, the full-scale (100%) chopping current is calculated as follows: 2.75V · TORQUE IFS = 256 · ISGAIN · RISENSE (2) Where TORQUE is the setting of the TORQUE bits, and ISGAIN is the programmed gain of the ISENSE amplifiers (5, 10, 20, or 40). Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DRV8711 13 DRV8711 SLVSC40 – JUNE 2013 www.ti.com Example: If a 0.1-Ω sense resistor is used, ISGAIN is set to 0 (gain of 5), and TORQUE is set to 255, the full-scale (100%) chopping current will be (2.75V * 255) / (256 * 5 * 0.1Ω) = 5.5A. Decay Modes During PWM current chopping, the H-bridge is enabled to drive through the motor winding until the PWM current chopping threshold is reached. This is shown in Figure 3, Item 1. The current flow direction shown indicates positive current flow in the step table below. Once the chopping current threshold is reached, the H-bridge can operate in two different states, fast decay or slow decay. In fast decay mode, once the PWM chopping current level has been reached, the H-bridge reverses state to allow winding current to flow in a reverse direction. If synchronous rectification is enabled (SRn pin logic low), the opposite FETs are turned on; as the winding current approaches zero, the bridge is disabled to prevent any reverse current flow. If SRn is high, current is recirculated through the body diodes, or through external Schottky diodes. Fast-decay mode is shown in Figure 3, Item 2. In slow-decay mode, winding current is re-circulated by enabling both of the low-side FETs in the bridge. This is shown in Figure 3, Item 3. VM PWM ON PWM OFF Slow Decay 1 Drive Current 1 xOUT2 xOUT1 3 2 Fast decay (reverse) Fast Decay 3 Slow decay (brake) 2 Mixed Decay TDECAY TBLANK TOFF Itrip Figure 3. Decay Modes The DRV8711 supports fast decay and slow decay modes in both indexer and direct PWM modes. In addition, in indexer mode only, it supports fixed mixed decay and auto mixed decay modes. Decay mode is selected by the DECMOD bits in the DECAY register. Mixed decay mode begins as fast decay, but after a programmable period of time (set by the TDECAY bits in the DECAY register) switches to slow decay mode for the remainder of the fixed off time. Even if mixed decay is selected, if the current is increasing or remaining the same (per the step table), then slow decay is used. Auto mixed decay mode samples the current level at the end of the blanking time, and if the current is above the Itrip threshold, immediately changes the H-bridge to fast decay. During fast decay, the (negative) current is monitored, and when it falls below the Itrip threshold (and another blanking time has passed), the bridge is switched to slow decay. Once the fixed off time expires, a new cycle is started. If the bridge is turned on and at the end of TBLANK the current is below the Itrip threshold, the bridge remains on until the current reaches Itrip. Then slow decay is entered for the fixed off time, and a new cycle begins. Refer to Figure 4 and Figure 5. 14 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DRV8711 DRV8711 www.ti.com SLVSC40 – JUNE 2013 The upper waveform shows the behavior if I < Itrip at the end of tBLANK. Note that (at slow motor speeds, where back EMF is not significant), the current increase during the ON phase is the same magnitude as the current decrease in fast decay, since both times are controlled by tBLANK, and the rate of change is the same (full VM is applied to the load inductance in both cases, but in opposite directions). In this case, the current will gradually be driven down until the peak current is just hitting Itrip at the end of the blanking time, after which some cycles will be slow decay, and some will be mixed decay. tON tON tOFF tBLANK I below Itrip after tBLANK tOFF tBLANK Itrip At Itrip and after tBLANK, slow decay I < Itrip tON tON tOFF I above Itrip after tBLANK tOFF On tBLANK tBLANK tBLANK tBLANK Fast Decay Itrip Slow Decay I > Itrip, start fast decay When I < Itrip in fast decay and tBLANK expires, change to slow decay Figure 4. I < Itrip at the End of tBLANK If the Itrip level changes during a PWM cycle (in response to a step command to the indexer), the current cycle is immediately terminated, and a new cycle is begun. Refer to the drawing below. If the Itrip level has increased, the H-bridge will immediately turn on; if the Itrip level has decreased, fast decay mode is begun immediately. The top waveform shows what happens when the Itrip threshold decreases during a PWM cycle. The lower Itrip level results in the current being above the Itrip threshold at the end of tBLANK on the following cycle. Fast decay is entered until the current is driven below the Itrip threshold. Itrip decrease tON tBLANK tOFF tON tBLANK tOFF Itrip Decrease in Itrip terminates cycle, fast decay begins Itrip increase tON tBLANK When I < Itrip in fast decay change to slow decay tON On tOFF tBLANK Fast Decay Slow Decay Itrip Increase in Itrip terminates cycle, bridge turns on Figure 5. Itrip Level Changing During a PWM Cycle Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DRV8711 15 DRV8711 SLVSC40 – JUNE 2013 www.ti.com Blanking Time After the current is enabled in an H-bridge, the voltage on the ISEN pin is ignored for a period of time before enabling the current sense circuitry. This blanking time is adjustable from 1 µS to 5.12 µs, in 20 ns increments, by setting the TBLANK bits in the BLANK register. Note that the blanking time also sets the minimum on time of the PWM. The same blanking time is applied to the fast decay period in auto decay mode. The PWM will ignore any transitions on Itrip after entering fast decay mode, until the blanking time has expired. To provide better current control at very low current steps, an adaptive blanking time mode can be enabled by setting the ABT bit in the BLANK register. If ABT is set, at current levels below 30% of full scale current (as determined by the step table), the blanking time (so also the minimum on time) is cut in half, to 50% of the value programmed by the TBLANK bits. For higher degrees of micro-stepping it is recommended to enable ABT bit for better current regulation. Pre-Drivers An internal charge pump circuit and pre-drivers inside the DRV8711 directly drive N-channel MOSFETs, which drive the motor current. The peak drive current of the pre-drivers is adjustable by setting the bits in the DRIVE register. Peak source currents may be set to 50 mA, 100 mA, 150 mA, or 200 mA. The peak sink current is approximately 2x the peak source current. Adjusting the peak current will change the output slew rate, which also depends on the FET input capacitance and gate charge. When changing the state of the output, the peak current is applied for a short period of time (tDRIVE), to charge the gate capacitance. After this time, a weak current source is used to keep the gate at the desired state. When selecting the gate drive strength for a given external FET, the selected current must be high enough to fully charge and discharge the gate during the time when driven at full current, or excessive power will be dissipated in the FET. During high-side turn-on, the low-side gate is pulled low. This prevents the gate-source capacitance of the lowside FET from inducing turn-on. The pre-driver circuits include enforcement of a dead time in analog circuitry, which prevents the high-side and low-side FETs from conducting at the same time. Additional dead time is added with digital delays. This delay can be selected by setting the DTIME bits in the CTRL register. 16 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DRV8711 DRV8711 www.ti.com SLVSC40 – JUNE 2013 tDRIVE High Z HS drive (mA) High Z High Z Low Z Low Z xHS (V) tDRIVE High Z Low Z High Z High Z LS drive (mA) Low Z xLS (V) tDEAD tDEAD Figure 6. Pre-Drivers Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DRV8711 17 DRV8711 SLVSC40 – JUNE 2013 www.ti.com Gate Pre-drive Source Capability I (mA) source I (mA) source TDRIVEP = 00 TDRIVEP = 01 200 mA 200 mA IDRIVEP = 11 IDRIVEP = 11 150 mA 150 mA IDRIVEP = 10 IDRIVEP = 10 100 mA 100 mA IDRIVEP = 01 IDRIVEP = 01 50 mA 50 mA IDRIVEP = 00 IDRIVEP = 00 Holding Current Holding Current t (ns) 250 ns 500 ns 1 µs t (ns) 2 µs 250 ns 500 ns I (mA) source 1 µs 2 µs I (mA) source TDRIVEP = 10 TDRIVEP = 11 200 mA 200 mA IDRIVEP = 11 IDRIVEP = 11 150 mA 150 mA IDRIVEP = 10 IDRIVEP = 10 100 mA 100 mA IDRIVEP = 01 IDRIVEP = 01 50 mA 50 mA IDRIVEP = 00 IDRIVEP = 00 Holding Current Holding Current t (ns) 250 ns 500 ns 1 µs t (ns) 2 µs 250 ns 500 ns 1 µs 2 µs Gate Pre-drive Sink Capability TDRIVEN = 00 250 ns 500 ns 1 µs TDRIVEN = 01 2 µs 250 ns 500 ns 1 µs 2 µs t (ns) Holding Current t (ns) Holding Current IDRIVEN = 00 IDRIVEN = 00 100 mA 100 mA IDRIVEN = 01 IDRIVEN = 01 200 mA 200 mA IDRIVEN = 10 IDRIVEN = 10 300 mA 300 mA IDRIVEN = 11 IDRIVEN = 11 400 mA 400 mA I (mA) sink 250 ns 500 ns I (mA) sink TDRIVEN = 10 1 µs 2 µs 250 ns 500 ns TDRIVEN = 11 1 µs 2 µs t (ns) t (ns) Holding Current Holding Current IDRIVEN = 00 100 mA IDRIVEN = 00 100 mA IDRIVEN = 01 200 mA IDRIVEN = 01 200 mA IDRIVEN = 10 300 mA IDRIVEN = 10 300 mA IDRIVEN = 11 400 mA IDRIVEN = 11 400 mA I (mA) sink I (mA) sink Figure 7. Gate Pre-Drive Source/Sink Capability Configuring Pre-drivers IDRIVE and TDRIVE are selected based on the size of external FETs used. These registers need to be configured so that the FET gates are charged completely during TDRIVE. If IDRIVE and TDRIVE are chosen to be too low for a given FET, then the FET may not turn on completely. It is suggested to adjust these values insystem with the required external FETs and stepper motor in order to determine the best possible setting for any application. Note that TDRIVE will not increase the PWM time or change the PWM chopping frequency. 18 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DRV8711 DRV8711 www.ti.com SLVSC40 – JUNE 2013 In a system with capacitor charge Q and desired rise time RT, IDRIVE and TDRIVE can be initially selected based on: IDRIVE > Q / RT TDRIVE > 2 x RT For best results, select the smallest IDRIVE and TDRIVE that meet the above conditions. Example: If the gate charge is 15 nC and the desired rise time is 400 ns, then select: IDRIVEP = 50 mA, IDRIVEN = 100 mA TDRIVEP = TDRIVEN = 1 µs External FET Selection In a typical setup, the DRV8711 can support external FETs over 50 nC each. However, this capacity can be lower or higher based on the device operation. For an accurate calculation of FET driving capacity, use the following equation. 20mA · (2 · DTIME + TBLANK + TOFF) Q< (3) 4 Example: If a DTIME is set to 0 (400 ns), TBLANK is set to 0 (1 µs), and TOFF is set to 0 (500 ns), then the DRV8711 will support Q < 11.5 nC FETs (please note that this is an absolute worst-case scenario with a PWM frequency ~ 430 kHz). If a DTIME is set to 0 (400 ns), TBLANK is set to 0 (1 µs), and TOFF is set to 0x14 (10 µs), then the DRV8711 will support Q < 59 nC FETs (PWM frequency ~ 85 kHz). If a DTIME is set to 0 (400 ns), TBLANK is set to 0 (1 µs), and TOFF is set to 0x60 (48 µs), then the DRV8711 will support Q < 249 nC FETs (PWM frequency ~ 20 kHz). Stall Detection The DRV8711 implements a back EMF monitoring scheme that is capable of detecting a stall during stepper motor motion. This stall detection is intended to be used to get an indication when a motor is run into a mechanical stop, or when an increased torque load on the motor causes it to stall. To determine that a stall has occurred, a drop in motor back EMF is detected. The DRV8711 supports two methods of this detection: an automatic internal stall detection circuit, or the ability to use an external microcontroller to monitor back EMF. During a zero-current step, one side of the H-bridge is placed in a high impedance state, and the opposite lowside FET is turned on for a brief duration defined by TORQUE register SMPLTH bit [10:8]. This allows the current to decay quickly through the low-side FET and the opposite body diode. Which side of the bridge is tri-state and which one is driven low depends on the current direction on the previous step. The bridge with the high side that has been actively PWMed (at the beginning of the PWM cycle during blank time) prior to entering the zerocurrent step will be held low and the opposite side will be tri-stated. Back EMF is sampled on the tri-stated output pin at the end of SMPLTH time (TORQUE register bit [10:8]). The back EMF from the selected pin is divided by 4, 8, 16, or 32, depending on the setting of the VDIV bits in the STALL register. The voltage is buffered and held on an external capacitor placed on the BEMF pin. The signal on the BEMF output pin can be further processed by a microcontroller to implement more advanced control and stall detection algorithms. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DRV8711 19 DRV8711 SLVSC40 – JUNE 2013 www.ti.com VM AOUT1 BEMF buffer 2 VDIV VM Step Motor AOUT2 2 control logic To STATUS register STALLn/ BEMFVn VDIV VM SDCNT 2 BOUT1 + counter comp 2 reference 1.80 V VM VDIV BOUT2 8 SDTHR DAC SDTHR DAC 2 VDIV Figure 8. Stall Detection Internal Stall Detection To use internal stall detection, the EXSTALL bit in the CTRL register is set to ‘0’. In this mode, the STALLn/BEMFVn output pin is used to signal a valid stall condition. Step time, or rate at which step input is applied to DRV8711, has to be greater than SMPLTH time for back EMF sampling. Using internal stall detection, a stall is detected when the sampled back EMF drops below the value set by the SDTHR bits in the STALL register. A programmable counter circuit allows the assertion of the STALLn output to be delayed until the back EMF has been sampled below the SDTHR value for more than one zero-current step. The counter is programmed by the SDCNT bits in the STALL register, and provides selections of 1, 2, 4, or 8 steps. When the stall is detected (at the end of a SMPLTH interval), the STALLn/BEMFVn pin is driven active low, and the STD bit and the STDLAT bit in the STATUS register are set. The STALLn/BEMFVn pin will deassert and the STD bit will automatically clear at the next zero-current step if a stall condition is not detected, while the STDLAT bit will remain set until a '0' is written to it. The STDLAT is reset when the STD bit clears after the first zero-cross step that does not detect a stall condition. This stall detection scheme is only effective when the motor is stalled while running at or above some minimum speed. Since it relies on detecting a drop in motor back EMF, the motor must be rotating with sufficient speed to generate a detectable back EMF. During motor start-up, and at very slow step rates, the stall detection is not reliable. Since back EMF can only be sampled during a zero-current state, stall detection is not possible in full step mode. During full-step operation, the stall detect circuit is gated off to prevent false signaling of a stall. The correct setting of the SDTHR bits needs to be determined experimentally. It is dependent on many factors, including the electrical and mechanical characteristics of the load, the peak current setting, and the supply voltage. 20 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DRV8711 DRV8711 www.ti.com SLVSC40 – JUNE 2013 External Stall Detection To use an external microcontroller to manage stall detection, the EXSTALL bit in the CTRL register is set to ‘1’. In this mode, the STALLn / BEMFVn output pin is used to signal a valid back EMF measurement is ready. In addition, the SDT and SDTLAT bits are also set at this time. BEMFVn and BEMF are still valid outputs in this mode even if the step time is smaller than SMPLTH time. When the BEMFVn pin goes active low, it is an indication that a valid back EMF voltage measurement is available. This signal could be used, for example, to trigger an interrupt on a microcontroller. The microcontroller can then sample the voltage present (using an A/D converter) on the BEMF pin. After sampling the back EMF voltage, the microcontroller writes a ‘0’ to the SDTLAT bit to clear the SDT bit and BEMFVn pin, in preparation for the next back EMF sample. If the SDTLAT bit is not cleared by the microcontroller, it will automatically be cleared in the next zero-current step. For either internal or external stall detection, at very high motor speeds when the PWM duty cycle approaches 100%, the inductance of the motor and the short duration of each step may cause the time required for current recirculation to exceed the step time. In this case, back EMF will not be correctly sampled, and stall detection cannot function. This condition occurs most at high degrees of micro-stepping, since the zero current step lasts for a shorter duration. It is advisable to run the motor at lower degrees of micro-stepping at higher speeds to allow time for current recirculation if stall detection is needed in this condition. RESET and SLEEPn Operation An internal power-up reset circuit monitors the voltage applied to the VM pin. If VM falls below the VM undervoltage lockout voltage, the part is reset, as described below for the case of asserting the RESET pin. If the RESET pin is asserted, all internal logic including the indexer is reset. All registers are returned to their initial default conditions. The power stage will be disabled, and all inputs, including STEP and the serial interface, are ignored when RESET is active. On exiting reset state, some time (approximately 1 mS) needs to pass before the part is fully functional. Applying an active low input to the SLEEPn input pin will place the device into a low power state. In sleep mode, the motor driver circuitry is disabled, the gate drive regulator and charge pump are disabled, and all analog circuitry is placed into a low power state. The digital circuitry in the device still operates, so the device registers can still be accessed via the serial interface. When SLEEPn is active, the RESET pin does not function. SLEEPn must be exited before RESET will take effect. When exiting from sleep mode, some time (approximately 1 mS) needs to pass before applying a STEP input, to allow the internal circuitry to stabilize. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DRV8711 21 DRV8711 SLVSC40 – JUNE 2013 www.ti.com Microstepping Drive Current The following plots are examples of stepper motor current in one of the windings. Since these waveforms are dependent on DRV8711 register settings as well as the external FETs, sense resistor, and stepper motor, they should only be used as a reference. 1/4 stepping 1/8 stepping Current Current STEP STEP 1/16 stepping 1/128 stepping Current STEP Current STEP Figure 9. Microstepping Drive Current 22 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DRV8711 DRV8711 www.ti.com SLVSC40 – JUNE 2013 Protection Circuits The DRV8711 is fully protected against undervoltage, overcurrent and overtemperature events. Overcurrent Protection (OCP) Overcurrent is sensed by monitoring the voltage drop across the external FETs. If the voltage across a driven FET exceeds the value programmed by the OCPTH bits in the DRIVE register for more than the time period specified by the OCPDEG bits in the DRIVE register, an OCP event is recognized. When operating in direct PWM mode, during an OCP event, the H-bridge experiencing the OCP event is disabled; if operating in indexer mode, both H-bridges will be disabled. In addition, the corresponding xOCP bit in the STATUS register is set, and the FAULTn pin is driven low. The H-bridge(s) will remain off, and the xOCP bit will remain set, until it is written to 0, or the device is reset. Pre-Driver Fault If excessive current is detected on the gate drive outputs (which would be indicative of a failed/shorted output FET or PCB fault), the H-bridge experiencing the fault is disabled, the xPDF bit in the STATUS register is set, and the FAULTn pin is driven low. The H-bridge will remain off, and the xPDF bit will remain set until it is written to 0, or the device is reset. Thermal Shutdown (TSD) If the die temperature exceeds safe limits, all FETs in the H-bridge will be disabled, the OTS bit in the STATUS register will be set, and the FAULTn pin will be driven low. Once the die temperature has fallen to a safe level operation will automatically resume and the OTS bit will reset. The FAULTn pin will be released after operation has resumed. Undervoltage Lockout (UVLO) If at any time the voltage on the VM pin falls below the undervoltage lockout threshold voltage, all FETs in the Hbridge will be disabled, the UVLO bit in the STATUS register will be set, and the FAULTn pin will be driven low. Operation will resume and the UVLO bit will reset when VM rises above the UVLO threshold. The FAULTn pin will be released after operat ion has resumed. During any of these fault conditions, the STEP input pin will be ignored. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DRV8711 23 DRV8711 SLVSC40 – JUNE 2013 www.ti.com Serial Data Format The serial data consists of a 16-bit serial write, with a read/write bit, 3 address bits and 12 data bits. The three address bits identify one of the registers defined in the register section above. To write to a register, data is shifted in after the address as shown in the timing diagram below: SCS SCLK 1 SDATI WRT A. 2 3 A2 4 A1 A0 5 6 D11 D10 7 Note 1 8 D9 D8 X 9 10 11 12 13 14 15 16 D7 D6 D5 D4 D3 D2 D1 D0 Any amount of time may pass between bits, as long as SCS stays active high. This allows two 8-bit writes to be used. Figure 10. Write Operation Data may be read from the registers through the SDATO pin. During a read operation, only the address is used form the SDATI pin; the data bits following are ignored. Reading is enabled by setting the READ bit at the beginning of the access: SCS SCLK 1 SDATI READ 2 A2 3 A1 4 6 D11 D10 7 8 Note 1 9 10 11 12 13 14 6 15 D6 D5 D4 D3 D2 D1 16 A0 SDATO (1) 5 D9 D8 D7 D0 Any amount of time may pass between bits, as long as SCS stays active high. This allows two 8-bit writes to be used. Figure 11. Read Operation 24 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DRV8711 DRV8711 www.ti.com SLVSC40 – JUNE 2013 CONTROL REGISTERS The DRV8711 uses internal registers to control the operation of the motor. The registers are programmed via a serial SPI communications interface. At power-up or reset, the registers will be pre-loaded with default values as shown below. Following is a map of the DRV8711 registers: DRV8711 REGISTER MAP Name 11 CTRL TORQUE 10 9 DTIME 8 7 6 5 4 EXSTALL ISGAIN 2 1 0 RSTEP RDIR ENBL Address Hex RW 00 TORQUE RW 01 MODE SMPLTH Reserved 3 OFF Reserved PWMMODE TOFF RW 02 BLANK Reserved ABT TBLANK RW 03 TDECAY RW 04 SDTHR RW 05 RW 06 DECAY DECMOD Reserved STALL VDIV SDCNT DRIVE IDRIVEP IDRIVEN STATUS Name TDRIVEP STDLAT Reserved 11 10 9 8 7 TDRIVEN STD 6 UVLO 5 OCPDEG BPDF 4 APDF 3 OCPTH BOCP 2 AOCP 1 OTS 0 RW 07 Address Hex Figure 12. DRV8711 Register Map Individual register contents are defined below. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DRV8711 25 DRV8711 SLVSC40 – JUNE 2013 www.ti.com CTRL Register Address = 0x00h BIT NAME SIZE R/W DEFAULT DESCRIPTION 0 ENBL 1 R/W 0 0: Disable motor 1: Enable motor 1 RDIR 1 R/W 0 0: Direction set by DIR pin 1: Direction set by inverse of DIR pin 2 RSTEP 1 W 0 0: No action 1: Indexer will advance one step; automatically cleared after write 0000: Full-step, 71% current 0001: Half step 0010: 1/4 step 0011: 1/8 step 0100: 1/16 step 0101: 1/32 step 0110: 1/64 step 0111: 1/128 step 1000: 1/256 step 1001 – 1111: Reserved 6-3 MODE 4 R/W 110 7 EXSTALL 1 R/W 0 0: Internal stall detect 1: External stall detect 0 ISENSE amplifier gain set 00: Gain of 5 01: Gain of 10 10: Gain of 20 11: Gain of 40 Dead time set 00: 400 ns dead time 01: 450 ns dead time 10: 650 ns dead time 11: 850 ns dead time 9-8 11-10 ISGAIN DTIME 2 R/W 2 R/W 11 TORQUE Register Address = 0x01h BIT NAME SIZE R/W DEFAULT 7-0 TORQUE 8 R/W 0xFFh DESCRIPTION Sets full-scale output current for both H-bridges 10-8 SIMPLTH 3 R/W 1 Back EMF sample threshold 000: 50 µs 001: 100 µs 010: 200 µs 011: 300 µs 100: 400 µs 101: 600 µs 110: 800 µs 111: 1000 µs 11 Reserved 1 - - Reserved OFF Register Address = 0x02h BIT NAME SIZE R/W DEFAULT 7-0 TOFF 8 R/W 0x30h 8 PWMMODE 1 R/W 0 0: Use internal indexer 1: Bypass indexer, use xINx inputs to control outputs 11-9 Reserved 3 - - Reserved 26 DESCRIPTION Sets fixed off time, in increments of 500 ns 0x00h: 500 ns 0xFFh: 128 µs Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DRV8711 DRV8711 www.ti.com SLVSC40 – JUNE 2013 BLANK Register Address = 0x03h BIT NAME SIZE R/W DEFAULT DESCRIPTION Sets current trip blanking time, in increments of 20 ns 0x00h: 1.00 µs … 0x32h: 1.00 µs 0x33h: 1.02 µs … 0xFEh: 5.10 µs 0xFFh: 5.12 µs Also sets minimum on-time of PWM 7-0 TBLANK 8 R/W 0x80h 8 ABT 1 R/W 0 0: Disable adaptive blanking time 1: Enable adaptive blanking time 11-9 Reserved 3 - - Reserved DECAY Register Address = 0x04h BIT NAME SIZE R/W DEFAULT 7-0 TDECAY 8 R/W 0x10h DESCRIPTION Sets mixed decay transition time, in increments of 500 ns 10-8 DECMOD 3 R/W 1 000: Force slow decay at all times 001: Slow decay for increasing current, mixed decay for decreasing current (indexer mode only) 010: Force fast decay at all times 011: Use mixed decay at all times 100: Slow decay for increasing current, auto mixed decay for decreasing current (indexer mode only) 101: Use auto mixed decay at all times 110 – 111: Reserved 11 Reserved 1 - - Reserved STALL Register Address = 0x05h BIT NAME SIZE R/W DEFAULT 7-0 SDTHR 8 R/W 0x40h 10-8 11 SDCNT VDIV 2 2 R/W R/W DESCRIPTION Sets stall detect threshold The correct setting needs to be determined experimentally 0 00: STALLn asserted on first step with back EMF below SDTHR 01: STALLn asserted after 2 steps 10: STALLn asserted after 4 steps 11: STALLn asserted after 8 steps 0 00: Back EMF is divided by 32 01: Back EMF is divided by 16 10: Back EMF is divided by 8 11: Back EMF is divided by 4 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DRV8711 27 DRV8711 SLVSC40 – JUNE 2013 www.ti.com DRIVE Register Address = 0x06h BIT 1-0 3-2 5-4 7-6 9-8 11-10 28 NAME OCPTH OCPDEG TDRIVEN TDRIVEP IDRIVEN IDRIVEP SIZE 2 2 2 2 2 2 R/W R/W R/W R/W R/W R/W R/W DEFAULT DESCRIPTION 0 OCP threshold 00: 250 mV 01: 500 mV 10: 750 mV 11: 1000 mV 10 OCP deglitch time 00: 1 µs 01: 2 µs 10: 4 µs 11: 8 µs 1 Low-side gate drive time 00: 250 ns 01: 500 ns 10: 1 µs 11: 2 µs 1 High-side gate drive time 00: 250 ns 01: 500 ns 10: 1 µs 11: 2 µs 0 Low-side gate drive peak current 00: 100 mA peak (sink) 01: 200 mA peak (sink) 10: 300 mA peak (sink) 11: 40 0mA peak (sink) 0 High-side gate drive peak current 00: 50 mA peak (source) 01: 100 mA peak (source) 10: 150 mA peak (source) 11: 200 mA peak (source) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DRV8711 DRV8711 www.ti.com SLVSC40 – JUNE 2013 STATUS Register Address = 0x07h BIT NAME SIZE R/W DEFAULT DESCRIPTION 0 OTS 1 R 0 0: Normal operation 1: Device has entered overtemperature shutdown OTS bit will clear once temperature has fallen to safe levels 1 AOCP 1 R/W 0 0: Normal operation 1: Channel A overcurrent shutdown Write a ‘0’ to this bit to clear the fault and resume operation 2 BOCP 1 R/W 0 0: Normal operation 1: Channel B overcurrent shutdown Write a ‘0’ to this bit to clear the fault and resume operation 3 UVLO 1 R 0 0: Normal operation 1: Undervoltage lockout UVLO bit will clear after VM has increased over VUVLO 4 APDF 1 R/W 0 0: Normal operation 1: Channel A predriver fault Write a ‘0’ to this bit to clear the fault and resume operation 5 BPDF 1 R/W 0 0: Normal operation 1: Channel B predriver fault Write a ‘0’ to this bit to clear the fault and resume operation 6 STD 1 R 0 0: Normal operation 1: Stall detected 7 STDLAT 1 R/W 0 0: Normal operation 1: Latched stall detect Write a ‘0’ to this bit to clear the fault and resume operation 11-8 Reserved 4 - - Reserved Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DRV8711 29 PACKAGE OPTION ADDENDUM www.ti.com 28-Jun-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) DRV8711DCP ACTIVE HTSSOP DCP 38 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 DRV8711 DRV8711DCPR ACTIVE HTSSOP DCP 38 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 DRV8711 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 Samples IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2013, Texas Instruments Incorporated