DRV8806 www.ti.com SLVSBA3 – JUNE 2012 QUAD SERIAL INTERFACE LOW-SIDE DRIVER IC Check for Samples: DRV8806 FEATURES 1 • 2 • 4-Channel Protected Low-Side Driver – Four NMOS FETs With Overcurrent Protection – Integrated Inductive Catch Diodes – Serial Interface – Open/Shorted Load Detection 2-A (Single Channel On)/1-A (All Channels On) Maximum Drive Current per Channel (at 25°C) • • 8.2-V to 40-V Operating Supply Voltage Range Thermally Enhanced Surface Mount Package APPLICATIONS • • • • Relay Drivers Unipolar Stepper Motor Drivers Solenoid Drivers General Low-Side Switch Applications DESCRIPTION The DRV8806 provides a 4-channel low side driver with overcurrent protection. It has built-in diodes to clamp turn-off transients generated by inductive loads and can be used to drive unipolar stepper motors, DC motors, relays, solenoids, or other loads. The DRV8806 can supply up to 2-A (single channel on) or 1-A (all channels on) continuous output current (with adequate PCB heatsinking at 25°C). A serial interface is provided to control the output drivers. Fault status can be read through the serial interface. Multiple DRV8806 devices can be chained together to use a single serial interface. Internal shutdown functions are provided for over current protection, short circuit protection, under voltage lockout and overtemperature and faults are indicated by a fault output pin. The DRV8806 is available in a 16-pin HTSSOP package (Eco-friendly: RoHS & no Sb/Br). ORDERING INFORMATION (1) ORDERABLE PART NUMBER TOP-SIDE MARKING Reel of 2000 DRV8806PWPR DRV8806 Tube of 90 DRV8806PWP DRV8806 PACKAGE (2) (HTSSOP) - PWP (1) (2) For the most current packaging and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012, Texas Instruments Incorporated DRV8806 SLVSBA3 – JUNE 2012 www.ti.com DEVICE INFORMATION Functional Block Diagram 8.2V - 40V Internal Reference Regs UVLO VM LS Gate Drive OCP, Open load, Gate Drive nENBL LATCH 8.2V - 40V Optional Zener Int. VCC VCLAMP OUT1 Inductive Load SDATIN 4.5V SDATOUT Control Logic SCLK OCP, Open load, Gate Drive OCP, Open load, Gate Drive RESET OUT2 Inductive Load OUT3 Inductive Load nFAULT Thermal Shut down OCP, Open load, Gate Drive OUT4 Inductive Load GND (multiple pins) 2 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): DRV8806 DRV8806 www.ti.com SLVSBA3 – JUNE 2012 Table 1. TERMINAL FUNCTIONS NAME PIN (HTSSOP) I/O (1) EXTERNAL COMPONENTS OR CONNECTIONS DESCRIPTION POWER AND GROUND GND 5, 12, PPAD - Device ground All pins must be connected to GND. 1 - Device power supply Connect to motor supply (8.2 V - 40 V). nENBL 8 I Enable input Active low enables outputs – internal pulldown RESET 9 I Reset input Active-high reset input initializes internal logic – internal pulldown LATCH 11 I Latch input Rising edge latches shift register to output stage, falling edge latches fault data into output shift register – internal pulldown SDATIN 14 I Serial data input Serial data input – internal pulldown SDATOUT 15 OD Serial data output Serial data output - open drain output - internal pullup SCLK 13 I Serial clock Serial clock input – internal pulldown 16 OD Fault Logic low when in fault condition (overtemp, overcurrent, open load) - open drain output OUT1 3 O Output 1 Connect to load 1 OUT2 4 O Output 2 Connect to load 2 OUT3 6 O Output 3 Connect to load 3 OUT4 7 O Output 4 Connect to load 4 VCLAMP 2 - Output clamp voltage Connect to VM supply, or zener diode to VM supply VM CONTROL STATUS nFAULT OUTPUT (1) Directions: I = input, O = output, OD = open-drain output PWP (HTSSOP) PACKAGE (TOP VIEW) VM VCLAMP OUT1 OUT2 GND OUT3 OUT4 nENBL 1 16 2 15 3 14 13 4 5 6 7 8 GND 12 11 10 9 nFAULT SDATOUT SDATIN SCLK GND LATCH NC RESET Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): DRV8806 3 DRV8806 SLVSBA3 – JUNE 2012 www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) (2) VALUE UNIT VM Power supply voltage range –0.3 to 43 V VOUTx Output voltage range –0.3 to 43 V VCLAMP Clamp voltage range –0.3 to 43 V SDATOUT, nFAULT Output current 20 mA 2 A 1 A Digital input pin voltage range –0.5 to 7 V Digital output pin voltage range –0.5 to 7 V Internally limited A Peak clamp diode current (3) DC or RMS clamp diode current (3) SDATOUT, nFAULT Peak motor drive output current, t < 1 μS Continuous total power dissipation (3) See Thermal Information table TJ Operating virtual junction temperature range (3) –40 to 150 °C Tstg Storage temperature range –60 to 150 °C (1) (2) (3) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. Power dissipation and thermal limits must be observed. THERMAL INFORMATION DRV8806 THERMAL METRIC (1) PWP UNITS 16 PINS Junction-to-ambient thermal resistance (2) θJA (3) 39.6 θJCtop Junction-to-case (top) thermal resistance θJB Junction-to-board thermal resistance (4) 20.3 ψJT Junction-to-top characterization parameter (5) 0.7 ψJB Junction-to-board characterization parameter (6) 20.1 θJCbot Junction-to-case (bottom) thermal resistance (7) 2.3 (1) (2) (3) (4) (5) (6) (7) 4 24.6 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): DRV8806 DRV8806 www.ti.com SLVSBA3 – JUNE 2012 RECOMMENDED OPERATING CONDITIONS MIN VM Power supply voltage range VCLAMP Output clamp voltage range (1) IOUT (1) (2) NOM MAX UNIT 8.2 40 V 0 40 V Continuous output current, single channel on, TA = 25°C (2) 2 Continuous output current, four channels on, TA = 25°C (2) 1 A VCLAMP is not a power supply input pin - it only connects to the output clamp diodes. Power dissipation and thermal limits must be observed. ELECTRICAL CHARACTERISTICS TA = 25°C, over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 1.6 3 UNIT POWER SUPPLIES IVM VM operating supply current VM = 24 V VUVLO VM undervoltage lockout voltage VM rising mA 8.2 V 0.8 V LOGIC-LEVEL INPUTS (SCHMITT TRIGGER INPUTS WITH HYSTERESIS) VIL Input low voltage VIH Input high voltage VHYS Input hysteresis IIL Input low current VIN = 0 IIH Input high current VIN = 3.3 V RPD Pulldown resistance 2 V 0.45 –20 V 20 μA 100 μA 100 kΩ nFAULT OUTPUT (OPEN-DRAIN OUTPUT) VOL Output low voltage IO = 5 mA IOH Output high leakage current VO = 3.3 V 0.5 V 1 μA SDATOUT OUTPUT (OPEN-DRAIN OUTPUT WITH INTERNAL PULLUP) VOL Output low voltage IO = 5 mA 0.5 V VOH Output high voltage IO = 100 µA 4.5 V LOW-SIDE FETS RDS(ON) FET on resistance IOFF Open load detect current VM = 24 V, IO = 700 mA, TJ = 25°C 0.5 VM = 24 V, IO = 700 mA, TJ = 85°C 0.75 0.8 25 50 μA -50 50 μA 0 Ω HIGH-SIDE DIODES VF Diode forward voltage VM = 24 V, IO = 700 mA, TJ = 25°C IOFF Off state leakage current VM = 24 V, TJ = 25°C 0.9 V tR Rise time VM = 24 V, IO = 700 mA, Resistive load 50 300 ns tF Fall time VM = 24 V, IO = 700 mA, Resistive load 50 150 ns 3 5 A OUTPUTS PROTECTION CIRCUITS IOCP Overcurrent protection trip level tOCP Overcurrent protection deglitch time 3.5 µs tOL Open load detect deglitch time 15 µs tRETRY Overcurrent protection re-try time 1.2 ms tTSD Thermal shutdown temperature Die temperature 150 160 180 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): DRV8806 °C 5 DRV8806 SLVSBA3 – JUNE 2012 www.ti.com TIMING REQUIREMENTS over operating free-air temperature range (unless otherwise noted) (1) NO. (1) PARAMETER DESCRIPTION MIN MAX UNIT 1 tCYC Clock cycle time 62 ns 2 tCLKH Clock high time 25 ns 3 tCLKL Clock low time 25 ns 4 tSU(SDATIN) Setup time, SDATIN to SCLK 5 ns 5 tH(SDATIN) Hold time, SDATIN to SCLK 1 6 tD(SDATOUT) Delay time, SCLK to SDATOUT 7 tW(LATCH) Pulse width, LATCH 8 tOE(ENABLE) Enable time, nENBL to output low 50 9 tD(LATCH) Delay time, LATCH to output change 50 - tRESET RESET pulse width 20 µs 10 tD(RESET) Reset delay before clock 20 µs 11 tSTARTUP Startup delay VM applied before clock 55 µs ns 15 200 ns ns ns ns Not production tested. 10 RESET nENBL 7 VM 11 1 SCLK LATCH 2 3 Data in valid SDATIN 4 SDATOUT OUTx 8 5 Data out valid 9 CLK 6 Figure 1. DRV8806 Timing Requirements 6 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): DRV8806 DRV8806 www.ti.com SLVSBA3 – JUNE 2012 FUNCTIONAL DESCRIPTION Output Drivers The DRV8806 contains four protected low-side drivers. Each output has an integrated clamp diode connected to a common pin, VCLAMP. VCLAMP can be connected to the main power supply voltage, VM. It can also be connected to a zener or TVS diode to VM, allowing the switch voltage to exceed the main supply voltage VM. This connection can be beneficial when driving loads that require very fast current decay, such as unipolar stepper motors. In all cases, the voltage on the outputs must not be allowed to exceed the maximum output voltage specification. Serial Interface Operation The DRV8806 is controlled with a simple serial interface. Logically, the interface is shown in Figure 2. nENBL LATCH RESET SCLK SDATIN D Q D OUT1 Q CLR CLR D Q D OUT2 Q CLR CLR D Q D OUT3 Q CLR CLR D Q D OUT4 Q CLR CLR 4.5V D Q CLR SDATOUT 0 1 from fault register Figure 2. Serial Interface Operation Data is shifted into a temporary holding shift register in the part using the SDATIN pin, one bit at each rising edge of the SCLK pin, while LATCH is low. Data is shifted from the last bit to the SDATOUT pin, so multiple devices may be daisy-chained together using a single serial interface. Note that the SDATOUT pin has a weak pullup to an internal 4.5-V power supply, which can support driving another DRV8806 SDATIN pin at clock frequencies of up to 1 MHz without an external pullup. To operate at faster than 1-MHz clock frequency or to interface to devices operating at other supply voltages, a pullup resistor of approximately 1 kΩ to the chosen logic supply voltage should be used. A rising edge on the LATCH pin latches the data from the temporary shift register into the output stage. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): DRV8806 7 DRV8806 SLVSBA3 – JUNE 2012 www.ti.com Fault Output Register The DRV8806 contains circuitry to detect open or shorted loads. The status of the loads can be read via the serial interface. The logic is shown in Figure 3. From output SR OUT1 OCP, Open load, Gate Drive Open load 25µA OCP S Q OCP_FAULT nFAULT R from other ch. S Q OPEN_FAULT R Overtemp SDATIN 1 0 D LD SCLK Q CLR 1 from output 2 0 D LD Q CLR LATCH D Q RESET 1 from output 3 0 CLR D LD Q CLR 4.5V 1 from output 4 0 D LD Q SDATOUT CLR 1 0 from output register Figure 3. Fault Output To overcome any leakage currents to accurately sense an open load, a small current source is connected to each output pin. This source pulls approximately 25-µA of current to ground. The voltage on the output pin is sensed during the time that the output is off, and if the voltage on the pin is less than 1.2 V (indicating that there is no load connected) after the open load deglitch time, the OPEN_FAULT latch is set. This latch is cleared whenever the output bit is set. When the output is turned on, if an overcurrent (OCP) fault is detected, the channel will be turned off and the OCP_FAULT latch is set. This latch will be cleared whenever the output bit is cleared. The state of the OCP_FAULT and OPEN_FAULT signals is combined into a single fault bit per channel, and loaded into a shift register while the LATCH pin is low. When the LATCH pin is taken high, the fault data is latched into the shift register at the first falling edge of SCLK. Data may then be shifted out on the SDATOUT pin on each falling edge of the SCLK pin. Note that the LATCH signal must be high for a minimum of 200 ns before valid data can be clocked out. The nFAULT pin will be driven active low whenever any of the OCP_FAULT or OPEN_FAULT latches are set, as well as whenever there is an overtemperature condition. 8 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): DRV8806 DRV8806 www.ti.com SLVSBA3 – JUNE 2012 Daisy-Chain Connection Two or more DRV8806 devices may be connected together to use a single serial interface. The SDATOUT pin of the first device in the chain is connected to the SDATIN pin of the next device. The SCLK, LATCH, RESET, and nFAULT pins are connected together. + + DRV8806 “A” SDATIN SCLK LATCH SDATOUT SDATIN SCLK LATCH RESET RESET nFAULT nFAULT DRV8806 “B” SDATOUT SDATOUT SDATIN SCLK LATCH RESET nFAULT Figure 4. Daisy-Chain Connection Figure 5 shows an example of a serial transaction, writing the output bits, and then reading the fault status bits, using two devices connected together in a daisy-chain. Note that the LATCH signal must be high for a minimum of 200 ns before valid data can be clocked out. LATCH Fault data latched SCLK SDATI SDATO OUTx 1 OUTB4 2 OUTB3 3 4 OUTB2 5 OUTB1 OUTA4 6 OUTA3 PREVIOUS WRITE DATA 7 OUTA2 8 1 2 3 4 5 6 7 8 OUTA1 FLTB4 FLTB3 FLTB2 OLD OUTPUT FLTB1 FLTA4 FLTA3 FLTA2 FLTA1 NEW OUTPUT Figure 5. Daisy-Chain Serial Transaction nENBL and RESET Operation The nENBL pin enables or disables the output drivers. nENBL must be low to enable the outputs. nENBL does not affect the operation of the serial interface logic. Note that nENBL has an internal pulldown. The RESET pin, when driven active high, resets internal logic, including the OCP fault. All serial interface registers are cleared. Note that RESET has an internal pulldown. An internal power-up reset is also provided, so it is not required to drive RESET at power-up. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): DRV8806 9 DRV8806 SLVSBA3 – JUNE 2012 www.ti.com Protection Circuits The DRV8806 is fully protected against undervoltage, overcurrent and overtemperature events. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this analog current limit persists for longer than the tOCP deglitch time (approximately 3.5 µs), the driver will be disabled and the nFAULT pin will be driven low. The driver will remain disabled for the tRETRY retry time (approximately 1.2 ms), then the fault will be automatically cleared. The fault will be cleared immediately if either RESET pin is activated or VM is removed and re-applied. Thermal Shutdown (TSD) If the die temperature exceeds safe limits, all output FETs will be disabled and the nFAULT pin will be driven low. Once the die temperature has fallen to a safe level, operation will automatically resume. Undervoltage Lockout (UVLO) If at any time the voltage on the VM pin falls below the undervoltage lockout threshold voltage, all circuitry in the device will be disabled, and internal logic will be reset. Operation will resume when VM rises above the UVLO threshold. 10 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): DRV8806 DRV8806 www.ti.com SLVSBA3 – JUNE 2012 THERMAL INFORMATION Thermal Protection The DRV8806 has thermal shutdown (TSD) as described above. If the die temperature exceeds approximately 150°C, the device will be disabled until the temperature drops to a safe level. Any tendency of the device to enter TSD is an indication of either excessive power dissipation, insufficient heatsinking, or too high an ambient temperature. Power Dissipation Power dissipation in the DRV8806 is dominated by the power dissipated in the output FET resistance, or RDS(ON). Average power dissipation of each FET when running a static load can be roughly estimated by Equation 1: P = RDS(ON) · (IOUT)2 (1) where P is the power dissipation of one FET, RDS(ON) is the resistance of each FET, and IOUT is equal to the average current drawn by the load. Note that at start-up and fault conditions this current is much higher than normal running current; these peak currents and their duration also need to be taken into consideration. When driving more than one load simultaneously, the power in all active output stages must be summed. The maximum amount of power that can be dissipated in the device is dependent on ambient temperature and heatsinking. Note that RDS(ON) increases with temperature, so as the device heats, the power dissipation increases. This must be taken into consideration when sizing the heatsink. Heatsinking The PowerPAD™ package uses an exposed pad to remove heat from the device. For proper operation, this pad must be thermally connected to copper on the PCB to dissipate heat. On a multi-layer PCB with a ground plane, this can be accomplished by adding a number of vias to connect the thermal pad to the ground plane. On PCBs without internal planes, copper area can be added on either side of the PCB to dissipate heat. If the copper area is on the opposite side of the PCB from the device, thermal vias are used to transfer the heat between top and bottom layers. For details about how to design the PCB, refer to TI Application Report SLMA002, "PowerPAD™ Thermally Enhanced Package" and TI Application Brief SLMA004, "PowerPAD™ Made Easy", available at www.ti.com. In general, the more copper area that can be provided, the more power can be dissipated. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): DRV8806 11 PACKAGE OPTION ADDENDUM www.ti.com 2-Jul-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) DRV8806PWP ACTIVE HTSSOP PWP 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR DRV8806PWPR ACTIVE HTSSOP PWP 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device DRV8806PWPR Package Package Pins Type Drawing SPQ HTSSOP 2000 PWP 16 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 12.4 Pack Materials-Page 1 6.9 B0 (mm) K0 (mm) P1 (mm) 5.6 1.6 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DRV8806PWPR HTSSOP PWP 16 2000 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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