DRV8811 www.ti.com ................................................................................................................................................. SLVS865D – SEPTEMBER 2008 – REVISED JULY 2009 STEPPER MOTOR CONTROLLER IC FEATURES APPLICATIONS • Pulse Width Modulation (PWM) Microstepping Motor Driver – Built-In Microstepping Indexer – Up to 2.5-A Current Per Winding – Three-Bit Winding Current Control Allows up to Eight Current Levels – Low MOSFET On-Resistance • 8-V to 38-V Operating Supply Voltage Range • Thermally Enhanced Surface Mount Package • • • • • • 1 2 Printers Scanners Office Automation Machines Gaming Machines Factory Automation Robotics DESCRIPTION/ORDERING INFORMATION The DRV8811 provides an integrated stepper motor driver solution for printers, scanners, and other automated equipment applications. The device has two H-bridge drivers, as well as microstepping indexer logic to control a stepper motor. The output driver block for each consists of N-channel power MOSFETs configured as full H-bridges to drive the motor windings. A simple step/direction interface allows easy interfacing to controller circuits. Pins allow configuration of the motor in full-step, half-step, quarter-step, or eighth-step modes. Decay mode and PWM off time are programmable. Internal shutdown functions are provided for over current protection, short circuit protection, under-voltage lockout and overtemperature. The DRV8811 is packaged in a PowerPAD™ 28-pin HTSSOP package with thermal pad (Eco-friendly: RoHS and no Sb/Br). ORDERING INFORMATION (1) TA –40°C to 85°C (1) (2) PACKAGE (2) PowerPAD™ (HTSSOP) – PWP ORDERABLE PART NUMBER Reel of 2000 Tube of 50 DRV8811PWPR DRV8811PWP TOP-SIDE MARKING DRV8811 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008–2009, Texas Instruments Incorporated DRV8811 SLVS865D – SEPTEMBER 2008 – REVISED JULY 2009 ................................................................................................................................................. www.ti.com FUNCTIONAL BLOCK DIAGRAM VM VCC CP1 Internal VCC VCC 0.22 µF Internal VGD Reference Charge CP2 Internal Ref VM Pump and VCC LS Gate Drive Regulator VCP Thermal 0.22 µF Shut down HS Gate VM Drive VMA VREF ENABLEn AOUT1 + SLEEPn STEP Motor Step Driver A Motor AOUT2 - DIR Indexer / USM0 + ISENA Control - Logic USM1 VCC RESETn SRn VM VMB HOMEn DECAY BOUT1 RCA Motor Driver B RCB BOUT2 ISENB GND 2 GND Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): DRV8811 DRV8811 www.ti.com ................................................................................................................................................. SLVS865D – SEPTEMBER 2008 – REVISED JULY 2009 TERMINAL FUNCTIONS NAME (1) NO. I/O DESCRIPTION EXTERNAL COMPONENTS OR CONNECTIONS GND 7, 21 - Device ground VMA 28 - Bridge A power supply Connect to motor supply (8 V to 38 V). Both pins must be connected to same supply. VMB 15 - Bridge B power supply Connect to motor supply (8 V to 38 V). Both pins must be connected to same supply. VCC 10 - Logic supply voltage Connect to 3-V to 5-V logic supply. Bypass to GND with a 0.1-µF ceramic capacitor CP1 23 IO Charge pump flying capacitor Connect a 0.22-µF capacitor between CP1 and CP2 CP2 24 IO Charge pump flying capacitor Connect a 0.22-µF capacitor between CP1 and CP2 VCP 22 IO High-side gate drive voltage Connect a 0.22-µF ceramic capacitor to VM VGD 20 IO Low-side gate drive voltage POWER AND GROUND Bypass to GND with a 0.22-µF ceramic capacitor CONTROL ENABLEn 26 I Enable input Logic high to disable device outputs, logic low to enable outputs SLEEPn 27 I Sleep mode input Logic high to enable device, logic low to enter low-power sleep mode DECAY 5 I Decay mode select Voltage applied sets decay mode - see motor driver description for details. Bypass to GND with a 0.1-µF ceramic capacitor STEP 19 I Step input Rising edge causes the indexer to move one step DIR 3 I Direction input Level sets the direction of stepping USM0 13 I Microstep mode 0 USM0 and USM1 set the step mode - full step, half step, quarter step, or eight microsteps/step USM1 12 I Microstep mode 1 USM0 and USM1 set the step mode - full step, half step, quarter step, or eight microsteps/step RESETn 17 I Reset input Active-low reset input initializes the indexer logic and disables the H-bridge outputs SRn 16 I Sync. Rect. enable input When active low, synchronous rectification is enabled VREF 8 I Current set reference input Reference voltage for winding current set RCA 6 I Bridge A blanking and off time adjust Connect a parallel resistor and capacitor to GND - see motor driver description for details RCB 9 I Bridge B blanking and off time adjust Connect a parallel resistor and capacitor to GND - see motor driver description for details ISENA 1 - Bridge A ground / Isense Connect to current sense resistor for bridge A ISENB 14 - Bridge B ground / Isense Connect to current sense resistor for bridge B OUTPUTS AOUT1 4 O Bridge A output 1 Connect to bipolar stepper motor winding A AOUT2 25 O Bridge A output 2 Positive current is AOUT1 → AOUT2 BOUT1 11 O Bridge B output 1 Connect to bipolar stepper motor winding B BOUT2 18 O Bridge B output 2 Positive current is BOUT1 → BOUT2 HOMEn 2 O Home position Logic low when at home state of step table, logic high at other states (1) Directions: I = input, O = output, OZ = 3-state output, OD = open-drain output, IO = input/output Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): DRV8811 3 DRV8811 SLVS865D – SEPTEMBER 2008 – REVISED JULY 2009 ................................................................................................................................................. www.ti.com PWP (HTSSOP) PACKAGE ISENA HOME DIR AOUT1 DECAY RCA GND VREF RCB VCC BOUT1 USM1 USM0 ISENB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 GND (PPAD) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VMA SLEEPn ENABLEn AOUT2 CP2 CP1 VCP GND VGD STEP BOUT2 RESETn SRn VMB ABSOLUTE MAXIMUM RATINGS (1) (2) (3) over operating free-air temperature range (unless otherwise noted) MIN MAX VMX Power supply voltage range –0.3 40 V VCC Power supply voltage range –0.3 7 V Digital pin voltage range –0.5 VCC V –0.3 V VCC V –0.3 0.5 V 6 A ±2.5 A VREF Input voltage range ISENSEx pin voltage range IO(peak) Peak motor drive output current, t < 1 µs IO Continuous motor drive output current PD Continuous total power dissipation TJ Operating virtual junction temperature range TA Operating ambient temperature range Tstg Storage temperature range (1) (2) (3) UNIT See Dissipation Ratings Table 0 150 °C –40 85 °C –60 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. Power dissipation and thermal limits must be observed. DISSIPATION RATINGS BOARD PACKAGE RθJA DERATING FACTOR ABOVE TA = 25°C TA < 25°C TA = 70°C TA = 85°C Low-K (1) PWP 67.5 °C/W 14.8 mW/°C 1.85 W 1.18 W 0.96 W (2) PWP 39.5 °C/W 25.3 mW/°C 3.16 W 2.02 W 1.64 W High-K (3) PWP 33.5 °C/W 29.8 mW/°C 3.73 W 2.38 W 1.94 W High-K (4) PWP 28 °C/W 35.7 mW/°C 4.46 W 2.85 W 2.32 W Low-K (1) (2) (3) (4) 4 The JEDEC Low-K board used to derive this data was a 76 mm x 114 mm, 2-layer, 1.6 mm thick PCB with no backside copper. The JEDEC Low-K board used to derive this data was a 76 mm x 114 mm, 2-layer, 1.6 mm thick PCB with 25 cm2 2-oz copper on backside. The JEDEC High-K board used to derive this data was a 76 mm x 114 mm, 4-layer, 1.6 mm thick PCB with no backside copper and solid 1 oz. internal ground plane. The JEDEC High-K board used to derive this data was a 76 mm x 114 mm, 4-layer, 1.6 mm thick PCB with 25 cm2 1-oz copper on backside and solid 1 oz. internal ground plane. Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): DRV8811 DRV8811 www.ti.com ................................................................................................................................................. SLVS865D – SEPTEMBER 2008 – REVISED JULY 2009 RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VM Motor power supply voltage range (1) 8 38 V VCC Logic power supply voltage range 3 5.5 V VREF VREF input voltage VCC V (1) All VM pins must be connected to the same supply voltage. Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): DRV8811 5 DRV8811 SLVS865D – SEPTEMBER 2008 – REVISED JULY 2009 ................................................................................................................................................. www.ti.com ELECTRICAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 8 mA Power Supplies IVM VM operating supply current VM = 35 V, fPWM < 50 KHz 4.5 IVCC VCC operating supply current fPWM < 50 KHz 0.4 4 mA IVMQ VM sleep mode supply current VM = 35 V 12 20 µA IVCCQ VCC sleep mode supply current 5 20 µA VUVLO VM undervoltage lockout voltage VM rising 6.7 8 VCC undervoltage lockout voltage VCC rising 2.71 2.95 V VREF Input/Current Control Accuracy IREF VREF input current ΔICHOP Chopping current accuracy VREF = 3.3 V –3 3 µA VREF = 2.0 V, 70% to 100% current –5 5 % VREF = 2.0 V, 20% to 56% current –10 10 % 0.3 × VCC V Logic-Level Inputs VIL Input low voltage VIH Input high voltage IIL Input low current VIN = 0.3 × VCC –20 20 µA IIH Input high current VIN = 0.3 × VCC –20 20 µA 0.3 × VCC V 0.7 × VCC V HOMEn Output VOL Output low voltage IO = 200 µA VOH Output high voltage IO = –200 µA 0.7 × VCC V Decay Input VIL Input low threshold voltage For fast decay mode VIH Input high threshold voltage For slow decay mode 0.21 × VCC V 0.6 × VCC V H-Bridge FETS Rds(on) HS FET on resistance Rds(on) LS FET on resistance VM = 24 V, IO = 2.5 A, TJ = 25°C 0.50 VM = 24 V, IO = 2.5 A, TJ = 85°C 0.60 VM = 24 V, IO = 2.5 A, TJ = 25°C 0.50 VM = 24 V, IO = 2.5 A, TJ = 85°C 0.60 IOFF –20 0.75 0.75 Ω Ω 20 µA Motor Driver tOFF Off time Rx = 56 kΩ, Cx = 680 pF 30 38 46 µs tBLANK Current sense blanking time Rx = 56 kΩ, Cx = 680 pF 700 950 1200 ns SRn = 0 100 475 800 ns 2.5 4.5 6.5 A 150 160 180 °C tDT Dead time (1) Protection Circuits IOCP tTSD (1) 6 Overcurrent protection trip level Thermal shutdown temperature (1) Die temperature Not tested in production - guaranteed by design. Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): DRV8811 DRV8811 www.ti.com ................................................................................................................................................. SLVS865D – SEPTEMBER 2008 – REVISED JULY 2009 TIMING REQUIREMENTS over operating free-air temperature range (unless otherwise noted) PARAMETER MIN MAX UNIT 500 kHz fSTEP Step frequency tWH(STEP) Pulse duration, STEP high tWL(STEP) Pulse duration, STEP low tSU(STEP) Setup time, command to STEP rising tH(STEP) Hold time, command to STEP rising 200 ns tWAKE Wakeup time, SLEEPn inactive to STEP 1 ms 1 µs 1 µs 200 ns 1 2 3 STEP DIR, USMx 4 5 SLEEPn 6 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): DRV8811 7 DRV8811 SLVS865D – SEPTEMBER 2008 – REVISED JULY 2009 ................................................................................................................................................. www.ti.com FUNCTIONAL DESCRIPTION PWM H-Bridge Drivers DRV8811 contains two H-bridge motor drivers with current-control PWM circuitry, and a microstepping indexer. A block diagram of the motor control circuitry is shown below. VM OCP VGD VMA VCP AOUT1 + RCA Predrive Step Motor AOUT2 – PWM + – OCP ISENA A=8 DAC OCP VGD VCP Control / Indexer Logic VM VMB BOUT1 Predrive BOUT2 PWM OCP ISENB A=8 DAC RCB DECAY VREF Figure 1. Block Diagram 8 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): DRV8811 DRV8811 www.ti.com ................................................................................................................................................. SLVS865D – SEPTEMBER 2008 – REVISED JULY 2009 Current Regulation The PWM chopping current is set by a comparator, which compares the voltage across a current sense resistor, multiplied by a factor of 8, with a reference voltage. The reference voltage is input from the VREF pin. The full-scale (100%) chopping current is calculated as follows: ICHOP = VREFX 8 · RISENSE (1) Example: If a 0.22-Ω sense resistor is used and the VREFx pin is 3.3 V, the full-scale (100%) chopping current is 3.3 V/(8 * 0.22 Ω) = 1.875 A. The reference voltage is also scaled by an internal DAC that allows torque control for fractional stepping of a bipolar stepper motor, as described in the "Microstepping Indexer" section below. When a winding is activated, the current through it rises until it reaches the chopping current threshold described above, then the current is switched off for a fixed off time. The off time is determined by the values of a resistor and capacitor connected to the RCA (for bridge A) and RCB (for bridge B) pins. The off time is approximated by: tOFF = R · C (2) To avoid falsely tripping on transient currents when the winding is first activated, a blanking period is used immediately after turning on the FETs, during which the state of the current sense comparator is ignored. The blanking time is determined by the value of the capacitor connected to the RCx pin and is approximated by: tBLANK = 1400 · C (3) Decay Mode During PWM current chopping, the H-bridge is enabled to drive through the motor winding until the PWM current chopping threshold is reached. This is shown in Figure 2, Item 1. The current flow direction shown indicates positive current flow in the step table below. Once the chopping current threshold is reached, the H-bridge can operate in two different states, fast decay or slow decay. In fast decay mode, once the PWM chopping current level has been reached, the H-bridge reverses state to allow winding current to flow in a reverse direction. If synchronous rectification is enabled (SRn pin logic low), the opposite FETs are turned on; as the winding current approaches zero, the bridge is disabled to prevent any reverse current flow. If SRn is high, current is recirculated through the body diodes, or through external Schottky diodes. Fast-decay mode is shown in Figure 2, Item 2. In slow-decay mode, winding current is re-circulated by enabling both of the low-side FETs in the bridge. This is shown in Figure 2, Item 3. Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): DRV8811 9 DRV8811 SLVS865D – SEPTEMBER 2008 – REVISED JULY 2009 ................................................................................................................................................. www.ti.com VM 1 Drive current 1 xOUT2 xOUT1 3 2 Fast decay (reverse) 3 Slow decay (brake) 2 Figure 2. Decay Mode The DRV8811 also supports a mixed decay mode. Mixed decay mode begins as fast decay, but after a period of time switches to slow decay mode for the remainder of the fixed off time. Fast and mixed decay modes are only active if the current through the winding is decreasing; if the current is increasing, then slow decay is always used. Which decay mode is used is selected by the voltage on the DECAY pin. If the voltage is greater than 0.6 x VCC, slow decay mode is always used. If DECAY is less than 0.21 x VCC, the device always operates in fast decay mode (when the winding current is decreasing). If the voltage is between these levels, mixed decay mode is enabled. In mixed decay mode, the voltage on the DECAY pin sets the point in the cycle that the change to slow decay mode occurs. This time can be approximated by: æ 0.6 · VCC ö tFD = R · C · In ç è VDECAY ÷ø (4) Operation of the blanking, fixed off time, and mixed decay mode is illustrated in Figure 3. 10 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): DRV8811 DRV8811 www.ti.com ................................................................................................................................................. SLVS865D – SEPTEMBER 2008 – REVISED JULY 2009 PWM ON Q PWM OFF ON ITRIP ON 0.6 × VCC Q (tOFF) PWM_ON S R ITRIP VBLANK BLANK RCx Winding Current PWM R 0.6 × VBLANK RCx VCC C VCC PWM_OFF 0.21 × VCC VDECAY Voltage 0.21 × VCC FAST BLANK (tFD) SLOW SLOW_DECAY DECAY DECAY To other PWM Figure 3. PWM Microstepping Indexer Built-in indexer logic in the DRV8811 allows a number of different stepping configurations. The USM1 and USM0 pins are used to configure the stepping format as shown in the table below: USM1 USM0 STEP MODE 0 0 Full step (2-phase excitation) 0 1 1/2 step (1-2 phase excitation) 1 0 1/4 step (W1-2 phase excitation) 1 1 Eight microsteps/steps The following table shows the relative current and step directions for different settings of USM1 and USM0. At each rising edge of the STEP input, the indexer travels to the next state in the table. The direction is shown with the DIR pin high; if the DIR pin is low the sequence is reversed. Positive current is defined as xOUT1 = positive with respect to xOUT2. Note that the home state is 45 degrees. This state is entered at power-up or device reset. The HOMEn output pin is driven low in this state. In all other states it is driven logic high. Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): DRV8811 11 DRV8811 SLVS865D – SEPTEMBER 2008 – REVISED JULY 2009 ................................................................................................................................................. www.ti.com FULL STEP USM = 00 1/4 STEP USM = 10 1/8 STEP USM = 11 1 1 1 100 0 0 2 98 20 11.325 3 92 38 22.5 4 83 56 33.75 5 71 71 45 (home state) 6 56 83 56.25 7 38 92 67.5 8 20 98 78.75 9 0 100 90 10 –20 98 101.25 11 –38 92 112.5 12 –56 83 123.75 13 –71 71 135 14 –83 56 146.25 15 –92 38 157.5 16 –98 20 168.75 17 –100 0 180 18 –98 –20 191.25 19 –92 –38 202.5 20 –83 –56 213.75 21 –71 –71 225 22 –56 –83 236.25 23 –38 –92 247.5 24 –20 –98 258.75 25 0 –100 270 26 20 –98 281.25 27 38 –92 292.5 28 56 –83 303.75 29 71 –71 315 30 83 –56 326.25 31 92 –38 337.5 32 98 –20 348.75 2 1 2 3 4 3 5 6 2 4 7 8 5 9 10 3 6 11 12 7 13 14 4 AOUTx BOUTx CURRENT CURRENT (% FULL-SCALE) (% FULL-SCALE) 1/2 STEP USM = 01 8 15 16 STEP ANGLE (DEGREES) RESETn, ENABLEn and SLEEPn Operation The RESETn pin, when driven active low, resets the step table to the home position. It also disables the H-bridge drivers. The STEP input is ignored while RESETn is active. The ENABLEn pin is used to control the output drivers. When ENABLEn is low, the output H-bridges are enabled. When ENABLEn is high, the H-bridges are disabled and the outputs are in a high-impedance state. Note that when ENABLEn is high, the input pins and control logic, including the indexer (STEP and DIR pins) are still functional. The SLEEPn pin is used to put the device into a low power state. If SLEEPn is low, the H-bridges are disabled, the gate drive charge pump is stopped, and all internal clocks are stopped. In this state all inputs are ignored until the SLEEPn pin returns high. 12 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): DRV8811 DRV8811 www.ti.com ................................................................................................................................................. SLVS865D – SEPTEMBER 2008 – REVISED JULY 2009 Protection Circuits Overcurrent Protection (OCP) If the current through any FET exceeds the preset overcurrent threshold, all FETs in the H-bridge will be disabled until the ENABLEn pin has been brought inactive high and then back low, or power is removed and re-applied. Overcurrent conditions are sensed in both directions; i.e., a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Note that overcurrent protection does not use the current sense circuitry used for PWM current control and is independent of the Isense resistor value or VREF voltage. Thermal Shutdown (TSD) If the die temperature exceeds safe limits, all drivers in the device are shut down and the indexer is reset to the home state. Once the die temperature has fallen to a safe level operation resumes. Undervoltage Lockout (UVLO) If at any time the voltage on the VM pins falls below the undervoltage lockout threshold voltage, all circuitry in the device is disabled and the indexer is reset to the home state. Operation resumes when VM rises above the UVLO threshold. Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): DRV8811 13 DRV8811 SLVS865D – SEPTEMBER 2008 – REVISED JULY 2009 ................................................................................................................................................. www.ti.com THERMAL INFORMATION Thermal Protection The DRV8811 has thermal shutdown (TSD) as described above. If the die temperature exceeds approximately 150°C, the device will be disabled until the temperature drops to a safe level. Any tendency of the device to enter thermal shutdown is an indication of either excessive power dissipation, insufficient heatsinking, or too high an ambient temperature. Power Dissipation Power dissipation in the DRV8811 is dominated by the power dissipated in the output FET resistance, or RDS(ON). Average power dissipation when running a stepper motor can be roughly estimated by: PTOT = 4 · RDS(ON) · (IOUT(RMS)) 2 (5) where PTOT is the total power dissipation, RDS(ON) is the resistance of each FET, and IOUT(RMS) is the RMS output current being applied to each winding. IOUT(RMS) is equal to the approximately 0.7x the full-scale output current setting. The factor of 4 comes from the fact that there are two motor windings, and at any instant two FETs are conducting winding current for each winding (one high-side and one low-side). The maximum amount of power that can be dissipated in the DRV8811 is dependent on ambient temperature and heatsinking. Figure 4 and Figure 5 show how the maximum allowable power dissipation varies according to temperature and PCB construction. Figure 4 shows data for a JEDEC low-K board, 2-layers with 2-oz. copper, 76 mm x 114 mm x 1.6 mm thick, with either no backside copper or a 24 cm2 copper area on the backside. Similarly, Figure 5 shows data for a JEDEC high-K board, 4 layers with 1-oz. copper, 76 mm x 114 mm x 1.6 mm thick, and a solid internal ground plane. In this case, the PowerPAD™ is tied to the ground plane using thermal vias, and no additional outer layer copper. Note that RDS(ON) increases with temperature, so as the device heats, the power dissipation increases. This must be taken into consideration when sizing the heatsink. Refer to Figure 6. Heatsinking The PowerPAD™ package uses an exposed pad to remove heat from the device. For proper operation, this pad must be thermally connected to copper on the PCB to dissipate heat. On a multi-layer PCB with a ground plane, this can be accomplished by adding a number of vias to connect the thermal pad to the ground plane. On PCBs without internal planes, copper area can be added on either side of the PCB to dissipate heat. If the copper area is on the opposite side of the PCB from the device, thermal vias are used to transfer the heat between top and bottom layers. For details about how to design the PCB, refer to TI Application Report SLMA002, "PowerPAD™ Thermally Enhanced Package" and TI Application Brief SLMA004, "PowerPAD™ Made Easy", available at www.ti.com. In general, the more copper area that can be provided, the more power can be dissipated. Figure 7 shows thermal resistance vs. copper plane area for a single-sided PCB with 2-oz. copper heatsink area. It can be seen that the heatsink effectiveness increases rapidly to about 20 cm2, then levels off somewhat for larger areas. 14 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): DRV8811 DRV8811 www.ti.com ................................................................................................................................................. SLVS865D – SEPTEMBER 2008 – REVISED JULY 2009 PD - Max Power Dissipation - Watts POWER DISSIPATION (2-LAYER) POWER DISSIPATION (4-LAYER) A A 2 TA - Ambien Temperature - °C Figure 4. Figure 5. TYPICAL RDS(ON) vs TEMPERATURE THERMAL RESISTANCE vs COPPER AREA RDS(ON) - mΩ θJA Temperature - °C Figure 6. Figure 7. Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): DRV8811 15 PACKAGE OPTION ADDENDUM www.ti.com 30-Jul-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty DRV8811PWP ACTIVE HTSSOP PWP 28 DRV8811PWPR ACTIVE HTSSOP PWP 28 50 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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