Features • • • • • • Industry Standard Architecture Low Cost Easy-to-Use Software Tools High Speed Electrically Erasable Programmable Logic Devices 5 ns Maximum Pin-to-Pin Delay CMOS and TTL Compatible Inputs and Outputs Latch Feature Holds Inputs to Previous Logic States Advanced Flash Technology Reprogrammable 100% Tested High Reliability CMOS Process 20 Year Data Retention 100 Erase/Write Cycles 2,000V ESD Protection 200 mA Latchup Immunity Dual-in-Line and Surface Mount Packages in Standard Pinouts High Performance E2 PLD ATF22V10C Logic Diagram Pin Configurations Pin Name Function CLK Clock IN Logic Inputs I/O Bidirectional Buffers * No Internal Connection VCC +5V Supply PD Power Down TSSOP Top View CLK/IN IN IN IN/PD IN IN IN IN IN IN IN GND 1 2 3 4 5 6 7 8 9 10 11 12 DIP/SOIC 24 23 22 21 20 19 18 17 16 15 14 13 VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IN ATF22V10C PLCC Top view Note: For PLCC, pins 1, 8, 15 and 22 can be left unconnected. For superior performance, connect VCC to pin 1 and ground to 8, 15, 22. Rev. 0735C/22V10C-D–04/98 Description The ATF22V10C is a high performance CMOS (Electrically Erasable) Programmable Logic Device (PLD) which utilizes Atmel’s proven electrically erasable Flash memory technology. Speeds down to 5 ns and power dissipation as low as 100 µA are offered. All speed ranges are specified over the full 5V ± 10% range for industrial temperature ranges, and 5V ± 5% for commercial temperature ranges. Several low power options allow selection of the best solution for various types of power-limited applications. Each of these options significantly reduces total system power and enhances system reliability. Absolute Maximum Ratings* Temperature Under Bias................... -40°C to +85°C Storage Temperature...................... -65°C to +150°C Voltage on Any Pin with Respect to Ground........................ -2.0V to +7.0V (1) *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage on Input Pins with Respect to Ground During Programming................... -2.0V to +14.0V (1) Programming Voltage with Respect to Ground...................... -2.0V to +14.0V (1) Note: 1. Minimum voltage is -0.6V dc, which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is VCC + 0.75V dc, which may overshoot to 7.0V for pulses of less than 20 ns. DC and AC Operating Conditions Operating Temperature (Case) VCC Power Supply 2 ATF22V10C Commercial Industrial 0°C - 70°C -40°C - 85°C 5V ± 5% 5V ± 10% ATF22V10C DC Characteristics Symbol Parameter Condition IIL Input or I/O Low Leakage Current 0 ≤ VIN ≤ VIL(MAX) IIH Input or I/O High Leakage Current 3.5 ≤ VIN ≤ VCC V = MAX, Power Supply Current, CC VIN = MAX, Standby Outputs Open C-5, 7, 10 Com. ICC C-10 ICC2 Clocked Power Supply VCC = MAX, Current Outputs Open ICC3 V = MAX, Clocked Power Supply CC Outputs Open, Current f = 15 MHz IPD IOS(1) Min Typ Max Units -35 -10 µA 10 µA 85 130 mA Ind. 90 140 mA C-5, 7, 10 Com. 1 mA/MHz(2) C-10 Ind. 1 mA/MHz(2) C-5, 7, 10 Com. 150 mA C-10 Ind. 160 mA Power Supply Current, VCC = MAX PD Mode VIN = 0, MAX Output Short Circuit VOUT = 0.5V Current Com. 10 100 µA Ind. 10 100 µA -130 mA VIL Input Low Voltage -0.5 0.8 V VIH Input High Voltage 2.0 VCC+0.75 V VOL Output Low Voltage VIN = VIH or VIL, IOL = 16 mA VCC = MIN IOL = 12 mA Com., Ind. 0.5 V Mil. 0.5 V VOH Output High Voltage VIN = VIH or VIL, IOH = -4.0 mA VCC = MIN 2.4 V Notes: 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec. 2. Low frequency only. See Supply Current versus Input Frequency curves. 3 AC Waveforms (1) Note: 1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified. AC Characteristics (1) -5 Symbol Parameter tPD Input or Feedback to Combinatorial Output -10 Min Max Min Max Min Max Units 1 5 3 7.5 3 10 ns 2 6.5 ns 4 ns (2) tCO Clock to Output tCF Clock to Feedback tS Input or Feedback Setup Time 3 3.5 4.5 ns tH Hold Time 0 0 0 ns FMAX 1 4 2 3 4.5 3.5 External Feedback 1/(tS + tCO) 142 125 (3) 90 MHz Internal Feedback 1/(tS + tCF) 166 142 117 MHz 125 MHz No Feedback 166 166 tP Clock Period 6 6 8 ns tW Clock Width 3 3 3 ns tEA Input or I/O to Output Enable 2 6 3 7.5 3 10 ns tER Input or I/O to Output Disable 2 5 3 7.5 3 9 ns tAP Input or I/O to Asynchronous Reset of Register 3 7 3 10 3 12 ns tAW Asynchronous Reset Width tAR 5.5 7 8 ns Asynchronous Reset Recovery Time 4 5 6 ns tSP Setup Time, Synchronous Preset 4 4.5 6 ns tSPR Synchronous Preset to Clock Recovery Time 4 5 8 ns Notes: 1. See ordering information for valid part numbers. 2. 5.5 ns for DIP package devices. 3. 111 MHz for DIP package devices. 4 -7 ATF22V10C ATF22V10C Power Down AC Characteristics (1, 2, 3) -5 Symbol Parameter Min Max Min -10 Max Min Max Units 5 7.5 10 ns tGVDH Valid OE Before PD High 0 0 0 ns tCVDH Valid Clock Before PD High 0 0 0 ns tIVDH tDHIX Valid Input Before PD High -7 Input Don’t Care After PD High 5 7 10 ns tDHGX OE Don’t Care After PD High 5 7 10 ns tDHCX Clock Don’t Care After PD High 5 7 10 ns tDLIV PD Low to Valid Input 5 7.5 10 ns tDLGV PD Low to Valid OE 15 20 25 ns tDLCV PD Low to Valid Clock 15 20 25 ns tDLOV PD Low to Valid Output 20 25 30 ns 3. Clock and input transitions are ignored. Notes: 1. Output data is latched and held. 2. HI-Z outputs remain HI-Z. Output Test Loads: Input Test Waveforms and Measurement Levels Commercial tR, tF < 3 ns Pin Capacitance (f = 1 MHz, T = 25°C) (1) Typ Max Units CIN 5 8 pF VIN = 0V COUT 6 8 pF VOUT = 0V Note: Conditions 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. Power Up Reset The registers in the ATF22V10Cs are designed to reset during power up. At a point delayed slightly from VCC crossing VRST, all registers will be reset to the low state. The output state will depend on the polarity of the output buffer. 1. The VCC rise must be monotonic, and starts below 0.7V, 2. After reset occurs, all input and feedback setup times must be met before driving the clock pin high, and 3. The clock must remain stable during tPR. This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the uncertainty of how VCC actually rises in the system, the following conditions are required: 5 V R ST Parameter Description Typ Max Units POWER t PR REGISTERED OUTPUTS tS tW tPR Power-Up Reset Time 600 1,000 ns VRST Power-Up Reset Voltage 3.8 4.5 V CLOCK Preload of Registered Outputs Security Fuse Usage The ATF22V10C’s registers are provided with circuitry to allow loading of each register with either a high or a low. This feature will simplify testing since any state can be forced into the registers to control test sequencing. A JEDEC file with preload is generated when a source file with vectors is compiled. Once downloaded, the JEDEC file preload sequence will be done automatically by most of the approved programmers after the programming. A single fuse is provided to prevent unauthorized copying of the ATF22V10C fuse patterns. Once programmed, fuse verify and preload are inhibited. However, the 64-bit User Signature remains accessible. Electronic Signature Word Programming/Erasing There are 64 bits of programmable memory that are always available to the user, even if the device is secured. These bits can be used for user-specific data. Programming/erasing is performed using standard PLD programmers. See CMOS PLD Programming Hardware & Software Support for information on software/programming. The security fuse should be programmed last, as its effect is immediate. Input and I/O Pin Keeper Circuits The ATF16V8C contains internal input and I/O pin keeper circuits. These circuits allow each ATF16V8C pin to hold its previous value even when it is not being driven by an external source or by the device’s output buffer. This helps insure that all logic array inputs are at known, valid logic levels. This reduces system power by preventing pins from floating to indeterminate levels. By using pin keeper Input Diagram 6 ATF22V10C circuits rather than pull-up resistors, there is no DC current required to hold the pins in either logic state (high or low). These pin keeper circuits are implemented as weak feedback inverters, as shown in the Input Diagram below. These keeper circuits can easily be overdriven by standard TTL- or CMOS-compatible drivers. The typical overdrive current required is 40 µA. I/O Diagram ATF22V10C Functional Logic Diagram ATF22V10C 7 Ordering Information tPD (ns) tS (ns) tCO (ns) 5 3 7.5 10 Ordering Code Package 4 ATF22V10C-5JC 28J Commercial (0°C to 70°C) 3.5 4.5 ATF22V10C-7JC ATF22V10C-7PC ATF22V10C-7SC ATF22V10C-7XC 28J 24P3 24S 24X Commercial (0°C to 70°C) 4.5 6.5 ATF22V10C-10JC ATF22V10C-10PC ATF22V10C-10SC ATF22V10C-10XC 28J 24P3 24S 24X Commercial (0°C to 70°C) ATF22V10C-10JI ATF22V10C-10PI ATF22V10C-10SI ATF22V10C-10XI 28J 24P3 24S 24X Industrial (-40°C to 85°C) Package Type 8 28J 28-Lead, Plastic J-Leaded Chip Carrier (PLCC) 24P3 24-Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 24S 24-Lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC) 24X 24-Lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline (TSSOP) ATF22V10C Operation Range