CY7C1365CV33
9-Mbit (256K × 32) Flow-Through
Sync SRAM
9-Mbit (256K × 32) Flow-Through Sync SRAM
Features
Functional Description
■
256K × 32 common I/O
■
3.3 V core power supply (VDD)
■
2.5 V/3.3 V I/O power supply (VDDQ)
■
Fast clock-to-output times
❐ 6.5 ns (133-MHz version)
■
Provide high-performance 2-1-1-1 access rate
■
User-selectable burst counter supporting Intel Pentium
interleaved or linear burst sequences
■
Separate processor and controller address strobes
■
Synchronous self-timed write
■
Asynchronous output enable
■
Supports 3.3 V I/O level
■
Available in JEDEC-standard lead-free 100-pin TQFP package
■
TQFP Available with 3-Chip Enable
■
“ZZ” Sleep Mode option
The CY7C1365CV33 is a 256K × 32 synchronous cache RAM
designed to interface with high-speed microprocessors with
minimum glue logic. Maximum access delay from clock rise is
6.5 ns (133-MHz version). A 2-bit on-chip counter captures the
first address in a burst and increments the address automatically
for the rest of the burst access. All synchronous inputs are gated
by registers controlled by a positive-edge-triggered Clock Input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining Chip Enable (CE1), depth-expansion
Chip Enables (CE2 and CE3), Burst Control inputs (ADSC,
ADSP, and ADV), Write Enables (BW[A:D], and BWE), and
Global Write (GW). Asynchronous inputs include the Output
Enable (OE) and the ZZ pin.
The CY7C1365CV33 allows either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects an
interleaved burst sequence, while a LOW selects a linear burst
sequence. Burst accesses can be initiated with the Processor
Address Strobe (ADSP) or the cache Controller Address Strobe
(ADSC) inputs. Address advancement is controlled by the
Address Advancement (ADV) input.
Addresses and Chip Enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or Address
Strobe Controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
Advance pin (ADV).
The CY7C1365CV33 operates from a +3.3 V core power supply
while all outputs may operate with either a +2.5 or +3.3 V supply.
All
inputs
and
outputs
are
JEDEC-standard
JESD8-5-compatible.
For a complete list of related documentation, click here.
Selection Guide
133 MHz
Unit
Maximum Access Time
Description
6.5
ns
Maximum Operating Current
250
mA
Maximum Standby Current
40
mA
Cypress Semiconductor Corporation
Document Number: 001-74473 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 15, 2016
CY7C1365CV33
Logic Block Diagram – CY7C1365CV33
ADDRESS
REGISTER
A0, A1, A
A[1:0]
MODE
BURST Q1
COUNTER
AND LOGIC
Q0
CLR
ADV
CLK
ADSC
ADSP
DQD
BWD
BYTE
WRITE REGISTER
DQC
BWC
BYTE
WRITE REGISTER
DQD
BYTE
WRITE REGISTER
DQC
BYTE
WRITE REGISTER
DQB
BWB
DQB
BYTE
BYTE
WRITE REGISTER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
BUFFERS
DQs
WRITE REGISTER
DQA
BWA
BWE
DQA
BYTE
BYTE
WRITE REGISTER
WRITE REGISTER
GW
ENABLE
REGISTER
CE1
CE2
INPUT
REGISTERS
CE3
OE
ZZ
SLEEP
CONTROL
Document Number: 001-74473 Rev. *E
Page 2 of 21
CY7C1365CV33
Contents
Pin Configurations ........................................................... 4
Pin Descriptions ............................................................... 5
Functional Overview ........................................................ 6
Single Read Accesses ................................................ 6
Single Write Accesses Initiated by ADSP ................... 6
Single Write Accesses Initiated by ADSC ................... 6
Burst Sequences ......................................................... 7
Sleep Mode ................................................................. 7
Interleaved Burst Address Table ................................. 7
Linear Burst Address Table ......................................... 7
ZZ Mode Electrical Characteristics .............................. 7
Truth Table ........................................................................ 8
Truth Table for Read/Write .............................................. 9
Maximum Ratings ........................................................... 10
Operating Range ............................................................. 10
Electrical Characteristics ............................................... 10
Capacitance .................................................................... 11
Thermal Resistance ........................................................ 11
Document Number: 001-74473 Rev. *E
AC Test Loads and Waveforms ..................................... 11
Switching Characteristics .............................................. 12
Timing Diagrams ............................................................ 13
Ordering Information ...................................................... 17
Ordering Code Definitions ......................................... 17
Package Diagram ............................................................ 18
Acronyms ........................................................................ 19
Document Conventions ................................................. 19
Units of Measure ....................................................... 19
Document History Page ................................................. 20
Sales, Solutions, and Legal Information ...................... 21
Worldwide Sales and Design Support ....................... 21
Products .................................................................... 21
PSoC®Solutions ....................................................... 21
Cypress Developer Community ................................. 21
Technical Support ..................................................... 21
Page 3 of 21
CY7C1365CV33
Pin Configurations
A
A
35
36
37
38
39
40
41
42
45
46
47
48
49
50
A
A1
A0
NC
NC
VSS
VDD
NC
A
A
A
A
A
A
A
A
44
34
Document Number: 001-74473 Rev. *E
43
81
82
83
84
BWE
OE
ADSC
ADSP
ADV
85
86
GW
89
87
CLK
91
88
VDD
VSS
93
90
BWSA
CE3
94
92
BWSC
BWSB
95
CE2
BWSD
CE1
98
96
A
99
97
A
31
VSSQ
VDDQ
DQD
DQD
NC
33
VSS
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
CY7C1365CV33
A
BYTE D
DQC
DQC
VSSQ
VDDQ
DQC
DQC
NC
VDD
NC
A
BYTE C
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
32
VDDQ
VSSQ
DQC
DQC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
NC
DQC
DQC
100
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout (3 Chip Enable) (A version)
NC
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
NC
BYTE B
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
BYTE A
VSSQ
VDDQ
DQA
DQA
NC
Page 4 of 21
CY7C1365CV33
Pin Descriptions
Name
A0, A1, A
BWA, BWB,
BWC, BWD
100-pin TQFP
I/O
Description
InputAddress Inputs used to select one of the 256K address locations. Sampled at the
37, 36, 32, 33,
34, 35, 44, 45, Synchronous rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are
sampled active. A[1:0] feed the 2-bit counter.
46, 47, 48, 49,
50, 81, 82, 99,
100, 92 (for 2
Chip Enable
Version), 43 (for
3 Chip Enable
Version)
93, 94, 95, 96
InputByte Write Select Inputs, active LOW. Qualified with BWE to conduct Byte Writes to
Synchronous the SRAM. Sampled on the rising edge of CLK.
GW
88
InputGlobal Write Enable Input, active LOW. When asserted LOW on the rising edge of
Synchronous CLK, a global write is conducted (ALL bytes are written, regardless of the values on
BW[A:D] and BWE).
BWE
87
InputByte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal
Synchronous must be asserted LOW to conduct a Byte Write.
CLK
89
Input-Clock Clock Input. Used to capture all synchronous inputs to the device. Also used to
increment the burst counter when ADV is asserted LOW, during a burst operation.
CE1
98
InputChip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
Synchronous conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is
HIGH. CE1 is sampled only when a new external address is loaded.
CE2
97
InputChip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
Synchronous conjunction with CE1 and CE3 to select/deselect the device. CE2 is sampled only when
a new external address is loaded.
CE3
92 (for 3 Chip
InputChip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
Enable Version) Synchronous conjunction with CE1 and CE2 to select/deselect the device. CE3 is sampled only when
a new external address is loaded.
OE
86
InputOutput Enable, asynchronous input, active LOW. Controls the direction of the I/O
Asynchronous pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are
tri-stated, and act as input data pins. OE is masked during the first clock of a Read cycle
when emerging from a deselected state.
ADV
83
InputAdvance Input signal, sampled on the rising edge of CLK. When asserted, it
Synchronous automatically increments the address in a burst cycle.
ADSP
84
InputAddress Strobe from Processor, sampled on the rising edge of CLK, active LOW.
Synchronous When asserted LOW, addresses presented to the device are captured in the address
registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both
asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH.
ADSC
85
InputAddress Strobe from Controller, sampled on the rising edge of CLK, active LOW.
Synchronous When asserted LOW, addresses presented to the device are captured in the address
registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both
asserted, only ADSP is recognized.
ZZ
64
InputZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a
Asynchronous non-time-critical “sleep” condition with data integrity preserved. For normal operation,
this pin has to be LOW or left floating. ZZ pin has an internal pull-down.
Document Number: 001-74473 Rev. *E
Page 5 of 21
CY7C1365CV33
Pin Descriptions (continued)
Name
100-pin TQFP
I/O
Description
DQs
I/OBidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is
52, 53, 56, 57,
58, 59, 62, 63, Synchronous triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by the addresses presented during the previous clock rise of
68, 69, 72, 73,
the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW,
74, 75, 78, 79,
2, 3, 6, 7, 8, 9,
the pins behave as outputs. When HIGH, DQs are placed in a tri-state condition.
12, 13, 18, 19,
22, 23, 24, 25,
28, 29
VDD
15, 41, 65, 91 Power Supply Power supply inputs to the core of the device.
VSS
17, 40, 67, 90
Ground
Ground for the core of the device.
VDDQ
4, 11, 20, 27,
54, 61, 70, 77
I/O Power
Supply
Power supply for the I/O circuitry.
VSSQ
5, 10, 21, 26,
55, 60, 71, 76
I/O Ground Ground for the I/O circuitry.
MODE
NC
31
InputStatic
1, 30, 51, 80,
14, 16, 38, 39,
42, 66, 43 (for
2 Chip Enable
Version)
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to
VDD or left floating selects interleaved burst sequence. This is a strap pin and should
remain static during device operation. Mode Pin has an internal pull-up.
No Connects. Not Internally connected to the die.
Functional Overview
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. Maximum access delay from the
clock rise (t CDV) is 6.5 ns (133-MHz device).
The CY7C1365CV33 supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486 processors.
The linear burst sequence is suited for processors that utilize a
linear burst sequence. The burst order is user-selectable, and is
determined by sampling the MODE input. Accesses can be
initiated with either the Processor Address Strobe (ADSP) or the
Controller Address Strobe (ADSC). Address advancement
through the burst sequence is controlled by the ADV input. A
two-bit on-chip wraparound burst counter captures the first
address in a burst sequence and automatically increments the
address for the rest of the burst access.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW[A:D]) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to all
four bytes. All writes are simplified with on-chip synchronous
self-timed write circuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. ADSP is ignored if CE1 is
HIGH.
Single Read Accesses
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted
active, and (2) ADSP or ADSC is asserted LOW (if the access is
Document Number: 001-74473 Rev. *E
initiated by ADSC, the write inputs must be deasserted during
this first cycle). The address presented to the address inputs is
latched into the address register and the burst counter/control
logic and presented to the memory core. If the OE input is
asserted LOW, the requested data will be available at the data
outputs a maximum to tCDV after clock rise. ADSP is ignored if
CE1 is HIGH.
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, CE3 are all asserted active,
and (2) ADSP is asserted LOW. The addresses presented are
loaded into the address register and the burst inputs (GW, BWE,
and BW[A:D]) are ignored during this first clock cycle. If the write
inputs are asserted active (see Write Cycle Descriptions table for
appropriate states that indicate a write) on the next clock rise, the
appropriate data will be latched and written into the device.Byte
writes are allowed. During byte writes, BWA controls DQA and
BWB controls DQB, BWC controls DQC, and BWD controls
DQD. All I/Os are tri-stated during a byte write.Since this is a
common I/O device, the asynchronous OE input signal must be
deasserted and the I/Os must be tri-stated prior to the
presentation of data to DQs. As a safety precaution, the data
lines are tri-stated once a write cycle is detected, regardless of
the state of OE.
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the write input signals (GW, BWE, and BW[A:D])
indicate a write access. ADSC is ignored if ADSP is active LOW.
Page 6 of 21
CY7C1365CV33
The addresses presented are loaded into the address register
and the burst counter/control logic and delivered to the memory
core. The information presented to DQ[D:A] will be written into
the specified address location. Byte writes are allowed. During
byte writes, BWA controls DQA, BWB controls DQB, BWC
controls DQC, and BWD controls DQD. All I/Os are tri-stated
when a write is detected, even a byte write. Since this is a
common I/O device, the asynchronous OE input signal must be
deasserted and the I/Os must be tri-stated prior to the
presentation of data to DQs. As a safety precaution, the data
lines are tri-stated once a write cycle is detected, regardless of
the state of OE.
Interleaved Burst Address Table
(MODE = Floating or VDD)
Burst Sequences
The CY7C1365CV33 provides an on-chip two-bit wraparound
burst counter inside the SRAM. The burst counter is fed by
A[1:0], and can follow either a linear or interleaved burst order.
The burst order is determined by the state of the MODE input. A
LOW on MODE will select a linear burst sequence. A HIGH on
MODE will select an interleaved burst order. Leaving MODE
unconnected will cause the device to default to a interleaved
burst sequence.
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Fourth
Address
A1:A0
Linear Burst Address Table
(MODE = GND)
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CEs,
ADSP, and ADSC must remain inactive for the duration of tZZREC
after the ZZ input returns LOW.
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min
Max
Unit
IDDZZ
Sleep mode standby current
ZZ > VDD– 0.2 V
–
50
mA
tZZS
Device operation to ZZ
ZZ > VDD – 0.2 V
–
2tCYC
ns
tZZREC
ZZ recovery time
ZZ < 0.2 V
2tCYC
–
ns
tZZI
ZZ Active to Sleep current
This parameter is sampled
–
2tCYC
ns
tRZZI
ZZ Inactive to exit Sleep current This parameter is sampled
0
–
ns
Document Number: 001-74473 Rev. *E
Page 7 of 21
CY7C1365CV33
Truth Table
The truth table for CY7C1365CV33 follows. [1, 2, 3, 4, 5]
Cycle Description
Address Used CE1 CE3 CE2 ZZ ADSP ADSC ADV WRITE OE CLK
DQ
Deselected Cycle, Power-down
None
H
X
X
L
X
L
X
X
X
L–H Tri-State
Deselected Cycle, Power-down
None
L
X
L
L
L
X
X
X
X
L–H Tri-State
Deselected Cycle, Power-down
None
L
H
X
L
L
X
X
X
X
L–H Tri-State
Deselected Cycle, Power-down
None
L
X
L
L
H
L
X
X
X
L–H Tri-State
Deselected Cycle, Power-down
None
X
X
H
L
H
L
X
X
X
L–H Tri-State
Sleep Mode, Power-down
None
X
X
X
H
X
X
X
X
X
X
Tri-State
Read Cycle, Begin Burst
External
L
L
H
L
L
X
X
X
L
L–H
Q
Read Cycle, Begin Burst
External
L
L
H
L
L
X
X
X
H
L–H Tri-State
Write Cycle, Begin Burst
External
L
L
H
L
H
L
X
L
X
L–H
D
Read Cycle, Begin Burst
External
L
L
H
L
H
L
X
H
L
L–H
Q
Read Cycle, Begin Burst
External
L
L
H
L
H
L
X
H
H
L–H Tri-State
Read Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
L
L–H
Read Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
H
L–H Tri-State
Read Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
L
L–H
Read Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
H
L–H Tri-State
Write Cycle, Continue Burst
Next
X
X
X
L
H
H
L
L
X
L–H
D
Write Cycle, Continue Burst
Next
H
X
X
L
X
H
L
L
X
L–H
D
Read Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
L
L–H
Q
Read Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
H
L–H Tri-State
Read Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
L
L–H
Read Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
H
L–H Tri-State
Write Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
L
X
L–H
D
Write Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
L
X
L–H
D
Q
Q
Q
Notes
1. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
2. WRITE = L when any one or more Byte Write Enable signals (BWA, BWB, BWC, BWD) and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals (BWA,
BWB, BWC, BWD), BWE, GW = H.
3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
4. The SRAM always initiates a Read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A: D]. Writes may occur only on subsequent clocks after
the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't care
for the remainder of the Write cycle.
5. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a read cycle all data bits are Tri-State when OE is inactive
or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document Number: 001-74473 Rev. *E
Page 8 of 21
CY7C1365CV33
Truth Table for Read/Write
The Truth Table for Read/Write for CY7C1365CV33 follows. [6, 7]
Function
GW
BWE
BWD
BWC
BWB
BWA
Read
H
H
X
X
X
X
Read
H
L
H
H
H
H
Write Byte (A, DQPA)
H
L
H
H
H
L
Write Byte (B, DQPB)
H
L
H
H
L
H
Write Bytes (B, A, DQPA, DQPB)
H
L
H
H
L
L
Write Byte (C, DQPC)
H
L
H
L
H
H
Write Bytes (C, A, DQPC, DQPA)
H
L
H
L
H
L
Write Bytes (C, B, DQPC, DQPB)
H
L
H
L
L
H
Write Bytes (C, B, A, DQPC, DQPB, DQPA)
H
L
H
L
L
L
Write Byte (D, DQPD)
H
L
L
H
H
H
Write Bytes (D, A, DQPD, DQPA)
H
L
L
H
H
L
Write Bytes (D, B, DQPD, DQPA)
H
L
L
H
L
H
Write Bytes (D, B, A, DQPD, DQPB, DQPA)
H
L
L
H
L
L
Write Bytes (D, B, DQPD, DQPB)
H
L
L
L
H
H
Write Bytes (D, B, A, DQPD, DQPC, DQPA)
H
L
L
L
H
L
Write Bytes (D, C, A, DQPD, DQPB, DQPA)
H
L
L
L
L
H
Write All Bytes
H
L
L
L
L
L
Write All Bytes
L
X
X
X
X
X
Notes
6. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
7. WRITE = L when any one or more Byte Write Enable signals (BWA, BWB, BWC, BWD) and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals (BWA,
BWB, BWC, BWD), BWE, GW = H.
Document Number: 001-74473 Rev. *E
Page 9 of 21
CY7C1365CV33
Maximum Ratings
DC Input Voltage ................................ –0.5 V to VDD + 0.5 V
Exceeding maximum ratings may impair the useful life of the
device. User guidelines are not tested.
Storage Temperature ............................... –65 C to +150 C
Ambient Temperature with
Power Applied ......................................... –55 C to +125 C
Supply Voltage on VDD Relative to GND .....–0.5 V to +4.6 V
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ........................... >2001 V
Latch-up Current ..................................................... >200 mA
Operating Range
Supply Voltage on VDDQ Relative to GND .... –0.5 V to +VDD
Range
DC Voltage Applied to Outputs
in Tri-State ........................................–0.5 V to VDDQ + 0.5 V
Ambient
Temperature
Commercial
0 °C to +70 °C
VDD
VDDQ
3.3 V– 5% / + 2.5 V – 5% to
10%
VDD
Electrical Characteristics
Over the Operating Range
Parameter [8, 9]
Description
VDD
Power Supply Voltage
VDDQ
I/O Supply Voltage
VOH
Output HIGH Voltage
CY7C1365CV33
Test Conditions
Unit
Min
Max
3.135
3.6
V
for 3.3 V I/O
3.135
3.6
V
for 2.5 V I/O
2.375
2.625
V
for 3.3 V I/O, IOH = –4.0 mA
2.4
–
V
for 2.5 V I/O, IOH = –1.0 mA
2.0
–
V
–
0.4
V
VOL
Output LOW Voltage
for 3.3 V I/O, IOL = 8.0 mA
–
0.4
V
VIH
Input HIGH Voltage
for 3.3 V I/O
2.0
VDD + 0.3
V
for 2.5 V I/O
1.7
VDD + 0.3
V
for 3.3 V I/O
–0.3
0.8
V
for 2.5 V I/O
for 2.5 V I/O, IOL = 1.0 mA
[8]
VIL
Input LOW Voltage
–0.3
0.7
V
IX
Input Leakage Current except ZZ GND VI VDDQ
and MODE
5
5
A
Input Current of MODE
Input = VSS
–30
–
A
Input = VDD
–
5
A
Input = VSS
–5
–
A
Input = VDD
–
30
A
Input Current of ZZ
IOZ
Output Leakage Current
GND VI VDDQ, Output Disabled
–5
5
A
IDD
VDD Operating Supply Current
VDD = Max, IOUT = 0 mA,
f = fMAX= 1/tCYC
–
250
mA
ISB1
Automatic CE Power-Down
Current – TTL Inputs
Max. VDD, Device Deselected, 7.5-ns cycle,
VIN VIH or VIN VIL, f = fMAX, 133 MHz
inputs switching
100
110
mA
ISB2
Automatic CE Power-Down
Current – CMOS Inputs
7.5-ns cycle,
Max. VDD, Device Deselected,
VIN VDD – 0.3 V or VIN 0.3 V, 133 MHz
f = 0, inputs static
–
40
mA
7.5-ns cycle,
133 MHz
Notes
8. Overshoot: VIH(AC) < VDD + 1.5 V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (Pulse width less than tCYC/2).
9. TPower-up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document Number: 001-74473 Rev. *E
Page 10 of 21
CY7C1365CV33
Electrical Characteristics (continued)
Over the Operating Range
Parameter [8, 9]
Description
CY7C1365CV33
Test Conditions
Min
Max
Unit
ISB3
Automatic CE Power-Down
Current – CMOS Inputs
Max. VDD, Device Deselected,
7.5-ns cycle,
VIN VDDQ – 0.3 V or VIN 0.3 V, 133 MHz
f = fMAX, inputs switching
–
100
mA
ISB4
Automatic CE Power-Down
Current – TTL Inputs
Max. VDD, Device Deselected,
VIN VIH or VIN VIL, f = 0,
inputs static.
–
40
mA
7.5-ns cycle,
133 MHz
Capacitance
Parameter [10]
Description
CIN
Input capacitance
CCLK
CI/O
100-pin TQFP Unit
Max
Test Conditions
TA = 25 °C, f = 1 MHz, VDD = 3.3 V, VDDQ = 2.5 V
5
pF
Clock input capacitance
5
pF
Input/Output capacitance
5
pF
Test Conditions
100-pin TQFP
Package
Unit
Test conditions follow standard test methods and
procedures for measuring thermal impedance, per
EIA/JESD51
29.41
C/W
6.13
C/W
Thermal Resistance
Parameter [10]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
3.3 V I/O Test Load
R = 317
3.3V
OUTPUT
OUTPUT
RL = 50
Z0 = 50
VT = 1.5V
(a)
INCLUDING
JIG AND
SCOPE
Z0 = 50
VT = 1.25V
(a)
R = 351
10%
(c)
ALL INPUT PULSES
VDDQ
INCLUDING
JIG AND
SCOPE
1 ns
(b)
GND
5 pF
90%
10%
90%
1 ns
R = 1667
2.5V
OUTPUT
RL = 50
GND
5 pF
2.5 V I/O Test Load
OUTPUT
ALL INPUT PULSES
VDDQ
R =1538
(b)
10%
90%
10%
90%
1 ns
1 ns
(c)
Note
10. Tested initially and after any design or process change that may affect these parameters.
Document Number: 001-74473 Rev. *E
Page 11 of 21
CY7C1365CV33
Switching Characteristics
Over the Operating Range
Parameter [11, 12]
tPOWER
Description
VDD(typical) to the first access [13]
-133
Unit
Min
Max
1
–
ms
Clock
tCYC
Clock cycle time
7.5
–
ns
tCH
Clock HIGH
3.0
–
ns
tCL
Clock LOW
3.0
–
ns
Output Times
tCDV
Data output valid after CLK rise
–
6.5
ns
tDOH
Data output hold after CLK rise
2.0
–
ns
0
–
ns
–
3.5
ns
–
3.5
ns
0
–
ns
–
3.5
ns
[14, 15, 16]
tCLZ
Clock to low Z
tCHZ
Clock to high Z [14, 15, 16]
tOEV
OE LOW to output valid
tOELZ
tOEHZ
OE LOW to output low Z
[14, 15, 16]
OE HIGH to output high Z
[14, 15, 16]
Set-up Times
tAS
Address set-up before CLK rise
1.5
–
ns
tADS
ADSP, ADSC set-up before CLK rise
1.5
–
ns
tADVS
ADV set-up before CLK rise
1.5
–
ns
tWES
GW, BWE, BW[A:D] set-up before CLK rise
1.5
–
ns
tDS
Data input set-up before CLK rise
1.5
–
ns
tCES
Chip enable set-up
1.5
–
ns
tAH
Address hold after CLK rise
0.5
–
ns
tADH
ADSP, ADSC hold after CLK rise
0.5
–
ns
tWEH
GW, BWE, BW[A:D] hold after CLK rise
0.5
–
ns
tADVH
ADV hold after CLK rise
0.5
–
ns
tDH
Data input hold after CLK rise
0.5
–
ns
tCEH
Chip enable hold after CLK rise
0.5
–
ns
Hold Times
Notes
11. Timing reference level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V.
12. Test conditions shown in (a) of Figure 2 on page 11 unless otherwise noted.
13. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a Read or Write operation can
be initiated.
14. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 2 on page 11. Transition is measured ±200 mV from steady-state voltage.
15. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
High Z prior to Low Z under the same system conditions.
16. This parameter is sampled and not 100% tested.
Document Number: 001-74473 Rev. *E
Page 12 of 21
CY7C1365CV33
Timing Diagrams
Figure 3. Read Cycle Timing [17]
tCYC
CLK
t
tADS
CH
t CL
tADH
ADSP
tADS
tADH
ADSC
tAS
tAH
A1
ADDRESS
A2
t
WES
t
WEH
GW, BWE,BW
[A:D]
tCES
Deselect Cycle
t CEH
CE
t
ADVS
t
ADVH
ADV
ADV suspends burst.
OE
t OEV
t OEHZ
t CLZ
Data Out (Q)
High-Z
Q(A1)
t OELZ
tCDV
t CHZ
tDOH
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
t CDV
Single READ
BURST
READ
DON’T CARE
Burst wraps around
to its initial state
UNDEFINED
Note
17. On this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
Document Number: 001-74473 Rev. *E
Page 13 of 21
CY7C1365CV33
Timing Diagrams (continued)
Figure 4. Write Cycle Timing [18, 19]
t CYC
CLK
t
tADS
t
CH
CL
tADH
ADSP
tADS
ADSC extends burst.
tADH
tADS
tADH
ADSC
tAS
tAH
A1
ADDRESS
A2
A3
Byte write signals are ignored for first cycle when
ADSP initiates burst.
tWES tWEH
BWE,
BW[A:D]
t
t
WES WEH
GW
tCES
tCEH
CE
tADVS tADVH
ADV
ADV suspends burst.
OE
t
Data in (D)
High-Z
t
OEHZ
DS
t
DH
D(A1)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
DON’T CARE
Extended BURST WRITE
UNDEFINED
Notes
18. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A:D] LOW.
19. The data bus (Q) remains in High Z following a Write cycle unless an ADSP, ADSC, or ADV cycle is performed.
Document Number: 001-74473 Rev. *E
Page 14 of 21
CY7C1365CV33
Timing Diagrams (continued)
Figure 5. Read/Write Timing [20, 21, 22]
tCYC
CLK
t
CH
tADS
tADH
tAS
tAH
t
CL
ADSP
ADSC
ADDRESS
A1
A2
A3
A4
A5
A6
D(A5)
D(A6)
t
t
WES WEH
BWE, BW[A:D]
tCES
tCEH
CE
ADV
OE
tDS
Data In (D)
Data Out (Q)
High-Z
t
OEHZ
Q(A1)
tDH
tOELZ
D(A3)
tCDV
Q(A2)
Back-to-Back READs
Q(A4)
Single WRITE
Q(A4+1)
Q(A4+2)
BURST READ
DON’T CARE
Q(A4+3)
Back-to-Back
WRITEs
UNDEFINED
Notes
20. On this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
21. The data bus (Q) remains in High Z following a Write cycle unless an ADSP, ADSC, or ADV cycle is performed.
22. GW is HIGH.
Document Number: 001-74473 Rev. *E
Page 15 of 21
CY7C1365CV33
Timing Diagrams (continued)
Figure 6. ZZ Mode Timing [23, 24]
CLK
t ZZ
ZZ
I
t ZZREC
t ZZI
SUPPLY
I DDZZ
t RZZI
ALL INPUTS
(except ZZ)
Outputs (Q)
DESELECT or READ Only
High-Z
DON’T CARE
Notes
23. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
24. DQs are in High Z when exiting ZZ sleep mode.
Document Number: 001-74473 Rev. *E
Page 16 of 21
CY7C1365CV33
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit
www.cypress.com for actual products offered.
Speed
(MHz)
133
Package
Diagram
Ordering Code
Package Type
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free (3 Chip Enable)
CY7C1365CV33-133AXC
Operating
Range
Commercial
Ordering Code Definitions
CY 7
C
1365 C V33 - 133
A
X C
Temperature range:
C = Commercial = 0 °C to +70 °C
X = Pb-free
Package Type:
A = 100-pin TQFP
Speed Grade: 133 MHz
V33 = 3.3 V VDD
Process Technology: C 90 nm
Part Identifier: 1365 = DCD, 256K × 32 (9 Mb)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 001-74473 Rev. *E
Page 17 of 21
CY7C1365CV33
Package Diagram
Figure 7. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050
51-85050 *E
Document Number: 001-74473 Rev. *E
Page 18 of 21
CY7C1365CV33
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CE
Chip Enable
CMOS
Complementary Metal Oxide Semiconductor
°C
degree Celsius
EIA
Electronic Industries Alliance
MHz
megahertz
I/O
Input/Output
µA
microampere
JEDEC
Joint Electron Devices Engineering Council
mA
milliampere
OE
Output Enable
mm
millimeter
SRAM
Static Random Access Memory
ms
millisecond
TQFP
Thin Quad Flat Pack
mV
millivolt
TTL
Transistor-Transistor Logic
ns
nanosecond
Document Number: 001-74473 Rev. *E
Symbol
Unit of Measure
ohm
%
percent
pF
picofarad
V
volt
W
watt
Page 19 of 21
CY7C1365CV33
Document History Page
Document Title: CY7C1365CV33, 9-Mbit (256K × 32) Flow-Through Sync SRAM
Document Number: 001-74473
Rev.
ECN No.
Issue Date
Orig. of
Change
**
3459992
01/09/2012
PRIT
New data sheet.
*A
3608159
05/04/2012
PRIT
Changed status from Preliminary to Final.
Updated Operating Range (Removed Industrial Temperature Range).
*B
3794817
10/26/2012
PRIT
No technical updates.
Completing Sunset Review.
*C
4573182
11/18/2014
PRIT
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Updated Package Diagram:
spec 51-85050 – Changed revision from *D to *E.
*D
5069042
12/31/2015
PRIT
Updated to new template.
Completing Sunset Review.
*E
5309766
06/15/2016
PRIT
Updated Truth Table.
Updated to new template.
Document Number: 001-74473 Rev. *E
Description of Change
Page 20 of 21
CY7C1365CV33
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC®Solutions
Products
ARM® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
Interface
Lighting & Power Control
Memory
cypress.com/clocks
cypress.com/interface
cypress.com/powerpsoc
cypress.com/memory
PSoC
Cypress Developer Community
Forums | Projects | Video | Blogs | Training | Components
Technical Support
cypress.com/support
cypress.com/psoc
Touch Sensing
cypress.com/touch
USB Controllers
Wireless/RF
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2012-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
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permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United
States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-74473 Rev. *E
Intel and Pentium are registered trademarks and i486 is a trademark of Intel Corporation.
Revised June 15, 2016
Page 21 of 21