CY7C1385D 18-Mbit (512 K × 32) Flow-Through SRAM 18-Mbit (512 K × 32) Flow-Through SRAM Features Functional Description ■ Supports 133 MHz bus operations ■ 512 K × 32 common I/O ■ 3.3 V core power supply (VDD) ■ 2.5 V or 3.3 V I/O supply (VDDQ) ■ Fast clock-to-output time ❐ 6.5 ns (133 MHz version) ■ Provides high performance 2-1-1-1 access rate ■ User selectable burst counter supporting Intel Pentium interleaved or linear burst sequences ■ Separate processor and controller address strobes ■ Synchronous self-timed write ■ Asynchronous output enable ■ CY7C1385D is available in JEDEC-standard Pb-free 100-pin TQFP package ■ ZZ sleep mode option The CY7C1385D is a 3.3 V, 512 K × 32 synchronous flow through SRAMs, designed to interface with high speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive edge triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, address pipelining chip enable (CE1), depth-expansion chip enables (CE2 and CE3), burst control inputs (ADSC, ADSP, and ADV), write enables (BWx, and BWE), and global write (GW). Asynchronous inputs include the output enable (OE) and the ZZ pin. The CY7C1385D allows interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the processor address strobe (ADSP) or the cache controller address strobe (ADSC) inputs. Address advancement is controlled by the address advancement (ADV) input. Addresses and chip enables are registered at rising edge of clock when address strobe processor (ADSP) or address strobe controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the advance pin (ADV). CY7C1385D operates from a +3.3 V core power supply while all outputs operate with a +2.5 V or +3.3 V supply. All inputs and outputs are JEDEC-standard and JESD8-5-compatible. For a complete list of related resources, click here. Selection Guide Description 133 MHz Unit Maximum Access Time 6.5 ns Maximum Operating Current 210 mA Maximum CMOS Standby Current 70 mA Cypress Semiconductor Corporation Document Number: 001-74016 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised December 29, 2015 CY7C1385D Logic Block Diagram – CY7C1385D Document Number: 001-74016 Rev. *C Page 2 of 22 CY7C1385D Contents Pin Configurations ........................................................... 4 Pin Definitions .................................................................. 5 Functional Overview ........................................................ 6 Single Read Accesses ................................................ 6 Single Write Accesses Initiated by ADSP ................... 6 Single Write Accesses Initiated by ADSC ................... 6 Burst Sequences ......................................................... 6 Sleep Mode ................................................................. 6 Interleaved Burst Address Table ................................. 7 Linear Burst Address Table ......................................... 7 ZZ Mode Electrical Characteristics .............................. 7 Truth Table ........................................................................ 8 Truth Table for Read/Write .............................................. 9 Maximum Ratings ........................................................... 10 Operating Range ............................................................. 10 Neutron Soft Error Immunity ......................................... 10 Electrical Characteristics ............................................... 10 Capacitance .................................................................... 11 Thermal Resistance ........................................................ 11 Document Number: 001-74016 Rev. *C AC Test Loads and Waveforms ..................................... 12 Switching Characteristics .............................................. 13 Timing Diagrams ............................................................ 14 Ordering Information ...................................................... 18 Ordering Code Definitions ......................................... 18 Package Diagrams .......................................................... 19 Acronyms ........................................................................ 20 Document Conventions ................................................. 20 Units of Measure ....................................................... 20 Document History Page ................................................. 21 Sales, Solutions, and Legal Information ...................... 22 Worldwide Sales and Design Support ....................... 22 Products .................................................................... 22 PSoC® Solutions ...................................................... 22 Cypress Developer Community ................................. 22 Technical Support ..................................................... 22 Page 3 of 22 CY7C1385D Pin Configurations Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout (3 Chip Enable) CY7C1385D (512 K × 32) Document Number: 001-74016 Rev. *C Page 4 of 22 CY7C1385D Pin Definitions Name A0, A1, A I/O Description Input Address inputs used to select one of the address locations. Sampled at the rising edge of the CLK Synchronous if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed the 2-bit counter. BWA, BWB, Input Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled BWC, BWD Synchronous on the rising edge of CLK. GW CLK Input Global write enable input, active LOW. When asserted LOW on the rising edge of CLK, a global write is Synchronous conducted (all bytes are written, regardless of the values on BW[A:D] and BWE). Input Clock Clock input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. CE1 Input Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 Synchronous and CE3 to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a new external address is loaded. CE2 Input Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 Synchronous and CE3 to select or deselect the device. CE2 is sampled only when a new external address is loaded. CE3 Input Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 Synchronous and CE2 to select or deselect the device. CE3 is sampled only when a new external address is loaded. OE Output enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW, Input Asynchronou the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tristated, and act as input data s pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. ADV Input Advance input signal. Sampled on the rising edge of CLK. When asserted, it automatically increments Synchronous the address in a burst cycle. ADSP Input Address strobe from processor, sampled on the rising edge of CLK, active LOW. When asserted Synchronous LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. ADSC Input Address strobe from controller, sampled on the rising edge of CLK, active LOW. When asserted Synchronous LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. BWE Input Byte write enable input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted Synchronous LOW to conduct a byte write. ZZ Input ZZ sleep input. This active HIGH input places the device in a non time critical sleep condition with data Asynchronou integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal s pull down. DQs I/O Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the Synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs are placed in a tristate condition.The outputs are automatically tristated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE. MODE VDD Input Static Selects burst order. When tied to GND selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. This is a strap pin and must remain static during device operation. Mode pin has an internal pull-up. Power Supply Power supply inputs to the core of the device. Document Number: 001-74016 Rev. *C Page 5 of 22 CY7C1385D Pin Definitions (continued) Name VDDQ VSS VSSQ NC VSS/DNU I/O Description I/O Power Supply Power supply for the I/O circuitry. Ground Ground for the core of the device. I/O Ground – Ground for the I/O circuitry. No connects. Not internally connected to the die. 36M, 72M, 144M, 288M, 576M, and 1G are address expansion pins and are not internally connected to the die. Ground/DNU This pin can be connected to ground or can be left floating. Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (t CDV) is 6.5 ns (133 MHz device). CY7C1385D supports secondary cache in systems using a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486 processors. The linear burst sequence is suited for processors that use a linear burst sequence. The burst order is user selectable, and is determined by sampling the MODE input. Accesses can be initiated with the processor address strobe (ADSP) or the controller address strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the byte write enable (BWE) and byte write select (BWX) inputs. A global write enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed write circuitry. Three synchronous chip selects (CE1, CE2, CE3) and an asynchronous output enable (OE) provide for easy bank selection and output tristate control. ADSP is ignored if CE1 is HIGH. Single Read Accesses A single read access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted active, and (2) ADSP or ADSC is asserted LOW (if the access is initiated by ADSC, the write inputs must be deasserted during this first cycle). The address presented to the address inputs is latched into the address register and the burst counter and/or control logic, and later presented to the memory core. If the OE input is asserted LOW, the requested data is available at the data outputs with a maximum to tCDV after clock rise. ADSP is ignored if CE1 is HIGH. Single Write Accesses Initiated by ADSP This access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, CE3 are all asserted active, and (2) ADSP is asserted LOW. The addresses presented are loaded into the address register and the burst inputs (GW, BWE, and BWX) are ignored during this first clock cycle. If the write inputs are asserted active (see Truth Table for Read/Write on Document Number: 001-74016 Rev. *C page 9 for appropriate states that indicate a write) on the next clock rise, the appropriate data is latched and written into the device. Byte writes are allowed. All I/O are tristated during a byte write. As this is a common I/O device, the asynchronous OE input signal must be deasserted and the I/O must be tristated prior to the presentation of data to DQs. As a safety precaution, the data lines are tristated when a write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC This write access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted active, (2) ADSC is asserted LOW, (3) ADSP is deasserted HIGH, and (4) the write input signals (GW, BWE, and BWX) indicate a write access. ADSC is ignored if ADSP is active LOW. The addresses presented are loaded into the address register and the burst counter, the control logic, or both, and delivered to the memory core The information presented to DQ[A:D] is written into the specified address location. Byte writes are allowed. All I/O are tristated when a write is detected, even a byte write. Because this is a common I/O device, the asynchronous OE input signal must be deasserted and the I/O must be tristated prior to the presentation of data to DQs. As a safety precaution, the data lines are tristated when a write cycle is detected, regardless of the state of OE. Burst Sequences CY7C1385D provides an on-chip two-bit wraparound burst counter inside the SRAM. The burst counter is fed by A[1:0], and can follow either a linear or interleaved burst order. The burst order is determined by the state of the MODE input. A LOW on MODE selects a linear burst sequence. A HIGH on MODE selects an interleaved burst order. Leaving MODE unconnected causes the device to default to a interleaved burst sequence. Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation sleep mode. Two clock cycles are required to enter into or exit from this sleep mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the sleep mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the sleep mode. CE1, CE2, CE3, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Page 6 of 22 CY7C1385D Interleaved Burst Address Table Linear Burst Address Table (MODE = Floating or VDD) (MODE = GND) First Address A1:A0 Second Address A1:A0 Third Address A1:A0 Fourth Address A1:A0 First Address A1:A0 Second Address A1:A0 Third Address A1:A0 00 01 01 00 Fourth Address A1:A0 10 11 00 01 10 11 11 10 01 10 11 00 10 11 00 01 10 11 00 01 11 10 01 00 11 00 01 10 ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max Unit IDDZZ Sleep mode standby current ZZ > VDD– 0.2 V – 80 mA tZZS Device operation to ZZ ZZ > VDD – 0.2 V – 2tCYC ns tZZREC ZZ recovery time ZZ < 0.2 V 2tCYC – ns tZZI ZZ active to sleep current This parameter is sampled – 2tCYC ns tRZZI ZZ inactive to exit sleep current This parameter is sampled 0 – ns Document Number: 001-74016 Rev. *C Page 7 of 22 CY7C1385D Truth Table The truth table for CY7C1385D follows. [1, 2, 3, 4, 5] Cycle Description Address Used CE1 CE2 CE3 ZZ ADSP ADSC ADV WRITE OE CLK DQ Deselected Cycle, Power Down None H X X L X L X X X L–H Tri-State Deselected Cycle, Power Down None L L X L L X X X X L–H Tri-State Deselected Cycle, Power Down None L X H L L X X X X L–H Tri-State Deselected Cycle, Power Down None L L X L H L X X X L–H Tri-State Deselected Cycle, Power Down None X X X L H L X X X L–H Tri-State Sleep Mode, Power Down None X X X H X X X X X X Tri-State Read Cycle, Begin Burst External L H L L L X X X L L–H Q Read Cycle, Begin Burst External L H L L L X X X H L–H Tri-State Write Cycle, Begin Burst External L H L L H L X L X L–H D Read Cycle, Begin Burst External L H L L H L X H L L–H Q Read Cycle, Begin Burst External L H L L H L X H H L–H Tri-State Read Cycle, Continue Burst Next X X X L H H L H L L–H Q Read Cycle, Continue Burst Next X X X L H H L H H L–H Tri-State Read Cycle, Continue Burst Next H X X L X H L H L L–H Q Read Cycle, Continue Burst Next H X X L X H L H H L–H Tri-State Write Cycle, Continue Burst Next X X X L H H L L X L–H D Write Cycle, Continue Burst Next H X X L X H L L X L–H D Read Cycle, Suspend Burst Current X X X L H H H H L L–H Q Read Cycle, Suspend Burst Current X X X L H H H H H L–H Tri-State Read Cycle, Suspend Burst Current H X X L X H H H L L–H Q Read Cycle, Suspend Burst Current H X X L X H H H H L–H Tri-State Write Cycle, Suspend Burst Current X X X L H H H L X L–H D Write Cycle, Suspend Burst Current H X X L X H H L X L–H D Notes 1. X = Don't Care, H = Logic HIGH, L = Logic LOW. 2. WRITE = L when any one or more byte write enable signals, and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H. 3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 4. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tristate. OE is a don't care for the remainder of the write cycle. 5. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tristate when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW). Document Number: 001-74016 Rev. *C Page 8 of 22 CY7C1385D Truth Table for Read/Write The truth table for CY7C1385D read/write follows. Function (CY7C1385D) GW BWE BWD BWC BWB BWA Read H H X X X X Read H L H H H H Write Byte A (DQA) H L H H H L Write Byte B(DQB) H L H H L H Write Bytes A, B (DQA, DQB) H L H H L L Write Byte C (DQC) H L H L H H Write Bytes C, A (DQC, DQA) H L H L H L Write Bytes C, B (DQC, DQB,) H L H L L H Write Bytes C, B, A (DQC, DQB, DQA) H L H L L L Write Byte D (DQD) H L L H H H Write Bytes D, A (DQD, DQA) H L L H H L Write Bytes D, B (DQD, DQA) H L L H L H Write Bytes D, B, A (DQD, DQB, DQA) H L L H L L Write Bytes D, B (DQD, DQB) H L L L H H Write Bytes D, B, A (DQD, DQC, DQA) H L L L H L Document Number: 001-74016 Rev. *C Page 9 of 22 CY7C1385D Maximum Ratings Operating Range Exceeding the maximum ratings may impair the useful life of the device. For user guidelines, not tested. Storage Temperature .............................. –65 °C to +150 °C Ambient Temperature with Power Applied ........................................ –55 °C to +125 °C Supply Voltage on VDD Relative to GND .....–0.3 V to +4.6 V Supply Voltage on VDDQ Relative to GND .... –0.3 V to +VDD DC Voltage Applied to Outputs in Tri-State ........................................–0.5 V to VDDQ + 0.5 V Industrial Static Discharge Voltage (per MIL-STD-883, Method 3015) .......................... > 2001 V Latch-up Current .................................................... > 200 mA VDD –40 °C to +85 °C VDDQ 3.3 V– 5% / 2.5 V – 5% to + 10% VDD Neutron Soft Error Immunity Test Parameter Description Conditions Typ Max [6] Unit LSBU Logical Single-Bit Upsets 25 °C 361 394 FIT/ Mb LMBU Logical Multi-Bit Upsets 25 °C 0 0.01 FIT/ Mb SEL Single Event Latch Up 85 °C 0 0.1 FIT/ Dev DC Input Voltage ................................ –0.5 V to VDD + 0.5 V Current into Outputs (LOW) ........................................ 20 mA Ambient Temperature Range Electrical Characteristics Over the Operating Range Parameter [7, 8] Description VDD Power Supply Voltage VDDQ I/O Supply Voltage VOH Output HIGH Voltage VOL Output LOW Voltage VIH Input HIGH Voltage [7] Test Conditions Min Max Unit 3.135 3.6 V for 3.3 V I/O 3.135 VDD V for 2.5 V I/O 2.375 2.625 V for 3.3 V I/O, IOH = –4.0 mA 2.4 – V for 2.5 V I/O, IOH = –1.0 mA 2.0 – V – 0.4 V for 3.3 V I/O, IOL = 8.0 mA for 2.5 V I/O, IOL = 1.0 mA [7] – 0.4 V for 3.3 V I/O 2.0 VDD + 0.3 V V for 2.5 V I/O 1.7 VDD + 0.3 V V for 3.3 V I/O –0.3 0.8 V for 2.5 V I/O VIL Input LOW Voltage –0.3 0.7 V IX Input Leakage Current except ZZ GND VI VDDQ and MODE –5 5 A Input Current of MODE Input = VSS –30 – A Input = VDD – 5 A Input = VSS –5 – A Input = VDD – 30 A Input Current of ZZ IOZ Output Leakage Current GND VI VDD, Output Disabled –5 5 A IDD VDD Operating Supply Current VDD = Max, IOUT = 0 mA, f = fMAX = 1/tCYC – 210 mA 7.5 ns cycle, 133 MHz Notes 6. No LMBU or SEL events occurred during testing; this column represents a statistical c2, 95% confidence limit calculation. For more details refer to Application Note AN54908 – Accelerated Neutron SER Testing and Calculation of Terrestrial Failure Rates. 7. Overshoot: VIH(AC) < VDD + 1.5 V (pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (pulse width less than tCYC/2). 8. Tpower up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD. Document Number: 001-74016 Rev. *C Page 10 of 22 CY7C1385D Electrical Characteristics (continued) Over the Operating Range Parameter [7, 8] Description Test Conditions 7.5 ns cycle, 133 MHz Min Max Unit – 140 mA ISB1 Automatic CE Power Down Current – TTL Inputs Max VDD, Device Deselected, VIN VIH or VIN VIL, f = fMAX, inputs switching ISB2 Automatic CE Power Down Current – CMOS Inputs Max VDD, Device Deselected, All speeds VIN VDD – 0.3 V or VIN 0.3 V, f = 0, inputs static – 70 mA ISB3 Automatic CE Power Down Current – CMOS Inputs 7.5 ns cycle, Max VDD, Device Deselected, VIN VDDQ – 0.3 V or VIN 0.3 V, 133 MHz f = fMAX, inputs switching – 130 mA ISB4 Automatic CE Power Down Current – TTL Inputs Max VDD, Device Deselected, VIN VDD – 0.3 V or VIN 0.3 V, f = 0, inputs static – 80 mA All Speeds Capacitance Parameter [9] Description Test Conditions TA = 25 °C, f = 1 MHz, VDD = 3.3 V, VDDQ = 2.5 V 100-pin TQFP Package Unit CIN Input capacitance 5 pF CCLK Clock input capacitance 5 pF CIO Input/Output capacitance 5 pF Test Conditions 100-pin TQFP Package Unit Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51. 28.66 °C/W 4.08 °C/W Thermal Resistance Parameter [9] Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) Note 9. Tested initially and after any design or process change that may affect these parameters. Document Number: 001-74016 Rev. *C Page 11 of 22 CY7C1385D AC Test Loads and Waveforms Figure 2. AC Test Loads and Waveforms 3.3 V I/O Test Load R = 317 3.3 V OUTPUT OUTPUT RL = 50 Z0 = 50 VT = 1.5 V (a) INCLUDING JIG AND SCOPE OUTPUT RL = 50 VT = 1.25 V (a) Document Number: 001-74016 Rev. *C R = 351 10% (c) ALL INPUT PULSES VDDQ INCLUDING JIG AND SCOPE 1 ns (b) GND 5 pF R = 1538 (b) 90% 10% 90% 1 ns R = 1667 2.5 V Z0 = 50 GND 5 pF 2.5 V I/O Test Load OUTPUT ALL INPUT PULSES VDDQ 10% 90% 10% 90% 1 ns 1 ns (c) Page 12 of 22 CY7C1385D Switching Characteristics Over the Operating Range Parameter [10, 11] tPOWER Description VDD(typical) to the first access [12] 133 MHz Unit Min Max 1 – ms Clock tCYC Clock cycle time 7.5 – ns tCH Clock HIGH 2.1 – ns tCL Clock LOW 2.1 – ns Output Times tCDV Data output valid after CLK rise – 6.5 ns tDOH Data output hold after CLK rise 2.0 – ns 2.0 – ns 0 4.0 ns – 3.2 ns 0 – ns – 4.0 ns [13, 14, 15] tCLZ Clock to low Z tCHZ Clock to high Z [13, 14, 15] tOEV OE LOW to output valid tOELZ tOEHZ OE LOW to output low Z [13, 14, 15] OE HIGH to output high Z [13, 14, 15] Setup Times tAS Address setup before CLK rise 1.5 – ns tADS ADSP, ADSC setup before CLK rise 1.5 – ns tADVS ADV setup before CLK rise 1.5 – ns tWES GW, BWE, BW[A:D] setup before CLK rise 1.5 – ns tDS Data input setup before CLK rise 1.5 – ns tCES Chip enable setup 1.5 – ns tAH Address hold after CLK rise 0.5 – ns tADH ADSP, ADSC hold after CLK rise 0.5 – ns tWEH GW, BWE, BW[A:D] hold after CLK rise 0.5 – ns tADVH ADV hold after CLK rise 0.5 – ns tDH Data input hold after CLK rise 0.5 – ns tCEH Chip enable hold after CLK rise 0.5 – ns Hold Times Notes 10. Timing reference level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V. 11. Test conditions shown in (a) of Figure 2 on page 12 unless otherwise noted. 12. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially, before a read or write operation can be initiated. 13. tCHZ, tCLZ, tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 2 on page 12. Transition is measured ±200 mV from steady-state voltage. 14. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve high Z prior to low Z under the same system condition. 15. This parameter is sampled and not 100% tested. Document Number: 001-74016 Rev. *C Page 13 of 22 CY7C1385D Timing Diagrams Figure 3. Read Cycle Timing [16] tCYC CLK t t ADS CH t CL tADH ADSP t ADS tADH ADSC t AS tAH A1 ADDRESS A2 t GW, BWE,BW WES t WEH X t CES Deselect Cycle t CEH CE t ADVS t ADVH ADV ADV suspends burst OE t OEV t OEHZ t CLZ Data Out (Q) High-Z Q(A1) t CDV t OELZ t CHZ t DOH Q(A2) Q(A2 + 1) Q(A2 + 2) t CDV Q(A2 + 3) Q(A2) Q(A2 + 1) Q(A2 + 2) Burst wraps around to its initial state Single READ BURST READ DON’T CARE UNDEFINED Note 16. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH. Document Number: 001-74016 Rev. *C Page 14 of 22 CY7C1385D Timing Diagrams (continued) Figure 4. Write Cycle Timing [17, 18] t CYC CLK t t ADS CH t CL tADH ADSP t ADS ADSC extends burst tADH t ADS tADH ADSC t AS tAH A1 ADDRESS A2 A3 Byte write signals are ignored for first cycle when ADSP initiates burst t WES tWEH BWE, BW X t WES t WEH GW t CES tCEH CE t ADVS tADVH ADV ADV suspends burst OE t Data in (D) High-Z t DS t DH D(A1) D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2) OEHZ Data Out (Q) BURST READ Single WRITE BURST WRITE DON’T CARE Extended BURST WRITE UNDEFINED Notes 17. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH. 18. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW. Document Number: 001-74016 Rev. *C Page 15 of 22 CY7C1385D Timing Diagrams (continued) Figure 5. Read/Write Cycle Timing [19, 20, 21] tCYC CLK t t ADS CH t CL tADH ADSP ADSC t AS ADDRESS A1 tAH A2 A3 A4 t WES t A5 A6 WEH BWE, BW X t CES tCEH CE ADV OE t DS Data In (D) Data Out (Q) High-Z t OEHZ Q(A1) tDH t OELZ D(A3) D(A5) Q(A2) Back-to-Back READs D(A6) t CDV Q(A4) Single WRITE Q(A4+1) BURST READ DON’T CARE Q(A4+2) Q(A4+3) Back-to-Back WRITEs UNDEFINED Notes 19. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH. 20. The data bus (Q) remains in high Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC. 21. GW is HIGH. Document Number: 001-74016 Rev. *C Page 16 of 22 CY7C1385D Timing Diagrams (continued) Figure 6. ZZ Mode Timing [22, 23] CLK t ZZ ZZ I t ZZREC t ZZI SUPPLY I DDZZ t RZZI ALL INPUTS (except ZZ) Outputs (Q) DESELECT or READ Only High-Z DON’T CARE Notes 22. Device must be deselected when entering ZZ mode. See Truth Table on page 8 for all possible signal conditions to deselect the device. 23. DQs are in high Z when exiting ZZ sleep mode. Document Number: 001-74016 Rev. *C Page 17 of 22 CY7C1385D Ordering Information Cypress offers other versions of this type of product in many different configurations and features. The below table contains only the list of parts that are currently available. For a complete listing of all options, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products or contact your local sales representative. Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office closest to you, visit us at t http://www.cypress.com/go/datasheet/offices. Speed (MHz) 133 Package Diagram Ordering Code CY7C1385D-133AXI Part and Package Type 51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free Operating Range lndustrial Ordering Code Definitions CY 7 C 1385 D - 133 A X I Temperature Range: I = Industrial Pb-free Package Type: A = 100-pin TQFP Frequency Range: 133 MHz Die Revision: X = D D 90 nm Part Identifier: 1385 = FT, 512 Kb × 32 (18 Mb) Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 001-74016 Rev. *C Page 18 of 22 CY7C1385D Package Diagrams Figure 7. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050 51-85050 *E Document Number: 001-74016 Rev. *C Page 19 of 22 CY7C1385D Acronyms Acronym Document Conventions Description Units of Measure CE Chip Enable CMOS Complementary Metal Oxide Semiconductor °C degree Celsius EIA Electronic Industries Alliance MHz megahertz I/O Input/Output µA microampere JEDEC Joint Electron Devices Engineering Council mA milliampere LMBU Logical Multi-Bit Upsets mm millimeter LSBU Logical Single-Bit Upsets ms millisecond OE Output Enable SEL Single Event Latch-up SRAM Static Random Access Memory TQFP Thin Quad Flat Pack TTL Transistor-Transistor Logic Document Number: 001-74016 Rev. *C Symbol Unit of Measure ns nanosecond ohm % percent pF picofarad V volt W watt Page 20 of 22 CY7C1385D Document History Page Document Title: CY7C1385D, 18-Mbit (512 K × 32) Flow-Through SRAM Document Number: 001-74016 Rev. ECN No. Orig. of Change Submission Date ** 3454705 NJY 12/04/2011 *A 3617718 PRIT / NJY 05/15/2012 Changed status from Preliminary to Final. *B 4585009 PRIT 12/02/2014 Updated Functional Description: Added “For a complete list of related resources, click here.” at the end. Updated Timing Diagrams: Updated Figure 3, Figure 4, Figure 5, Figure 6. Updated Package Diagrams: spec 51-85050 – Changed revision from *D to *E. Updated to new template. Completing Sunset Review. *C 5067238 PRIT 12/29/2015 Updated to new template. Completing Sunset Review. Document Number: 001-74016 Rev. *C Description of Change New data sheet. Page 21 of 22 CY7C1385D Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/memory cypress.com/go/psoc cypress.com/go/touch psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2011-2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-74016 Rev. *C Revised December 29, 2015 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 22 of 22