CYPRESS CY7C1481BV25

CY7C1481BV25
72-Mbit (2 M × 36) Flow-Through SRAM
72-Mbit (2 M × 36) Flow-Through SRAM
Features
Functional Description
■
Supports 133 MHz bus operations
■
2 M × 36 common I/O
■
2.5 V core power supply (VDD)
■
2.5 V I/O supply (VDDQ)
■
Fast clock to output time
❐ 6.5 ns (133 MHz version)
■
Provide high performance 2-1-1-1 access rate
■
User selectable burst counter supporting Intel® Pentium®
interleaved or linear burst sequences
■
Separate processor and controller address strobes
■
Synchronous self timed write
■
Asynchronous output enable
■
CY7C1481BV25 available in JEDEC standard Pb-free 100-pin
TQFP package
■
IEEE 1149.1 JTAG compatible boundary scan
■
ZZ sleep mode option
The CY7C1481BV25 is a 2.5 V, 2 M × 36 synchronous flow
through SRAM designed to interface with high speed
microprocessors with minimum glue logic. Maximum access
delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip
counter captures the first address in a burst and increments the
address automatically for the rest of the burst access. All
synchronous inputs are gated by registers controlled by a
positive edge triggered Clock Input (CLK). The synchronous
inputs include all addresses, all data inputs, address pipelining
Chip Enable (CE1), depth expansion Chip Enables (CE2 and
CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write
Enables (BWx and BWE), and Global Write (GW). Asynchronous
inputs include the Output Enable (OE) and the ZZ pin.
The CY7C1481BV25 enables either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects an
interleaved burst sequence, while a LOW selects a linear burst
sequence. Burst accesses are initiated with the Processor
Address Strobe (ADSP) or the cache Controller Address Strobe
(ADSC) inputs. Address advancement is controlled by the
Address Advancement (ADV) input.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or Address
Strobe Controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
Advance pin (ADV).
Selection Guide
133 MHz
Unit
Maximum Access Time
Description
6.5
ns
Maximum Operating Current
305
mA
Maximum CMOS Standby Current
120
mA
Cypress Semiconductor Corporation
Document Number: 001-74847 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 24, 2013
CY7C1481BV25
Logic Block Diagram – CY7C1481BV25
ADDRESS
REGISTER
A 0, A1, A
A [1:0]
MODE
BURST Q1
COUNTER
AND LOGIC
Q0
CLR
ADV
CLK
ADSC
ADSP
DQ D , DQP D
BW D
BYTE
WRITE REGISTER
DQ C, DQP C
BW C
BYTE
WRITE REGISTER
DQ D , DQP D
BYTE
WRITE REGISTER
DQ C, DQP C
BYTE
WRITE REGISTER
DQ B , DQP B
BW B
DQ B , DQP B
BYTE
BYTE
WRITE REGISTER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
BUFFERS
DQ s
DQP A
DQP B
DQP C
DQP D
WRITE REGISTER
DQ A , DQP A
BW A
BWE
DQ A , DQPA
BYTE
BYTE
WRITE REGISTER
WRITE REGISTER
GW
ENABLE
REGISTER
CE1
CE2
INPUT
REGISTERS
CE3
OE
ZZ
SLEEP
CONTROL
Document Number: 001-74847 Rev. *A
Page 2 of 21
CY7C1481BV25
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 5
Functional Overview ........................................................ 6
Single Read Accesses ................................................ 6
Single Write Accesses Initiated by ADSP ................... 6
Single Write Accesses Initiated by ADSC ................... 6
Burst Sequences ......................................................... 6
Sleep Mode ................................................................. 6
Interleaved Burst Address Table ................................. 7
Linear Burst Address Table ......................................... 7
ZZ Mode Electrical Characteristics .............................. 7
Truth Table ........................................................................ 8
Truth Table for Read/Write .............................................. 9
Maximum Ratings ........................................................... 10
Operating Range ............................................................. 10
Electrical Characteristics ............................................... 10
Document Number: 001-74847 Rev. *A
Capacitance .................................................................... 11
Thermal Resistance ........................................................ 11
AC Test Loads and Waveforms ..................................... 11
Switching Characteristics .............................................. 12
Timing Diagrams ............................................................ 13
Ordering Information ...................................................... 17
Ordering Code Definitions ......................................... 17
Package Diagrams .......................................................... 18
Acronyms ........................................................................ 19
Document Conventions ................................................. 19
Units of Measure ....................................................... 19
Document History Page ................................................. 20
Sales, Solutions, and Legal Information ...................... 21
Worldwide Sales and Design Support ....................... 21
Products .................................................................... 21
PSoC Solutions ......................................................... 21
Page 3 of 21
CY7C1481BV25
Pin Configurations
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1481BV25
(2 M × 36)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPB
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
DQPA
Document Number: 001-74847 Rev. *A
A
A
A
A
A
A
A
A
A
MODE
A
A
A
A
A1
A0
A
A
VSS
VDD
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DQPC
DQC
DQC
VDDQ
VSSQ
DQC
DQC
DQC
DQC
VSSQ
VDDQ
DQC
DQC
NC
VDD
NC
VSS
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
VSSQ
VDDQ
DQD
DQD
DQPD
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE1
CE2
BWD
BWC
BWB
BWA
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout
Page 4 of 21
CY7C1481BV25
Pin Definitions
Pin Name
A0, A1, A
I/O
Description
InputAddress Inputs Used to Select One of the Address Locations. Sampled at the rising edge of the CLK
Synchronous if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed the 2-bit counter.
InputByte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte writes to the SRAM.
BWA, BWB,
BWC, BWD Synchronous Sampled on the rising edge of CLK.
GW
CLK
InputGlobal Write Enable Input, Active LOW. When asserted LOW on the rising edge of CLK, a global write
Synchronous is conducted (ALL bytes are written, regardless of the values on BWX and BWE).
InputClock
Clock Input. Captures all synchronous inputs to the device. Also used to increment the burst counter
when ADV is asserted LOW during a burst operation.
CE1
InputChip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
Synchronous and CE3 to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a
new external address is loaded.
CE2
InputChip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE3 to select or deselect the device. CE2 is sampled only when a new external address is loaded.
CE3
InputChip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE2 to select or deselect the device. CE3 is sampled only when a new external address is loaded.
OE
InputOutput Enable, Asynchronous Input, Active LOW. Controls the direction of the I/O pins. When LOW,
Asynchronous the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data
pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.
ADV
InputAdvance Input Signal, Sampled on the Rising Edge of CLK. When asserted, it automatically
Synchronous increments the address in a burst cycle.
ADSP
InputAddress Strobe from Processor, Sampled on the Rising Edge of CLK, Active LOW. When asserted
Synchronous LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is
ignored when CE1 is deasserted HIGH.
ADSC
InputAddress Strobe from Controller, Sampled on the Rising Edge of CLK, Active LOW. When asserted
Synchronous LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
BWE
InputByte Write Enable Input, Active LOW. Sampled on the rising edge of CLK. This signal must be asserted
Synchronous LOW to conduct a byte write.
ZZ
InputZZ “Sleep” Input, Active HIGH. When asserted HIGH, places the device in a non time-critical “sleep”
Asynchronous condition with data integrity preserved. For normal operation, this pin must be LOW or left floating. ZZ
pin has an internal pull down.
DQs
I/OBidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered by the
Synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled
by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX are placed
in a tri-state condition. The outputs are automatically tri-stated during the data portion of a write sequence,
the first clock when emerging from a deselected state, and when the device is deselected, regardless of
the state of OE.
DQPX
I/OBidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQs. During write
Synchronous sequences, DQPx is controlled by BWX correspondingly.
MODE
Input-Static Selects Burst Order. When tied to GND, selects linear burst sequence. When tied to VDD or left floating,
selects interleaved burst sequence. This is a strap pin and must remain static during device operation.
Mode Pin has an internal pull up.
VDD
VDDQ
VSS
Power Supply Power Supply Inputs to the Core of the Device.
I/O Power
Supply
Power Supply for the I/O Circuitry.
Ground
Ground for the Core of the Device.
Document Number: 001-74847 Rev. *A
Page 5 of 21
CY7C1481BV25
Pin Definitions (continued)
Pin Name
VSSQ
NC
I/O
Description
I/O Ground Ground for the I/O Circuitry.
–
No Connects. Not internally connected to the die. 144M, 288M, 576M, and 1G are address expansion
pins are not internally connected to the die.
Functional Overview
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. Maximum access delay from the
clock rise (t CDV) is 6.5 ns (133 MHz device).
The CY7C1481BV25 supports secondary cache in systems
using either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486™ processors.
The linear burst sequence is suited for processors that use a
linear burst sequence. The burst order is user selectable and is
determined by sampling the MODE input. Accesses are initiated
with either the Processor Address Strobe (ADSP) or the
Controller Address Strobe (ADSC). Address advancement
through the burst sequence is controlled by the ADV input. A
2-bit on-chip wraparound burst counter captures the first address
in a burst sequence and automatically increments the address
for the rest of the burst access.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BWX) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to all
four bytes. All writes are simplified with on-chip synchronous self
timed write circuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide easy bank selection
and output tri-state control. ADSP is ignored if CE1 is HIGH.
Single Read Accesses
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted
active, and (2) ADSP or ADSC is asserted LOW (if the access is
initiated by ADSC, the write inputs must be deasserted during
this first cycle). The address presented to the address inputs is
latched into the address register and the burst counter/control
logic. It is then presented to the memory core. If the OE input is
asserted LOW, the requested data is available at the data
outputs a maximum of tCDV after clock rise. ADSP is ignored if
CE1 is HIGH.
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, CE3 are all asserted active,
and (2) ADSP is asserted LOW. The addresses presented are
loaded into the address register and the burst inputs (GW, BWE,
and BWX) are ignored during this first clock cycle. If the write
inputs are asserted active on the next clock rise, the appropriate
Document Number: 001-74847 Rev. *A
data is latched and written into the device. The device allows
byte writes. All I/Os are tri-stated during a byte write. Because
this is a common I/O device, the asynchronous OE input signal
must be deasserted and the I/Os must be tri-stated prior to the
presentation of data to DQs. As a safety precaution, the data
lines are tri-stated after a write cycle is detected, regardless of
the state of OE.
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the write input signals (GW, BWE, and BWX)
indicate a write access. ADSC is ignored if ADSP is active LOW.
The addresses presented are loaded into the address register
and the burst counter/control logic and delivered to the memory
core. The information presented to DQS is written into the
specified address location. The device allows byte writes. All
I/Os are tri-stated when a write is detected, even a byte write.
Because this is a common I/O device, the asynchronous OE
input signal must be deasserted and the I/Os must be tri-stated
before data is presented to DQs. As a safety precaution, the data
lines are tri-stated after a write cycle is detected, regardless of
the state of OE.
Burst Sequences
The CY7C1481BV25 provides an on-chip 2-bit wraparound burst
counter inside the SRAM. The burst counter is fed by A[1:0], and
can follow either a linear or interleaved burst order. The burst
order is determined by the state of the MODE input. A LOW on
MODE selects a linear burst sequence. A HIGH on MODE
selects an interleaved burst order. Leaving MODE unconnected
causes the device to default to an interleaved burst sequence.
Sleep Mode
The ZZ input pin is asynchronous. Asserting ZZ places the
SRAM in a power conservation “sleep” mode. Two clock cycles
are required to enter into or exit from this “sleep” mode. While in
this mode, data integrity is guaranteed. Accesses pending when
entering the “sleep” mode are not considered valid nor is the
completion of the operation guaranteed. The device must be
deselected before entering the “sleep” mode. CE1, CE2, CE3,
ADSP, and ADSC must remain inactive for the duration of tZZREC
after the ZZ input returns LOW.
Page 6 of 21
CY7C1481BV25
Linear Burst Address Table
Interleaved Burst Address Table
(MODE = GND)
(MODE = Floating or VDD)
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min
Max
Unit
IDDZZ
Sleep mode standby current
ZZ > VDD– 0.2 V
–
120
mA
tZZS
Device operation to ZZ
ZZ > VDD – 0.2 V
–
2tCYC
ns
tZZREC
ZZ recovery time
ZZ < 0.2 V
2tCYC
–
ns
tZZI
ZZ active to sleep current
This parameter is sampled
–
2tCYC
ns
tRZZI
ZZ inactive to exit sleep current
This parameter is sampled
0
–
ns
Document Number: 001-74847 Rev. *A
Page 7 of 21
CY7C1481BV25
Truth Table
The truth table for CY7C1481BV25 follows. [1, 2, 3, 4, 5]
Cycle Description
Address Used CE1 CE2 CE3 ZZ ADSP ADSC ADV WRITE OE CLK
Deselected Cycle, Power Down
None
H
Deselected Cycle, Power Down
None
L
Deselected Cycle, Power Down
None
L
Deselected Cycle, Power Down
None
L
Deselected Cycle, Power Down
None
X
Sleep Mode, Power Down
X
DQ
X
L
X
L
X
X
X
L–H Tri-State
L
X
L
L
X
X
X
X
L–H Tri-State
X
H
L
L
X
X
X
X
L–H Tri-State
L
X
L
H
L
X
X
X
L–H Tri-State
X
X
L
H
L
X
X
X
L–H Tri-State
None
X
X
X
H
X
X
X
X
X
X
Tri-State
Read Cycle, Begin Burst
External
L
H
L
L
L
X
X
X
L
L–H
Q
Read Cycle, Begin Burst
External
L
H
L
L
L
X
X
X
H
L–H Tri-State
Write Cycle, Begin Burst
External
L
H
L
L
H
L
X
L
X
L–H
D
Q
Read Cycle, Begin Burst
External
L
H
L
L
H
L
X
H
L
L–H
Read Cycle, Begin Burst
External
L
H
L
L
H
L
X
H
H
L–H Tri-State
Read Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
L
L–H
Read Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
H
L–H Tri-State
Read Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
L
L–H
Read Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
H
L–H Tri-State
Write Cycle, Continue Burst
Next
X
X
X
L
H
H
L
L
X
L–H
D
Write Cycle, Continue Burst
Next
H
X
X
L
X
H
L
L
X
L–H
D
Read Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
L
L–H
Q
Read Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
H
L–H Tri-State
Read Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
L
L–H
Read Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
H
L–H Tri-State
Write Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
L
X
L–H
D
Write Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
L
X
L–H
D
Q
Q
Q
Notes
1. X = Do Not Care, H = Logic HIGH, L = Logic LOW.
2. WRITE = L when any one or more byte write enable signals and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H.
3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
4. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after the
ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to enable the outputs to tri-state. OE is a do not care for
the remainder of the write cycle.
5. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is inactive
or when the device is deselected, and all data bits behave as outputs when OE is active (LOW).
Document Number: 001-74847 Rev. *A
Page 8 of 21
CY7C1481BV25
Truth Table for Read/Write
The read-write truth table for CY7C1481BV25 follows. [6, 7]
Function (CY7C1481BV25)
GW
BWE
BWD
BWC
BWB
BWA
Read
H
H
X
X
X
X
Read
H
L
H
H
H
H
Write Byte A (DQA, DQPA)
H
L
H
H
H
L
Write Byte B(DQB, DQPB)
H
L
H
H
L
H
Write Bytes A, B (DQA, DQB, DQPA, DQPB)
H
L
H
H
L
L
Write Byte C (DQC, DQPC)
H
L
H
L
H
H
Write Bytes C, A (DQC, DQA, DQPC, DQPA)
H
L
H
L
H
L
Write Bytes C, B (DQC, DQB, DQPC, DQPB)
H
L
H
L
L
H
Write Bytes C, B, A (DQC, DQB, DQA, DQPC, DQPB,
DQPA)
H
L
H
L
L
L
Write Byte D (DQD, DQPD)
H
L
L
H
H
H
Write Bytes D, A (DQD, DQA, DQPD, DQPA)
H
L
L
H
H
L
Write Bytes D, B (DQD, DQA, DQPD, DQPA)
H
L
L
H
L
H
Write Bytes D, B, A (DQD, DQB, DQA, DQPD, DQPB,
DQPA)
H
L
L
H
L
L
Write Bytes D, B (DQD, DQB, DQPD, DQPB)
H
L
L
L
H
H
Write Bytes D, B, A (DQD, DQC, DQA, DQPD, DQPC,
DQPA)
H
L
L
L
H
L
Write Bytes D, C, A (DQD, DQB, DQA, DQPD, DQPB,
DQPA)
H
L
L
L
L
H
Write All Bytes
H
L
L
L
L
L
Write All Bytes
L
X
X
X
X
X
Notes
6. X = Do Not Care, H = Logic HIGH, L = Logic LOW.
7. Table only includes a partial listing of the byte write combinations. Any combination of BWX is valid. An appropriate write is performed based on which byte write is active.
Document Number: 001-74847 Rev. *A
Page 9 of 21
CY7C1481BV25
Maximum Ratings
DC Input Voltage ................................ –0.5 V to VDD + 0.5 V
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ............................... –65 C to +150 C
Ambient Temperature with
Power Applied ......................................... –55 C to +125 C
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage
(MIL-STD-883, Method 3015) ................................. >2001 V
Latch Up Current ................................................... >200 mA
Operating Range
Supply Voltage on VDD Relative to GND .....–0.3 V to +3.6 V
Range
Supply Voltage on VDDQ Relative to GND .... –0.3 V to +VDD
DC Voltage Applied to Outputs
in Tri-State ........................................–0.5 V to VDDQ + 0.5 V
Commercial
Industrial
Ambient
Temperature
0 °C to +70 °C
–40 °C to +85 °C
VDD
VDDQ
2.5 V– 5% / 2.5 V – 5% to
+ 5%
VDD
Electrical Characteristics
Over the Operating Range
Parameter [8, 9]
Description
VDD
Power Supply Voltage
Test Conditions
Min
Max
Unit
2.375
2.625
V
2.375
VDD
V
2.0
–
V
VDDQ
I/O Supply Voltage
For 2.5 V I/O
VOH
Output HIGH Voltage
For 2.5 V I/O, IOH = –1.0 mA
VOL
Output LOW Voltage
For 2.5 V I/O, IOL = 1.0 mA
–
0.4
V
VIH
Input HIGH Voltage [8]
For 2.5 V I/O
1.7
VDD + 0.3 V
V
For 2.5 V I/O
–0.3
0.7
V
[8]
VIL
Input LOW Voltage
IX
Input Leakage Current except ZZ GND  VI  VDDQ
and MODE
–5
5
A
Input Current of MODE
Input = VSS
–30
–
A
Input = VDD
–
5
A
Input Current of ZZ
Input = VSS
–5
–
A
Input = VDD
–
30
A
IOZ
Output Leakage Current
GND  VI  VDDQ, Output Disabled
–5
5
A
IDD [10]
VDD Operating Supply Current
VDD = Max, IOUT = 0 mA,
f = fMAX = 1/tCYC
7.5 ns cycle,
133 MHz
–
305
mA
ISB1
Automatic CE Power Down
Current – TTL Inputs
Max. VDD, Device Deselected,
VIN  VIH or VIN  VIL, f = fMAX,
inputs switching
7.5 ns cycle,
133 MHz
–
170
mA
ISB2
Automatic CE Power Down
Current – CMOS Inputs
7.5 ns cycle,
Max. VDD, Device Deselected,
VIN  VDD – 0.3 V or VIN  0.3 V, 133 MHz
f = 0, inputs static
–
120
mA
ISB3
Automatic CE Power Down
Current – CMOS Inputs
7.5 ns cycle,
Max. VDD, Device Deselected,
VIN  VDDQ – 0.3 V or VIN  0.3 V, 133 MHz
f = fMAX, inputs switching
–
170
mA
ISB4
Automatic CE Power Down
Current – TTL Inputs
Max. VDD, Device Deselected,
VIN  VDD – 0.3 V or VIN  0.3 V,
f = 0, inputs static
7.5 ns cycle,
133 MHz
–
135
mA
Notes
8. Overshoot: VIH(AC) < VDD + 1.5 V (pulse width less than tCYC/2). Undershoot: VIL(AC) > –2 V (pulse width less than tCYC/2).
9. TPower-up: assumes a linear ramp from 0 V to VDD(minimum) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
10. The operation current is calculated with 50% read cycle and 50% write cycle.
Document Number: 001-74847 Rev. *A
Page 10 of 21
CY7C1481BV25
Capacitance
Parameter [11]
Description
Test Conditions
100-pin TQFP
Package
Unit
6
pF
TA = 25 C, f = 1 MHz, VDD = 2.5 V, VDDQ = 2.5 V
CADDRESS
Address Input Capacitance
CDATA
Data Input Capacitance
5
pF
CCTRL
Control Input Capacitance
8
pF
CCLK
Clock Input Capacitance
6
pF
CIO
Input/Output Capacitance
5
pF
100-pin TQFP
Package
Unit
24.63
C/W
2.28
C/W
Thermal Resistance
Parameter [11]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Test Conditions
Test conditions follow standard test methods and
procedures for measuring thermal impedance, per
EIA/JESD51.
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
2.5 V IO Test Load
R = 1667
2.5V
OUTPUT
OUTPUT
RL = 50
Z0 = 50
GND
5 pF
R = 1583
VL = 1.25V
(a)
ALL INPUT PULSES
VDDQ
INCLUDING
JIG AND
SCOPE
(b)
10%
90%
10%
90%
 1 ns
 1 ns
(c)
Note
11. Tested initially and after any design or process change that may affect these parameters.
Document Number: 001-74847 Rev. *A
Page 11 of 21
CY7C1481BV25
Switching Characteristics
Over the Operating Range
Parameter [12, 13]
tPOWER
Description
VDD(typical) to the First Access [14]
133 MHz
Unit
Min
Max
1
–
ms
Clock
tCYC
Clock Cycle Time
7.5
–
ns
tCH
Clock HIGH
2.5
–
ns
tCL
Clock LOW
2.5
–
ns
Output Times
tCDV
Data Output Valid After CLK Rise
–
6.5
ns
tDOH
Data Output Hold After CLK Rise
2.5
–
ns
3.0
–
ns
–
3.8
ns
–
3.0
ns
0
–
ns
–
3.0
ns
[15, 16, 17]
tCLZ
Clock to Low Z
tCHZ
Clock to High Z [15, 16, 17]
tOEV
OE LOW to Output Valid
tOELZ
tOEHZ
OE LOW to Output Low Z
[15, 16, 17]
OE HIGH to Output High Z
[15, 16, 17]
Setup Times
tAS
Address Setup Before CLK Rise
1.5
–
ns
tADS
ADSP, ADSC Setup Before CLK Rise
1.5
–
ns
tADVS
ADV Setup Before CLK Rise
1.5
–
ns
tWES
GW, BWE, BWX Setup Before CLK Rise
1.5
–
ns
tDS
Data Input Setup Before CLK Rise
1.5
–
ns
tCES
Chip Enable Setup
1.5
–
ns
tAH
Address Hold After CLK Rise
0.5
–
ns
tADH
ADSP, ADSC Hold After CLK Rise
0.5
–
ns
tWEH
GW, BWE, BWX Hold After CLK Rise
0.5
–
ns
Hold Times
tADVH
ADV Hold After CLK Rise
0.5
–
ns
tDH
Data Input Hold After CLK Rise
0.5
–
ns
tCEH
Chip Enable Hold After CLK Rise
0.5
–
ns
Notes
12. Timing reference level is 1.25 V when VDDQ = 2.5 V.
13. Test conditions shown in (a) of Figure 2 on page 11 unless otherwise noted.
14. This part has an internal voltage regulator; tPOWER is the time that the power is supplied above VDD(minimum) initially, before a read or write operation can be initiated.
15. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 2 on page 11. Transition is measured ±200 mV from steady-state voltage.
16. At any supplied voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. The device is designed to achieve
High Z before Low Z under the same system conditions.
17. This parameter is sampled and not 100% tested.
Document Number: 001-74847 Rev. *A
Page 12 of 21
CY7C1481BV25
Timing Diagrams
Figure 3. Read Cycle Timing [18]
tCYC
CLK
t
t ADS
CH
t CL
tADH
ADSP
t ADS
tADH
ADSC
t AS
tAH
A1
ADDRESS
A2
t
WES
t
WEH
GW, BWE, BW X
t CES
Deselect Cycle
t CEH
CE
t
ADVS
t
ADVH
ADV
ADV suspends burst
OE
t OEV
t OEHZ
t CLZ
Data Out (Q)
High-Z
Q(A1)
t CDV
t OELZ
t CHZ
t DOH
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
t CDV
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Burst wraps around
to its initial state
Single READ
BURST
READ
DON’T CARE
UNDEFINED
Note
18. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH, CE2 is LOW, or CE3 is HIGH.
Document Number: 001-74847 Rev. *A
Page 13 of 21
CY7C1481BV25
Timing Diagrams (continued)
Figure 4. Write Cycle Timing [19, 20]
t CYC
CLK
t
t ADS
CH
t
CL
tADH
ADSP
t ADS
ADSC extends burst
tADH
t ADS
tADH
ADSC
t AS
tAH
A1
ADDRESS
A2
A3
Byte write signals are ignored for first cycle when
ADSP initiates burst
t WES tWEH
BWE, BW X
t
WES
t
WEH
GW
t CES
tCEH
CE
t ADVS tADVH
ADV
ADV suspends burst
OE
t
Data in (D)
High-Z
t
DS
t
DH
D(A1)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
OEHZ
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
DON’T CARE
Extended BURST WRITE
UNDEFINED
Notes
19. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH, CE2 is LOW, or CE3 is HIGH.
20. Full width write can be initiated by either GW LOW, or by GW HIGH, BWE LOW and BWX LOW.
Document Number: 001-74847 Rev. *A
Page 14 of 21
CY7C1481BV25
Timing Diagrams (continued)
Figure 5. Read/Write Cycle Timing [21, 22, 23]
tCYC
CLK
t
t ADS
CH
t
CL
tADH
ADSP
ADSC
t AS
ADDRESS
A1
tAH
A2
A3
A4
t
WES
t
A5
A6
WEH
BWE, BW X
t CES
tCEH
CE
ADV
OE
t DS
Data In (D)
Data Out (Q)
High-Z
t
OEHZ
Q(A1)
tDH
t OELZ
D(A3)
D(A5)
Q(A2)
Back-to-Back READs
D(A6)
t CDV
Q(A4)
Single WRITE
Q(A4+1)
BURST READ
DON’T CARE
Q(A4+2)
Q(A4+3)
Back-to-Back
WRITEs
UNDEFINED
Notes
21. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH, CE2 is LOW, or CE3 is HIGH.
22. The data bus (Q) remains in High Z following a write cycle, unless a new read access is initiated by ADSP or ADSC.
23. GW is HIGH.
Document Number: 001-74847 Rev. *A
Page 15 of 21
CY7C1481BV25
Timing Diagrams (continued)
Figure 6. ZZ Mode Timing [24, 25]
CLK
t ZZ
ZZ
I
t ZZREC
t ZZI
SUPPLY
I DDZZ
t RZZI
ALL INPUTS
DESELECT or READ Only
(except ZZ)
Outputs (Q)
High-Z
DON’T CARE
Notes
24. Device must be deselected when entering ZZ mode. See Truth Table on page 8 for all possible signal conditions to deselect the device.
25. DQs are in High Z when exiting ZZ sleep mode.
Document Number: 001-74847 Rev. *A
Page 16 of 21
CY7C1481BV25
Ordering Information
Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or visit
www.cypress.com for actual products offered.
Speed
(MHz)
133
Package
Diagram
Ordering Code
CY7C1481BV25-133AXI
Part and Package Type
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Operating
Range
Industrial
Ordering Code Definitions
CY 7
C
1481 B V25 - 133
A
X
I
Temperature range:
I = Industrial = –40 °C to +85 °C
X = Pb-free
Package Type:
A = 100-pin TQFP
Speed Grade: 133 MHz
V25 = 2.5 V VDD
Process Technology: B  errata fix PCN084636
Part Identifier: 1481 = SCD, 2 Mb × 36 (72 Mb)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 001-74847 Rev. *A
Page 17 of 21
CY7C1481BV25
Package Diagrams
Figure 7. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050
51-85050 *D
Document Number: 001-74847 Rev. *A
Page 18 of 21
CY7C1481BV25
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CE
Chip Enable
CMOS
Complementary Metal-Oxide-Semiconductor
°C
degree Celsius
EIA
Electronic Industries Alliance
MHz
megahertz
I/O
Input/Output
µA
microampere
JEDEC
Joint Electron Devices Engineering Council
mA
milliampere
OE
Output Enable
mm
millimeter
SRAM
Static Random Access Memory
ms
millisecond
TQFP
Thin Quad Flat Pack
mV
millivolt
TTL
Transistor-Transistor Logic
ns
nanosecond

ohm
%
percent
pF
picofarad
V
volt
W
watt
Document Number: 001-74847 Rev. *A
Symbol
Unit of Measure
Page 19 of 21
CY7C1481BV25
Document History Page
Document Title: CY7C1481BV25, 72-Mbit (2 M × 36) Flow-Through SRAM
Document Number: 001-74847
Rev.
ECN No.
Issue Date
Orig. of
Change
**
3617660
05/15/2012
PRIT /
GOPA
New data sheet.
*A
4010294
05/24/2013
PRIT
No technical updates. Completing Sunset Review.
Document Number: 001-74847 Rev. *A
Description of Change
Page 20 of 21
CY7C1481BV25
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
PSoC Solutions
cypress.com/go/automotive
cypress.com/go/clocks
psoc.cypress.com/solutions
cypress.com/go/interface
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
Optical & Image Sensing
PSoC
Touch Sensing
cypress.com/go/memory
cypress.com/go/image
cypress.com/go/psoc
cypress.com/go/touch
USB Controllers
Wireless/RF
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2012-2013. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-74847 Rev. *A
Revised May 24, 2013
Page 21 of 21
i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation. All products and company names mentioned in this document
may be the trademarks of their respective holders.