FM28V100 1-Mbit (128 K × 8) F-RAM Memory 1-Mbit (128 K × 8) F-RAM Memory Features ■ 1-Mbit ferroelectric random access memory (F-RAM) logically organized as 128 K × 8 14 ❐ High-endurance 100 trillion (10 ) read/writes ❐ 151-year data retention (see the Data Retention and Endurance table) ❐ NoDelay™ writes ❐ Page mode operation to 30 ns cycle time ❐ Advanced high-reliability ferroelectric process ■ SRAM compatible ❐ Industry-standard 128 K × 8 SRAM pinout ❐ 60-ns access time, 90-ns cycle time ■ Superior to battery-backed SRAM modules ❐ No battery concerns ❐ Monolithic reliability ❐ True surface mount solution, no rework steps ❐ Superior for moisture, shock, and vibration ■ Low power consumption ❐ Active current 7 mA (typ) ❐ Standby current 90 A (typ) ■ Low-voltage operation: VDD = 2.0 V to 3.6 V ■ Industrial temperature: –40 C to +85 C ■ 32-pin thin small outline package (TSOP) Type I ■ Restriction of hazardous substances (RoHS) compliant Functional Overview The FM28V100 is a 128 K × 8 nonvolatile memory that reads and writes similar to a standard SRAM. A ferroelectric random access memory or F-RAM is nonvolatile, which means that data is retained after power is removed. It provides data retention for over 151 years while eliminating the reliability concerns, functional disadvantages, and system design complexities of battery-backed SRAM (BBSRAM). Fast write timing and high write endurance make the F-RAM superior to other types of memory. The FM28V100 operation is similar to that of other RAM devices and therefore, it can be used as a drop-in replacement for a standard SRAM in a system. Read and write cycles may be triggered by chip enable or simply by changing the address. The F-RAM memory is nonvolatile due to its unique ferroelectric memory process. These features make the FM28V100 ideal for nonvolatile memory applications requiring frequent or rapid writes. The device is available in a 32-pin TSOP I surface mount package. Device specifications are guaranteed over the industrial temperature range –40 °C to +85 °C. For a complete list of related documentation, click here. Logic Block Diagram A 2-0 128 K x 8 F-RAM Array ... Row Decoder A 16-3 Address Latch A 16-0 ... CE 1, CE 2 WE OE Column Decoder Control Logic Cypress Semiconductor Corporation Document Number: 001-86202 Rev. *E I/O Latch & Bus Driver • 198 Champion Court • DQ 7-0 San Jose, CA 95134-1709 • 408-943-2600 Revised August 12, 2015 FM28V100 Contents Pinout ................................................................................ 3 Pin Definitions .................................................................. 3 Device Operation .............................................................. 4 Memory Operation ....................................................... 4 Read Operation ........................................................... 4 Write Operation ........................................................... 4 Page Mode Operation ................................................. 4 Pre-charge Operation .................................................. 4 SRAM Drop-In Replacement ....................................... 5 Maximum Ratings ............................................................. 6 Operating Range ............................................................... 6 DC Electrical Characteristics .......................................... 6 Data Retention and Endurance ....................................... 7 Capacitance ...................................................................... 7 Thermal Resistance .......................................................... 7 AC Test Conditions .......................................................... 7 Document Number: 001-86202 Rev. *E AC Switching Characteristics ......................................... 8 SRAM Read Cycle ...................................................... 8 SRAM Write Cycle ....................................................... 9 Power Cycle Timing ....................................................... 12 Functional Truth Table ................................................... 13 Ordering Information ...................................................... 14 Ordering Code Definitions ......................................... 14 Package Diagrams .......................................................... 15 Acronyms ........................................................................ 16 Document Conventions ................................................. 16 Units of Measure ....................................................... 16 Document History Page ................................................. 17 Sales, Solutions, and Legal Information ...................... 18 Worldwide Sales and Design Support ....................... 18 Products .................................................................... 18 PSoC® Solutions ...................................................... 18 Cypress Developer Community ................................. 18 Technical Support ..................................................... 18 Page 2 of 18 FM28V100 Pinout Figure 1. 32-pin TSOP I pinout A11 A9 A8 A13 WE CE2 A15 VDD [1] NC A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 32-pin TSOP I (x 8) Top view (not to scale) OE A10 CE1 DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 Pin Definitions Pin Name I/O Type Description A16–A0 Input Address inputs: The 17 address lines select one of 131,072 bytes in the F-RAM array. The lowest two address lines A2–A0 may be used for page mode read and write operations. DQ7–DQ0 Input/Output Data I/O Lines: 8-bit bidirectional data bus for accessing the F-RAM array. WE Input Write Enable: A write cycle begins when WE is asserted. The rising edge causes the FM28V100 to write the data on the DQ bus to the F-RAM array. The falling edge of WE latches a new column address for page mode write cycles. CE1, CE2 Input Chip Enable: The device is selected and a new memory access begins on the falling edge of CE1 (while CE2 is HIGH) or the rising edge of CE2 (while CE1 is LOW). The entire address is latched internally at this point. The CE2 pin is pulled up internally. Subsequent changes to the A2–A0 address inputs allow page mode operation. OE Input Output Enable: When OE is LOW, the FM28V100 drives the data bus when the valid read data is available. Deasserting OE HIGH tristates the DQ pins. VSS Ground VDD NC Ground for the device. Must be connected to the ground of the system. Power supply Power supply input to the device. No connect No connect. This pin is not connected to the die. Note 1. Reserved for address A17 on 2-Mbit device. Document Number: 001-86202 Rev. *E Page 3 of 18 FM28V100 Device Operation The FM28V100 is a byte-wide F-RAM memory logically organized as 131,072 × 8 and accessed using an industry-standard parallel interface. All data written to the part is immediately nonvolatile with no delay. The device offers page mode operation, which provides high-speed access to addresses within a page (row). Access to a different page requires that either chip enable transitions LOW or the upper address (A16–A3) changes. See the Functional Truth Table on page 13 for a complete description of read and write modes. Memory Operation Users access 131,072 memory locations, each with 8 data bits through a parallel interface. The F-RAM array is organized as 16,384 rows and each row has eight column locations, which allow fast access in page mode operation. When an initial address is latched by the falling edge of CE1 (while CE2 is HIGH), or the rising edge of CE2 (while CE1 is LOW), subsequent column locations may be accessed without the need to toggle chip enable. When chip enable pin is deasserted HIGH, a pre-charge operation begins. Writes occur immediately at the end of the access with no delay. The WE pin must be toggled for each write operation. The write data is stored in the nonvolatile memory array immediately, which is a feature unique to F-RAM called NoDelay writes. Read Operation A read operation begins on the falling edge of CE1 (while CE2 is HIGH), or the rising edge of CE2 (while CE1 is LOW). The chip enable initiated access causes the address to be latched and starts a memory read cycle if WE is HIGH. Data becomes available on the bus after the access time is met. When the address is latched and the access completed, a new access to a random location (different row) may begin while both chip enables are still active. The minimum cycle time for random addresses is tRC. Note that unlike SRAMs, the FM28V100's chip enable-initiated access time is faster than the address access time. The FM28V100 will drive the data bus when OE is asserted LOW and the memory access time is met. If OE is asserted after the memory access time is met, the data bus will be driven with valid data. If OE is asserted before completing the memory access, the data bus will not be driven until valid data is available. This feature minimizes supply current in the system by eliminating transients caused by invalid data being driven to the bus. When OE is deasserted HIGH, the data bus will remain in a HI-Z state. Write Operation In the FM28V100, writes occur in the same interval as reads. The FM28V100 supports both chip enable and WE controlled write cycles. In both cases, the address is latched on the falling edge of CE1 (while CE2 is HIGH), or the rising edge of CE2 (while CE1 is LOW). In a chip enable-controlled write, the WE signal is asserted before beginning the memory cycle. That is, WE is LOW when Document Number: 001-86202 Rev. *E the device is activated with the chip enable. In this case, the device begins the memory cycle as a write. The FM28V100 will not drive the data bus regardless of the state of OE as long as WE is LOW. Input data must be valid when the device is deselected with a chip enable. In a WE-controlled write, the memory cycle begins when the device is activated with a chip enable. The WE signal falls some time later. Therefore, the memory cycle begins as a read. The data bus will be driven if OE is LOW; however, it will be HI-Z when WE is asserted LOW. The chip enable and WE controlled write timing cases are shown in the page 11. In the Figure 8 on page 11 diagram, the data bus is shown as a HI-Z condition while the chip is write-enabled and before the required setup time. Although this is drawn to look like a mid-level voltage, it is recommended that all DQ pins comply with the minimum VIH/VIL operating levels. Write access to the array begins on the falling edge of WE after the memory cycle is initiated. The write access terminates on the deassertion of WE or CE1 or CE2, whichever comes first. A valid write operation requires the user to meet the access time specification before deasserting WE or chip enable. The data setup time indicates the interval during which data cannot change before the end of the write access. Unlike other nonvolatile memory technologies, there is no write delay with F-RAM. Because the read and write access times of the underlying memory are the same, the user experiences no delay through the bus. The entire memory operation occurs in a single bus cycle. Data polling, a technique used with EEPROMs to determine if a write is complete, is unnecessary. Page Mode Operation The FM28V100 provides the user fast access to any data within a row element. Each row has eight column-address locations (bytes). Address inputs A2–A0 define the column address to be accessed. An access can start anywhere within a row and other column locations may be accessed without the need to toggle the chip enable pins. For fast access reads, after the first data byte is driven to the bus, the column address inputs A2–A0 may be changed to a new value. A new data byte is then driven to the DQ pins. For fast access writes, the first write pulse defines the first write access. While the device is selected (both chip enables asserted), a subsequent write pulse along with a new column address provides a page mode write access. Pre-charge Operation The pre-charge operation is an internal condition in which the memory state is prepared for a new access. Pre-charge is user-initiated by driving at least one of the chip enable signals to an inactive state. The chip enable must remain inactive at least the minimum pre-charge time, tPC. Pre-charge is also activated by changing the upper addresses, A16–A3. The current row is first closed before accessing the new row. The device automatically detects an upper order address change, which starts a pre-charge operation. The new address is latched and the new read data is valid within the tAA address access time; see Figure 4 on page 10. A similar sequence occurs for write cycles; see Figure 9 on page 11. The rate at which Page 4 of 18 FM28V100 random addresses can be issued is tRC and tWC, respectively. SRAM Drop-In Replacement The FM28V100 is designed to be a drop-in replacement for standard asynchronous SRAMs. The device does not require chip enable pins to toggle for each new address. Both chip enable pins may remain active indefinitely while VDD is applied. When both chip enable pins are active, the device automatically detects address changes and a new access begins. It also allows page mode operation at speeds up to 33 MHz. A typical application is shown in Figure 2. It shows a pull-up resistor on CE1, which will keep the pin HIGH during power cycles, assuming the MCU / MPU pin tristates during the reset condition.The pull-up resistor value should be chosen to ensure the CE1 pin tracks VDD to a high enough value, so that the current drawn when CE1 is LOW is not an issue. Although not required, it is recommended that CE2 be tied to VDD if the controller provides an active-low chip enable. A 10-k resistor draws 330 µA when CE1 is LOW and VDD = 3.3 V. Figure 2. Use of Pull-up Resistor on CE1 VDD FM28V100 CE2 CE1 WE MCU / MPU OE A 16-0 Note that if CE1 is tied to ground and CE2 tied to VDD, the user must be sure WE is not LOW at power-up or power-down events. If the chip is enabled and WE is LOW during power cycles, data will be corrupted. Figure 3 shows a pull-up resistor on WE, which will keep the pin HIGH during power cycles, assuming the MCU/MPU pin tristates during the reset condition.The pull-up resistor value should be chosen to ensure the WE pin tracks VDD to a high enough value, so that the current drawn when WE is LOW is not an issue. A 10-k resistor draws 330 µA when WE is LOW and VDD = 3.3 V. Figure 3. Use of Pull-up Resistor on WE VDD FM28V100 CE2 CE1 WE MCU / MPU OE A 16-0 DQ 7-0 For applications that require the lowest power consumption, the chip enable signal should be active only during memory accesses. Due to the external pull-up resistor, some supply current will be drawn while CE1 is LOW. When CE1 is HIGH, the device draws no more than the maximum standby current ISB. DQ 7-0 Document Number: 001-86202 Rev. *E Page 5 of 18 FM28V100 Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested. Storage temperature ................................ –55 C to +125 C Maximum accumulated storage time At 125 °C ambient temperature ................................. 1000 h At 85 °C ambient temperature ................................ 10 Years Package power dissipation capability (TA = 25 °C) ................................................. 1.0 W Surface mount Pb soldering temperature (3 seconds) ......................................... +260 C DC output current (1 output at a time, 1s duration) .... 15 mA Static discharge voltage Human Body Model (AEC-Q100-002 Rev. E) ............ 2 kV Charged Device Model (AEC-Q100-011 Rev. B) .. 1.25 kV Ambient temperature with power applied ................................... –55 °C to +125 °C Machine Model (AEC-Q100-003 Rev. E) ................. 200 V Supply voltage on VDD relative to VSS ........–1.0 V to + 4.5 V Latch-up current ................................................... > 140 mA Voltage applied to outputs in High Z state .................................... –0.5 V to VDD + 0.5 V Operating Range Input voltage .......... –1.0 V to + 4.5 V and VIN < VDD + 1.0 V Transient voltage (< 20 ns) on any pin to ground potential ................. –2.0 V to VCC + 2.0 V Range Industrial Ambient Temperature (TA) VDD –40 C to +85 C 2.0 V to 3.6 V DC Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min Typ [2] Max Unit 2.0 3.3 3.6 V VDD Power supply voltage IDD VDD supply current VDD = 3.6 V, chip enable cycling at min. cycle time. All inputs toggling at CMOS levels (0.2 V or VDD – 0.2 V), all DQ pins unloaded. – 7 12 mA ISB Standby current VDD = 3.6 V, CE1 at VDD or CE2 at VSS, All other pins are static and at CMOS levels (0.2 V or VDD – 0.2 V) – 90 150 µA ILI Input leakage current VIN between VDD and VSS – – +1 µA ILO Output leakage current VOUT between VDD and VSS – – +1 µA VIH Input HIGH voltage 0.7 × VDD – VDD + 0.3 V VIL Input LOW voltage – 0.3 – 0.3 × VDD V VOH1 Output HIGH voltage IOH = –1.0 mA, VDD > 2.7 V 2.4 – – V VOH2 Output HIGH voltage IOH = –100 µA VDD – 0.2 – – V VOL1 Output LOW voltage IOL = 2 mA, VDD > 2.7 V – – 0.4 V VOL2 Output LOW voltage IOL = 150 µA – – 0.2 V 40 – – k 1 – – M RIN [3] Address input resistance For VIN = VIH(min) (CE2) For VIN = VIL(max) Note 2. Typical values are at 25 °C, VDD = VDD (typ). Not 100% tested. 3. The input pull-up circuit is strong (> 40 k) when the input voltage is above VIH and weak (> 1 M) when the input voltage is below VIL. Document Number: 001-86202 Rev. *E Page 6 of 18 FM28V100 Data Retention and Endurance Parameter TDR NVC Description Data retention Endurance Test condition At +85 C Min Max Unit 10 – Years At +75 C 38 – At +65 C 151 – Over operating temperature 1014 – Cycles Max Unit 8 pF 6 pF Capacitance Parameter Description CI/O Input/Output capacitance (DQ) CIN Input capacitance Test Conditions TA = 25 C, f = 1 MHz, VDD = VDD(Typ) Thermal Resistance Description Parameter JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) Test Conditions 32-pin TSOP I Unit Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51. 80 C/W 21 C/W AC Test Conditions Input pulse levels ...................................................0 V to 3 V Input rise and fall times (10%–90%) ........................... < 3 ns Input and output timing reference levels ....................... 1.5 V Output load capacitance ............................................... 30 pF Document Number: 001-86202 Rev. *E Page 7 of 18 FM28V100 AC Switching Characteristics Over the Operating Range Parameters [4] Cypress Parameter VDD = 2.0 V to 2.7 V Description Alt Parameter VDD = 2.7 V to 3.6 V Unit Min Max Min Max – 70 – 60 ns 105 – 90 – ns SRAM Read Cycle tCE tACE Chip enable access time tRC – Read cycle time tAA – Address access time – 105 – 90 ns tOH tOHA Output hold time 20 – 20 – ns tAAP – Page mode address access time – 40 – 30 ns tOHP – Page mode output hold time 3 – 3 – ns tCA – Chip enable active time 70 – 60 – ns tPC – Pre-charge time 35 – 30 – ns tAS tSA Address setup time (to CE1, CE2 active) 0 – 0 – ns tAH tHA Address hold time (Chip Enable Controlled) 70 – 60 – ns tOE tDOE Output enable access time – 25 – 15 ns tHZ[5, 6] tHZCE Chip Enable to output HI-Z – 10 – 10 ns tOHZ[5, 6] tHZOE Output enable HIGH to output HI-Z – 10 – 10 ns Notes 4. Test conditions assume a signal transition time of 3 ns or less, timing reference levels of 0.5 × VDD, input pulse levels of 0 to 3 V, output loading of the specified IOL/IOH and load capacitance shown in AC Test Conditions on page 7. 5. tHZ and tOHZ are specified with a load capacitance of 5 pF. Transition is measured when the outputs enter a high impedance state. 6. This parameter is characterized but not 100% tested. Document Number: 001-86202 Rev. *E Page 8 of 18 FM28V100 AC Switching Characteristics (continued) Over the Operating Range Parameters [4] Cypress Parameter VDD = 2.0 V to 2.7 V Description Alt Parameter VDD = 2.7 V to 3.6 V Min Max Min Max Unit SRAM Write Cycle tWC tWC Write cycle time 105 – 90 – ns tCA – Chip enable active time 70 – 60 – ns tCW tSCE Chip enable to write enable HIGH 70 – 60 – ns tPC – Pre-charge time 35 – 30 – ns tPWC – Page mode write enable cycle time 40 – 30 – ns tWP tPWE Write enable pulse width 22 – 18 – ns tAS tSA Address setup time (to CE1, CE2 active) 0 – 0 – ns tAH tHA Address hold time (Chip Enable Controlled) 70 – 60 – ns tASP – Page mode address setup time (to WE LOW) 8 – 5 – ns tAHP – Page mode address hold time (to WE LOW) 20 – 15 – ns tWLC tPWE Write enable LOW to chip disabled 30 – 25 – ns tWLA – Write enable LOW to A16-3 change 30 – 25 – ns tAWH – A16-3 change to write enable HIGH 105 – 90 – ns tDS tSD Data input setup time 20 – 15 – ns tDH tHD Data input hold time 0 – 0 – ns tWZ[7, 8] tHZWE Write enable LOW to output HI-Z – 10 – 10 ns tWX[8] – Write enable HIGH to output driven 5 – 5 – ns tWS[8, 9] – Write enable to CE LOW setup time 0 – 0 – ns [8, 9] – Write enable to CE HIGH hold time 0 – 0 – ns tWH Notes 7. tWZ is specified with a load capacitance of 5 pF. Transition is measured when the outputs enter a high impedance state. 8. This parameter is characterized but not 100% tested. 9. The relationship between CE (falling edge of CE1 (while CE2 is HIGH), or the rising edge of CE2 (while CE1 is LOW) and WE determines if a chip enable or WE controlled write occurs. Document Number: 001-86202 Rev. *E Page 9 of 18 FM28V100 Figure 4. Read Cycle Timing 1 (CE1 LOW, CE2 HIGH, OE LOW) tRC A 16-0 tAA tOH DQ 7-0 tOH Previous Data Valid Data Figure 5. Read Cycle Timing 2 (Chip Enable Controlled) tCA tPC CE1 CE2 tAH tAS A16-0 tHZ tOE OE tOHZ tCE D out DQ 7-0 Figure 6. Page Mode Read Cycle Timing [10] tPC tCA CE1 CE2 tAS A16-3 A 2-0 Col 0 Col 1 tAAP tOE OE tHZ tOHP tCE DQ 7-0 Col 2 Data 0 tOHZ Data 1 Data 2 Note 10. Although sequential column addressing is shown, it is not required Document Number: 001-86202 Rev. *E Page 10 of 18 FM28V100 Figure 7. Write Cycle Timing 1 (WE Controlled) [11] tCA tPC tCW CE1 CE2 tWLC tAS A16-0 tWP tWX WE tDH tWZ DQ 7-0 tHZ ttDS DS D out D out D in Figure 8. Write Cycle Timing 2 (CE Controlled) tPC tCA CE1 CE2 tAS tAH A16-0 tWH WE tWS tDS DQ 7-0 tDH D in Figure 9. Write Cycle Timing 3 (CE1 LOW, CE2 HIGH) [11] tWC tAWH A 16-0 tWLA WE tWZ DQ 7-0 D out tDH tWX tDS D in D out D in Note 11. OE (not shown) is LOW only to show the effect of WE on DQ pins. Document Number: 001-86202 Rev. *E Page 11 of 18 FM28V100 Figure 10. Page Mode Write Cycle Timing tCA tPC tCW CE1 CE2 tWLC tAS A16-3 tAH A 2-0 tASP tAHP Col 0 Col 1 Col 2 tPWC tWP WE OE tDH tDS DQ 7-0 Data 0 Data 1 Data 2 Power Cycle Timing Over the Operating Range Parameter Description Min Max Unit 250 – µs tPU Power-up (after VDD min. is reached) to first access time tPD Last write (WE HIGH) to power down time 0 – µs tVR[12] VDD power-up ramp rate 50 – µs/V tVF[12] VDD power-down ramp rate 100 – µs/V Figure 11. Power Cycle Timing VDD VDD min VDD min t VR t VF t PU t PD Access Allowed Note 12. Slope measured at any point on the VDD waveform. Document Number: 001-86202 Rev. *E Page 12 of 18 FM28V100 Functional Truth Table Operation [13, 14] CE1 CE2 WE A16-A3 A2-A0 H X X X X X L X X X ↓ H ↑ H H V V V V L H H No Change Change L H H Change V Random Read ↓ H ↑ L L V V V V Chip Enable -Controlled Write[14] L H ↓ V V WE-Controlled Write [14, 15] L H ↓ No Change V Page Mode Write [16] ↑ H X X X X X X Starts pre-charge L L L ↓ Standby/Idle Read Page Mode Read Notes 13. H = Logic HIGH, L = Logic LOW, V = Valid Data, X = Don't Care, ↓ = toggle LOW, ↑ = toggle HIGH. 14. For write cycles, data-in is latched on the rising edge of CE1 or WE of the falling edge of CE2, whichever comes first. 15. WE-controlled write cycle begins as a Read cycle and then A16-A3 is latched. 16. Addresses A2-A0 must remain stable for at least 15 ns during page mode operation. Document Number: 001-86202 Rev. *E Page 13 of 18 FM28V100 Ordering Information Package Diagram Ordering Code FM28V100-TG 001-91156 32-pin TSOP I FM28V100-TGTR 001-91156 32-pin TSOP I Package Type Operating Range Industrial All the above parts are Pb-free. Ordering Code Definitions FM 28 V 100 - TG TR Option: blank = Standard; TR = Tape and Reel Package Type: TG = 32-pin TSOP I Density: 100 = 1-Mbit Voltage: V = 2.0 V to 3.6 V Parallel F-RAM Cypress Document Number: 001-86202 Rev. *E Page 14 of 18 FM28V100 Package Diagrams Figure 12. 32-pin TSOP I Package Outline, 001-91156 001-91156 ** Document Number: 001-86202 Rev. *E Page 15 of 18 FM28V100 Acronyms Acronym Document Conventions Description Units of Measure CPU Central Processing Unit CMOS Complementary Metal Oxide Semiconductor °C degree Celsius JEDEC Joint Electron Devices Engineering Council Hz hertz JESD JEDEC Standards kHz kilohertz EIA Electronic Industries Alliance k kiloohm F-RAM Ferroelectric Random Access Memory Mb megabit I/O Input/Output MHz megahertz MCU Microcontroller Unit A microampere MPU Microprocessor Unit F microfarad RoHS Restriction of Hazardous Substances s microsecond R/W Read and Write mA milliampere SRAM Static Random Access Memory ms millisecond M megaohm TSOP Thin Small Outline Package ns nanosecond ohm % percent pF picofarad V volt W watt Document Number: 001-86202 Rev. *E Symbol Unit of Measure Page 16 of 18 FM28V100 Document History Page Document Title: FM28V100, 1-Mbit (128 K × 8) F-RAM Memory Document Number: 001-86202 Rev. ECN No. Orig. of Change Submission Date ** 3912933 GVCH 02/25/2013 New data sheet. *A 4191946 GVCH 11/14/2013 Added watermark as “Not recommended for new designs.” *B 4274812 GVCH 03/11/2014 Converted to Cypress standard format Updated Maximum Ratings table - Removed Moisture Sensitivity Level (MSL) - Added junction temperature and latch up current Updated Data Retention and Endurance table Added Thermal Resistance table Removed Package Marking Scheme (top mark) *C 4481463 GVCH 08/22/2014 Removed watermark as “Not recommended for new designs.” *D 4579647 GVCH 11/25/2014 Added related documentation hyperlink in page 1. *E 4881722 ZSK / PSR 08/12/2015 Updated Maximum Ratings: Removed “Maximum junction temperature”. Added “Maximum accumulated storage time”. Added “Ambient temperature with power applied”. Updated to new template. Document Number: 001-86202 Rev. *E Description of Change Page 17 of 18 FM28V100 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory PSoC Touch Sensing cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/memory cypress.com/go/psoc cypress.com/go/touch USB Controllers Wireless/RF psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2013-2015. The information contained herein is subject to change without notice. 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Document Number: 001-86202 Rev. *E Revised August 12, 2015 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 18 of 18