MM54C174/MM74C174 Hex D Flip-Flop General Description Features The MM54C174/MM74C174 hex D flip-flop is a monolithic complementary MOS (CMOS) integrated circuit constructed with N- and P-channel enhancement transistors. All have a direct clear input. Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clear is independent of clock and accomplished by a low level at the clear input. All inputs are protected by diodes to VCC and GND. Y Y Y Y Wide supply voltage range Guaranteed noise margin High noise immunity Low power TTL compatibility 3.0V to 15V 1.0V 0.45 VCC (typ.) Fan out of 2 driving 74L Logic and Connection Diagrams TL/F/5899 – 2 TL/F/5899 – 1 TL/F/5899 – 3 Truth Table Dual-In-Line Package Inputs Output Clear Clock D Q L H H H X X H L X L H L Q u u L TL/F/5899 – 4 Top View Order Number MM54C174 or MM74C174 C1995 National Semiconductor Corporation TL/F/5899 RRD-B30M105/Printed in U. S. A. MM54C174/MM74C174 Hex D Flip-Flop February 1988 Absolute Maximum Ratings (Note 1) Voltage at Any Pin b 0.3V to VCC a 0.3V Operating Temperature Range MM54C174 MM74C174 b 65§ C to a 150§ C Storage Temperature Range Power Dissipation (PD) Dual-In-Line Small Outline Operating VCC Range If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. b 55§ C to a 125§ C b 40§ C to a 85§ C 700 mW 500 mW Absolute Maximum VCC Lead Temperature (Soldering, 10 sec.) 3.0V to 15V 18V 260§ C DC Electrical Characteristics Min/Max limits apply across temperature range unless otherwise specified Symbol Parameter Conditions Min Typ Max Units CMOS TO CMOS VIN(1) Logical ‘‘1’’ Input Voltage VCC e 5V VCC e 10V 3.5 8.0 VIN(0) Logical ‘‘0’’ Input Voltage VCC e 5V VCC e 10V VOUT(1) Logical ‘‘1’’ Output Voltage VCC e 5V, IO e b10 mA VCC e 10V, IO e b10 mA VOUT(0) Logical ‘‘0’’ Output Voltage VCC e 5V, IO e 10 mA VCC e 10V, IO e 10 mA IIN(1) Logical ‘‘1’’ Input Current VCC e 15V, VIN e 15V IIN(0) Logical ‘‘0’’ Input Current VCC e 15V, VIN e 0V ICC Supply Current VCC e 15V V V 1.5 2.0 4.5 9.0 V V 0.005 b 1.0 V V 0.5 1.0 V V 1.0 mA b 0.005 0.05 mA 300 mA CMOS/LPTTL INTERFACE VIN(1) Logical ‘‘1’’ Input Voltage 54C, VCC e 4.5V 74C, VCC e 4.75V VIN(0) Logical ‘‘0’’ Input Voltage 54C, VCC e 4.5V 74C, VCC e 4.75V VOUT(1) Logical ‘‘1’’ Output Voltage 54C, VCC e 4.5V, IO e b360 mA 74C, VCC e 4.75V, IO e b360 mA VOUT(0) Logical ‘‘0’’ Output Voltage 54C, VCC e 4.5V, IO e 360 mA 74C, VCC e 4.75V, IO e 360 mA VCCb1.5 VCCb1.5 V V 0.8 0.8 2.4 2.4 V V V V 0.4 0.4 V V OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sheet) (short circuit current) ISOURCE Output Source Current (P-Channel) VCC e 5V TA e 25§ C, VOUT e 0V b 1.75 ISOURCE Output Source Current (P-Channel) VCC e 10V TA e 25§ C, VOUT e 0V b 8.0 ISINK Output Sink Current (N-Channel) VCC e 5V TA e 25§ C, VOUT e 0V ISINK Output Sink Current (N-Channel) VCC e 5V TA e 25§ C, VOUT e 0V b 3.3 mA b 15 mA 1.75 3.6 mA 8.0 16 mA Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation. 2 AC Electrical Characteristics* TA e 25§ C, CL e 50 pF, unless otherwise noted Typ Max Units tpd Symbol Propagation Delay Time to a Logical ‘‘0’’ or Logical ‘‘1’’ from Clock to Q Parameter VCC e 5V VCC e 10V Conditions Min 150 70 300 110 ns ns tpd Propagation Delay Time to a Logical ‘‘0’’ from Clear VCC e 5V VCC e 10V 110 50 300 110 ns ns tS1, tS0 Time Prior to Clock Pulse that Data Must be Present VCC e 5V VCC e 10V 75 25 tH1, tH0 Time after Clock Pulse that Data Must be Held VCC e 5V VCC e 10V 0 0 tW Minimum Clock Pulse Width VCC e 5V VCC e 10V 50 35 250 100 ns ns tW Minimum Clear Pulse Width VCC e 5V VCC e 10V 65 35 140 70 ns ns tr, tf Maximum Clock Rise and Fall Time VCC e 5V VCC e 10V 15 5.0 l 1200 l 1200 ms ms fMAX Maximum Clock Frequency VCC e 5V VCC e 10V 2.0 5.0 6.5 12 MHz MHz CIN Input Capacitance Clear Input (Note 2) Any Other Input 11 5.0 pF pF CPD Power Dissipation Capacitance Per Package (Note 3) 95 pF ns ns b 10 b 5.0 ns ns *AC Parameters are guaranteed by DC correlated testing. Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation. Note 2: Capacitance is guaranteed by periodic testing. Note 3: CPD determines the no load AC power consumption of any CMOS device. For complete explanation see 54C/74C Family Characteristics Application Note AN-90. Switching Time Waveforms AC Test Circuit CMOS to CMOS TL/F/5899 – 6 TL/F/5899 – 5 tr e tf e 20 ns 3 MM54C174/MM74C174 Hex D Flip-Flop Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number MM54C174J or MM74C174J NS Package Number J16A Molded Dual-In-Line Package (N) Order Number MM54C174N or MM74C174N NS Package Number N16E LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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