MM54C906/MM74C906 Hex Open Drain N-Channel Buffers MM54C907/MM74C907 Hex Open Drain P-Channel Buffers General Description Features These buffers employ monolithic CMOS technology in achieving open drain outputs. The MM54C906/MM74C906 consists of six inverters driving six N-channel devices; and the MM54C907/MM74C907 consists of six inverters driving six P-channel devices. The open drain feature of these buffers makes level shifting or wire AND and wire OR functions by just the addition of pull-up or pull-down resistors. All inputs are protected from static discharge by diode clamps to VCC and to ground. Y Y Y Y Wide supply voltage range Guaranteed noise margin High noise immunity High current sourcing and sinking open drain outputs 3V to 15V 1V 0.45 VCC (typ.) Connection and Logic Diagrams Dual-In-Line Package TL/F/5911 – 1 Top View Order Number MM54C906, MM54C907, MM74C906 or MM74C907 MM54C907/MM74C907 MM54C906/MM74C906 TL/F/5911 – 2 TL/F/5911 – 3 C1995 National Semiconductor Corporation TL/F/5911 RRD-B30M105/Printed in U. S. A. MM54C906/MM74C906 Hex Open Drain N-Channel Buffers MM54C907/MM74C907 Hex Open Drain P-Channel Buffers March 1988 Absolute Maximum Ratings (Note 1) Storage Temperature Range If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Voltage at Any Input Pin Voltage at Any Output Pin MM54C906/MM74C906 MM54C907/MM74C907 b 0.3V to VCC a 0.3V b 0.3V to a 18V VCC b 18 to VCC a 0.3V Operating Temperature Range MM54C906/MM54C907 MM74C906/MM74C907 b 65§ C to a 150§ C Power Dissipation Dual-In-Line Small Outline Operating VCC Range 700 mW 500 mW 3V to 15V 18V Absolute Maximum VCC Lead Temperature (TL) (Soldering, 10 seconds) b 55§ C to a 125§ C b 40§ C to a 85§ C 260§ C DC Electrical Characteristics Min/Max limits apply across temperature range unless otherwise noted Symbol Parameter Conditions Min Typ Max Units CMOS TO CMOS VIN(1) Logical ‘‘1’’ Input Voltage VCC e 5V VCC e 10V VIN(0) Logical ‘‘0’’ Input Voltage VCC e 5V VCC e 10V IIN(1) Logical ‘‘1’’ Input Current VCC e 15V, VIN e 15V IIN(0) Logical ‘‘0’’ Input Current ICC Supply Current VCC e 15V, VIN e 0V VCC e 15V, Output Open Output Leakage MM54C906 MM74C906 MM54C907 MM74C907 3.5 8.0 V V 1.5 2 0.005 b 1.0 VCC e 4.5V, VIN e VCC b 1.5V VCC e 4.5V, VOUT e 18V VCC e 4.75V, VIN e VCC b 1.5V VCC e 4.75V, VOUT e 18V VCC e 4.5V, VIN e 1V a 0.1 VCC VCC e 4.5V, VOUT e VCC b18V VCC e 4.75V, VIN e 1V a 0.1 VCC VCC e 4.75V, VOUT e VCC b18V 1 b 0.005 V V mA mA 0.05 15 mA 0.005 5 mA 0.005 5 mA 0.005 5 mA 0.005 5 mA CMOS/LPTTL INTERFACE VIN(1) Logical ‘‘1’’ Input Voltage 54C, VCC e 4.5V 74C, VCC e 4.75V VIN(0) Logical ‘‘0’’ Input Voltage 54C, VCC e 4.5V 74C, VCC e 4.75V VCC b 1.5V VCC b 1.5V V V 0.8 0.8 V V OUTPUT DRIVE CURRENT MM54C906 MM74C906 MM54C907 MM74C907 MM54C906/MM74C906 MM54C907/MM74C907 VCC e 4.5V, VIN e 1V a 0.1 VCC VCC e 4.5V, VOUT e 0.5V VCC e 4.5V, VOUT e 1.0V 2.1 4.2 8.0 12.0 mA mA VCC e 4.75V, VIN e 1V a 0.1 VCC VCC e 4.75V, VOUT e 0.5V VCC e 4.75V, VOUT e 1.0V 2.1 4.2 8.0 12.0 mA mA VCC e 4.5V, VIN e VCC b1.5V VCC e 4.5V, VOUT e VCC b 0.5V VCC e 4.5V, VOUT e VCC b 1V b 1.05 b 2.1 b 1.5 b 3.0 mA mA VCC e 4.75V, VIN e VCC b1.5V VCC e 4.75V, VOUT e VCC b 0.5V VCC e 4.75V, VOUT e VCC b 1V b 1.05 b 2.1 b 1.5 b 3.0 mA mA VCC e 10V, VIN e 2V VCC e 10V, VOUT e 0.5V VCC e 10V, VOUT e 1V 4.2 8.4 b 20 b 30 mA mA VCC e 10V, VIN e 8V VCC e 10V, VOUT e 9.5V VCC e 10V, VOUT e 9V b 2.1 b 4.2 b 4.0 b 8.0 mA mA 2 AC Electrical Characteristics* TA e 25§ C, CL e 50 pF, unless otherwise specified Symbol tpd Parameter Propagation Delay Time to a Logical ‘‘0’’ MM54C906/MM74C906 MM54C907/MM74C907 tpd Propagation Delay Time to a Logical ‘‘1’’ MM54C906/MM74C906 MM54C907/MM74C907 Conditions Min Typ Max Units VCC VCC VCC VCC e 5.0V, R e 10k e 10V, R e 10k e 5.0V (Note 4) e 10V (Note 4) 150 75 150 a 0.7 RC 75 a 0.7 RC ns ns ns ns VCC VCC VCC VCC e e e e 5.0V (Note 4) 10V (Note 4) 5.0V, R e 10k 10V, R e 10k 150 a 0.7 RC 75 a 0.7 RC 150 75 ns ns ns ns CIN Input Capacitance (Note 2) 5.0 pF COUT Output Capacity (Note 2) 20 pF CPD Power Dissipation Capacity (Note 3) Per Buffer 30 pF *AC Parameters are guaranteed by DC correlated testing. Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation. Note 2: Capacitance is guaranteed by periodic testing. Note 3: CPD determines the no load AC power consumption of any CMOS device. For complete explanation see 54C/74C Family Characteristics Application Note, AN-90. (Assumes outputs are open). Note 4: ‘‘C’’ used in calculating propagation includes output load capacity (CL) plus device output capacity (COUT). Typical Applications Wire OR Gate Wire AND Gate TL/F/5911 – 5 TL/F/5911 – 4 Note: Can be extended to more than 2 inputs. Note: Can be extended to more than 2 inputs. CMOS or TTL to PMOS Interface Note: VCC a VDD s 18V VCC s 15V CMOS or TTL to CMOS at a Higher VCC TL/F/5911 – 7 TL/F/5911 – 6 3 MM54C906/MM74C906 Hex Open Drain N-Channel Buffers MM54C907/MM74C907 Hex Open Drain P-Channel Buffers Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number MM54C906J, MM54C907J, MM74C906J, MM74C907J NS Package Number J14A Molded Dual-In-Line Package (N) Order Number MM54C906N, MM54C907N, MM74C906N or MM74C907N NS Package Number N14A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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