PHILIPS NE56632-43D

INTEGRATED CIRCUITS
NE56632-XX
Active-LOW system reset
with adjustable delay time
Product data
2002 Mar 25
Philips Semiconductors
Product data
Active-LOW system reset with adjustable delay time
NE56632-XX
DESCRIPTION
The NE56632-XX is a family of Active-LOW, power-on reset that
offers precision threshold voltage detection within ±1.5% and super
low operating supply current of typically 3.0 µA. It includes a reset
delay that is user adjustable with an external capacitor.
Several detection threshold voltages are available at 1.9V , 2.0 V,
2.7 V, 2.8 V, 2.9 V, 3.0 V, 3.1 V, 4.2 V, 4.3 V, 4.4 V, 4.5 V, and 4.6 V.
Other thresholds are offered upon request at 100 mV steps from
1.9 V to 4.6 V.
With its ultra low supply current and high precision voltage threshold
detection capability, the NE56632-XX is well suited for various
battery powered applications such as reset circuits for logic and
microprocessors, voltage check, and level detecting. It is available in
the SOT23-5 package.
FEATURES
APPLICATIONS
• High precision threshold detection voltage: VS ±1.5%
• Super low operating supply current: 3 µA typ.
• Built-in hysteresis voltage: 50 mV typ.
• Detection threshold voltage: 1.9 V, 2.0 V, 2.7 V, 2.8 V, 2.9 V,
• Reset for microprocessor and logic circuits
• Voltage level detection circuit
• Battery voltage check circuit
• Detection circuit for battery back-up
3.0 V, 3.1 V, 4.2 V, 4.3 V, 4.4 V, 4.5 V, and 4.6 V.
• Reset Output: Active-LOW, open collector
• Other detection threshold voltages available upon request at
100 mV steps from 1.9 V to 4.6 V.
• Large low reset output current: 30 mA typ.
• Power-on reset delay time adjustable with external capacitor:
200 µs to 200 ms
• Reset assertion with VCC down to 0.65 V
SIMPLIFIED SYSTEM DIAGRAM
TO VCC
TO RESET
TERMINAL
OF CPU
RPU
5
4
NE56632-XX
1
2
3
CD
SL01605
Figure 1. Simplified system diagram.
2002 Mar 25
2
853–2329 27919
Philips Semiconductors
Product data
Active-LOW system reset with adjustable delay time
NE56632-XX
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NE56632-XXD
TEMPERATURE
RANGE
NAME
DESCRIPTION
SOT23-5 / SOT25 (SO5)
plastic small outline package; 5 leads (see dimensional drawing)
NOTE:
The device has 12 voltage output options, indicated by the XX on
the ‘Type number’.
–20 to +75 °C
Part number marking
The package is marked with a four letter code. The first three letters
designate the product. The fourth letter, represented by ‘x’, is a date
tracking code.
XX
VOLTAGE (Typical)
19
1.9 V
Part Number
Marking
20
2.0 V
NE56632-19D
AKZx
27
2.7 V
NE56632-20D
ALAx
NE56632-27D
ALBx
NE56632-28D
ALCx
NE56632-29D
ALDx
NE56632-30D
ALEx
NE56632-31D
ALFx
NE56632-42D
ALGx
28
2.8 V
29
2.9 V
30
3.0 V
31
3.1 V
42
4.2 V
43
4.3 V
NE56632-43D
ALHx
44
4.4 V
NE56632-44D
ALJx
45
4.5 V
NE56632-45D
ALKx
46
4.6 V
NE56632-46D
ALLx
PIN CONFIGURATION
PIN DESCRIPTION
PIN
TC
1
SUB
2
GND
5
VCC
NE56632-XX
3
4
VOUT
SL01604
SYMBOL
DESCRIPTION
1
TC
Delay time control; set with external
capacitor.
2
SUB
Substrate. Connect to ground (GND).
3
GND
Ground. Negative supply.
4
VOUT
Reset output voltage. Active-LOW.
5
VCC
Positive supply voltage; detection threshold
voltage input.
Figure 2. Pin configuration.
MAXIMUM RATINGS
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
VCC
Supply voltage
–0.3
+10
V
Tamb
Ambient operating temperature
–20
+75
°C
Tstg
Storage temperature
–40
+125
°C
P
Power dissipation
–
150
mW
2002 Mar 25
3
Philips Semiconductors
Product data
Active-LOW system reset with adjustable delay time
NE56632-XX
ELECTRICAL CHARACTERISTICS
Tamb = 25 °C, unless otherwise specified.
SYMBOL
VS
PARAMETER
Detection threshold
CONDITIONS
-XX
MIN.
TYP.
MAX.
UNIT
VCC = HIGH-to-LOW; RL = 4.7 kΩ; S1=ON;
VOL ≤ 0.4
0 4 V;
V
Test Circuit 1 (Figure 27)
46
4.531
4.600
4.669
V
45
4.432
4.500
4.568
V
44
4.334
4.400
4.466
V
43
4.235
4.300
4.365
V
42
4.137
4.200
4.263
V
31
3.053
3.100
3.147
V
30
2.955
3.000
3.045
V
29
2.856
2.900
2.944
V
28
2.758
2.800
2.842
V
27
2.659
2.700
2.741
V
20
1.970
2.000
2.030
V
19
1.871
1.900
1.929
V
RL = 4.7 kΩ; VCC = LOW-to-HIGH-to-LOW; S1 = ON; Test
Circuit 1 (Figure 27)
25
50
100
mV
Vhys
Hysteresis voltage
VS/∆T
Detection threshold voltage
temperature coefficient
RL = 4.7 kΩ; Tamb = –20 °C to +75 °C; S1 = ON;
Test Circuit 1 (Figure 27)
–
±0.01
–
%/°C
VOL
LOW-level output voltage
VCC1 = VS(min) – 0.05 V; RL = 4.7 kΩ; S1 = ON;
Test Circuit 1 (Figure 27)
–
0.2
0.4
V
ILO
Output leakage current
VCC1 = VCC2 = 10 V; S2 = ON; Test Circuit 1 (Figure 27)
–
–
±0.1
µA
ICCL
Supply current (ON time)
VCC1 = VS(min) – 0.05 V; RL = ∞; Test Circuit 1 (Figure 27)
–
5.0
9.0
µA
ICCH
Supply current (OFF time)
VCC1 = VS(typ)/0.85; RL = ∞; Test Circuit 1 (Figure 27)
–
3.0
5.0
µA
tPLH
LOW-to-HIGH delay time
CL = 100 pF; RL = 4.7 kΩ; CD = 10 nF (Note 1)
–
(Note 3)
–
ms
tPHL
HIGH-to-LOW delay time
CL = 100 pF; RL = 4.7 kΩ; CD = 10 nF (Note 2)
–
(Note 3)
–
µs
VOPL
Minimum operating
threshold voltage
RL = 4.7 kΩ; VOL ≤ 0.4 V; S1 = ON;
Test Circuit 1 (Figure 27)
–
0.65
0.80
V
IOL1
Output current (ON Time 1)
VO = 0.4 V; RL = 0; VCC1 = VS(min) – 0.05 V;
VCC2 = 0.4 V; S2 = ON; Test Circuit 1 (Figure 27)
5
–
–
mA
IOL2
Output current (ON Time 2)
VO = 0.4 V; RL = 0; VCC1 = VS(min) – 0.05 V;
Tamb = –20 °C to +75 °C; S2 = ON;
Test Circuit 1 (Figure 27)
3
–
–
mA
NOTES:
1. tPLH: VCC = (VS(typ) – 0.4 V) to (VS(typ) + 0.4 V); tPLH is release delay time (Test Circuit 2, Figure 28).
2. tPHL: VCC = (VS(typ) + 0.4 V) to (VS(typ) – 0.4 V); tPHL is assertion delay time (Test Circuit 2, Figure 28).
3. See Table 1.
Table 1. NE56632-XX series typical delay time
–XX
tPLH
tPHL
46
195 ms
140 µs
45
190 ms
140 µs
44
185 ms
140 µs
43
180 ms
140 µs
42
175 ms
140 µs
31
120 ms
120 µs
30
115 ms
120 µs
29
110 ms
120 µs
28
105 ms
100 µs
27
100 ms
100 µs
20
65 ms
100 µs
19
60 ms
100 µs
2002 Mar 25
4
Philips Semiconductors
Product data
Active-LOW system reset with adjustable delay time
NE56632-XX
TYPICAL PERFORMANCE CURVES, NE56632-20
100
2.0050
Vhys , HYSTERESIS VOLTAGE (mV)
VS, DETECTION THRESHOLD (V)
2.0025
2.0000
1.9975
1.9950
1.9925
Test Circuit 1
VCC = HIGH-to-LOW
RL = 4.7 kΩ
VOL ≤ 0.4 V
S1 = ON
1.9900
1.9875
1.9850
–40
–20
0
20
40
60
80
90
80
70
60
50
40
Test Circuit 1
VCC = LOW-to-HIGH-to-LOW
RL = 4.7 kΩ
S1 = ON
30
–40
100
–20
AMBIENT TEMPERATURE, Tamb (°C)
0
20
40
60
80
SL01620
SL01621
Figure 3. Detection threshold versus temperature.
Figure 4. Hysteresis voltage versus temperature.
9
I CCL , SUPPLY CURRENT (ON time), (µA)
VOL, LOW-LEVEL OUTPUT VOLTAGE (V)
0.225
0.220
0.215
0.210
0.205
0.200
0.195
Test Circuit 1
VCC1 = VS(min) – 0.05 V
RL = 4.7 kΩ
S1 = ON
0.190
0.185
–40
–20
0
20
40
60
80
8
7
6
5
4
Test Circuit 1
VCC1 = VS(min) – 0.05 V
RL = ∞
3
–40
100
–20
AMBIENT TEMPERATURE, Tamb (°C)
0
20
40
60
80
SL01623
Figure 6. Supply current (ON time) versus temperature.
VOPL , MIN. OPERATING THRESHOLD VOLTAGE (V)
Figure 5. LOW-level output voltage versus temperature.
4.5
4.0
3.5
3.0
2.5
Test Circuit 1
RL = ∞
VCC1 = VS(typ)/0.85
2.0
–40
–20
0
20
40
60
80
100
AMBIENT TEMPERATURE, Tamb (°C)
0.9
0.8
0.7
0.6
0.5
0.4
Test Circuit 1
RL = 4.7 kΩ
VOL ≤ 0.4 V
S1 = ON
0.3
–40
–20
0
20
40
60
80
100
AMBIENT TEMPERATURE, Tamb (°C)
SL01624
SL01625
Figure 7. Supply current (OFF time) versus temperature.
2002 Mar 25
100
AMBIENT TEMPERATURE, Tamb (°C)
SL01622
I CCH, SUPPLY CURRENT (OFF time), ( µA)
100
AMBIENT TEMPERATURE, Tamb (°C)
Figure 8. Min. operating threshold voltage versus temperature.
5
Philips Semiconductors
Product data
Active-LOW system reset with adjustable delay time
NE56632-XX
100
37
tPLH, LOW-to-HIGH DELAY TIME (ms)
I OL1 , OUTPUT CURRENT (ON Time 1), (mA)
TYPICAL PERFORMANCE CURVES, NE56632-20 (continued)
35
33
31
29
27
Test Circuit 1
VCC1 = VS(min) – 0.05 V
VCC2 = 0.4 V
VO = 0.4 V
RL = 0 Ω
S2 = ON
25
–40
–20
0
20
40
60
80
100
tPHL, HIGH-to-LOW DELAY TIME (µs)
105
100
95
90
VCC = (VS(typ) + 0.4 V) to (VS(typ)– 0.4 V)
tPHL = Assertion Delay Time
0
20
40
60
80
100
AMBIENT TEMPERATURE, Tamb (°C)
SL01628
Figure 11. HIGH-to-LOW delay time versus temperature.
2002 Mar 25
tPLH = Release Delay Time
–20
0
20
40
60
80
100
Figure 10. LOW-to-HIGH delay time versus temperature.
Test Circuit 2
CL = 100 pF
RL = 4.7 kΩ
CD = 10 nF
–20
50
SL01627
120
80
–40
60
AMBIENT TEMPERATURE, Tamb (°C)
Figure 9. Output current (ON time 1) versus temperature.
85
70
40
–40
SL01626
110
80
VCC = (VS(typ) – 0.4 V) to (VS(typ)+ 0.4 V)
AMBIENT TEMPERATURE, Tamb (°C)
115
90
Test Circuit 2
CL = 100 pF
RL = 4.7 kΩ
CD = 10 nF
6
Philips Semiconductors
Product data
Active-LOW system reset with adjustable delay time
NE56632-XX
TYPICAL PERFORMANCE CURVES, NE56632-31
90
Vhys , HYSTERESIS VOLTAGE (mV)
VS, DETECTION THRESHOLD (V)
3.11
3.10
3.09
Test Circuit 1
VCC = HIGH-to-LOW
RL = 4.7 kΩ
VOL ≤ 0.4 V
S1 = ON
3.08
–40
–20
0
20
40
60
80
80
70
60
50
40
Test Circuit 1
VCC = LOW-to-HIGH
RL = 4.7 kΩ
S1 = ON
30
–40
100
–20
AMBIENT TEMPERATURE, Tamb (°C)
0
20
40
60
80
SL01629
SL01630
Figure 12. Detection threshold versus temperature.
Figure 13. Hysteresis voltage versus temperature.
9
I CCL , SUPPLY CURRENT (ON time), (µA)
VOL, LOW-LEVEL OUTPUT VOLTAGE (V)
0.23
0.22
0.21
0.20
0.19
Test Circuit 1
VCC1 = VS(min) – 0.05 V
RL = 4.7 kΩ
S1 = ON
0.18
0.17
–40
–20
0
20
40
60
80
8
7
6
5
4
3
Test Circuit 1
VCC1 = VS(min) – 0.05 V
RL = ∞
2
–40
100
–20
AMBIENT TEMPERATURE, Tamb (°C)
0
20
40
60
80
SL01632
Figure 15. Supply current (ON time) versus temperature.
VOPL , MIN. OPERATING THRESHOLD VOLTAGE (V)
Figure 14. LOW–level output voltage versus temperature.
4.5
4.0
3.5
3.0
2.5
Test Circuit 1
RL = ∞
VCC1 = VS(typ)/0.85
2.0
–40
–20
0
20
40
60
80
100
AMBIENT TEMPERATURE, Tamb (°C)
0.9
0.8
0.7
0.6
0.5
0.4
Test Circuit 1
RL = 4.7 kΩ
VOL ≤ 0.4 V
S1 = ON
0.3
–40
–20
0
20
40
60
80
100
AMBIENT TEMPERATURE, Tamb (°C)
SL01633
SL01634
Figure 16. Supply current (OFF time) versus temperature.
2002 Mar 25
100
AMBIENT TEMPERATURE, Tamb (°C)
SL01631
I CCH, SUPPLY CURRENT (OFF time), (µA)
100
AMBIENT TEMPERATURE, Tamb (°C)
Figure 17. Min. operating threshold voltage versus
temperature.
7
Philips Semiconductors
Product data
Active-LOW system reset with adjustable delay time
NE56632-XX
36
I OL2 , OUTPUT CURRENT (ON Time 2), (mA)
I OL1 , OUTPUT CURRENT (ON Time 1), (mA)
TYPICAL PERFORMANCE CURVES, NE56632-31 (continued)
34
32
30
28
26
24
22
Test Circuit 1
VCC1 = VS(min) – 0.05 V
VCC2 = 0.4 V
VO = 0.4 V
RL = 0 Ω
S2 = ON
20
–40
–20
0
20
40
60
80
37
35
33
31
29
Test Circuit 1
VCC1 = VS(min) – 0.05 V
VCC2 = 0.4 V
VO = 0.4 V
RL = 0 Ω
S2 = ON
27
–40
100
–20
AMBIENT TEMPERATURE, Tamb (°C)
0
20
40
60
80
100
AMBIENT TEMPERATURE, Tamb (°C)
SL01635
SL01636
Figure 18. Output current (ON time 1) versus temperature.
Figure 19. Output current (ON time 2) versus temperature.
160
160
Test Circuit 2
CL = 100 pF
RL = 4.7 kΩ
CD = 10 nF
tPHL, HIGH-to-LOW DELAY TIME (µs)
t PLH, LOW-to-HIGH DELAY TIME (ms)
180
140
120
100
80
60
40
–40
Test Circuit 2
CL = 100 pF
RL = 4.7 kΩ
CD = 10 nF
140
130
120
110
100
VCC = (VS(typ) + 0.4 V) to (VS(typ)– 0.4 V)
90
VCC = (VS(typ) – 0.4 V) to (VS(typ)+ 0.4 V)
tPHL = Assertion Delay Time
tPLH = Release Delay Time
–20
0
20
40
60
80
80
–40
100
AMBIENT TEMPERATURE, Tamb (°C)
–20
0
20
40
60
80
100
AMBIENT TEMPERATURE, Tamb (°C)
SL01637
SL01638
Figure 20. LOW-to-HIGH delay time versus temperature.
2002 Mar 25
150
Figure 21. HIGH-to-LOW delay time versus temperature.
8
Philips Semiconductors
Product data
Active-LOW system reset with adjustable delay time
NE56632-XX
the threshold comparator which is less than VREF, causing the output
of the comparator to go to a HIGH state. This causes the common
emitter amplifier, Q1 to turn ON pulling down the non-inverting
terminal of Comparator 2 which causes its output to go to a HIGH
state. This HIGH output level turns on the output common emitter
transistor, Q2. The collector output of Q2 is pulled LOW through the
external pull-up resistor, thereby asserting the Active-LOW reset.
TECHNICAL DISCUSSION
The NE56632-XX is a bipolar IC designed to provide power source
monitoring and a system reset function in the event the power sags
below an acceptable level for the system to operate reliably. The
reset threshold incorporates a typical hysteresis of 50 mV to prevent
erratic reasserts from being generated. An internal delay time circuit
provides a adjustable power-on reset delay of typically 200 µs to
200 ms using an external capacitor.
Threshold hysteresis is established by turning on the bipolar common
emitter transistor, Q1 when the input threshold Comparator 1 goes
to a HIGH state. This occurs when VCC sags to or below the
threshold level. With the output of Q1 connected to the non-inverting
terminal of Comparator 2, the non-inverting terminal has a level near
ground at about 0.4 V when the reset is asserted (Active-LOW). For
the Comparator 2 to reverse its output, the Comparator 1 output and
Q1 must overcome the additional pull-down voltage present on the
inverting input of Comparator 2. The differential voltage required to
do this establishes the hysteresis voltage of the sensed threshold
voltage. Typically, it is 50 mV.
The output of the NE56632-XX utilizes an open collector topology,
which requires an external pull-up resistor to VCC. Though this may
be regarded as a disadvantage, it is advantageous in many
sensitive applications. Because the open collector output cannot
source reset current when both are operated from a common supply,
the NE56632-XX offers a safe interconnect to a wide variety of
microprocessors.
The NE56632-XX operates at low supply currents, typically 3 µA,
while offering precision threshold detection (±1.5%).
Figure 22 is a functional block diagram of the NE56632-XX. The
internal reference source voltage, VREF, is typically 0.65 V over the
temperature range. The reference voltage is connected to the
non-inverting inputs of the threshold Comparator 1 and
Comparator 2, while the inverting input of Comparator 1 monitors
the supply voltage through a voltage divider (R1 and R2). The output
of the comparator drives the series base resistor, R3 of a common
emitter amplifier, Q1. The collector of Q1 is connected to the
inverting terminal of Comparator 2. The output of Comparator 2 is
connected to the series base resistor, R4 of the output common
emitter transistor, Q2. The open collector output of Q2 provides the
reset output.
When VCC sags, and it is below the detection Threshold (VSL), the
device will assert a Reset LOW output at or near ground potential.
As VCC rises from (VCC < VSL) to VSH or higher, the Reset is
released and the output follows VCC. Conversely, decreases in VCC
from (VCC > VSL) to VSL will cause the output to be pulled to ground.
The Delay Time Control is outputted at the junction of the collector
of Q1 and the inverting input of Comparator 2. The reset release
time delay, tPLH is set with an external capacitor. Figures 25 and 26
show tPLH as a function of the external delay capacitor, CD.
When VCC drops below the minimum operating voltage, typically
0.65 V, the output is undefined and the output reset low assertion is
no longer guaranteed. At this level of VCC the output will try to rise to
VCC. As VCC drops even further to zero, VOUT reset also goes to
zero.
Hysteresis voltage = Release voltage – Detection Threshold voltage
Vhys = VSH – VSL
where:
VSH = VSL + Vhys
VSL = VSH – Vhys
When the supply voltage sags to the threshold detection voltage, the
resistor divider network supplies a voltage to the inverting terminal of
VCC
5
ID
R1
COMP1
VREF
COMP2
R3
R2
Q1
VOUT
3
GND
2
SUB
Q2
1
TC
Figure 22. Functional diagram.
2002 Mar 25
4
R4
9
(SUBSTRATE)
SL01607
Philips Semiconductors
Product data
Active-LOW system reset with adjustable delay time
NE56632-XX
TIMING DIAGRAM
The timing diagram in Figure 23 depicts the operation of the device.
Letters A–N on the TIME axis indicates specific events.
G-H: At “G”, VCC is above the upper threshold and begins to fall,
causing VOUT to follow it. As long as VCC remains above the VSH,
no reset signal will be generated.
A: At “A”, VCC begins to increase. Also the VOUT voltage initially
increases but abruptly decreases when VCC reaches the level
(approximately 0.65 V) that activates the internal bias circuitry and
RESET is asserted.
H: At event “H”, VCC falls until the VSL undervoltage detection
threshold is reached. At this level, a RESET signal is generated and
VOUT goes LOW.
B: At “B”, VCC reaches the threshold level of VSH. At this point the
delay time, tPLH is initiated while VCC rises above VSH to its normal
operating level. The VOUT voltage remains in a low voltage state.
H-I: Between “H” and “I”, VCC continues to fall and then starts to
rise rising. VCC rises to the VSH level at “I”, where the delay time is
again initiated.
C: At “C”, VCC is above VSL and the delay time elapses. At this
instant, the IC releases the hold on the VOUT reset. The reset output
then goes HIGH (assuming the reset pull-up resistor RPU is
connected to VCC). In a microprocessor based system these events
release the reset from the microprocessor, allowing the
microprocessor to function normally.
I-J: Between “I” and “J”, VCC rises above VSH to VCC normal and
then falls back to VSL level at “J”. At “J”, the reset signal is
reasserted before the delay time has elapsed. The time between “I”
and “J” is less than tPLH (reset delay time). Thus, the reset is not
released and the reset output remains LOW.
K–L: Between “K” and “L”, VCC rises again back to normal
operating level causing the reset delay to be initiated at “K” and the
reset to be released at “L”.
D-E: At “D”, VCC begins to fall, causing VOUT to follow. VCC
continues to fall until the VSL undervoltage detection threshold is
reached at “E”. This causes a reset signal to be generated (VOUT
goes LOW).
M: At “M”, VCC falls to VSL where the reset is asserted (VOUT
Reset goes LOW).
E-F: Between “E” and “F”, VCC continues to fall and then starts
rising.
N: At “N”, the VCC voltage has decreased until normal internal
circuit bias is unable to maintain a VOUT reset. As a result, VCC may
rise to less than 0.65 V. As VCC decreases further, the VOUT reset
also decreases to zero.
F: At “F”, VCC rises to the VSH level. Once again, the device
initiates the delay timer.
F-G: VCC rises above VSH and returns to normal. At “G”, the delay
(tPLH) times out and once again, then it releases the hold on the
VOUT reset.
V
Vhys
VSH
VSL
VCC
< tPLH
V
VOUT
(RESET)
tPLH
A
B
tPLH
C
D E
F
tPLH
G
H
I
J
K
L
M
N
SL01606
Figure 23. Timing diagram.
2002 Mar 25
10
Philips Semiconductors
Product data
Active-LOW system reset with adjustable delay time
NE56632-XX
APPLICATION INFORMATION
A typical application circuit for the NE56632-XX is shown in
Figure 24. Note that a pull-up resistor, RPU is necessary since the
output is an open collector. The value of RPU is calculated by the
following expression.
1.0E+00
1.0E–01
RPU ≥ (VCC – VRESET) / IOL
where:
t PLH (s)
1.0E–02
VCC = VS(min) – 0.05 V (for a 3 V reset this is 2.905 V)
VRESET = 0.4 V (this is VOL(max))
IOL = 5 mA; minimum output current at Tamb = 25 °C
1.0E–03
1.0E–04
Substituting these values into the expression and calculating, finds
RPU should be greater than or equal to 510 Ω. To ensure that the
Active-LOW level is sufficient, a value of 4.7 kΩ is chosen in the test
and application examples.
1.0E–05
1.0E+00
1.0E+01
1.0E+02
1.0E+03
1.0E+04
CD (pF)
SL01611
TO VCC
5
Figure 25. NE56632-20 CD versus tPLH characteristics.
TO RESET
TERMINAL
OF CPU
RPU
1.0E+00
4
1.0E–01
NE56632-XX
2
1.0E–02
3
t PLH (s)
1
CD
SL01605
1.0E–03
1.0E–04
Figure 24. Typical application.
1.0E–05
1.0E+00
Figure 25 (NE56632-20 CD versus tPLH) and Figure 26
(NE56632-44 CD versus tPLH) show how tPHL, the “H” transmission
delay or reset release delay time varies as a function of the external
delay capacitance, CD. From Figure 26, typical range of the delay
capacitance is 1 pF to 10 nF which yields typical delays from 200 µs
to 200 ms.
1.0E+02
1.0E+03
1.0E+04
CD (pF)
SL01612
Figure 26. NE56632-44 CD versus tPLH characteristics.
Table 2. Delay time coefficient
The following formula can be used to find the approximate delay
time based on external delay capacitance, CD and the delay time
coefficient, d shown in Table 2.
tPLH (ms) ≈ CD (µF) × d
For example, a NE56632-44 using an external capacitor,
CD = 1 nF = 1000 pF yields:
tPLH (ms) ≈ (1 × 10–3) (1.85 × 104) ≈ 18.5 ms
Compare this to the value of tPLH ≈ 17 ms for CD = 1000 pF that is
extracted from Figure 26.
2002 Mar 25
1.0E+01
11
Device
d
NE56632–46
1.95 × 104
NE56632–45
1.90 × 104
NE56632–44
1.85 × 104
NE56632–43
1.80 × 104
NE56632–42
1.75 × 104
NE56632–31
1.20 × 104
NE56632–30
1.15 × 104
NE56632–29
1.10 × 104
NE56632–28
1.05 × 104
NE56632–27
1.00 × 104
NE56632–20
0.65 × 104
NE56632–19
0.60 × 104
Philips Semiconductors
Product data
Active-LOW system reset with adjustable delay time
NE56632-XX
TEST CIRCUITS
S1
RL
A1
S2
A2
5
4
10 µF
/10 V
V1
VCC1
V2
NE56632-XX
CD
1
S3
2
VCC2
3
SL01608
Figure 27. Test circuit 1.
5
4
RL
10 µF
/10 V
VS(typ) – 0.4 V
VS(typ) + 0.4 V
5.0 V
INPUT
PULSE
0V
NE56632-XX
SL01610
1
2
3
CL
100 pF
Figure 29. Input pulse.
CRT
CD
NOTES:
A = DC amperemeter
V = DC voltmeter
CRT = oscilloscope
SL01609
Figure 28. Test circuit 2.
2002 Mar 25
12
Philips Semiconductors
Product data
Active-LOW system reset with adjustable delay time
NE56632-XX
PACKING METHOD
The NE56632-XX is packed in reels, as shown in Figure 30.
GUARD
BAND
TAPE
REEL
ASSEMBLY
TAPE DETAIL
COVER TAPE
CARRIER TAPE
BARCODE
LABEL
BOX
SL01305
Figure 30. Tape and reel packing method.
2002 Mar 25
13
Philips Semiconductors
Product data
Active-LOW system reset with adjustable delay time
NE56632-XX
SOT23-5: plastic small outline package; 5 leads; body width 1.5 mm
1.35
2002 Mar 25
1.2
1.0
0.025
0.55
0.41
0.22
0.08
3.00
2.70
1.70
1.50
0.55
0.35
14
Philips Semiconductors
Product data
Active-LOW system reset with adjustable delay time
NOTES
2002 Mar 25
15
NE56632-XX
Philips Semiconductors
Product data
Active-LOW system reset with adjustable delay time
NE56632-XX
Data sheet status
Data sheet status [1]
Product
status [2]
Definitions
Objective data
Development
This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be
published at a later date. Philips Semiconductors reserves the right to change the specification
without notice, in order to improve the design and supply the best possible product.
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply.
Changes will be communicated according to the Customer Product/Process Change Notification
(CPCN) procedure SNW-SQ-650A.
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL
http://www.semiconductors.philips.com.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
 Koninklijke Philips Electronics N.V. 2002
All rights reserved. Printed in U.S.A.
Contact information
For additional information please visit
http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
Date of release: 08-02
For sales offices addresses send e-mail to:
[email protected].
Document order number:
2002 Mar 25
16
9397 750 10239