INTEGRATED CIRCUITS NE56605-42 System reset with built-in watchdog timer Product data Supersedes data of 2001 Apr 24 File under Integrated Circuits, Standard Analog 2001 Aug 22 Philips Semiconductors Product data System reset with built-in watchdog timer NE56605-42 GENERAL DESCRIPTION The NE56605-42 is designed to generate a reset signal, at a threshold voltage of 4.2 V, for a variety of microprocessor and logic systems. Accurate reset signals are generated during momentary power interruptions, or whenever power supply voltages sag to intolerable levels. The NE56605-42 has a built-in Watchdog Timer to monitor the microprocessor and ensure it is operating properly. Any abnormal system operations due to microprocessor malfunctions are terminated by the watchdog’s generating a system reset. The NE56605-42 has a watchdog monitoring time of 10 ms (typical). The NE56605-42 is offered in the SO8 surface mount package. FEATURES • Both positive and negative logic reset output signals are available • Accurate threshold detection • Internal power-on reset delay • Internal watchdog timer programmable with external capacitor • Watchdog monitoring time of 10 ms • Reset assertion with VCC down to 0.8 VDC (typical) • Few external components required. APPLICATIONS • Microcomputer systems • Logic systems. SIMPLIFIED SYSTEM DIAGRAM VCC 5 R VS 6 WDC NE56605-42 LOGIC SYSTEM 8 7 RESET GENERATOR 2 R RESET RESET RESET RESET VREF PROGRAMMABLE WATCHDOG TIMER C 4 GND 3 CLK CLK GND 1 CT SL01282 Figure 1. Simplified system diagram. ORDERING INFORMATION PACKAGE TYPE NUMBER NE56605-42D 2001 Aug 22 NAME DESCRIPTION TEMPERATURE RANGE SO8 plastic small outline package; 8 leads; body width 3.9 mm –20 to +70 °C 2 853–2251 26949 Philips Semiconductors Product data System reset with built-in watchdog timer Part number marking NE56605-42 PIN CONFIGURATION TOP VIEW CT 1 RESET 2 8 RESET 7 VS SO8 CLK 3 6 WDC GND 4 5 VCC 5 6 7 8 The package is marked with a four letter code in the first line to the right of the logo. The first three letters designate the product. The fourth letter, represented by ‘x’, is a date tracking code. The remaining two or three lines of characters are internal manufacturing codes. SL01279 4 3 2 1 Figure 2. Pin configuration. Part number Marking NE56605-42 AA E x PIN DESCRIPTION PIN SYMBOL DESCRIPTION 1 CT tWDM, tWDR, tPR adjustment pin. tWDM, tWDR, tPR times are dependent on the value of external CT capacitor used. See Figure 18 (Timing Diagram) for definition of tWDM, tWDR, tPR times. 2 RESET Reset HIGH output pin. 3 CLK Clock input pin from logic system for watchdog timer. 4 GND Circuit ground. 5 VCC Power supply pin for circuit. 6 WDC Watchdog timer control pin. The watchdog timer is enabled when this pin is unconnected, and disabled when this pin is connected to ground. 7 VS Detection threshold adjustment pin. The detection threshold can be increased by connecting this pin to VCC with a pull-up resistor. The detection threshold can be decreased by connecting this pin to ground with a pull-down resistor. 8 RESET Reset LOW output pin. MAXIMUM RATINGS MIN. MAX. UNIT VCC SYMBOL Power supply voltage –0.3 10 V VS VS pin voltage –0.3 10 V VCLK CLK pin voltage –0.3 10 V VOH RESET and RESET pin voltage –0.3 10 V Toper Operating temperature –20 70 °C Tstg Storage temperature –40 125 °C P Power dissipation – 250 mW 2001 Aug 22 PARAMETER 3 Philips Semiconductors Product data System reset with built-in watchdog timer NE56605-42 DC ELECTRICAL CHARACTERISTICS Characteristics measured with VCC = 5.0 V, and Tamb = 25 °C, unless otherwise specified. See Figure 23 (Test circuit 1) for test configuration used for DC parameters. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT – 0.7 1.0 mA ICC Supply current during watchdog timer operation VSL Reset detection threshold VS = open; VCC = falling 4.05 4.20 4.35 V VSH Reset detection threshold VS = open; VCC = rising 4.15 4.30 4.45 V ∆VS/∆Tamb Temperature coefficient of reset threshold –20 °C ≤ Tamb ≤ 70 °C – ±0.01 – %/°C Vhys Reset threshold hysteresis VHYS = VSH (rising VCC) – VSL (falling VCC) 50 100 150 mV VTH CLK input threshold 0.8 1.2 2.0 V IIH CLK input current, HIGH-level VCLK = 5.0 V – 0 1.0 µA IIL CLK input current, LOW-level VCLK = 0 V –20 –10 –3.0 µA VOH1 Output voltage, HIGH-level IRESET = –5.0 µA; VS = open 4.5 4.8 – V IRESET current = –5.0 mA; VS = 0 V 4.5 4.8 – V IRESET = 3.0 mA; VS = 0 V – 0.2 0.4 V VOL2 IRESET = 10 mA; VS = 0 V – 0.3 0.5 V VOL3 IRESET = 0.5 mA; VS = open – 0.2 0.4 V VOL4 IRESET = 1.0 mA; VS = open – 0.3 0.5 V VRESET = 1.0 V; VS = 0 V 10 16 – mA VRESET = 1.0 V; VS = open 1.0 2.0 – mA VCT = 1.0 V; WDC = open during watchdog operation –8 –12 –24 µA VCT = 1.0 V; during power-on reset operation –0.8 –1.2 –2.4 µA VRESET = 0.4 V; RESET current = 0.2 mA – 0.8 1.0 V VRESET = VCC – 0.1 V; 1 MΩ resistor (pin 2 to GND) – 0.8 1.0 V VOH2 VOL1 IOL1 Output voltage, LOW-level Output sink current IOL2 ICT1 CT charge current ICT2 VCCL1 VCCL2 2001 Aug 22 Supply voltage to assert reset operation 4 Philips Semiconductors Product data System reset with built-in watchdog timer NE56605-42 AC ELECTRICAL CHARACTERISTICS Characteristics measured with VCC = 5.0 V, and Tamb = 25 °C, unless otherwise specified. See Figure 24 (Test circuit 2) for test configuration used for AC parameters. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT 4.0 V ≤ negative-going VCC pulse ≤ 5.0 V 8.0 – – µs tP1 Minimum power supply pulse width for detection tCLKW Clock input pulse width 3.0 – – µs tCLK Clock input cycle 20 – – µs tWDM Watchdog monitoring time (Notes 1, 6) CT = 0.1 µF; RCT = open 5.0 10 15 ms tWDR Watchdog reset time (Notes 2, 6) CT = 0.1 µF 1.0 2.0 3.0 ms tPR Power-on reset delay time (Notes 3, 6) VCC = rising from 0 V; CT = 0.1 µF 50 100 150 ms tPD1 RESET, RESET propagation delay time (Note 4) RESET: RL1 = 2.2 kΩ; CL1 = 100 pF – 2.0 10 µs RESET: RL2 = 10 kΩ; CL2 = 20 pF – 3.0 10 µs RESET, RESET rise time (Note 5) RESET: RL1 = 2.2 kΩ; CL1 = 100 pF – 1.0 1.5 µs RESET: RL2 = 10 kΩ; CL2 = 20 pF – 1.0 1.5 µs RESET: RL1 = 2.2 kΩ; CL1 = 100 pF – 0.1 0.5 µs RESET: RL2 = 10 kΩ; CL2 = 20 pF – 0.5 1.0 µs tPD2 tR1 tR2 tF1 RESET, RESET fall time (Note 5) tF2 NOTES: 1. ‘Watchdog monitoring time’ is the duration from the last pulse (negative-going edge) of the timer clear clock pulse until reset output pulse occurs (see Figure 18). A reset signal is output if a clock pulse is not input during this time. 2. ‘Watchdog reset time’ is the reset pulse width (see Figure 18). 3. ‘Power-on reset delay time’ is the duration measured from the time VCC exceeds the upper detection threshold (VSH) and power-on reset release is experienced (RESET output HIGH; RESET output LOW). 4. ‘RESET, RESET propagation delay time’ is the duration from when the supply voltage sags below the lower detection threshold (VSL) and reset occurs (RESET output LOW, RESET output HIGH). 5. RESET, RESET rise and fall times are measured at 10% and 90% output levels. 6. Watchdog monitoring time (tWDM), watchdog reset time (tWDR), and power-on reset delay time (tPR) during power-on can be modified by varying the CT capacitance. The times can be approximated by applying the following formula. The recommended range for CT is 0.001 µF to 10 µF. Formula 1. Calculation for approximate tPR, tWDM, and tWDR values: tPR (ms) ≈ 1000 × CT (µF) tWDM (ms) ≈ 100 × CT (µF) tWDR (ms) ≈ 20 × CT (µF) Example: When CT = 0.1 µF and WDC = open: tPR ≈ 100 ms tWDM ≈ 10 ms tWDR ≈ 2.0 ms 2001 Aug 22 5 Philips Semiconductors Product data System reset with built-in watchdog timer NE56605-42 TYPICAL PERFORMANCE CURVES 6.0 Tamb = 35 °C RESET PULL-UP R = 10 kΩ 1 .2 VRST, RESET OUTPUT VOLTAGE (V) I CC POWER SUPPLY CURRENT (mA) 1 .4 WITHOUT CLOCK SIGNALS TO WATCHDOG 1.0 0.8 0.6 WITH CLOCK SIGNALS TO WATCHDOG 0.4 0.2 0 5.0 Tamb = –25 °C, 25 °C, 75 °C 4.0 3.0 2.0 VSL VSH VOL 1.0 0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 0 10.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 SL01303 SL01304 Figure 3. Power supply current versus voltage. Figure 4. RESET output voltage versus supply voltage. 4.5 RESET PULL-UP R = 2.2 kΩ VSL , V SH , DETECTION THRESHOLD (V) VRST , RESET OUTPUT VOLTAGE (V) 6.0 5.0 4.0 3.0 VSL VSH 2.0 Tamb = –25 °C Tamb = 25 °C 1.0 VOL Tamb = 75 °C 0 0 1.0 2.0 3.0 4.0 5.0 VCC = RISING (VSH) VCC = FALLING (VSL) 4.4 VSH 4.3 VSL 4.2 4.1 4.0 –40 6.0 –20 0 VCC POWER SUPPLY VOLTAGE (V) 20 40 60 80 SL01301 Figure 5. RESET output voltage versus supply voltage. 600 Figure 6. Detection threshold versus temperature. 600 VOL , RESET OUTPUT SATURATION (mV) VCC = 5.0 V RESET PULL-UP R = 10 kΩ 500 400 Tamb = 75 °C 300 100 Tamb, AMBIENT TEMPERATURE (°C) SL01302 VOL , RESET OUTPUT SATURATION (mV) 8.0 VCC, POWER SUPPLY VOLTAGE (V) VCC, POWER SUPPLY VOLTAGE (V) 200 100 Tamb = –25 °C Tamb = 25 °C VCC = 5.0 V RESET PULL-UP R = 2.2 kΩ 500 400 Tamb = 75 °C 300 Tamb = 25 °C Tamb = –25 °C 200 100 0 0 0 –0.2 –0.4 –0.6 –0.8 –1.0 –1.2 –1.4 –1.6 0 –1.8 IOL, RESET OUTPUT SINK CURRENT (mA) –4 –6 –8 –10 –12 –14 –16 –18 IOL, RESET OUTPUT SINK CURRENT (mA) SL01300 SL01299 Figure 7. RESET saturation versus sink current. 2001 Aug 22 –2 Figure 8. RESET saturation versus sink current. 6 Philips Semiconductors Product data System reset with built-in watchdog timer 5.0 VCC = 5.0 V Tamb = 25 °C VOM, RESET HIGH LEVEL OUTPUT (V) VOM, RESET HIGH LEVEL OUTPUT (V) 5.2 NE56605-42 5.0 4.8 4.6 4.4 4.2 4.0 4.8 VCC = 5.0 V Tamb = 25 °C 4.6 4.4 4.2 4.0 3.8 3.6 0 –2 –4 –6 –8 –10 –12 –14 –16 0 –18 IOM, RESET HIGH OUTPUT LEAKAGE CURRENT (µA) –2.0 –4.0 –6.0 –8.0 –10 –12 –14 IOM, RESET HIGH OUTPUT LEAKAGE CURRENT (µA) SL01298 SL01297 Figure 9. RESET HIGH-level voltage versus current. Figure 10. RESET HIGH-level voltage versus current. 140 VCC = 5.0 V CT = 0.1 µF RCT = Open t WDM , WATCHDOG MONITORING (ms) t PR , POWER-ON RESET HOLD (ms) 140 120 100 80 60 VCC = 5.0 V CT = 0.1 µF RCT = Open 120 100 80 60 –40 –20 0 20 40 60 80 100 –40 Tamb, AMBIENT TEMPERATURE (5C) VCC = 5.0 V CT = 0.1 µF 2.5 2.0 1.5 0 20 40 60 80 100 Tamb, AMBIENT TEMPERATURE (°C) SL01294 Figure 13. Watchdog reset time versus temperature. 2001 Aug 22 20 40 60 80 100 Figure 12. Watchdog monitoring time versus temperature. 3.0 –20 0 SL01295 Figure 11. Power–on reset hold time versus temperature. 1.0 –40 –20 Tamb, AMBIENT TEMPERATURE (5C) SL01296 t WDR , WATCHDOG RESET (ms) –16 7 Philips Semiconductors Product data System reset with built-in watchdog timer NE56605-42 102 VCC = 5.0 V Tamb = 25 °C VCC = 5.0 V Tamb = 25 °C t WDR , WATCHDOG RESET (ms) t PR , POWER-ON RESET HOLD (ms) 104 103 102 10 1.0 10–3 10–2 10–1 1.0 10 1.0 10–1 10–2 10–3 10 CT, CAPACITANCE (µF) 10–2 10–1 1.0 SL01290 SL01291 Figure 14. Power-on reset hold time versus CT. Figure 15. Watchdog reset time versus CT. t WDM, WATCHDOG MONITORING (ms) 103 VCC = 5.0 V Tamb = 25 °C 102 10 1.0 10–1 10–3 10–2 10–1 1.0 10 CT, CAPACITANCE (µF) SL01292 Figure 16. Watchdog reset time versus CT. 2001 Aug 22 10 CT, CAPACITANCE (µF) 8 Philips Semiconductors Product data System reset with built-in watchdog timer NE56605-42 external capacitor (CT) must be connected from Pin 1 to ground. Normally a 0.1 µF capacitor is used for CT. The CT capacitor and a fixed internal resistance establish the required minimum frequency of watchdog input signal for the device to not output a reset signal. In the absence of a watchdog input pulse, the CT capacitor charges to the 0.2 volt threshold of the internal comparator, causing a reset signal to be output. If microprocessor clock signals are received within the required interval, no watchdog reset signal will be output. Grounding the watchdog control pin (WDC, Pin 6) disables the watchdog function. Removing the ground from Pin 6, allowing it to float, enables the watchdog function. Enabling or disabling the watchdog function has no effect on the undervoltage detection function. TECHNICAL DESCRIPTION General discussion The NE56605-42 combines a watchdog timer and an undervoltage reset function in a single SO8 surface mount package. This provides a space-saving solution for maintaining proper operation of typical 5.0 volt microprocessor-based logic systems. Either function, or both, can force the microprocessor into a reset. While the watchdog monitors the microprocessor operation, the undervoltage reset monitors the supply voltage to the microprocessor. If the microprocessor clock signal ceases or becomes erratic, the NE56605-42 outputs a reset signal to the microprocessor. If the microprocessor supply voltage sags to 4.2 volts or less, the NE56605-42 outputs a reset signal for the duration of the supply voltage deficiency. The undervoltage reset signal allows the microprocessor to shut down in an orderly manner to avoid system corruption. In addition to a single reset output, the NE56605-42 has complementary RESET and RESET outputs for system use. The undervoltage detection threshold incorporates hysteresis to prevent generating erratic resets. Although the temperature coefficient of detection threshold is specified over a temperature of –20 °C to +70 °C, the device will support operation in excess of this temperature range. See the supporting curves for performance over the full temperature range of –30 °C to +85 °C. Some degradation in performance will be experienced at the temperature extremes and the system designer should take this into account. The watchdog timer requires a pulse input. Normally this signal comes from the system microprocessor’s clock. For operation, an VCC WDC 6 5 CP 1.2 µA 1.2 µA R 47 kΩ 0.1 V R R 12 µA 54 kΩ S Q 7 R R R R 26 kΩ C S Q R R R S Q 8.2 kΩ 3 PULSE GENERATOR R 0.2 V 1 CT 4 GND 2 8 RESET RESET SL01293 Figure 17. Functional diagram. 2001 Aug 22 9 Philips Semiconductors Product data System reset with built-in watchdog timer NE56605-42 Timing diagram E–F: Immediately before ‘E’, falling VCC causes the RESET signal to sag. CLK signals are still being received, CT is within normal operating range, and reset signals are not output. VCC continues to sag until the VSL undervoltage threshold is reached. At that time, reset signals are generated (RESET goes LOW; RESET goes HIGH). The timing diagram shown in Figure 18 depicts the operation of the device. Letters indicate events on the TIME axis. A: At start-up ‘A’, the VCC and RESET voltages begin to rise. Also the RESET voltage initially rises, but then abruptly returns to a LOW state. This is due to VCC reaching the level (approximately 0.8 V) that activates the internal bias circuitry, asserting RESET. At ‘E’, VCC starts to rise, and the Reset voltage rises with VCC. However, CT voltage does not start to ramp up until ‘F’ when VCC reaches the VSH upper threshold. B: Just before ‘B’, the CT voltage starts to ramp up. This is caused by, and coincident to, VCC reaching the threshold level of VSH. At this level the device is in full operation. The RESET output continues to rise as VCC rises above VSH. This is normal. G: The reset outputs are released at ‘G’ when CT reaches the upper threshold level again. After ‘G’, normal CLK signals are received, but at a lower frequency than those following event ‘C’. The frequency is above the minimum frequency required to keep the device from outputting reset signals. C: At ‘C’, VCC is above the undervoltage detect threshold, and CT has ramped up to its upper detect level. At this point, the device removes the hold on the resets. RESET goes HIGH while RESET goes LOW. Also, an internal ramp discharge transistor activates, discharging CT. G–H: At ‘H’, VCC is normal, CLK signals are being received, and no reset signals are output. At event ‘H’, the VCC starts falling, causing RESET to also fall. In a microprocessor-based system these events remove the reset from the microprocessor, allowing it to function normally. The system must send clock signals to the Watchdog Timer often enough to prevent CT from ramping up to the CT threshold, to prevent reset signals from being generated. Each clock signal discharges CT. J: At event ‘J’, VCC sags to the point where the VSL undervoltage threshold point is reached, and at that level reset signals are output (RESET to a LOW state, and RESET to a HIGH state). As the VCC voltage falls lower, the Reset voltage falls lower. C–D: Midway between ‘C’ and ‘D’, the CLK signals cease allowing the CT voltage to ramp up to its upper threshold at ‘D’. At this time, reset signals are generated (RESET goes LOW; RESET goes HIGH). The device attempts to come out of reset as the CT voltage is discharged and finally does come out of reset when CLK signals are re-established after two attempts of CT. K: At event ‘K’, the VCC voltage has deteriorated to a level where normal internal circuit bias is no longer able to maintain a RESET, and as a result may exhibit a slight rise to something less than 0.8 V. As VCC decays even further, RESET also decreases to zero. VSH VSL VCC tCLK CLK CTthresh CT tPR tWDM tWDR RESET 0.8 V RESET A B C D E F G H J K TIME SL01283 Figure 18. Timing diagram. 2001 Aug 22 10 Philips Semiconductors Product data System reset with built-in watchdog timer NE56605-42 Application information The Reset Detection Threshold can be decreased by connecting an external resistor R1 from Pin 7 to VCC, as shown in Figure 19. See Figure 20 to determine the approximate value of R1 to use. The detection threshold voltage can be adjusted by externally influencing the internal divider reference voltage. Figures 19 and 21 show a method to lower and raise the threshold voltage. Figures 20 and 22 show the influence of the pull-down and pull-up resistors on the threshold voltage. The use of a capacitor (1000 pF or larger) from Pin 7 to ground is recommended to filter out noise from being imposed on the threshold voltages. VCC The Reset Detection Threshold can be increased by connecting an external resistor R2 from Pin 7 to ground, as shown in Figure 21. See Figure 22 to determine the approximate value of R2 to use. 5.0 Vs, RESET DETECTION THRESHOLD (V) LOGIC SYSTEM R1 3 NE56605-42 2 RESET 8 1 CLK 7 RESET 6 GND 5 4 1000 pF VCC = 5.0 V Tamb = 25 °C CT = 0.1 µF VSH 4.0 VSL 3.5 3.0 0 100 200 300 400 500 600 700 R1, EXTERNAL PIN 7 TO VCC RESISTOR (kΩ) SL01286 SL01289 Figure 19. Circuit to lower detection threshold. VCC Figure 20. Reset detection threshold versus external R1. 5.1 3 NE56605-42 2 RESET 8 1 Vs, RESET DETECTION THRESHOLD (V) LOGIC SYSTEM CLK 7 RESET 6 GND 4 5 R2 1000 pF VCC = 5.0 V Tamb = 25 °C CT = 0.1 µF 5.0 4.9 4.8 4.7 4.6 VSH 4.5 VSL 4.4 4.3 0 100 200 300 400 500 600 700 R2, EXTERNAL PIN 7 TO GROUND RESISTOR (kΩ) SL01287 SL01288 Figure 21. Circuit to raise detection threshold. 2001 Aug 22 Figure 22. Reset detection threshold versus external R2. 11 Philips Semiconductors Product data System reset with built-in watchdog timer NE56605-42 Parametric testing DC and AC Characteristics can be tested using the circuits shown in Figures 23 and 24. Associated switch and power supply settings are shown in Table 1 and Table 2, respectively. S5 1000 pF S2 IO1 A A B C V S1 8 7 6 5 RESET VS RCT VCC RESET CLK GND S3 VO1 CT 1 IRESET CRT A CRT1 3 A ICT VO0 VCT 2 0.1 µF A ICC 4 A IO2 VCC ICLK S4 A S7 S6 V C VO2 B CRT R 1.0 MΩ VCLK CRT2 IRESET SL01284 Figure 23. Test Circuit 1 (DC parameters). Table 1. DC characteristics Test Circuit 1 switch and power supply settings Parameter Symbol S1 S2 S3 S4 S5 S6 S7 VCC VCLK VCT IRESET IRESET Read ICC B OFF OFF B OFF ON ON 5.0 V 5.0 V 0V – – ICC Reset threshold (LOW) (Note 1) VSL B OFF OFF B ON ON ON 5.0 to 4.0 V 3.0 V 3.0 V – – VO1, CRT1 Reset threshold (HIGH) (Note 2) VSH B OFF OFF B ON ON ON 4.0 to 5.0 V 3.0 V 3.0 V – – VO1, CRT1 Clock input threshold (Note 3) VTH B OFF OFF B OFF ON ON 5.0 V 0 to 3.0 V 1.0V – – ICLK Clock input current (HIGH) ITH B OFF OFF B OFF ON ON 5.0 V 5.0 V 0V – – ICLK Clock input current (LOW) ITL B OFF OFF B OFF ON ON 5.0 V 0V 0V – – ICLK VOH1 B OFF ON B ON ON ON 5.0 V 5.0 V 3.0 V –5.0 µA – VO1 VOH2 B ON OFF C ON ON ON 5.0 V 5.0 V 3.0 V – –5.0 µA VO2 VOL1 B ON ON B ON ON ON 5.0 V 5.0 V 3.0 V 3.0 mA – VO1 VOL2 B ON ON B ON ON ON 5.0 V 5.0 V 3.0 V 10 mA – VO1 VOL3 B OFF OFF C ON ON ON 5.0 V 5.0 V 3.0 V – 0.5 mA VO2 VOL4 B OFF OFF C ON ON ON 5.0 V 5.0 V 3.0 V – 1.0 mA VO2 Reset output sink current (N t 4) (Note IOL1 C ON OFF B ON ON ON 5.0 V 5.0 V 3.0 V – – IO1 IOL2 A OFF OFF B ON ON ON 5.0 V 5.0 V 3.0 V – – IO2 CT charge current 1 ICT1 B OFF OFF B OFF OFF ON 5.0 V – 1.0 V – – ICT CT charge current 2 ICT2 B OFF OFF B ON OFF ON 5.0 V – 1.0 V – – ICT Minimum power supply for RESET (Note 5) VCCL1 B OFF ON B ON ON ON 0 to 2.0 V 0V 0V – – VO1, VCC Minimum power supply for RESET (Note 6) VCCL2 B ON OFF A ON ON ON 0 to 2.0 V 0V 0V – – VO2, VCC Power supply current Reset output voltage (HIGH) Reset output voltage (LOW) NOTES: 1. Decrease VCC from 5.0 V to 4.0 V and note the VCC value when VO1 (observed on CRT1) transitions to an abrupt LOW state. 2. Increase VCC from 4.0 V to 5.0 V and note the VCC value when VO1 (observed on CRT1) transitions to an abrupt HIGH state. 3. Increase the Clock voltage (VCLK) from 0 V to 3.0 V and observe the value of VCLK when ICLK transitions to an abrupt increase. 4. Measured with VO0 = 1.0 V. 5. Increase VCC from 0 V to 2.0 V and note the VCC value when VO1 (observed on CRT1) transitions to an abrupt LOW state. The VO1 value will initially track the VCC voltage increase until the internal circuit bias becomes active, at which time the VO1 value will return to a LOW state. 6. Increase VCC from 0 V to 2.0 V and note the VCC value when VO2 (observed on CRT2) starts to track the VCC voltage. 2001 Aug 22 12 Philips Semiconductors Product data System reset with built-in watchdog timer R 2.2 kΩ 100 pF NE56605-42 VCC S1 CRT A 8 7 6 5 RESET VS RCT VCC C CRT B CRT1 CRT4 CT RESET CLK GND 1 2 3 4 VCCA S2 0.1 µF CRT A CRT2 R 10 kΩ C B 20pF VCLK CRT VCLKA CRT3 SL01285 Figure 24. Test Circuit 2 (AC parameters). Table 2. Switch and power supply settings, AC parameters Parameter VCC pulse width for detection (Note 1) Clock input pulse width (Note 2) Symbol S1 S2 tP1 C C VCCA – 5.0 V t1 4.0 V tCLKW A VCC C VCLKA 1.4 V t2 tCLK A – 1, 2, 3 – 1, 2, 3 – 1, 2, 3 t3 – C CRT 0V 5.0 V 1.4 V t2 t2 0V Clock input cycle (Note 3) VCLK – 5.0 V 1.4 V t2 0V t3 Watchdog monitoring time tWDM A A – 5.0 V – 5.0 V 1, 2, 3 Watchdog reset time Power-on reset delay time tWDR A A – 5.0 V – 5.0 V 1, 2, 3 tPR B to A A – 5.0 V – 5.0 V 1, 2, 3 RESET, RESET propagation delay time tPD1 C B – – 0V 1, 2 – – 0V 2, 3 5.0 V 4.0 V tPD2 C B 5.0 V 4.0 V RESET, RESET rise time RESET, RESET fall time tR1 A A – 5.0 V – 5.0 V 1 tR2 A A – 5.0 V – 5.0 V 3 tF1 A A – 5.0 V – 5.0 V 1 tF2 A A – 5.0 V – 5.0 V 3 NOTES: 1. t1 = 8.0 µs. 2. t2 = 3.0 µs. 3. t3 = 20 µs. 2001 Aug 22 13 Philips Semiconductors Product data System reset with built-in watchdog timer NE56605-42 PACKING METHOD The NE56605-42 is packed in reels, as shown in Figure 25. GUARD BAND TAPE REEL ASSEMBLY TAPE DETAIL COVER TAPE CARRIER TAPE BARCODE LABEL BOX SL01305 Figure 25. Tape and reel packing method 2001 Aug 22 14 Philips Semiconductors Product data System reset with built-in watchdog timer NE56605-42 SO8: plastic small outline package; 8 leads; body width 3.9 mm pin 1 index B2 1.73 4.95 4.80 0.51 0.33 0.068 0.189 0.195 0.013 0.020 4.95 4.80 SO8 2001 Aug 22 15 1.27 0.38 0.076 0.050 0.015 0.003 Philips Semiconductors Product data System reset with built-in watchdog timer NE56605-42 Data sheet status Data sheet status [1] Product status [2] Definitions Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Koninklijke Philips Electronics N.V. 2001 All rights reserved. Printed in U.S.A. Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 Date of release: 10-01 For sales offices addresses send e-mail to: [email protected]. Document order number: 2001 Aug 22 16 9397 750 08733