Freescale Semiconductor MPC5533 Microcontroller Reference Manual This MPC5533 Reference Manual set consists of the following files: • MPC5533 Reference Manual Addendum, Rev 1 • MPC5533 Microcontroller Reference Manual, Rev 0 © Freescale Semiconductor, Inc., 2012. All rights reserved. MPC5533RM Rev. 0.1, 04/2012 Freescale Semiconductor Reference Manual Addendum MPC5533RMAD Rev. 1, 04/2012 MPC5533 Reference Manual Addendum This errata document describes corrections to the MPC5533 Microcontroller Reference Manual, order number MPC5533RM. For convenience, the addenda items are grouped by revision. Please check our website at http://www.freescale.com/powerarchitecture for the latest updates The current version available of the MPC5533 Microcontroller Reference Manual is Revision 0. © Freescale Semiconductor, Inc., 2012. All rights reserved. Table of Contents 1 2 Addendum for Revision 0 . . . . . . . . . . . . . . . . . . . 2 Revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Addendum for Revision 0 1 Addendum for Revision 0 Table 1. MPC5533RM Rev. 0 Addendum Location Description Section 11.3.1.1 Deleted the last note in PREDIV field description that states: “Synthesizer Control Register “To use the 8–20 MHz OSC, the PLL predivider must be configured for divide-by-two operation (FMPLL_SYNCR)” by tying PLLCFG[2] low (set PREDIV to 0b000).” 2 Revision history Table 2 provides a revision history for this document. Table 2. Revision history Revision 1.0 Substantive changes Initial release. Date of release 04/2012 MPC5533 Reference Manual Addendum, Rev. 1 2 Freescale Semiconductor How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 [email protected] Asia/Pacific: Freescale Semiconductor China Ltd. Exchange Building 23F No. 118 Jianguo Road Chaoyang District Beijing 100022 China +86 10 5879 8000 [email protected] For Literature Requests Only: Freescale Semiconductor Literature Distribution Center 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 [email protected] Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners.© Freescale Semiconductor, Inc. 2012. All rights reserved. MPC5533RMAD Rev. 1 04/2012 MPC5533 Microcontroller Reference Manual Devices Supported: MPC5533 Document Number: MPC5533RM Rev. 0 02/2010 How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 [email protected] Asia/Pacific: Freescale Semiconductor China Ltd. Exchange Building 23F No. 118 Jianguo Road Chaoyang District Beijing 100022 China +86 10 5879 8000 [email protected] Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or +1-303-675-2140 Fax: +1-303-675-2150 [email protected] Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2010. All rights reserved. MPC5533RM Rev. 0 02/2010 Chapter 1 Overview 1.1 1.2 1.3 1.4 1.5 1.6 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.1.1 MPC5500 Family Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 MPC5533 Features List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1.2.1 Operating Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1.2.2 e200z3 Core Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.2.3 Crossbar Switch (XBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 1.2.4 Enhanced Direct Memory Access (eDMA) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 1.2.5 Interrupt Controller (INTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 1.2.6 Frequency Modulated Phase-Locked Loop (FMPLL) . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 1.2.7 External Bus Interface (EBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 1.2.8 System Integration Unit (SIU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 1.2.9 Error Correction Status Module (ECSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 1.2.10 On-chip Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 1.2.11 On-chip Static RAM (SRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 1.2.12 Boot Assist Module (BAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 1.2.13 Enhanced Time Processor Unit (eTPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 1.2.14 Enhanced Queued A/D Converter (eQADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 1.2.15 Deserial Serial Peripheral Interface (DSPI) Module . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 1.2.16 Enhanced Serial Communication Interface (eSCI) Module . . . . . . . . . . . . . . . . . . . . . 1-13 1.2.17 FlexCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 1.2.18 Nexus Development Interface (NDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 1.2.19 IEEE 1149.1 JTAG controller (JTAGC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 1.2.20 On-chip Voltage Regulator Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 MPC5533 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 1.3.1 External Master Mode Operation Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17 Detailed Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18 1.4.1 e200z3 Core Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18 1.4.2 Crossbar Switch (XBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20 1.4.3 Enhanced Direct Memory Access (eDMA) Controller . . . . . . . . . . . . . . . . . . . . . . . . . 1-21 1.4.4 Interrupt Controller (INTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21 1.4.5 Frequency Modulated Phase-Locked Loop (FMPLL) . . . . . . . . . . . . . . . . . . . . . . . . . 1-21 1.4.6 External Bus Interface (EBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22 1.4.7 System Integration Unit (SIU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22 1.4.8 On-chip Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22 1.4.9 Static Random Access Memory (SRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22 1.4.10 Boot Assist Module (BAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23 1.4.11 Enhanced Time Processing Unit (eTPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23 1.4.12 Enhanced Queued Analog/Digital Converter (eQADC) . . . . . . . . . . . . . . . . . . . . . . . 1-24 1.4.13 Deserial/Serial Peripheral Interface (DSPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25 1.4.14 Enhanced System Communications Interface (eSCI) . . . . . . . . . . . . . . . . . . . . . . . . . 1-25 1.4.15 Flexible Controller Area Network (FlexCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25 1.4.16 Nexus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25 1.4.17 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27 Chip Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27 Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-29 MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor i Chapter 2 Signals 2.1 2.2 2.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 External Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.2.1 Multiplexed Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.2.2 Device Signals Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Detailed Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 2.3.1 Reset and Configuration Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 2.3.1.1 External Reset Input RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 2.3.1.2 External Reset Output RSTOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 2.3.1.3 FMPLL Mode Selection / External Interrupt Request / GPIO PLLCFG[0]_IRQ[4]_GPIO[208] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 2.3.1.4 FMPLL Mode Selection / External Interrupt Request / DSPI D / GPIO PLLCFG[1]_IRQ[5]_SOUTD_GPIO[209] . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 2.3.1.5 Reset Configuration Input / GPIO RSTCFG_GPIO[210] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 2.3.1.6 Reset Configuration / External Interrupt Request / GPIO BOOTCFG[0:1]_IRQ[2:3]_GPIO[211:212] . . . . . . . . . . . . . . . . . . . . . . . . 2-17 2.3.1.7 Weak Pull Configuration / GPIO WKPCFG_GPIO[213] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 2.3.2 External Bus Interface (EBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 2.3.2.1 External Chip Selects / External Address / GPIO CS[0]_ADDR[8]_GPIO[0] 2-17 2.3.2.2 External Chip Selects / External Address / GPIO CS[1:3]_ADDR[9:11]_GPIO[1:3] 2-17 2.3.2.3 External Address / GPIO ADDR[12:31]_GPIO[8:27] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 2.3.2.4 External Data / GPIO DATA[0:15]_GPIO[28:43] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 2.3.2.5 External Read/Write / GPIO RD_WR_GPIO[62] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 2.3.2.6 External Burst Data In Progress / GPIO BDIP_GPIO[63] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 2.3.2.7 External Write/Byte Enable / GPIO WE/BE[0:1]_GPIO[64:65] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 2.3.2.8 External Output Enable / GPIO OE_GPIO[68] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 2.3.2.9 External Transfer Start / GPIO TS_GPIO[69] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 2.3.2.10 External Transfer Acknowledge TA_GPIO[70] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 2.3.3 Nexus Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 2.3.3.1 Nexus Event In EVTI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 2.3.3.2 Nexus Event Out EVTO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 2.3.3.3 Nexus Message Clock Out MCKO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 2.3.3.4 Nexus Message Data Out MDO[3:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 2.3.3.5 Nexus Message Data Out / GPIO MPC5533 Microcontroller Reference Manual, Rev. 0 ii Freescale Semiconductor MDO[11:4]_GPIO[82:75] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 Nexus Message Start/End Out MSEO[1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 2.3.3.7 Nexus Ready Output RDY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 2.3.4.1 JTAG Test Clock Input TCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 2.3.4.2 JTAG Test Data Input TDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 2.3.4.3 JTAG Test Data Output TDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 2.3.4.4 JTAG Test Mode Select Input TMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 2.3.4.5 JTAG Compliance Input JCOMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 2.3.4.6 Test Mode Enable Input TEST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 Flexible Controller Area Network (FlexCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 2.3.5.1 FlexCAN A Transmit / GPIO CNTXA_GPIO[83] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 2.3.5.2 FlexCAN A Receive / GPIO CNRXA_GPIO[84] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 2.3.5.3 FlexCAN B Transmit / DSPI C Chip Select / GPIO CNTXB_PCSC[3]_GPIO[85] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 2.3.5.4 FlexCAN B Receive / DSPI C Chip Select / GPIO CNRXB_PCSC[4]_GPIO[86] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 2.3.5.5 FlexCAN C Transmit / DSPI D Chip Select / GPIO CNTXC_PCSD[3]_GPIO[87] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 2.3.5.6 FlexCAN C Receive / DSPI D Chip Select / GPIO CNRXC_PCSD[4]_GPIO[88] 2-21 Enhanced Serial Communications Interface (eSCI) . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 2.3.6.1 eSCI A Transmit / GPIO TXDA_GPIO[89] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 2.3.6.2 eSCI A Receive / GPIO RXDA_GPIO[90] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 2.3.6.3 eSCI B Transmit / DSPI D Chip Select / GPIO TXDB_PCSD[1]_GPIO[91] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 2.3.6.4 eSCI B Receive / DSPI D Chip Select / GPIO RXDB_PCSD[5]_GPIO[92] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 Deserial/Serial Peripheral Interface (DSPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 2.3.7.1 DSPI A Clock / DSPI C / GPIO SCKA_PCSC[1]_GPIO[93] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 2.3.7.2 DSPI A Input / DSPI C / GPIO SINA_PCSC[2]_GPIO[94] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 2.3.7.3 DSPI A Output / DSPI C / GPIO SOUTA_PCSC[5]_GPIO[95] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 2.3.7.4 DSPI A / DSPI D / GPIO PCSA[0]_PCSD[2]_GPIO[96] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 2.3.7.5 DSPI A / DSPI B / GPIO PCSA[1]_PCSB[2]_GPIO[97] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 2.3.7.6 DSPI A / DSPI D Clock / GPIO PCSA[2]_SCKD_GPIO[98] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23 2.3.7.7 DSPI A / DSPI D Data Input / GPIO 2.3.3.6 2.3.4 2.3.5 2.3.6 2.3.7 MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor iii PCSA[3]_SIND_GPIO[99] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23 DSPI A / DSPI D Data Output / GPIO PCSA[4]_SOUTD_GPIO[100] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23 2.3.7.9 DSPI A / DSPI B / GPIO PCSA[5]_PCSB[3]_GPIO[101] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23 2.3.7.10 DSPI B Clock / DSPI C Chip Select / GPIO SCKB_PCSC[1]_GPIO[102] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23 2.3.7.11 DSPI B Data Input / DSPI C Chip Select / GPIO SINB_PCSC[2]_GPIO[103] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23 2.3.7.12 DSPI B Data Output / DSPI C Chip Select / GPIO SOUTB_PCSC[5]_GPIO[104] 2-23 2.3.7.13 DSPI B Chip Select / DSPI D Chip Select / GPIO PCSB[0]_PCSD[2]_GPIO[105] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24 2.3.7.14 DSPI B Chip Select / DSPI D Chip Select / GPIO PCSB[1]_PCSD[0]_GPIO[106] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24 2.3.7.15 DSPI B Chip Select / DSPI C Data Output / GPIO PCSB[2]_SOUTC_GPIO[107] 2-24 2.3.7.16 DSPI B Chip Select / DSPI C Data Input / GPIO PCSB[3]_SINC_GPIO[108] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24 2.3.7.17 DSPI B Chip Select / DSPI C Clock / GPIO PCSB[4]_SCKC_GPIO[109] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24 2.3.7.18 DSPI B Chip Select / DSPI C Chip Select / GPIO PCSB[5]_PCSC[0]_GPIO[110] 2-24 Enhanced Queued Analog/Digital Converter (eQADC) . . . . . . . . . . . . . . . . . . . . . . . 2-25 2.3.8.1 Analog Input / Differential Analog Input AN[0]_DAN0+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25 2.3.8.2 Analog Input / Differential Analog Input AN[1]_DAN0– . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25 2.3.8.3 Analog Input / Differential Analog Input AN[2]_DAN1+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25 2.3.8.4 Analog Input / Differential Analog Input AN[3]_DAN1– . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25 2.3.8.5 Analog Input / Differential Analog Input AN[4]_DAN2+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25 2.3.8.6 Analog Input / Differential Analog Input AN[5]_DAN2– . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25 2.3.8.7 Analog Input / Differential Analog Input AN[6]_DAN3+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25 2.3.8.8 Analog Input / Differential Analog Input AN[7]_DAN3– . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26 2.3.8.9 Analog Input / Multiplexed Analog Input AN[8]_ANW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26 2.3.8.10 Analog Input / Multiplexed Analog Input AN[9]_ANX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26 2.3.8.11 Analog Input / Multiplexed Analog Input AN[10]_ANY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26 2.3.8.12 Analog Input / Multiplexed Analog Input AN[11]_ANZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26 2.3.8.13 Analog Input / Mux Address 0 / eQADC Serial Data Strobe AN[12]_MA[0]_SDS 2-26 2.3.8.14 Analog Input / Mux Address 1 / eQADC Serial Data Out AN[13]_MA[1]_SDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27 2.3.8.15 Analog Input / Mux Address 2 / eQADC Serial Data In AN[14]_MA[2]_SDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27 2.3.8.16 Analog Input / eQADC Free Running Clock AN[15]_FCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27 2.3.8.17 Analog Input 2.3.7.8 2.3.8 MPC5533 Microcontroller Reference Manual, Rev. 0 iv Freescale Semiconductor AN[16:39] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Reference High VRH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.8.19 Voltage Reference Low VRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.8.20 Reference Bypass Capacitor REFBYPC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Enhanced Time Processing Unit (eTPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.9.1 eTPU A TCR Clock / External Interrupt Request / GPIO TCRCLKA_IRQ[7]_GPIO[113] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.9.2 eTPU A Channel / eTPU A Channel (Output Only) / GPIO ETPUA[0:11]_ETPUA[12:23]_GPIO[114:125] . . . . . . . . . . . . . . . . . . . . . 2.3.9.3 eTPU A Channel / DSPI / GPIO ETPUA[12:19]_PCSDn_GPIO[126:133] . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.9.4 eTPU A Channel / External Interrupt Request / GPIO ETPUA[20:27]_IRQ[8:15]_GPIO[134:141] . . . . . . . . . . . . . . . . . . . . . . . 2.3.9.5 eTPU A Channels / DSPI C / GPIO ETPUA[28:31]_PCSC[1:4]_GPIO[142:145] . . . . . . . . . . . . . . . . . . . . . . . Enhanced Modular Input/Output System (eMIOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.10.1 eMIOS Channels / eTPU A Channels (Output Only) / GPIO EMIOS[0:9]_ETPUA[0:9]_GPIO[179:188] . . . . . . . . . . . . . . . . . . . . . . . . 2.3.10.2 eMIOS Channels / GPIO EMIOS[10:11]_GPIO[189:190] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.10.3 eMIOS Channel (Output Only) / DSPI C Data Output / GPIO EMIOS[12]_SOUTC_GPIO[191] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.10.4 eMIOS Channel (Output Only) / DSPI D Data Output / GPIO EMIOS[13]_SOUTD_GPIO192 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.10.5 eMIOS Channel (Output Only) / External Interrupt Request / GPIO EMIOS[14:15]_IRQ[0:1]_GPIO[193:194] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.10.6 eMIOS Channel (Output Only) / GPIO EMIOS[16:23]_GPIO[195:202] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.11.1 GPIO EMIOS[14:15]_GPIO[203:204] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.11.2 GPIO GPIO[206:207] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.12.1 Crystal Oscillator Output XTAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.12.2 Crystal Oscillator Input / External Clock Input EXTAL_EXTCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.12.3 System Clock Output CLKOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.12.4 Engineering Clock Output ENGCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power/Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.13.1 Voltage Regulator Control Supply Input VRC33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.13.2 Voltage Regulator Control Ground Input VRCVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.13.3 Voltage Regulator Control Output VRCCTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.13.4 eQADC Analog Supply 2-27 2.3.8.18 2.3.9 2.3.10 2.3.11 2.3.12 2.3.13 2-27 2-27 2-27 2-28 2-28 2-28 2-28 2-28 2-28 2-28 2-28 2-29 2-29 2-29 2-29 2-29 2-29 2-29 2-30 2-30 2-30 2-30 2-30 2-30 2-30 2-30 2-30 2-31 MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor v VDDAn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . eQADC Analog Ground Reference VSSAn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.13.6 Clock Synthesizer Power Input VDDSYN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.13.7 Clock Synthesizer Ground Input VSSSYN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.13.8 Flash Read Supply Input VFLASH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.13.9 Flash Program/Erase Supply Input VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.13.10 SRAM Standby Power Input VSTBY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.13.11 Internal Logic Supply Input VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.13.12 External I/O Supply Input VDDEn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.13.13 External I/O Supply Input VDDEHn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.13.14 Fixed 3.3 V Internal Supply Input VDD33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.13.15 Ground VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.14 I/O Power/Ground Segmentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . eTPU Pin Connections and Serialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.1 ETPUA[0:15] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.2 ETPUA[16:31] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31 2.3.13.5 2.4 2-31 2-31 2-31 2-31 2-31 2-31 2-31 2-32 2-32 2-32 2-32 2-32 2-33 2-33 2-35 Chapter 3 Core Complex (e200z3) 3.1 3.2 3.3 3.4 3.5 3.6 3.7 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2.1 e200z3 Core Features Not Supported in the Device . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Microarchitecture Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.3.1 Instruction Unit Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.3.2 Integer Unit Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.3.3 Load/Store Unit Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.3.4 e200 System Bus Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.3.5 MMU Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.3.6 Nexus 3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 Memory Management Unit (MMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.5.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.5.2 Translation Lookaside Buffer (TLB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.5.3 Translation Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.5.4 Permissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 Bus Interface Unit (BIU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 Core Registers and Programmer’s Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 3.7.1 PowerPC Book E Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 3.7.1.1 User-level Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 3.7.1.2 Supervisor-level Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 3.7.2 e200-specific Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 3.7.2.1 User-level Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 MPC5533 Microcontroller Reference Manual, Rev. 0 vi Freescale Semiconductor 3.7.2.2 Supervisor-level Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Processing Extension APU (SPE APU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.2 SPE Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9 Instruction Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9.1 SPE APU Simple and Complex Integer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9.2 SPE APU Scalar and Vector Floating Point Instructions . . . . . . . . . . . . . . . . . . . . . . . 3.9.3 SPE APU Load and Store Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10 Book E Instruction Extensions—VLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8 3-17 3-18 3-18 3-18 3-19 3-19 3-24 3-26 3-27 Chapter 4 Reset 4.1 4.2 4.3 4.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2.1 Reset Input (RESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2.2 Reset Output (RSTOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2.3 Reset Configuration (RSTCFG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.2.4 Weak Pull Configuration (WKPCFG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.2.5 Boot Configuration (BOOTCFG[0:1]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.3.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.3.1.1 Reset Status Register (SIU_RSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.3.1.2 System Reset Control Register (SIU_SRCR) . . . . . . . . . . . . . . . . . . . . . . 4-6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.4.1 Reset Vector Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.4.2 Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.4.2.1 FMPLL Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.4.2.2 Flash High Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.4.2.3 Reset Source Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.4.3 Reset Configuration and Configuration Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 4.4.3.1 RSTCFG Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 4.4.3.2 WKPCFG Pin (Reset Weak Pullup/Pulldown Configuration) . . . . . . . . . . 4-13 4.4.3.3 BOOTCFG[0:1] Pins (MCU Configuration) . . . . . . . . . . . . . . . . . . . . . . . 4-13 4.4.3.4 PLLCFG[0:1] Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 4.4.3.5 Reset Configuration Half Word (RCHW) . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 4.4.4 Reset Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17 4.4.5 Reset Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19 Chapter 5 Peripheral Bridge 5.1 5.2 5.3 5.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.2.1 Access Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.1.1 Master Privilege Control Register (PBRIDGE_x_MPCR) . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.1 Peripheral Write Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.1.1 Read Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5-1 5-1 5-1 5-2 5-2 5-2 5-2 5-2 5-3 5-5 5-5 5-5 MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor vii 5.4.2 5.4.1.2 Write Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 5.4.1.3 Buffered Write Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 General Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 Chapter 6 System Integration Unit (SIU) 6.1 6.2 6.3 6.4 6.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 6.2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6.2.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 6.3.1 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 6.3.1.1 Reset Input (RESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 6.3.1.2 Reset Output (RSTOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 6.3.1.3 General-Purpose I/O Pins (GPIO[0:213]) . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 6.3.1.4 Boot Configuration Pins (BOOTCFG[0:1]) . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 6.3.1.5 I/O Pin Weak Pull Up Reset Configuration Pin (WKPCFG) . . . . . . . . . . . . 6-6 6.3.1.6 External Interrupt Request Input Pins (IRQ[0:5, 7:15]) . . . . . . . . . . . . . . . 6-7 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 6.4.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 6.4.1.1 MCU ID Register (SIU_MIDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 6.4.1.2 Reset Status Register (SIU_RSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12 6.4.1.3 System Reset Control Register (SIU_SRCR) . . . . . . . . . . . . . . . . . . . . . 6-14 6.4.1.4 External Interrupt Status Register (SIU_EISR) . . . . . . . . . . . . . . . . . . . . 6-15 6.4.1.5 Interrupt Request Enable Register (SIU_DIRER) . . . . . . . . . . . . . . . . . . 6-16 6.4.1.6 DMA/Interrupt Request Select Register (SIU_DIRSR) . . . . . . . . . . . . . . 6-17 6.4.1.7 Overrun Status Register (SIU_OSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18 6.4.1.8 Overrun Request Enable Register (SIU_ORER) . . . . . . . . . . . . . . . . . . . 6-19 6.4.1.9 IRQ Rising-Edge Event Enable Register (SIU_IREER) . . . . . . . . . . . . . . 6-20 6.4.1.10 IRQ Falling-Edge Event Enable Register (SIU_IFEER) . . . . . . . . . . . . . 6-21 6.4.1.11 IRQ Digital Filter Register (SIU_IDFR) . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21 6.4.1.12 Pad Configuration Registers (SIU_PCR) . . . . . . . . . . . . . . . . . . . . . . . . . 6-22 6.4.1.13 GPIO Pin Data Output Registers 0–213 (SIU_GPDOn) . . . . . . . . . . . . . 6-64 6.4.1.14 GPIO Pin Data Input Registers 0–213 (SIU_GPDIn) . . . . . . . . . . . . . . . . 6-65 6.4.1.15 eQADC Trigger Input Select Register (SIU_ETISR) . . . . . . . . . . . . . . . . 6-65 6.4.1.16 External IRQ Input Select Register (SIU_EIISR) . . . . . . . . . . . . . . . . . . . 6-67 6.4.1.17 DSPI Input Select Register (SIU_DISR) . . . . . . . . . . . . . . . . . . . . . . . . . 6-69 6.4.1.18 Chip Configuration Register (SIU_CCR) . . . . . . . . . . . . . . . . . . . . . . . . . 6-71 6.4.1.19 External Clock Control Register (SIU_ECCR) . . . . . . . . . . . . . . . . . . . . . 6-72 6.4.1.20 Compare A High Register (SIU_CARH) . . . . . . . . . . . . . . . . . . . . . . . . . 6-73 6.4.1.21 Compare A Low Register (SIU_CARL) . . . . . . . . . . . . . . . . . . . . . . . . . . 6-74 6.4.1.22 Compare B High Register (SIU_CBRH) . . . . . . . . . . . . . . . . . . . . . . . . . 6-74 6.4.1.23 Compare B Low Register (SIU_CBRL) . . . . . . . . . . . . . . . . . . . . . . . . . . 6-75 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-75 6.5.1 System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-75 6.5.1.1 Boot Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-75 6.5.1.2 Pad Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-76 6.5.2 Reset Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-76 6.5.2.1 RESET Pin Glitch Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-76 6.5.3 External Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-77 6.5.4 GPIO Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-78 6.5.5 Internal Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-78 6.5.5.1 eQADC External Trigger Input Multiplexing . . . . . . . . . . . . . . . . . . . . . . . 6-78 MPC5533 Microcontroller Reference Manual, Rev. 0 viii Freescale Semiconductor 6.5.5.2 6.5.5.3 SIU External Interrupt Input Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . 6-79 Multiplexed Inputs for DSPI Multiple Transfer Operation . . . . . . . . . . . . . 6-79 Chapter 7 Error Correction Status Module (ECSM) 7.1 7.2 7.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.1.1 Types of ECC Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.1.2 ECC Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 7.2.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 7.2.1.1 Software Watchdog Timer Registers: Control, Service, and Interrupt (ECSM_SWTCR, ECSM_SWTSR, and ECSM_SWTIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 7.2.1.2 ECC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 7.2.1.3 ECC Configuration Register (ECSM_ECR) . . . . . . . . . . . . . . . . . . . . . . . . 7-5 7.2.1.4 ECC Status Register (ECSM_ESR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 7.2.1.5 ECC Error Generation Register (ECSM_EEGR) . . . . . . . . . . . . . . . . . . . . 7-7 7.2.1.6 Flash ECC Address Register (ECSM_FEAR) . . . . . . . . . . . . . . . . . . . . . . 7-8 7.2.1.7 Flash ECC Master Number Register (ECSM_FEMR) . . . . . . . . . . . . . . . . 7-9 7.2.1.8 Flash ECC Attributes Register (ECSM_FEAT) . . . . . . . . . . . . . . . . . . . . 7-10 7.2.1.9 Flash ECC Data High Register (ECSM_FEDRH) . . . . . . . . . . . . . . . . . . 7-11 7.2.1.10 Flash ECC Data Low Registers (ECSM_FEDRL) . . . . . . . . . . . . . . . . . . 7-11 7.2.1.11 SRAM ECC Address Register (ECSM_REAR) . . . . . . . . . . . . . . . . . . . . 7-12 7.2.1.12 SRAM ECC Master Number Register (ECSM_REMR) . . . . . . . . . . . . . . 7-13 7.2.1.13 SRAM ECC Attributes Register (ECSM_REAT) . . . . . . . . . . . . . . . . . . . 7-14 7.2.1.14 SRAM ECC Data High Register (ECSM_REDRH) . . . . . . . . . . . . . . . . . 7-15 7.2.1.15 SRAM ECC Data Low Registers (ECSM_REDRL) . . . . . . . . . . . . . . . . . 7-15 Initialization and Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16 Chapter 8 Crossbar Switch (XBAR) 8.1 8.2 8.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 8.2.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 8.2.1.1 Master Priority Registers (XBAR_MPRn) . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 8.2.1.2 Slave General-Purpose Control Registers (XBAR_SGPCRn) . . . . . . . . . . 8-6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8 8.3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8 8.3.2 General Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8 8.3.3 Master Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9 8.3.4 Slave Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9 8.3.5 Priority Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10 8.3.6 Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10 8.3.6.1 Fixed Priority Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10 8.3.6.2 Round-Robin Priority Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10 Chapter 9 Enhanced Direct Memory Access (eDMA) 9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor ix 9.1.2 9.2 9.3 9.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 9.1.2.1 Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 9.1.2.2 Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 9.2.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 9.2.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6 9.2.2.1 eDMA Control Register (EDMA_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6 9.2.2.2 eDMA Error Status Register (EDMA_ESR) . . . . . . . . . . . . . . . . . . . . . . . . 9-8 9.2.2.3 eDMA Enable Error Interrupt Register (EDMA_EEIRL) . . . . . . . . . . . . . . 9-11 9.2.2.4 eDMA Set Enable Request Register (EDMA_SERQR) . . . . . . . . . . . . . . 9-11 9.2.2.5 eDMA Clear Enable Request Register (EDMA_CERQR) . . . . . . . . . . . . 9-12 9.2.2.6 eDMA Set Enable Error Interrupt Register (EDMA_SEEIR) . . . . . . . . . . 9-13 9.2.2.7 eDMA Clear Enable Error Interrupt Register (EDMA_CEEIR) . . . . . . . . 9-13 9.2.2.8 eDMA Clear Interrupt Request Register (EDMA_CIRQR) . . . . . . . . . . . . 9-14 9.2.2.9 eDMA Clear Error Register (EDMA_CER) . . . . . . . . . . . . . . . . . . . . . . . 9-14 9.2.2.10 eDMA Set START Bit Register (EDMA_SSBR) . . . . . . . . . . . . . . . . . . . 9-15 9.2.2.11 eDMA Clear DONE Status Bit Register (EDMA_CDSBR) . . . . . . . . . . . . 9-16 9.2.2.12 eDMA Interrupt Request Register (EDMA_IRQRL) . . . . . . . . . . . . . . . . . 9-16 9.2.2.13 eDMA Error Register (EDMA_ERL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17 9.2.2.14 DMA Hardware Request Status (EDMA_HRSL) . . . . . . . . . . . . . . . . . . . 9-18 9.2.2.15 eDMA Channel n Priority Registers (EDMA_CPRn) . . . . . . . . . . . . . . . . 9-19 9.2.2.16 Transfer Control Descriptor (TCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-27 9.3.1 eDMA Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-27 9.3.2 eDMA Basic Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-29 9.3.3 eDMA Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-31 Initialization and Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-35 9.4.1 eDMA Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-35 9.4.2 DMA Programming Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-37 9.4.3 DMA Request Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-37 9.4.4 DMA Arbitration Mode Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-38 9.4.4.1 Fixed-Group Arbitration and Fixed-Channel Arbitration . . . . . . . . . . . . . . 9-38 9.4.4.2 Round-Robin Group Arbitration, Fixed-Channel Arbitration . . . . . . . . . . 9-39 9.4.4.3 Round-Robin Group Arbitration, Round-Robin Channel Arbitration . . . . 9-39 9.4.4.4 Fixed-Group Arbitration, Round-Robin Channel Arbitration . . . . . . . . . . 9-39 9.4.5 DMA Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-40 9.4.5.1 Single Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-40 9.4.5.2 Multiple Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-41 9.4.5.3 Modulo Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-43 9.4.6 TCD Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-43 9.4.6.1 Minor Loop Complete . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-43 9.4.6.2 Active Channel TCD Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-44 9.4.6.3 Preemption Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-44 9.4.7 Channel Linking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-44 9.4.8 Dynamic Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-46 9.4.8.1 Dynamic Channel Linking and Dynamic Scatter/Gather . . . . . . . . . . . . . 9-46 Chapter 10 Interrupt Controller (INTC) 10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10-1 10-2 10-4 MPC5533 Microcontroller Reference Manual, Rev. 0 x Freescale Semiconductor 10.2 10.3 10.4 10.5 10.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 10.1.4.1 Software Vector Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 10.1.4.2 Hardware Vector Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8 10.3.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8 10.3.1.1 INTC Module Configuration Register (INTC_MCR) . . . . . . . . . . . . . . . . . 10-9 10.3.1.2 INTC Current Priority Register (INTC_CPR) . . . . . . . . . . . . . . . . . . . . . . 10-9 10.3.1.3 INTC Interrupt Acknowledge Register (INTC_IACKR) . . . . . . . . . . . . . 10-10 10.3.1.4 INTC End-of-Interrupt Register (INTC_EOIR) . . . . . . . . . . . . . . . . . . . . 10-11 10.3.1.5 INTC Software Set/Clear Interrupt Registers (INTC_SSCIR[0–7]) . . . . 10-12 10.3.1.6 INTC Priority Select Registers (INTC_PSR[0–50, 67–130, 136–146, 152–193]) 10-12 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13 10.4.1 Interrupt Request Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13 10.4.1.1 Peripheral Interrupt Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-20 10.4.1.2 Software Configurable Interrupt Requests . . . . . . . . . . . . . . . . . . . . . . . 10-21 10.4.1.3 Unique Vector for Each Interrupt Request Source . . . . . . . . . . . . . . . . 10-21 10.4.2 Priority Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-21 10.4.2.1 Current Priority and Preemption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-21 10.4.2.2 LIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-22 10.4.3 Details on Handshaking with Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-23 10.4.3.1 Software Vector Mode Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-23 10.4.3.2 Hardware Vector Mode Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . 10-24 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-25 10.5.1 Initialization Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-25 10.5.2 Interrupt Exception Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-26 10.5.2.1 Software Vector Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-26 10.5.2.2 Hardware Vector Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-27 10.5.3 ISR, RTOS, and Task Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-27 10.5.4 Order of Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-28 10.5.5 Priority Ceiling Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-29 10.5.5.1 Elevating Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-29 10.5.5.2 Ensuring Coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-29 10.5.6 Selecting Priorities According to Request Rates and Deadlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-30 10.5.7 Software Settable Interrupt Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-30 10.5.7.1 Scheduling a Lower Priority Portion of an ISR . . . . . . . . . . . . . . . . . . . . 10-31 10.5.7.2 Scheduling an ISR on Another Processor . . . . . . . . . . . . . . . . . . . . . . . 10-31 10.5.8 Lowering Priority Within an ISR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-31 10.5.9 Negating an Interrupt Request Outside of its ISR . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-32 10.5.9.1 Negating an Interrupt Request as a Side Effect of an ISR . . . . . . . . . . 10-32 10.5.9.2 Negating Multiple Interrupt Requests in One ISR . . . . . . . . . . . . . . . . . 10-32 10.5.9.3 Proper Setting of Interrupt Request Priority . . . . . . . . . . . . . . . . . . . . . . 10-32 10.5.10 Examining LIFO Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-33 Chapter 11 Frequency Modulated Phase Locked Loop and System Clocks (FMPLL) 11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.1 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.1.1 FMPLL and Clock Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.1.2 FMPLL Bypass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.1.3 FMPLL External Reference Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.1.4 FMPLL Crystal Reference Mode Without FM . . . . . . . . . . . . . . . . . . . . . 11-1 11-1 11-2 11-3 11-4 11-5 MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor xi 11.1.1.5 FMPLL Crystal Reference Mode With FM . . . . . . . . . . . . . . . . . . . . . . . . 11-6 11.1.1.6 FMPLL Dual-Controller Mode (1:1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 11.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8 11.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8 11.1.4 FMPLL Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9 11.1.4.1 Crystal Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9 11.1.4.2 External Reference Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11 11.1.4.3 Bypass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11 11.1.4.4 Dual-Controller Mode (1:1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11 11.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12 11.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12 11.3.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12 11.3.1.1 Synthesizer Control Register (FMPLL_SYNCR) . . . . . . . . . . . . . . . . . . 11-12 11.3.1.2 Synthesizer Status Register (FMPLL_SYNSR) . . . . . . . . . . . . . . . . . . . 11-16 11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19 11.4.1 Clock Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19 11.4.1.1 Software Controlled Power Management/Clock Gating . . . . . . . . . . . . 11-19 11.4.1.2 Clock Dividers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-20 11.4.2 Clock Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21 11.4.2.1 Input Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21 11.4.2.2 Reduced Frequency Divider (RFD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21 11.4.2.3 Programmable Frequency Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21 11.4.2.4 FMPLL Lock Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21 11.4.2.5 FMPLL Loss-of-Lock Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-22 11.4.2.6 Loss-of-Clock Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-22 11.4.3 Clock Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-24 11.4.3.1 Programming System Clock Frequency Without Frequency Modulation 11-24 11.4.3.2 Programming System Clock Frequency with Frequency Modulation . . 11-26 11.4.3.3 FM Calibration Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-28 Chapter 12 External Bus Interface (EBI) 12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.3.1 Single Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.3.2 External Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.3.3 Module Disable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.3.4 Configurable Bus Speed Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.3.5 16-Bit Data Bus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.3.6 Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.1 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.1.1 Address Lines 8–31 (ADDR[8:31]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.1.2 Burst Data in Progress (BDIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.1.3 Clockout (CLKOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.1.4 Chip Selects 0–3 (CS[0:3]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.1.5 Data Lines 0–15 (DATA[0:15]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.1.6 Output Enable (OE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.1.7 Read/Write (RD_WR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.1.8 Transfer Acknowledge (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.1.9 Transfer Start (TS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 12-1 12-3 12-4 12-4 12-4 12-4 12-4 12-4 12-5 12-5 12-6 12-6 12-6 12-6 12-6 12-6 12-7 12-7 12-7 12-7 MPC5533 Microcontroller Reference Manual, Rev. 0 xii Freescale Semiconductor 12.2.1.10 Write/Byte Enables (WE/BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7 12.2.2 Signal Function and Direction by Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8 12.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9 12.3.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9 12.3.1.1 Writing EBI Registers While a Transaction is in Progress . . . . . . . . . . . . 12-9 12.3.1.2 Separate Input Clock for Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10 12.3.1.3 EBI Module Configuration Register (EBI_MCR) . . . . . . . . . . . . . . . . . . 12-10 12.3.1.4 EBI Transfer Error Status Register (EBI_TESR) . . . . . . . . . . . . . . . . . . 12-11 12.3.1.5 EBI Bus Monitor Control Register (EBI_BMCR) . . . . . . . . . . . . . . . . . . 12-12 12.3.1.6 EBI Base Registers 0–3 (EBI_BRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-13 12.3.1.7 EBI Option Registers 0–3 (EBI_ORn) . . . . . . . . . . . . . . . . . . . . . . . . . . 12-14 12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-15 12.4.1 External Bus Interface Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-15 12.4.1.1 32-Bit Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-15 12.4.1.2 16-Bit Data Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-16 12.4.1.3 Support for External Master Accesses to Internal Addresses . . . . . . . . 12-16 12.4.1.4 Memory Controller with Support for Various Memory Types . . . . . . . . . 12-16 12.4.1.5 Burst Support (Wrapped Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-18 12.4.1.6 Bus Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-18 12.4.1.7 Port Size Configuration per Chip Select . . . . . . . . . . . . . . . . . . . . . . . . 12-19 12.4.1.8 Configurable Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-19 12.4.1.9 Four Chip Select (CS[0:3]) Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-19 12.4.1.10 Two Write/Byte Enable (WE/BE) Signals . . . . . . . . . . . . . . . . . . . . . . . 12-19 12.4.1.11 Optional Automatic CLKOUT Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-20 12.4.1.12 Compatible with MPC500 External Bus (with Some Limitations) . . . . . 12-20 12.4.2 External Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-20 12.4.2.1 External Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-20 12.4.2.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-20 12.4.2.3 Basic Transfer Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-20 12.4.2.4 Single-Beat Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-21 12.4.2.5 Burst Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-29 12.4.2.6 Small Accesses (Small Port Size and Short Burst Length) . . . . . . . . . . 12-34 12.4.2.7 Size, Alignment, and Packaging on Transfers . . . . . . . . . . . . . . . . . . . . 12-36 12.4.2.8 Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-38 12.4.2.9 Termination Signals Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-39 12.4.2.10 Bus Operation in External Master Mode . . . . . . . . . . . . . . . . . . . . . . . . 12-39 12.4.2.11 Non-Chip-Select Burst in 16-bit Data Bus Mode . . . . . . . . . . . . . . . . . . 12-45 12.5 Initialization and Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-47 12.5.1 Booting from External Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-47 12.5.2 Running with SDR (Single Data Rate) Burst Memories . . . . . . . . . . . . . . . . . . . . . . 12-47 12.5.3 Using Asynchronous Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-48 12.5.3.1 Example Wait State Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-48 12.5.3.2 Timing and Connections for Asynchronous Memories . . . . . . . . . . . . . 12-48 12.5.4 Connecting an MCU to Multiple Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-50 12.5.5 Dual-MCU Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-50 12.5.5.1 Connecting 16-bit MCU to 32-bit MCU (Master and Slave) . . . . . . . . . . 12-50 12.5.5.2 Arbiting a Master and Slave configuration . . . . . . . . . . . . . . . . . . . . . . . 12-51 12.5.5.3 Setting the Transfer Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-51 12.5.5.4 Acknowledging a Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-51 12.5.5.5 Detecting a Transfer Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-51 12.5.5.6 Detecting Burst Data in Progress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-51 12.5.6 Summary of Differences from MPC500 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-52 MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor xiii Chapter 13 Flash Memory 13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3 13.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3 13.1.4.1 User Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3 13.1.4.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3 13.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 13.2.1 Voltage for Flash Only VFLASH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 13.2.2 Program and Erase Voltage for Flash Only VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 13.3 Memory Map/Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 13.3.1 Flash Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6 13.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7 13.3.2.1 Module Configuration Register FLASH_MCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7 13.3.2.2 Low/Mid Address Space Block Locking Register FLASH_LMLR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-12 13.3.2.3 High Address Space Block Locking Register (FLASH_HLR) . . . . . . . . 13-13 13.3.2.4 Secondary Low/Mid Address Space Block Locking Register FLASH_SLMLR 13-14 13.3.2.5 Low/Mid Address Space Block Select Register FLASH_LMSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-15 13.3.2.6 High Address Space Block Select Register FLASH_HSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-15 13.3.2.7 Address Register FLASH_AR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-16 13.3.2.8 Flash Bus Interface Unit Control Register FLASH_BIUCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-16 13.3.2.9 Flash Bus Interface Unit Access Protection Register FLASH_BIUAPR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-20 13.3.2.10 Flash Bus Interface Unit Control Register 2 FLASH_BIUCR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-21 13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-22 13.4.1 Flash Bus Interface Unit (FBIU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-22 13.4.1.1 FBIU Basic Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-23 13.4.1.2 FBIU Access Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-23 13.4.1.3 Flash Read Cycles—Buffer Miss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-23 13.4.1.4 Flash Read Cycles—Buffer Hit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-23 13.4.1.5 Flash Access Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-23 13.4.1.6 Flash Error Response Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-23 13.4.1.7 FBIU Line Read Buffers and Prefetch Operation . . . . . . . . . . . . . . . . . . 13-24 13.4.1.8 Prefetch Triggering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-24 13.4.1.9 FBIU Buffer Invalidation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-25 13.4.1.10 Flash Wait-state Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-25 13.4.2 Flash Memory Array: User Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-25 13.4.2.1 Flash Read and Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-25 13.4.2.2 Read While Write (RWW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-26 13.4.2.3 Flash Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-26 13.4.2.4 Flash Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-29 MPC5533 Microcontroller Reference Manual, Rev. 0 xiv Freescale Semiconductor 13.4.2.5 Flash Shadow Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4.2.6 Censorship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4.3 Flash Memory Array: Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4.4 Flash Memory Array: Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-32 13-32 13-35 13-35 Chapter 14 Internal Static RAM (SRAM) 14.1 14.2 14.3 14.4 14.5 14.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SRAM Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SRAM ECC Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.6.1 Access Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.6.2 Reset Effects on SRAM Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.7 Initialization and Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.7.1 Example Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 14-1 14-1 14-2 14-2 14-2 14-3 14-3 14-3 14-4 Chapter 15 Boot Assist Module (BAM) 15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 15.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 15.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2 15.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2 15.1.3.1 Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2 15.1.3.2 Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2 15.1.3.3 Internal Boot Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2 15.1.3.4 External Boot Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2 15.1.3.5 Serial Boot Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3 15.2 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3 15.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3 15.3.1 BAM Program Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3 15.3.2 BAM Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4 15.3.2.1 Boot Mode Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6 15.3.2.2 Internal Boot Mode Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7 15.3.2.3 External Boot Modes Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8 15.3.2.4 Serial Boot Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9 15.3.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-17 Chapter 16 Enhanced Time Processing Unit (eTPU) 16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.1.1 eTPU Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.3 eTPU Operation Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.3.1 eTPU Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.3.1.1 Time Bases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.3.1.2 eTPU Timer Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.3.2 Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.3.3 Shared Data Memory (SDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.3.4 Task Scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.3.5 Microengine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.3.6 Debug Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 16-1 16-2 16-3 16-4 16-4 16-5 16-5 16-6 16-7 16-8 16-8 MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor xv 16.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-8 16.5 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-10 16.5.1 User Configuration Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-10 16.5.2 User Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-11 16.5.3 Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-11 16.5.4 Module Disable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-11 16.6 eTPU Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-11 16.7 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-11 16.8 eTPU Detailed Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-11 16.8.1 Output and Input Channel Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-11 16.8.2 Time Base Clock Signal (TCRCLKA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13 16.8.2.1 Time Base Clock Signal (TCRCLKA) . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13 16.9 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-14 16.9.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-14 16.9.2 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-14 16.9.2.1 System Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-17 16.10 Time Base Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-24 16.10.1 eTPU Time Base Configuration Register (ETPU_TBCR) . . . . . . . . . . . . . . . . . . . . . 16-24 16.10.2 eTPU Time Base 1 (TCR1) Visibility Register (ETPU_TB1R) . . . . . . . . . . . . . . . . . 16-27 16.10.3 eTPU Time Base 2 (TCR2) Visibility Register (ETPU_TB2R) . . . . . . . . . . . . . . . . . 16-27 16.10.4 STAC Bus Configuration Register (ETPU_REDCR) . . . . . . . . . . . . . . . . . . . . . . . . . 16-28 16.10.5 Global Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-30 16.10.5.1 eTPU Channel Interrupt Status Register (ETPU_CISR) . . . . . . . . . . . . 16-30 16.10.5.2 eTPU Channel Data Transfer Request Status Register (ETPU_CDTRSR) 16-31 16.10.5.3 eTPU Channel Interrupt Overflow Status Register (ETPU_CIOSR) . . . 16-31 16.10.5.4 eTPU Channel Data Transfer Request Overflow Status Register (ETPU_CDTROSR) 16-33 16.10.5.5 eTPU Channel Interrupt Enable Register (ETPU_CIER) . . . . . . . . . . . . 16-34 16.10.5.6 eTPU Channel Data Transfer Request Enable Register (ETPU_CDTRER) 16-35 16.10.5.7 eTPU Channel Pending Service Status Register (ETPU_CPSSR) . . . . 16-36 16.10.6 Channel Configuration and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-37 16.10.6.1 Channel Registers Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-38 16.10.6.2 eTPU Channel n Configuration Register (ETPU_CnCR) . . . . . . . . . . . . 16-38 16.10.6.3 eTPU Channel n Status Control Register (ETPU_CnSCR) . . . . . . . . . . 16-40 16.11 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-42 16.12 Initialization and Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-42 Chapter 17 Enhanced Queued Analog-to-Digital Converter (eQADC) 17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 17.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2 17.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2 17.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 17.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5 17.1.4.1 Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5 17.1.4.2 Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5 17.1.4.3 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6 17.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-7 17.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-9 17.3.1 eQADC Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-10 17.3.2 eQADC Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-12 17.3.2.1 eQADC Module Configuration Register (EQADC_MCR) . . . . . . . . . . . 17-12 17.3.2.2 eQADC Null Message Send Format Register (EQADC_NMSFR) . . . . 17-13 MPC5533 Microcontroller Reference Manual, Rev. 0 xvi Freescale Semiconductor 17.3.2.3 17.3.2.4 17.3.2.5 17.3.2.6 17.3.2.7 17.3.2.8 17.3.2.9 17.3.2.10 eQADC CFIFO Push Registers 0–5 (EQADC_CFPRn) . . . . . . . . . . . . 17-15 eQADC Result FIFO Pop Registers 0–5 (EQADC_RFPRn) . . . . . . . . . 17-16 eQADC CFIFO Control Registers 0–5 (EQADC_CFCRn) . . . . . . . . . . . 17-17 eQADC Interrupt and eDMA Control Registers 0–5 (EQADC_IDCRn) . 17-18 eQADC FIFO and Interrupt Status Registers 0–5 (EQADC_FISRn) . . . 17-21 eQADC CFIFO Transfer Counter Registers 0–5 (EQADC_CFTCRn) . . 17-25 eQADC CFIFO Status Snapshot Registers 0–2 . . . . . . . . . . . . . . . . . . 17-25 eQADC CFIFO Status Register EQADC_CFSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-29 17.3.2.11 eQADC SSI Control Register EQADC_SSICR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-30 17.3.2.12 eQADC SSI Receive Data Register EQADC_SSIRDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-32 17.3.2.13 eQADC CFIFO Registers (EQADC_CF[0–5]Rn) . . . . . . . . . . . . . . . . . . 17-32 17.3.2.14 eQADC RFIFO Registers (EQADC_RF[0–5]Rn) . . . . . . . . . . . . . . . . . . 17-34 17.3.3 On-Chip ADC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-35 17.3.3.1 ADC0 Control Register (ADC0_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-35 17.3.3.2 ADC Time Stamp Control Register (ADC_TSCR) . . . . . . . . . . . . . . . . . 17-37 17.3.3.3 ADC Time Base Counter Registers (ADC_TBCR) . . . . . . . . . . . . . . . . 17-38 17.3.3.4 ADC Gain Calibration Constant Register (ADC0_GCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-39 17.3.3.5 ADC Offset Calibration Constant Register (ADC0_OCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-40 17.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-40 17.4.1 Data Flow in the eQADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-41 17.4.1.1 Assumptions/Requirements Regarding the External Device . . . . . . . . . 17-43 17.4.1.2 Message Format in eQADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-44 17.4.2 Command and Result Queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-56 17.4.3 eQADC Command FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-56 17.4.3.1 CFIFO Basic Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-56 17.4.3.2 CFIFO Prioritization and Command Transfer . . . . . . . . . . . . . . . . . . . . 17-60 17.4.3.3 External Trigger from eTPU Channels . . . . . . . . . . . . . . . . . . . . . . . . . . 17-63 17.4.3.4 CFIFO Scan Trigger Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-64 17.4.3.5 CFIFO and Trigger Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-69 17.4.4 Result FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-79 17.4.4.1 RFIFO Basic Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-79 17.4.4.2 Distributing Result Data into RFIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-82 17.4.5 On-Chip ADC Configuration and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-83 17.4.5.1 Enabling and Disabling the on-chip ADC . . . . . . . . . . . . . . . . . . . . . . . . 17-83 17.4.5.2 ADC Clock and Conversion Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-84 17.4.5.3 Time Stamp Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-86 17.4.5.4 ADC Calibration Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-86 17.4.5.5 ADC Control Logic Overview and Command Execution . . . . . . . . . . . . 17-88 17.4.6 Internal and External Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-91 17.4.6.1 Channel Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-91 17.4.6.2 External Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-93 17.4.7 eQADC eDMA or Interrupt Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-95 17.4.8 eQADC Synchronous Serial Interface (SSI) Submodule . . . . . . . . . . . . . . . . . . . . . 17-98 17.4.8.1 eQADC SSI Data Transmission Protocol . . . . . . . . . . . . . . . . . . . . . . . 17-99 17.4.8.2 Baud Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-100 17.4.9 Analog Submodule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-103 17.4.9.1 Reference Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-103 17.4.9.2 Analog-to-Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-103 MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor xvii 17.5 Initialization and Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.5.1 Multiple Queues Control Setup Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.5.1.1 Initialization of the On-Chip ADC and an External Device . . . . . . . . . . 17.5.1.2 Configuring eQADC for Applications . . . . . . . . . . . . . . . . . . . . . . . . . . 17.5.2 eQADC to eDMA Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.5.2.1 Command Queue and CFIFO Transfers . . . . . . . . . . . . . . . . . . . . . . . 17.5.2.2 Receive Queue/RFIFO Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.5.3 Sending Immediate Command Setup Example . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.5.4 Modifying Queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.5.5 Command Queue and Result Queue Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.5.6 ADC Result Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.5.6.1 MAC Configuration Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.5.6.2 Example Calculation of Calibration Constants . . . . . . . . . . . . . . . . . . . 17.5.6.3 Quantization Error Reduction During Calibration . . . . . . . . . . . . . . . . . 17.5.7 eQADC versus QADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-105 17-105 17-106 17-107 17-109 17-109 17-110 17-110 17-111 17-112 17-113 17-114 17-115 17-115 17-116 Chapter 18 Deserial Serial Peripheral Interface (DSPI) 18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 18.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2 18.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2 18.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3 18.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-5 18.1.4.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-5 18.1.4.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-5 18.1.4.3 Module Disable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-5 18.1.4.4 Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-5 18.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-6 18.2.1 Signal Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-6 18.2.2 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-6 18.2.2.1 Peripheral Chip Select / Slave Select PCSx[0]_SS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-6 18.2.2.2 Peripheral Chip Selects 1–3 PCSx[1:3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-6 18.2.2.3 Peripheral Chip Select 4 / Master Trigger PCSx[4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7 18.2.2.4 Peripheral Chip Select 5 / Peripheral Chip Select Strobe PCSx[5]_PCSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7 18.2.2.5 Serial Input (SINx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7 18.2.2.6 Serial Output (SOUTx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7 18.2.2.7 Serial Clock (SCKx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7 18.2.2.8 Internal Hardware Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7 18.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7 18.3.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7 18.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-9 18.3.2.1 DSPI Module Configuration Register (DSPIx_MCR) . . . . . . . . . . . . . . . . 18-9 18.3.2.2 DSPI Transfer Count Register (DSPIx_TCR) . . . . . . . . . . . . . . . . . . . . 18-12 18.3.2.3 DSPI Clock and Transfer Attributes Registers 0–7 (DSPIx_CTARn) . . 18-12 18.3.2.4 DSPI Status Register (DSPIx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-19 18.3.2.5 DSPI DMA and Interrupt Request Select and Enable Register (DSPIx_RSER) 18-21 18.3.2.6 DSPI PUSH TX FIFO Register (DSPIx_PUSHR) . . . . . . . . . . . . . . . . . 18-23 18.3.2.7 DSPI POP RX FIFO Register (DSPIx_POPR) . . . . . . . . . . . . . . . . . . . 18-25 18.3.2.8 DSPI Transmit FIFO Registers 0–3 (DSPIx_TXFRn) . . . . . . . . . . . . . . 18-26 MPC5533 Microcontroller Reference Manual, Rev. 0 xviii Freescale Semiconductor 18.3.2.9 DSPI Receive FIFO Registers 0–3 (DSPIx_RXFRn) . . . . . . . . . . . . . . . 18.3.2.10 DSPI DSI Configuration Register (DSPIx_DSICR) . . . . . . . . . . . . . . . . 18.3.2.11 DSPI DSI Serialization Data Register (DSPIx_SDR) . . . . . . . . . . . . . . . 18.3.2.12 DSPI DSI Alternate Serialization Data Register (DSPIx_ASDR) . . . . . . 18.3.2.13 DSPI DSI Transmit Comparison Register (DSPIx_COMPR) . . . . . . . . . 18.3.2.14 DSPI DSI Deserialization Data Register (DSPIx_DDR) . . . . . . . . . . . . 18.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.4.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.4.1.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.4.1.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.4.1.3 Module Disable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.4.1.4 Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.4.2 Start and Stop of DSPI Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.4.3 Serial Peripheral Interface (SPI) Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.4.3.1 SPI Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.4.3.2 SPI Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.4.3.3 FIFO Disable Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.4.3.4 Using the TX FIFO Buffering Mechanism . . . . . . . . . . . . . . . . . . . . . . . 18.4.3.5 Using the RX FIFO Buffering Mechanism . . . . . . . . . . . . . . . . . . . . . . . 18.4.4 Deserial Serial Interface (DSI) Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.4.4.1 DSI Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.4.4.2 DSI Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.4.4.3 DSI Serialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.4.4.4 DSI Deserialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.4.4.5 DSI Transfer Initiation Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.4.4.6 Multiple Transfer Operation (MTO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.4.5 Combined Serial Interface (CSI) Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.4.5.1 CSI Serialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.4.5.2 CSI Deserialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.4.6 DSPI Baud Rate and Clock Delay Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.4.6.1 Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.4.6.2 PCS to SCK Delay (tCSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.4.6.3 After SCK Delay (tASC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.4.6.4 Delay after Transfer (tDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.4.6.5 Peripheral Chip Select Strobe Enable (PCSS) . . . . . . . . . . . . . . . . . . . 18.4.7 Transfer Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.4.7.1 Classic SPI Transfer Format (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . 18.4.7.2 Classic SPI Transfer Format (CPHA = 1) . . . . . . . . . . . . . . . . . . . . . . . 18.4.7.3 Continuous Selection Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.4.7.4 Clock Polarity Switching between DSPI Transfers . . . . . . . . . . . . . . . . 18.4.8 Continuous Serial Communications Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.4.9 Interrupts and DMA Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.4.9.1 End-of-Queue Interrupt Request (EOQF) . . . . . . . . . . . . . . . . . . . . . . . 18.4.9.2 Transmit FIFO Fill Interrupt or DMA Request (TFFF) . . . . . . . . . . . . . . 18.4.9.3 Transfer Complete Interrupt Request (TCF) . . . . . . . . . . . . . . . . . . . . . 18.4.9.4 Transmit FIFO Underflow Interrupt Request (TFUF) . . . . . . . . . . . . . . . 18.4.9.5 Receive FIFO Drain Interrupt or DMA Request (RFDF) . . . . . . . . . . . . 18.4.9.6 Receive FIFO Overflow Interrupt Request (RFOF) . . . . . . . . . . . . . . . . 18.4.9.7 FIFO Overrun Request (TFUF) or (RFOF) . . . . . . . . . . . . . . . . . . . . . . 18.4.10 Power Saving Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.4.10.1 Module Disable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.4.10.2 Slave Interface Signal Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.5 Initialization and Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-27 18-28 18-30 18-31 18-32 18-33 18-33 18-34 18-35 18-35 18-35 18-36 18-36 18-37 18-37 18-37 18-38 18-38 18-39 18-40 18-40 18-41 18-41 18-42 18-42 18-47 18-47 18-48 18-49 18-50 18-50 18-50 18-51 18-51 18-51 18-52 18-53 18-54 18-55 18-56 18-57 18-58 18-58 18-59 18-59 18-59 18-59 18-59 18-59 18-60 18-60 18-60 18-60 MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor xix 18.5.1 18.5.2 18.5.3 18.5.4 18.5.5 How to Change Queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Baud Rate Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Delay Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPC5xx QSPI Compatibility with the DSPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Calculation of FIFO Pointer Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.5.5.1 Address Calculation for the First-in Entry and Last-in Entry in the TX FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.5.5.2 Address Calculation for the First-in Entry and Last-in Entry in the RX FIFO . . . . . . . . . . . . . . . . . . . 18-60 18-61 18-63 18-63 18-64 18-65 18-65 Chapter 19 Enhanced Serial Communication Interface (eSCI) 19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1 19.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1 19.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2 19.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2 19.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2 19.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3 19.2.1 Detailed Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3 19.2.1.1 eSCI Transmit (TXDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3 19.2.1.2 eSCI Receive Pin (RXDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3 19.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3 19.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3 19.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4 19.3.2.1 eSCI Control Register 1 (ESCIx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4 19.3.2.2 eSCI Control Register 2 (ESCIx_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 19-7 19.3.2.3 eSCI Data Register (ESCIx_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-9 19.3.2.4 eSCI Status Register (ESCIx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-9 19.3.2.5 LIN Control Register (ESCIx_LCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-12 19.3.2.6 LIN Transmit Register (ESCIx_LTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-14 19.3.2.7 LIN Receive Register (ESCIx_LRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-18 19.3.2.8 LIN CRC Polynomial Register (ESCIx_LPR) . . . . . . . . . . . . . . . . . . . . . 19-19 19.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-19 19.4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-19 19.4.2 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-20 19.4.3 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-21 19.4.4 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-22 19.4.4.1 Transmitter Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-22 19.4.4.2 Character Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-23 19.4.4.3 Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-24 19.4.4.4 Idle Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-25 19.4.4.5 Fast Bit Error Detection in LIN Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-25 19.4.5 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-26 19.4.5.1 Receiver Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-27 19.4.5.2 Character Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-27 19.4.5.3 Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-27 19.4.5.4 Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-29 19.4.5.5 Baud Rate Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-29 19.4.5.6 Receiver Wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-31 19.4.6 Single-Wire Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-33 19.4.7 Loop Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-33 19.4.8 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-34 19.4.8.1 Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-34 MPC5533 Microcontroller Reference Manual, Rev. 0 xx Freescale Semiconductor 19.4.8.2 Disabling the eSCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.4.9 Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.4.10 Using the LIN Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.4.10.1 Features of the LIN Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.4.10.2 Generating a TX Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.4.10.3 Generating an RX Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.4.10.4 LIN Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.4.10.5 LIN Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-34 19-34 19-36 19-37 19-37 19-38 19-39 19-40 Chapter 20 FlexCAN2 Controller Area Network 20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1 20.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2 20.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2 20.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3 20.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-5 20.1.4.1 Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-5 20.1.4.2 Freeze Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-5 20.1.4.3 Listen-Only Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-5 20.1.4.4 Loop-Back Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-5 20.1.4.5 Module Disabled Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-5 20.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6 20.2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6 20.2.2 Detailed Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6 20.2.2.1 CNRXx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6 20.2.2.2 CNTXx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6 20.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6 20.3.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-7 20.3.2 Message Buffer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-8 20.3.3 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-11 20.3.3.1 Module Configuration Register (CANx_MCR) . . . . . . . . . . . . . . . . . . . . 20-11 20.3.3.2 Control Register (CANx_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-13 20.3.3.3 Free Running Timer (CANx_TIMER) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-16 20.3.3.4 RX Mask Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-17 20.3.3.5 RX Individual Mask Registers (CANx_RXIMR0 through CANx_RXIMR63) 20-19 20.3.3.6 Error Counter Register (CANx_ECR) . . . . . . . . . . . . . . . . . . . . . . . . . . 20-20 20.3.3.7 Error and Status Register (CANx_ESR) . . . . . . . . . . . . . . . . . . . . . . . . 20-21 20.3.3.8 Interrupt Masks High Register (CANx_IMRH) . . . . . . . . . . . . . . . . . . . . 20-23 20.3.3.9 Interrupt Masks Low Register (CANx_IMRL) . . . . . . . . . . . . . . . . . . . . . 20-24 20.3.3.10 Interrupt Flags High Register (CANx_IFRH) . . . . . . . . . . . . . . . . . . . . . 20-24 20.3.3.11 Interrupt Flags Low Register (CANx_IFRL) . . . . . . . . . . . . . . . . . . . . . . 20-25 20.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-26 20.4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-26 20.4.2 Transmit Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-26 20.4.2.1 Arbitration Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-26 20.4.3 Receive Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-27 20.4.3.1 Matching Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-27 20.4.3.2 Reception Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-28 20.4.3.3 Self Received Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-28 20.4.4 Message Buffer Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-28 20.4.4.1 Notes on TX Message Buffer Deactivation . . . . . . . . . . . . . . . . . . . . . . 20-29 20.4.4.2 Notes on RX Message Buffer Deactivation . . . . . . . . . . . . . . . . . . . . . . 20-29 20.4.4.3 Data Coherency Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-29 MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor xxi 20.4.5 CAN Protocol Related Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.4.5.1 Remote Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.4.5.2 Overload Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.4.5.3 Time Stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.4.5.4 Protocol Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.4.5.5 Arbitration and Matching Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.4.6 Modes of Operation Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.4.6.1 Freeze Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.4.6.2 Module Disabled Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.4.8 Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.5 Initialization and Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.5.1 FlexCAN2 Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.5.2 FlexCAN2 Addressing and RAM Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-30 20-30 20-30 20-31 20-31 20-33 20-33 20-33 20-34 20-34 20-35 20-35 20-35 20-36 Chapter 21 Voltage Regulator Controller (VRC) and POR Module 21.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.4.1 Voltage Regulator Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.4.2 POR Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.4.2.1 1.5 V POR Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.4.2.2 3.3 V POR Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.4.2.3 RESET Power POR Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.5 Initialization and Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.5.1 Voltage Regulator Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.5.2 Compatible Power Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.5.3 Power Sequencing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.5.3.1 Power-Up Sequence If VRC33 Grounded . . . . . . . . . . . . . . . . . . . . . . . . . 21.5.3.2 Power-Down Sequence If VRC33 Grounded . . . . . . . . . . . . . . . . . . . . . . 21.5.3.3 Input Value of Pins During POR Dependent on VDD33 . . . . . . . . . . . . . . 21.5.3.4 Pin Values after POR Negates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1 21-1 21-2 21-2 21-2 21-2 21-3 21-4 21-4 21-4 21-5 21-5 21-5 21-5 21-6 21-6 21-6 21-7 Chapter 22 IEEE 1149.1 Test Access Port Controller (JTAGC) 22.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.1.4.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.1.4.2 IEEE 1149.1-2001 Defined Test Modes . . . . . . . . . . . . . . . . . . . . . . . . . 22.1.4.3 Bypass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.1.4.4 TAP Sharing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.3.1 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.3.2 Bypass Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.3.3 Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.3.4 Boundary Scan Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1 22-1 22-2 22-2 22-2 22-2 22-3 22-3 22-3 22-4 22-4 22-4 22-5 22-5 22-5 MPC5533 Microcontroller Reference Manual, Rev. 0 xxii Freescale Semiconductor 22.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6 22.4.1 JTAGC Reset Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6 22.4.2 IEEE 1149.1-2001 (JTAG) Test Access Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6 22.4.3 TAP Controller State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6 22.4.3.1 Enabling the TAP Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8 22.4.3.2 Selecting an IEEE 1149.1-2001 Register . . . . . . . . . . . . . . . . . . . . . . . . 22-8 22.4.4 JTAGC Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8 22.4.4.1 BYPASS Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-9 22.4.4.2 ACCESS_AUX_TAP_x Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-9 22.4.4.3 CLAMP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-9 22.4.4.4 EXTEST—External Test Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-9 22.4.4.5 HIGHZ Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-10 22.4.4.6 IDCODE Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-10 22.4.4.7 SAMPLE Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-10 22.4.4.8 SAMPLE/PRELOAD Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-10 22.4.5 Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-10 22.5 Initialization and Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-11 Chapter 23 Nexus Development Interface 23.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1 23.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2 23.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2 23.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-4 23.1.3.1 Nexus Reset Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-4 23.1.3.2 Full-Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-4 23.1.3.3 Reduced-Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-4 23.1.3.4 Disabled-Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5 23.1.3.5 Censored Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5 23.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5 23.2.1 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5 23.2.1.1 Event Out (EVTO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-6 23.2.1.2 Event In (EVTI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-6 23.2.1.3 Message Data Out (MDO[3:0] or [11:0]) . . . . . . . . . . . . . . . . . . . . . . . . . 23-6 23.2.1.4 Message Start/End Out (MSEO[1:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-6 23.2.1.5 Ready (RDY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-6 23.2.1.6 JTAG Compliancy (JCOMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-6 23.2.1.7 Test Data Output (TDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-6 23.2.1.8 Test Clock Input (TCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-6 23.2.1.9 Test Data Input (TDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-7 23.2.1.10 Test Mode Select (TMS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-7 23.3 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-7 23.4 NDI Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-10 23.4.1 Enabling Nexus Clients for TAP Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-10 23.4.2 Configuring the NDI for Nexus Messaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-10 23.4.3 Programmable MCKO Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-11 23.4.4 Nexus Messaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-11 23.4.5 System Clock Locked Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-12 23.5 Nexus Port Controller (NPC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-12 23.5.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-12 23.5.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-12 23.6 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-13 23.6.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-13 MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor xxiii 23.7 23.8 23.9 23.10 23.11 23.12 23.13 23.6.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.6.2.1 Bypass Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.6.2.2 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.6.2.3 Nexus Device ID Register (DID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.6.2.4 Port Configuration Register (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . NPC Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.7.1 NPC Reset Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.7.2 Auxiliary Output Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.7.2.1 Output Message Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.7.2.2 Output Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.7.2.3 IEEE‚ 1149.1-2001 (JTAG) TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.7.2.4 Nexus Auxiliary Port Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.7.2.5 Nexus JTAG Port Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.7.2.6 MCKO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.7.2.7 EVTO Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.7.2.8 Nexus Reset Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NPC Initialization and Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.8.1 Accessing NPC Tool-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nexus Single eTPU Development Interface (NSEDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e200z3 Class 3 Nexus Module (NZ3C3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.10.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.10.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.10.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.10.5 Enabling Nexus3 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.10.6 TCODEs Supported by NZ3C3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NZ3C3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.11.1 Port Configuration Register (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.11.2 Development Control Registers 1 and 2 (DC1, DC2) . . . . . . . . . . . . . . . . . . . . . . . . 23.11.3 Development Status Register (DS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.11.4 Read/Write Access Control and Status (RWCS) . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.11.5 Read/Write Access Address (RWA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.11.6 Read/Write Access Data (RWD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.11.7 Watchpoint Trigger Register (WT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.11.8 Data Trace Control Register (DTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.11.9 Data Trace Start Address Registers 1 and 2 (DTSAn) . . . . . . . . . . . . . . . . . . . . . . . 23.11.10Data Trace End Address Registers 1 and 2 (DTEAn) . . . . . . . . . . . . . . . . . . . . . . . 23.11.11 NZ3C3 Register Access via JTAG / OnCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ownership Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.12.1 Ownership Trace Messaging (OTM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.12.2 OTM Error Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.12.3 OTM Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Program Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.13.1 Branch Trace Messaging (BTM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.13.1.1 e200z3 Indirect Branch Message Instructions (Power Architecture Book E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.13.1.2 e200z3 Direct Branch Message Instructions (Power Architecture Book E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.13.1.3 BTM Using Branch History Messages . . . . . . . . . . . . . . . . . . . . . . . . . 23.13.1.4 BTM Using Traditional Program Trace Messages . . . . . . . . . . . . . . . . 23.13.2 BTM Message Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.13.2.1 Indirect Branch Messages (History) . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.13.2.2 Indirect Branch Messages (Traditional) . . . . . . . . . . . . . . . . . . . . . . . . 23-13 23-13 23-13 23-15 23-15 23-17 23-17 23-17 23-17 23-18 23-19 23-24 23-24 23-24 23-24 23-25 23-25 23-25 23-25 23-26 23-26 23-27 23-28 23-29 23-29 23-30 23-34 23-35 23-36 23-38 23-38 23-40 23-40 23-40 23-42 23-43 23-43 23-44 23-45 23-45 23-45 23-46 23-46 23-46 23-47 23-47 23-47 23-48 23-48 23-48 23-49 MPC5533 Microcontroller Reference Manual, Rev. 0 xxiv Freescale Semiconductor 23.13.2.3 Direct Branch Messages (Traditional) . . . . . . . . . . . . . . . . . . . . . . . . . 23-49 23.13.2.4 Resource Full Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-49 23.13.2.5 Debug Status Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-50 23.13.2.6 Program Correlation Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-50 23.13.2.7 BTM Overflow Error Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-50 23.13.3 Program Trace Synchronization Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-51 23.14 BTM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-53 23.14.1 Enabling Program Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-53 23.14.2 Relative Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-53 23.14.3 Branch and Predicate Instruction History (HIST) . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-54 23.14.4 Sequential Instruction Count (I-CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-54 23.14.5 Program Trace Queueing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-54 23.14.5.1 Program Trace Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-55 23.14.6 Data Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-56 23.14.6.1 Data Trace Messaging (DTM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-56 23.14.6.2 DTM Message Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-56 23.14.6.3 DTM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-59 23.14.6.4 Data Trace Timing Diagrams (Eight MDO Configuration) . . . . . . . . . . 23-61 23.14.7 Watchpoint Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-61 23.14.7.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-61 23.14.7.2 Watchpoint Messaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-62 23.14.7.3 Watchpoint Error Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-62 23.14.7.4 Watchpoint Timing Diagram (Two MDO and One MSEO Configuration) 23-63 23.14.8 NZ3C3 Read/Write Access to Memory-Mapped Resources . . . . . . . . . . . . . . . . . . 23-63 23.14.8.1 Single Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-64 23.14.8.2 Block Write Access (Non-Burst Mode) . . . . . . . . . . . . . . . . . . . . . . . . . 23-64 23.14.8.3 Block Write Access (Burst Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-65 23.14.8.4 Single Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-65 23.14.8.5 Block Read Access (Non-Burst Mode) . . . . . . . . . . . . . . . . . . . . . . . . . 23-66 23.14.8.6 Block Read Access (Burst Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-66 23.14.8.7 Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-67 23.14.8.8 Read/Write Access Error Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-67 23.14.9 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-68 23.14.10 IEEE‚ 1149.1 (JTAG) RD/WR Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-69 23.14.10.1 JTAG Sequence for Accessing Internal Nexus Registers . . . . . . . . . . . 23-69 23.14.10.2 JTAG Sequence for Read Access of Memory-Mapped Resources . . . 23-70 23.14.10.3 JTAG Sequence for Write Access of Memory-Mapped Resources . . . . 23-70 Appendix A MPC5533 Register Map A.1 A.2 MPC5533 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 e200z3 Core SPR Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-41 Appendix B MPC5533RM Revision History B.1 Rev. 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor xxv MPC5533 Microcontroller Reference Manual, Rev. 0 xxvi Freescale Semiconductor Chapter 1 Overview The MPC5533 microcontroller (MCU) is a member of the MPC5500 family of next generation powertrain microcontrollers built on Power Architecture™ technology. The MPC5500 family contains a host processor core that complies with the Power Architecture embedded category, which is 100 percent user mode compatible with the original Power PC™ user instruction set architecture (UISA). This family of parts contains many new features coupled with high-performance CMOS technology to provide significant performance improvement over the MPC565. The e200z3 CPU of the MPC5500 family is part of the family of CPU cores that implement versions built on the Power Architecture embedded category. This core also has additional instructions, including digital signal processing (DSP) instructions, beyond the classic PowerPC instruction set. The e200z3 of the MPC5533 is compatible with the PowerPC Book E architecture. It is 100% user mode compatible (with floating point library) with the classic PowerPC instruction set. The Book E architecture has enhancements that improve the PowerPC architecture’s fit in embedded applications. This core also has additional instructions, including digital signal processing (DSP) instructions, beyond the classic PowerPC instruction set. The host processor core of the MPC5533 also includes an instruction set enhancement allowing variable length encoding (VLE). This allows optional encoding of mixed 16- and 32-bit instructions. With this enhancement, it is possible to achieve significant code size footprint reduction. The MPC5533 has a single-level of memory hierarchy consisting of 48-KB on-chip SRAM and 768 KB of internal flash memory. Both the SRAM and the flash memory can hold instructions and data. The External Bus Interface (EBI) supports most standard memories used with the MPC5xx family. This device does not support arbitration between itself and other masters on the external bus. It must be the only master on the EBI or be a slave-only device. The complex I/O timer functions of MPC5533 are performed by an Enhanced Time Processor Unit engine (eTPU). The eTPU engine controls 32 hardware channels and has been enhanced over the MPC500 family’s TPU by providing 24-bit timers, double-action hardware channels, a variable number of parameters per channel, angle clock hardware, and additional control and arithmetic instructions. The eTPU is programmed using a high-level programming language. Off-chip communication is performed by a suite of serial protocols including flexible controller area networks (FlexCANs), enhanced SPIs (Deserialize/Serialize Peripheral Interface) and SCIs. The DSPIs support pin reduction through hardware serialization and deserialization of timer channels and GPIO signals. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 1-1 Overview The MPC5533 MCU has an on-chip 40-channel Enhanced Queued Analog-to-Digital Converter (eQADC), with 5 V conversion range. The System Integration Unit (SIU) performs several chip-wide configuration functions. Pad configuration and General-Purpose Input and Output (GPIO) are controlled from the SIU. External interrupts and reset control are configured in the SIU. The Internal Multiplexer sub-block (IMUX) provides multiplexing of eQADC trigger sources, daisy chaining the DSPIs, and external interrupt signal multiplexing. On-chip modules include: • Single issue, 32-bit PowerPC Book E compatible CPU core complex; includes VLE enhancements for code size footprint reduction • 32-channel enhanced direct memory access controller (eDMA) • Interrupt controller (INTC) capable of handling 178 selectable-priority interrupt sources • Frequency Modulated Phase-locked loop (FMPLL) • External bus interface (EBI) with error correction status module (ECSM) • System integration unit (SIU) • 768 KB on-chip flash with flash control unit (FCU) • 48 KBs on-chip static RAM (SRAM) • Boot assist module (BAM) • 32-channel enhanced time processor unit (eTPU) • One enhanced 5 V Queued Analog-to-Digital Converters (eQADC) • Two deserial serial peripheral interface (DSPI) modules • One enhanced serial communication interface (eSCI) modules (with LIN support) • Two controller area network (FlexCAN) modules • Nexus development interface (NDI) per IEEE-ISTO 5001-2003 standard • Device/board test support per Joint Test Action Group (JTAG) of IEEE (IEEE 1149.1) • On-chip voltage regulator controller for regulating 3.3 V down to 1.5 V for core logic 1.1 Block Diagram Figure 1-1 shows a top-level block diagram of the MPC5533. MPC5533 Microcontroller Reference Manual, Rev. 0 1-2 Freescale Semiconductor Overview e200z3 Core 1.5 V Regulator Control Signal Processing Engine Integer Execution Unit FMPLL Multiply Unit JTAG Nexus Interface Nexus 64-bit General Purpose Registers Core Timers Unit (FIT, TB, DEC) Special Purpose Registers Exception Handler Instruction Unit Variable Length Encoded Instruction Branch Prediction Unit Load/Store Unit Interrupt Controller Memory Management Unit Master Master Master External Bus Interface External Master Interface eDMA 32 channels Master Crossbar Switch (XBAR) Slave Slave Flash 768 KB Slave Slave SRAM 48 KB Boot Assist Module System/Bus Integration eQADC ADCi ADC AMUX LEGEND MPC5500 Device Module Acronyms CAN DSPI DMA eQADC eSCI eTPU FMPLL SRAM FlexCAN 12 KB Code RAM eSCI 2.5 KB Data RAM DSPI eTPU 32 channel DSPI Peripheral Bridge B (PBRIDGE_B) Peripheral Bridge A (PBRIDGE_A) FlexCAN Slave e200z3 Core Component Acronyms – Controller area network (FlexCAN) – Deserial/serial peripheral interface – Enhanced direct memory access – Enhanced queued analog/digital converter – Enhanced serial communications interface – Enhanced time processing units – Frequency modulated phase-locked loop – Static RAM DEC FIT TB WDT – Decrementer – Fixed interval timer – Time base – Watchdog timer Figure 1-1. MPC5533 Block Diagram MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 1-3 Overview 1.1.1 MPC5500 Family Comparison The following table compares the features of the MPC553X and MPC555X products: Table 1-1. MPC5500 Family Members MPC5500 Device Power PC core Variable Length Instruction support Unified cache (KB) Memory management unit (MMU) Crossbar (Master x Slave) Core Nexus Static RAM (SRAM) (KB) Flash memory Main Array (MB) Shadow Block (KB) External bus interface (EBI) MPC5533 MPC5534 MPC5553 MPC5554 e200z3 e200z3 e200z6 e200z6 Y Y — — — — 1 16 entry 16 entry 32 entry 32 entry 4x5 4x5 4x5 3x5 Class 3+ (NZ3C3) Class 3+ (NZ3C3) Class 3+ (NZ6C3) Class 3+ (NZ6C3) 48 KB 64 KB 64 KB 64 KB 768 KB 3 1 1.54 24 1 1 1 1 8 10 32 bit Data Bus 16 bit 16 bit Address Bus 24 bit 24 bit 24 bit 24 bit — Y Partial — 32 channel 32 channel 32 channel 64 channel DMA Nexus — — Class 3 Class 3 Enhanced serial communications interface (eSCI) 1 2 2 2 eSCI A Y Y Y Y eSCI B — Y Y Y 2 2 2 3 CAN A 64 buffers 64 buffers 64 buffers 64 buffers CAN B — — — 64 buffers CAN C 64 buffers 64 buffers 64 buffers 64 buffers 2 3 3 4 DSPI A — — — Y DSPI B — Y Y Y DSPI C Y Y Y Y Calibration bus interface (CBI) Enhanced direct memory access (eDMA) Flexible controller area network (FlexCAN) Deserial/serial peripheral interface (DSPI) DSPI D Enhanced management input/output system (eMIOS) Enhanced time processing unit (eTPU) eTPU A Interrupt controller 32 bit 32 2 Y Y Y Y — 24 channel 24 channel 24 channel 32 channel 32 channel 32 channel 64 channel Y Y Y Y eTPU B — — — Y Code memory (KB) 12 12 12 16 Parameter RAM (KB) 2.5 204 2.5 5 212 2.5 6 212 3 7 308 8 MPC5533 Microcontroller Reference Manual, Rev. 0 1-4 Freescale Semiconductor Overview Table 1-1. MPC5500 Family Members (continued) MPC5500 Device MPC5533 MPC5534 40 channels 9 40 channels 9 40 channels Enhanced Analog to Digital Converter (eQADC) Y Y Y ADC 1 — Y Y Y — — Y Y Crystal frequency range Voltage Regulator Controller (VRC) 40 channels Y Fast Ethernet Controller (FEC) Maximum system frequency MPC5554 ADC 0 Frequency Modulated (FM) Phase Lock Loop (PLL) 11 MPC5553 12 82 12 Y 10 Y 132 — Y 13 132 13 (MHz) 82 (MHz) 8–20 8–20 8–20 8–20 Y Y Y Y 1 2-way associative 8-way associative 3 16-byte flash page size for programming 4 32-byte flash page size for programming 5 The number of vectors is 204 (0–203): 158 peripheral interrupts, 8 software interrupts, and 38 reserved vectors. 6 The number of vectors is 212 (0–211): 190 peripheral interrupts, 8 software interrupts, and 14 reserved vectors. 7 The number of vectors is 212 (0–211): 193 peripheral interrupts, 8 software interrupts, and 11 reserved vectors. 8 The number of vectors is 308 (0–307): 285 peripheral interrupts, 8 software interrupts, and 15 reserved vectors. 9 eQADC has 34 channels on the 208 package: 40 channels on the 324 package. 10 The FEC signals are shared with the data bus pins DATA[16:31] 11 Initial automotive temperature range qualification 12 82 MHz parts allow for 80 MHz system clock + 2% FM 13 132 MHz parts allow for 128 MHz system clock + 2% FM 2 1.2 MPC5533 Features List This section provides a high-level description of the features found on the MPC5533. 1.2.1 • • • • • • Operating Parameters Fully static operation, 0–80 MHz -40° to 150° C junction temperature (125° C ambient temperature) Low-power design — Less than 0.8 Watts power dissipation — Designed for dynamic power management of core and peripherals — Software controlled clock gating of peripherals — Separate power supply for stand-by operation for a portion of SRAM Fabricated in 0.13 μm process 1.5 V internal logic Input and output pins with 3.0–5.5 V range — 35% or 65% VDDE CMOS switch levels (with hysteresis) — Selectable hysteresis — Selectable slew rate control MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 1-5 Overview • • 1.2.2 • • • • • • • • • • • External bus and Nexus pins support 1.6–3.6 V operation — Selectable drive strength control — Unused pins configurable as GPIO Designed with EMI reduction techniques — Frequency Modulated Phase-Locked Loop (FMPLL) — On-chip bypass capacitance — Selectable slew rate and drive strength e200z3 Core Processor Single issue, 32-bit PowerPC Architecture compatible CPU — In-order execution and retirement — Precise exception handling — User-mode binary compatible with MPC5xx except floating point instructions Variable Length Encoding Enhancements — e200z3 core supports both PowerPC Architecture Book E and VLE instruction sets — Allows optional encoding of mixed 16- and 32-bit instructions — Results in smaller code size footprint — Regions of the memory map are designated as PowerPC Architecture Book E or VLE based on configuration of the Memory Management Unit Branch processing unit — Dedicated branch address calculation adder — Branch acceleration using Branch Lookahead Instruction Buffer Load and store unit — Fully pipelined — Big and Little endian support — Misaligned access support — Zero load-to-use pipeline bubbles — Supports throughput of one load or store operation per cycle — Memory interface support for saving and restoring two registers per cycle Thirty-two 64-bit general purpose registers (GPRs) Memory management unit (MMU) with 16-entry fully-associative translation look-aside buffer (TLB) Separate instruction bus and load/store bus Vectored interrupt support Interrupt latency < 116 ns at 80 MHz (measured from interrupt request to execution of first instruction of interrupt exception handler) Reservation instructions for implementing read-modify-write constructs (CPU master only) Numerics and DSP MPC5533 Microcontroller Reference Manual, Rev. 0 1-6 Freescale Semiconductor Overview • • • • 1.2.3 • • 1.2.4 • • • • • • • • • • • — Saturated, unsaturated, and fractional arithmetic — Support for DSP addressing modes — Pipelined dual 32x32 MAC with one clock throughput Signal processing extension APU — Operating on all 32 GPRs that are all extended to 64 bits wide — Single Instruction Multiple Data (SIMD) provides a full compliment of vector and scalar integer and floating point arithmetic operations (integer vector MAC and MUL operations) — Provides rich array of extended 64-bit loads and stores to and from the extended GPRs — Fully code compatible with e200z6 core Floating point — IEEE 754 compatible with software wrapper — Scalar single precision in hardware, double precision with software library — Conversion instructions between single precision floating point and fixed point — Fully code compatible with e200z6 core Long cycle time instructions, except for guarded loads, do not increase interrupt latency Extensive system development support through Nexus debug port Crossbar Switch (XBAR) Three master ports, and five slave ports — Masters: CPU Instruction bus, CPU Load/store bus, eDMA, EBI — Slave: Flash, SRAM, Peripheral Bridge A, Peripheral Bridge B; EBI 32-bit internal address bus, 64-bit internal data bus Enhanced Direct Memory Access (eDMA) Controller 32 channels support independent 8-, 16- or 32-bit single value or block transfers Supports variable sized queues and circular queues Source and destination address registers are independently configured to post-increment or remain constant Each transfer is initiated by a peripheral, CPU, or eDMA channel request Each eDMA channel can optionally send an interrupt request to the CPU on completion of a single value or block transfer All data movement via dual-address transfers: read from source, write to destination Programmable source and destination addresses, transfer size, plus support for enhanced addressing modes Transfer control descriptor organized to support two-deep, nested transfer operations An inner data transfer loop defined by a ‘minor’ byte transfer count An outer data transfer loop defined by a ‘major’ iteration count Channel activation via one of three methods: MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 1-7 Overview • • • • • • 1.2.5 • • • 1.2.6 • • • • • • • • — Explicit software initiation — Initiation via a channel-to-channel linking mechanism for continuous transfers — Peripheral-paced hardware requests (one per channel) Support for fixed-priority and round-robin channel arbitration Channel completion reported via optional interrupt requests One interrupt per channel, optionally asserted at completion of major iteration count Error termination interrupts are optionally enabled Support for scatter/gather DMA processing Channel transfers can be suspended by a higher priority channel Interrupt Controller (INTC) Unique 9-bit vector per interrupt source for 204 (0–203) total interrupt sources: — 158 peripheral interrupt sources — Eight software settable interrupt sources — 38 reserved interrupt sources 16 priority levels with fixed hardware arbitration within priority levels for each interrupt source Priority elevation for shared resources Frequency Modulated Phase-Locked Loop (FMPLL) Input clock frequency from 8–20 MHz Current controlled oscillator (ICO) range from 48 MHz to maximum device frequency Reduced frequency divider (RFD) for reduced frequency operation without forcing the FMPLL to re-lock Four modes of operation — Bypass mode — PLL normal mode with crystal reference (default) — PLL normal mode with external oscillator reference — PLL dual controller mode for EXTAL to CLKOUT skew minimization Programmable frequency modulation — Modulation enabled/disabled through software — Triangle wave modulation — Programmable modulation depth (1% or 2% deviation from center frequency) — Programmable modulation frequency dependent on reference frequency Lock detect circuitry reports when the FMPLL has achieved frequency lock and continuously monitors lock status to report loss of lock conditions Programmable interrupt request on system reset or loss of lock Loss-of-clock (LOC) detection for reference and feedback clocks MPC5533 Microcontroller Reference Manual, Rev. 0 1-8 Freescale Semiconductor Overview • • 1.2.7 Programmable interrupt request on system reset or loss of clock Self-clocked mode (SCM) operation External Bus Interface (EBI) NOTE EBI features apply to devices using the 324 package. The EBI is not available in the 208 package. • • • • • • • • • • • • • • • 1.2.8 • • 1.8–3.3 V I/O Up to 24-bit address bus — Four most significant signals multiplexed with four chip selects 16-bit data bus Memory controller with support for various memory types: — Standard SRAM — Synchronous burst SDR (flash and SRAM) — Asynchronous/legacy (flash and SRAM) Most standard memories used with the MPC5xx family Single-master only or slave only operation Bus monitor — User selectable — Programmable time-out period (with 8 external bus clock resolution) Configurable wait states (via chip selects) Four chip-select (CS[0:3]) signals (multiplexed with four most significant address signals) Two write/byte enable (WE/BE[0:1]) signals Configurable bus speed modes — system frequency — ½ of system frequency — ¼ of system frequency Configurable wait states Optional automatic CLKOUT gating to save power and reduce EMI Compatible with MPC5xx external bus (with some limitations) Selectable drive strengths through pad control in SIU; 10pF, 20pF, 30pF, 50pF System Integration Unit (SIU) System configuration — MCU reset configuration via external pins — Pad configuration control System reset monitoring and generation MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 1-9 Overview • • • — Power-on reset support — Reset status register provides last reset source to software — Glitch detection on reset input — Software controlled reset assertion External interrupt — Sixteen interrupt requests — Rising- or falling-edge event detection — Programmable digital filter for glitch rejection GPIO — GPIO function on 155 I/O pins — Dedicated input and output registers for setting each GPIO Internal Multiplexing — Allows serial and parallel chaining of DSPIs — Allows flexible selection of eQADC trigger inputs — Allows selection of interrupt requests between external pins and DSPI 1.2.9 • Error Correction Status Module (ECSM) Configurable error-correcting codes (ECC) reporting 1.2.10 • • • • • • • • • On-chip Flash 768 KB burst flash memory — Configured as 48 KB x 128 bits — 1-KB shadow block compatible with all other parts in the family for storing censorship and configuration information (censorship protection scheme to prevent flash content visibility) — Accessed via a 64-bit wide bus interface Quadruple 128-bit wide prefetch/burst buffers to provide single cycle in-line accesses (prefetch buffers can be configured to prefetch code or data or both) Hardware read-while-write feature that allows blocks to be erased/programmed while other blocks are being read (used for EEPROM emulation and data calibration) Page mode (128-bits) programming for rapid end-of-line programming Hardware programming state machine Supports a 64-bit data bus. Byte, halfword, word and doubleword reads are supported. Only aligned word and doubleword writes are supported. Hardware and software configurable read and write access protections on a per-master basis. Interface to the flash array controller is pipelined with a depth of 1, allowing overlapped accesses to proceed in parallel for interleaved or pipelined flash array designs. Configurable access timing allowing use in a wide range of system frequencies. MPC5533 Microcontroller Reference Manual, Rev. 0 1-10 Freescale Semiconductor Overview • • • • • • • • • Multiple-mapping support and mapping-based block access timing (0–31 additional cycles) allowing use for emulation of other memory types. Software programmable block program/erase restriction control. Erase of selected block(s) Read page size of 128 bits (4 words) ECC with single-bit correction, double-bit detection. Embedded hardware program and erase algorithm Erase suspend, program suspend and erase-suspended program Shadow information stored in non-volatile shadow block Independent program/erase of the shadow block 1.2.11 • • • • • Supports read/write accesses mapped to the SRAM memory from any master 48-KB general purpose RAM of which 32 KBs are on standby power 32-KB block powered by separate supply for standby operation Byte, halfword, word and doubleword addressable ECC performs single bit correction, double bit detection on 32-bit data element 1.2.12 • • • • • • • • • • Boot Assist Module (BAM) Enables and manages the transition of MCU from reset to user code execution in the following configurations: — Execution from internal or external flash — Download and execution of code via FlexCAN or eSCI Sets up MMU to cover all resources and mapping all physical address to logical addresses with minimum address translation Sets up the MMU to allow user boot code to execute as either PowerPC Architecture Book E code (default) or as VLE code Location and detection of user boot code Automatic switch to serial boot mode if internal or external flash is blank or invalid Supports user programmable 64-bit password protection for serial boot mode Supports serial bootloading via FlexCAN bus and eSCI Supports serial bootloading of either PowerPC Architecture Book E code (default) or VLE code Supports censorship protection for internal flash memory Provides an option to enable the core watchdog timer 1.2.13 • On-chip Static RAM (SRAM) Enhanced Time Processor Unit (eTPU) eTPU engine is an event triggered VLIW processor timer subsystem MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 1-11 Overview • • • • • • • • • • High level assembler/compiler 32 channels 24-bit timer resolution Code memory—12 KB; Data memory—2.5 KB Variable number of parameters allocatable per channel Double match/capture channels Angle clock hardware support Shared time or angle counter bus (STAC) for all eTPU channels DMA and interrupt request support Nexus Class 3 Debug support (with some Class 4 support) 1.2.14 • • • • • • • • • • • • Enhanced Queued A/D Converter (eQADC) One independent ADC — 12 Bit AD Resolution — Up to 10 bit accuracy at 400 ksample/s and 8-bit accuracy at 800 ksample/s — Differential conversions — Single-ended signal range from 0–5 V — Sample times of two (default), eight, 64 or 128 ADC clock cycles — Provides time stamp information when requested — Parallel interface to eQADC CFIFOs and RFIFOs — Supports both right-justified unsigned and signed formats for conversion results 0–5 V common mode conversion range 40 single-ended inputs channels (40 in 324 BGA; 34 in 208 BGA), with support for up to 25 additional channels using external multiplexers Eight channels can be used as 4 pairs of differential analog input channels 10-bit accuracy at 400 ksample/s, 8-bit accuracy at 800 ksample/s Supports six FIFO queues with fixed priority. Queue modes with priority-based preemption, initiated by software command, internal (eTPU), or external triggers DMA and interrupt request support Supports all functional modes from QADC (MPC5xx family) Four pairs of differential analog input channels Full duplex synchronous serial interface (SSI) to an external device — Free-running clock for use by an external device — Supports a 26-bit message length Priority based CFIFOs MPC5533 Microcontroller Reference Manual, Rev. 0 1-12 Freescale Semiconductor Overview • • — Supports six CFIFOs with fixed priority. The lower the CFIFO number, the higher its priority. When commands of distinct CFIFOs are bound for the same CBuffer, the higher priority CFIFO is always served first — Supports software and hardware trigger modes to arm a particular CFIFO — Generates interrupt when command coherency is not achieved External hardware triggers — Supports rising-edge, falling-edge, high-level and low-level triggers — Supports configurable digital filter Supports 4 external 8-to-1 muxes which can expand the input channels 1.2.15 • • • Two DSPI modules SPI — Full duplex communication ports with interrupt and DMA request support — Supports all functional modes from QSPI sub-block of QSMCM (MPC5xx family) — Support for queues in RAM — Six chip selects, expandable to 64 with external demultiplexers — Programmable frame size, baud rate, clock delay and clock phase on a per frame basis — Modified SPI mode for interfacing to peripherals with longer setup time requirements Deserial serial interface (DSI) — Pin reduction by hardware serialization and deserialization of eTPU channels — Chaining of DSI sub-blocks — Triggered transfer control and change in data transfer control (for reduced EMI) 1.2.16 • • • • • • • • • Deserial Serial Peripheral Interface (DSPI) Module Enhanced Serial Communication Interface (eSCI) Module One eSCI module UART mode provides NRZ format and half or full duplex interface eSCI bit rate up to 1 Mbps Advanced error detection, and optional parity generation and detection Separately enabled transmitter and receiver eDMA support 13-bit baud rate selection Programmable 8- or 9-bit data format LIN support — Autonomous transmission of entire frames — Configurable to support all revisions of the LIN standard — Automatic parity bit generation MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 1-13 Overview • • • • • • • • — Double stop bit after bit error — 10- or 13-bit break support Separately enabled transmitter and receiver Programmable transmitter output parity Two receiver wake-up methods, idle line and address mark Interrupt-driven operation with flags Receiver framing error detection Hardware parity checking 1/16 bit-time noise detection Two channel eDMA interface 1.2.17 • • • • • • • • • • • • • • • • • • • • FlexCAN Two FlexCAN modules 64 message buffers each (0–8 bytes data length) Based on and including all existing features of the Freescale TouCAN module Full Implementation of the CAN protocol specification, Version 2.0B — Standard data and remote frames — Extended data and remote frames — Zero to eight bytes data length — Programmable bit rate up to 1 Mb/sec Programmable acceptance filters Short latency time for high priority transmit messages Arbitration scheme according to message ID or message buffer number Listen only mode capabilities Programmable clock source: system clock or oscillator clock Content-related addressing Each message buffer is configurable as receive (Rx) or transmit (Tx) buffers that support standard and extended messages Includes 1056 bytes of embedded memory for message buffer storage Programmable loop-back mode supporting self-test operation Three programmable Mask Registers Programmable transmit-first scheme: lowest ID or lowest buffer number Time Stamp based on 16-bit free-running timer Global network time, synchronized by a specific message Maskable interrupts Independent of the transmission medium (an external transceiver is assumed) Multi master concept MPC5533 Microcontroller Reference Manual, Rev. 0 1-14 Freescale Semiconductor Overview • • • High immunity to EMI Short latency time due to an arbitration scheme for high-priority messages Low-power mode, with programmable wake-up on bus activity 1.2.18 • • • • • • Per IEEE-ISTO 5001-2003 Real time development support for e200z3 core and eTPU engine through Nexus Class 3 (selected Class 4 support) Read and write access — Run-time access of entire memory map — Calibration (table constants calibrated using MMU and internal and external RAM; scalar constants calibrated using cache line locking) Configured via the IEEE 1149.1 (JTAG) port High bandwidth mode for fast message transmission Reduced bandwidth mode for reduced pin usage 1.2.19 • • • • • • • 1.3 IEEE 1149.1 JTAG controller (JTAGC) IEEE 1149.1-2001 Test Access Port (TAP) interface 4 pins (TDI, TMS, TCK, and TDO) JCOMP input that provides the ability to share the TAP (selectable modes of operation include JTAGC/debug or normal system operation) Selectable modes of operation include JTAGC/debug or normal system operation Five-bit instruction register that supports the following IEEE 1149.1-2001 defined instructions: — BYPASS, IDCODE, EXTEST, SAMPLE, SAMPLE/PRELOAD, HIGHZ, CLAMP Five-bit instruction register that supports the additional following public instructions: — ACCESS_AUX_TAP_NPC, ACCESS_AUX_TAP_ONCE, ACCESS_AUX_TAP_eTPU Three test data registers: a bypass register, a boundary scan register, and a device identification register A TAP controller state machine that controls the operation of the data registers, instruction register and associated circuitry 1.2.20 • • Nexus Development Interface (NDI) On-chip Voltage Regulator Controller Uses external NPN bipolar transistor Regulates 3.3 V down to 1.5 V for the core logic MPC5533 Memory Map This section describes the MPC5533 memory map. All addresses in the device, including those that are reserved, are identified in the tables. The addresses represent the physical addresses assigned to each IP block. Logical addresses are translated by the MMU into physical addresses. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 1-15 Overview Under software control of the Memory Management Unit (MMU), the logical addresses allocated to IP blocks can be changed on a minimum of a 4-KB boundary. Table 1-2 shows the MPC5533 memory map. Peripheral blocks can be redundantly mapped. You must use the MMU to prevent corruption. Table 1-2. MPC5533 Memory Map Bytes Address Range1 Module Allocated Used 0x0000_0000–0x000F_FFFF 768 KB 768 KB 0x0010_0000–0x00FF_FBFF 15 MB — 0x00FF_FC00–0x00FF_FFFF 1 KB 1 KB Flash Shadow Block 0x0100_0000–0x1FFF_FFFF 496 MB 1 MB Emulation mapping of Flash Array 0x2000_0000–0x3FFF_FFFF 256 MB — 0x4000_0000–0x4000_7FFF 32 KB 32 KB SRAM Array, Standby Powered 0x4000_8000–0x4000_BFFF 16 KB 16 KB SRAM Array 0x4000_C000–0xBFFF_FFFF 2048 MB – 48 KB — Flash Array Reserved External Memory Reserved Bridge A Peripherals 0xC000_0000–0xC3EF_FFFF 63 MB — Reserved 0xC3F0_0000–0xC3F0_3FFF 16 KB 4B Bridge A Registers 0xC3F0_4000–0xC3F7_FFFF 496 KB — Reserved 0xC3F8_0000–0xC3F8_3FFF 16 KB 20 B Frequency Modulated Phase-Locked Loop (FMPLL) 0xC3F8_4000–0xC3F8_7FFF 16 KB 48 B External Bus Interface (EBI) Configuration 0xC3F8_8000–0xC3F8_BFFF 16 KB 28 B Flash Configuration 0xC3F8_C000–0xC3F8_FFFF 16 KB — 0xC3F9_0000–0xC3F9_3FFF 16 KB 2.5 KB 0xC3F9_4000–0xC3F9_FFFF 64 KB — Reserved 0xC3FA_4000–0xC3FB_FFFF 112 KB — Reserved 0xC3FC_0000–0xC3FC_3FFF 16 KB 3 KB 0xC3FC_4000–0xC3FC_7FFF 16 KB — 0xC3FC_8000–0xC3FC_BFFF 16 KB 2.5 KB Enhanced Time Processing Unit (eTPU) Parameter RAM 0xC3FC_C000–0xC3FC_FFFF 16 KB 2.5 KB Enhanced Time Processing Unit (eTPU) Parameter RAM mirror 0xC3FD_0000–0xC3FD_3FFF 16 KB 12 KB Enhanced Time Processing Unit (eTPU) Code RAM 0xC3FD_4000–0xC3FF_FFFF 176 KB — Reserved 0xC400_0000–0xDFFF_FFFF (512 – 64) MB — Reserved Reserved System Integration Unit (SIU) Enhanced Time Processing Unit (eTPU) Registers Reserved Bridge B Peripherals MPC5533 Microcontroller Reference Manual, Rev. 0 1-16 Freescale Semiconductor Overview Table 1-2. MPC5533 Memory Map (continued) Bytes Address Range1 1 Module Allocated Used 0xE000_0000–0xFBFF_FFFF (512 – 64) MB — Reserved 0xFC00_0000–0xFFEF_FFFF 63 MB — Reserved 0xFFF0_0000–0xFFF0_3FFF 16 KB — Bridge B Registers 0xFFF0_4000–0xFFF0_7FFF 16 KB — Crossbar (XBAR) 0xFFF0_8000–0xFFF0_FFFF 32 KB — Reserved 0xFFF1_0000–0xFFF3_FFFF 192 KB — Reserved 0xFFF4_0000–0xFFF4_3FFF 16 KB — Error Correction Status Module (ECSM) 0xFFF4_4000–0xFFF4_7FFF 16 KB — Enhanced Direct Memory Access Controller 2 (eDMA) 0xFFF4_8000–0xFFF4_BFFF 16 KB — Interrupt Controller (INTC) 0xFFF4_C000–0xFFF4_FFFF 16 KB — Reserved 0xFFF5_0000–0xFFF7_FFFF 192 KB — Reserved 0xFFF8_0000–0xFFF8_3FFF 16 KB 164 B 0xFFF8_4000–0xFFF9_3FFF 64 KB — 0xFFF9_8000–0xFFF9_BFFF 16 KB 200 B Deserial Serial Peripheral Interface (DSPI C) 0xFFF9_C000–0xFFF9_FFFF 16 KB 200 B Deserial Serial Peripheral Interface (DSPI D) 0xFFFA_0000–0xFFFA_FFFF 64 KB — 0xFFFB_0000–0xFFFB_3FFF 16 KB 44 B 0xFFFB_8000–0xFFFB_FFFF 32 KB — 0xFFFC_0000–0xFFFC_3FFF 16 KB 1152 B Flexible Controller Area Network (FlexCAN A) 0xFFFC_4000–0xFFFC_7FFF 16 KB 1152 B Reserved 0xFFFC_8000–0xFFFC_BFFF 16 KB 1152 B Flexible Controller Area Network (FlexCAN C) 0xFFFC_C000–0xFFFF_BFFF 192 KB — 0xFFFF_C000–0xFFFF_FFFF 16 KB 4 KB Enhanced Queued Analog to Digital Converter (eQADC) Reserved Reserved Enhanced Serial Communications Interface (eSCI A) Reserved Reserved Boot Assist Module (BAM) If the allocated size is greater than the used size, the base address for the block is the lowest address of the listed address range, unless noted otherwise. 1.3.1 External Master Mode Operation Memory Map When the MPC5533 MCU acts as a slave from an external master device, the External Bus Interface (EBI) translates the 24-bit external address to a 32-bit internal address. Table 1-3 lists the translation parameters. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 1-17 Overview Table 1-3. External to Internal Memory Map Translation Table for Slave Mode 1 2 Ext addr[8:11]1 Internal addr[0:11] Size (bytes) Internal Slave Internal Address Range 0b0xxx — 8 MB — Reserved for off-chip access 0b10xx 0b0000_0000_00xx 4 MB Internal Flash 0x0000_0000–0x003F_FFFF 0b1100 0b0100_0000_0000 1 MB SRAM 0x4000_0000–0x400F_FFFF 0b1101 0b0110_0000_0000 1 MB Reserved2 0x6000_0000–0x600F_FFFF 0b1110 0b1100_0011_1111 1 MB Bridge A Peripherals 0xC3F0_0000–0xC3FF_FFFF 0b1111 0b1111_1111_1111 1 MB Bridge B Peripherals 0xFFF0_0000–0xFFFF_FFFF Only the lower 24 address signals (ADDR[8:31]) are available off-chip. Reserved for a future block that requires its own crossbar slave port. Table 1-4 shows the memory map for a MPC5533 MCU acting as a slave from the point of view of the external master. Table 1-4. MPC5533 Slave Memory Map as seen from an External Master External Address Range1 Bytes 0x00_00002–0x7F_FFFF 8 MB Used for off-chip memory accesses 0x80_0000–0x8F_FFFF 1 MB Slave flash3 0x90_0000–0xBF_FFFF 3 MB Reserved 0xC0_0000–0xC0_BFFF 48 KB Slave SRAM 0xC1_0000–0xCF_FFFF Use 1 MB–64 KB Reserved 0xD0_0000–0xCF_FFFF 1 MB Reserved 0xE0_0000–0xEF_FFFF 1 MB Slave Bridge A Peripherals 0xF0_0000–0xFF_FFFF 1 MB Slave Bridge B Peripherals 1 Only the lower 24 address signals (ADDR[8:31]) are available off-chip. This address range is not part of the MPC5533 slave memory map. It is shown to illustrate the addressing scheme for off-chip accesses when the MPC5533 is operating in slave mode. 3 The shadow block of the slave flash is not accessible by an external master 2 1.4 Detailed Features The following sections provided detailed information about each of the on-chip modules. 1.4.1 e200z3 Core Overview The e200z3 processor uses a four-stage pipeline for instruction execution: • Instruction Fetch (stage 1) • Instruction Decode/Register file Read/Effective Address Calculation (stage 2) • Execute/Memory Access (stage 3) • Register Writeback (stage 4) MPC5533 Microcontroller Reference Manual, Rev. 0 1-18 Freescale Semiconductor Overview The operation of the stages overlap, allowing single-clock instruction execution for most instructions. The integer execution unit consists of: • 32-bit Arithmetic Unit (AU) • Logic Unit (LU) • 32-bit Barrel shifter (Shifter) • Mask-Insertion Unit (MIU) • Condition Register manipulation Unit (CRU) • Count-Leading-Zeros unit (CLZ) • 32x32 Hardware Multiplier array • Result feed-forward hardware • Support hardware for division Most arithmetic and logical operations are executed in a single cycle with the exception of the divide instructions. A Count-Leading-Zeros unit operates in a single clock cycle. The Instruction Unit contains a PC incrementer and a dedicated Branch Address adder to minimize delays during change of flow operations. Sequential prefetching is performed to ensure a supply of instructions into the execution pipeline. Branch target prefetching is performed to accelerate taken branches. Prefetched instructions are placed into an instruction buffer capable of holding six instructions. Branches can also be decoded at the instruction buffer and branch target addresses calculated prior to the branch reaching the instruction decode stage, allowing the branch target to be prefetched early. When a branch is detected at the instruction buffer, a prediction can be made on whether the branch is taken or not. If the branch is predicted to be taken, a target fetch is initiated and its target instructions are placed in the instruction buffer following the branch instruction. Many branches take zero cycles to execute by using branch folding. Branches are folded out from the instruction execution pipe whenever possible. These include unconditional branches and conditional branches with condition codes that can be resolved early. Conditional branches that are not taken and not folded execute in a single clock. Branches with successful target prefetching that are not folded have an effective execution time of one clock. All other taken branches have an execution time of two clocks. Memory load and store operations are provided for byte, halfword, and word (32-bit) data with automatic zero or sign extension of byte and halfword load data as well as optional byte reversal of data. These instructions can be pipelined to allow effective single cycle throughput. Load and store multiple word instructions allow low overhead context save and restore operations. The load/store unit contains a dedicated effective address adder to allow effective address generation to be optimized. Also, a load-to-use dependency does not incur any pipeline bubbles for most cases. The Condition register unit supports the condition register (CR) and condition register operations defined by the PowerPC architecture. The condition register consists of eight 4-bit fields that reflect the results of certain operations, such as move, integer and floating-point compare, arithmetic, and logical instructions, and provide a mechanism for testing and branching. Vectored and autovectored interrupts are supported by the CPU. Vectored interrupt support is provided to allow multiple interrupt sources to have unique interrupt handlers invoked with no software overhead. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 1-19 Overview The hardware floating-point unit uses the IEEE-754 single-precision floating-point format and supports single-precision floating-point operations in a pipelined process. The general purpose register file is used for source and destination operands, thus there is a unified storage model for single-precision floating-point data types of 32-bits and the normal integer type. Single-cycle floating-point add, subtract, multiply, compare, and conversion operations are provided. Divide instructions are multi-cycle and are not pipelined. The Signal Processing Extension (SPE) Auxiliary Processing Unit (APU) provides hardware SIMD operations and supports a full compliment of dual integer arithmetic operation including Multiply Accumulate (MAC) and dual-integer multiply (MUL) in a pipelined process. The general purpose register file is enhanced such that all 32 of the GPRs are extended to 64 bits wide and are used for source and destination operands, thus there is a unified storage model for 32x32 MAC operations which generate greater than 32 bit results. The majority of both scalar and vector operations (including MAC and MUL) are executed in a single clock cycle. Both Scalar and Vector divides take multiple clocks. The SPE APU also provides extended load and store operations to support the transfer of data to and from the extended 64 bit GPRs. This SPE APU is fully binary compatible with the e200z6 SPE APU used in MPC5554 and MPC5553. The CPU includes support for variable length encoding (VLE) instruction enhancements. This allows the optional execution of an alternate instruction set consisting of a mixture of 16-bit and 32-bit instructions. This results in a significantly smaller code size footprint without affecting performance noticeably. The e200z3 core supports both the PowerPC Architecture Book E and VLE instruction sets. 1.4.2 Crossbar Switch (XBAR) The XBAR multi-port crossbar switch supports simultaneous connections between three master ports and five slave ports. • Three master ports: — Core CPU - Instruction — Core CPU - Data — eDMA — EBI • Five slave ports — Flash (64-bit data access) — EBI (16-bit data access) — SRAM (32-bit data access) — Peripheral Bridge A (32-bit data access) — Peripheral Bridge B (32-bit data access) The crossbar allows for concurrent transactions to occur from any master port to any slave port. It is possible for all master ports and slave ports to be in use at the same time as a result of independent master requests. If a slave port is simultaneously requested by more than one master port, arbitration logic selects the higher priority master and grant it ownership of the slave port. All other masters requesting that slave port stall until the higher priority master completes its transactions. By default, requesting masters have MPC5533 Microcontroller Reference Manual, Rev. 0 1-20 Freescale Semiconductor Overview equal priority and are granted access to a slave port in round-robin process, based upon the ID of the last master to be granted access. 1.4.3 Enhanced Direct Memory Access (eDMA) Controller The enhanced direct memory access (eDMA) controller is a second-generation module capable of performing complex data movements via 32 programmable channels, with minimal intervention from the host processor. The hardware micro architecture includes a DMA engine which performs source and destination address calculations, and the actual data movement operations, along with an SRAM-based memory containing the transfer control descriptors (TCD) for the channels. This implementation is utilized to minimize the overall block size. 1.4.4 Interrupt Controller (INTC) The INTC (interrupt controller) provides priority-based preemptive scheduling of interrupt requests, suitable for statically scheduled hard real-time systems. The INTC allows interrupt request servicing from up to 204 interrupt sources. For high priority interrupt requests, the time from the assertion of the interrupt request from the peripheral to when the processor is executing the interrupt service routine (ISR) has been minimized. The INTC provides a unique vector for each interrupt request source for quick determination of which ISR needs to be executed. It also provides an ample number of priorities so that lower priority ISRs do not delay the execution of higher priority ISRs. To allow the appropriate priorities for each source of interrupt request, the priority of each interrupt request is software configurable. When multiple tasks share a resource, coherent accesses to that resource must be supported. The INTC supports the priority ceiling protocol for coherent accesses. By providing a modifiable priority mask, the priority can be raised temporarily so that all tasks which share the resource can not preempt each other. Multiple processors can assert interrupt requests to each other through software settable interrupt requests. These same software settable interrupt requests also can be used to break the work involved in servicing an interrupt request into a high priority portion and a low priority portion. The high priority portion is initiated by a peripheral interrupt request, but then the ISR asserts a software settable interrupt request to finish the servicing in a lower priority ISR. Therefore these software settable interrupt requests can be used instead of the peripheral ISR scheduling a task through the RTOS. 1.4.5 Frequency Modulated Phase-Locked Loop (FMPLL) The frequency modulated PLL allows you to generate high speed system clocks from an 8–20 MHz crystal oscillator or external clock generator. Further, the FMPLL supports programmable frequency modulation of the system clock. The FMPLL multiplication factor, output clock divider ratio, modulation depth, and modulation rate are all software configurable. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 1-21 Overview 1.4.6 External Bus Interface (EBI) NOTE The EBI is available on the 324 package only—the EBI is not available on the 208 package due to pin limitations. The EBI controls data transfer across the crossbar switch to/from memories or peripherals in the external address space. The EBI includes a memory controller that generates interface signals to support a variety of external memories. The EBI memory controller supports single data rate (SDR) burst mode flash, SRAM, and asynchronous memories. In addition, the EBI supports up to four regions via chip selects (multiplexed with four address bits), along with programmed region-specific attributes. 1.4.7 System Integration Unit (SIU) The SIU controls MCU reset configuration, pad configuration, external interrupt, general purpose I/O (GPIO), internal peripheral multiplexing, and the system reset operation. The reset configuration block contains the external pin boot configuration logic. The pad configuration block controls the static electrical characteristics of I/O pins. The GPIO block provides uniform and discrete input/output control of the I/O pins of the MCU. The reset controller performs reset monitoring of internal and external reset sources, and drives the RSTOUT pin. The SIU is accessed by the e200z3 core through the crossbar switch. For more information on configuring the MPC5533 at reset see Section 1.5, “Chip Configuration. 1.4.8 On-chip Flash The MPC5533 provides 768 KB of programmable, non-volatile, flash memory. The non-volatile memory (NVM) can be used for instruction and/or data storage. The flash module interfaces the system bus to a dedicated flash memory array controller. It supports a 64-bit data bus width at the system bus port, and a 128-bit read data interface to flash memory. The module contains a four-entry, 128-bit prefetch buffer and a prefetch controller which prefetches sequential lines of data from the flash array into the buffer. Prefetch buffer hits allow no-wait responses. Normal flash array accesses are registered and are forwarded to the system bus on the following cycle, incurring three wait-states. Prefetch operations can be automatically controlled, and can be restricted to servicing a single bus master. Prefetches can also be restricted to being triggered for instruction or data accesses. 1.4.9 Static Random Access Memory (SRAM) The MPC5533 SRAM module provides a general-purpose 48-KB memory block. The first 32 KB block of the SRAM is powered by its own power supply pin, called VSTBY. This allows the contents of this memory region to be preserved when the rest of the MCU is powered down. ECC handling is done on a 32-bit boundary and is completely software compatible with MPC5500 family devices with an e200z6 core and 64-bit wide ECC syndrome. Because the e200z3 core in MPC5533 is a cacheless processor, the platform RAM is organized on a 32-bit boundary versus the 64-bit organization used on other MPC5500 family MCUs based on the e200z6 core. MPC5533 Microcontroller Reference Manual, Rev. 0 1-22 Freescale Semiconductor Overview 1.4.10 Boot Assist Module (BAM) The BAM is a block of read-only memory that is hard-coded by Freescale and is identical for all MPC5500 family MCUs with an e200zn core. The BAM program executes when the MCU is powered-on or reset in normal mode. The BAM supports the following modes of booting: • Booting from internal flash memory • Single master booting from external memory (for devices in 324 BGA that have an external bus) • Serial boot loading (a program is downloaded into RAM via eSCI or the FlexCAN and then executed) The BAM reads the reset configuration half word (RCHW) from flash memory and configures the device. Flash memory can be either internal (208 and 324 packages) or external (324 package only). For more information on configuring the MPC5533 at reset, see Section 1.5, “Chip Configuration. 1.4.11 Enhanced Time Processing Unit (eTPU) The eTPU is an enhanced co-processor designed for timing control. Operating in parallel with the host CPU, the eTPU processes instructions and real-time input events, performs output waveform generation, and accesses shared data without host intervention. Consequently, for each timer event, the host CPU setup and service times are minimized or eliminated. A powerful timer subsystem is formed by combining the eTPU with its own instruction and data RAM. High-level assembler/compiler and documentation allows customers to develop their own functions on the eTPU. The eTPU is an enhanced version of the TPU module implemented on the MC68332 and MPC500 products. Enhancements of the eTPU include a more powerful processor which handles high-level C code efficiently and allows for more functionality and increased performance. Although there is no compatibility at microcode level, the eTPU maintains several features of older TPU versions and is conceptually almost identical. The eTPU library is a superset of the standard TPU library functions modified to take advantage of enhancements in the eTPU. These, along with a C compiler, make it relatively easy to port previous applications. By providing source code for the Freescale library, the eTPU can support your own function development. The eTPU includes these distinctive features: • 32 channels, each channel is associated with one input and one output signal. — Enhanced input digital filters on the input pins for improved noise immunity. — Identical, orthogonal channels: each channel can perform any time function. Each time function can be assigned to more than one channel as a given time, so each signal can have any functionality. — Each channel has an event mechanism which supports single and double action functionality in various combinations. It includes two 24-bit capture registers, two 24-bit match registers, 24-bit greater-equal and equal-only comparators — Input and output signal states visible from the host • Two independent 24-bit time bases for channel synchronization: MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 1-23 Overview • • • — First time base clocked by system clock with programmable prescale division from 2 to 512 (in steps of 2), or by output of second time base prescaler — Second time base counter can work as a continuous angle counter, enabling angle based applications to match angle instead of time — Both timebases visible from the host Event-triggered microengine: — Fixed-length instruction execution in two-system-clock microcycle — 12 KB of code memory (SCM) — 2.5 KB of parameter (data) RAM (SPRAM) — Parallel execution of data memory, ALU, channel control and flow control sub-instructions in selected combinations — 32-bit microengine registers and 24-bit wide ALU, with 1 microcycle addition and subtraction, absolute value, bitwise logical operations on 24-bit, 16-bit, or byte operands, single bit manipulation, shift operations, sign extension and conditional execution — Additional 24 bit Multiply/MAC/Divide unit which supports all signed/unsigned Multiply/MAC combinations, and unsigned 24-bit divide. The MAC/Divide unit works in parallel with the regular microcode commands Resource sharing features support channel use of common channel registers, memory and microengine time: — Hardware scheduler works as a “task management” unit, dispatching event service routines by pre-defined, host-configured priority. — Automatic channel context switch when a "task switch" occurs, such as one function thread ends and another begins to service a request from other channel: channel-specific registers, flags and parameter base address are automatically loaded for the next serviced channel — SPRAM shared between host CPU and eTPU, supporting communication either between channels and host or inter-channel — Dual-parameter coherency hardware support allows atomic access to two parameters by host Test and development support features: — Nexus Class 3 debug, supporting single-step execution, arbitrary microinstruction execution, hardware breakpoints and watchpoints on several conditions (see Section 1.4.16, “Nexus,” for more details on the Nexus module) — Software breakpoints — SCM continuous signature-check built-in self test (MISC—multiple input signature calculator), runs concurrently with eTPU normal operation 1.4.12 Enhanced Queued Analog/Digital Converter (eQADC) The enhanced queued analog to digital converter (eQADC) block provides accurate and fast conversions for a wide range of applications. The eQADC provides a parallel interface to an on-chip analog-to-digital converter (ADC), and a single master to single slave serial interface to an off-chip external device. The on-chip ADC is designed to allow access to all the analog channels. MPC5533 Microcontroller Reference Manual, Rev. 0 1-24 Freescale Semiconductor Overview The eQADC transfers commands from multiple command FIFOs (CFIFOs) to the on-chip ADC or to the external device. The block also receives data from the on-chip ADC or from an off-chip external device into multiple result FIFOs (RFIFOs) in parallel, independently of the CFIFOs. The eQADC supports software and external hardware triggers from other blocks to initiate transfers of commands from the CFIFOs to the on-chip ADC or to the external device. It also monitors the fullness of CFIFOs and RFIFOs, and accordingly generates DMA or interrupt requests to control data movement between the FIFOs and the system memory, which is external to the eQADC. 1.4.13 Deserial/Serial Peripheral Interface (DSPI) The deserial serial peripheral interface (DSPI) block provides a synchronous serial interface for communication between the MPC5533 MCU and external devices. The DSPI supports pin count reduction through serialization and deserialization of eTPU channels and memory-mapped registers. The channels and register content are transmitted using a SPI-like protocol. There are two identical DSPI blocks on the MPC5533 MCU. The DSPIs have three configurations: • Serial peripheral interface (SPI) configuration where the DSPI operates as a SPI with support for queues • Deserial serial interface (DSI) configuration where the DSPI serializes eTPU output channels and deserializes the received data by placing it on the eTPU input channels • Combined serial interface (CSI) configuration where the DSPI operates in both SPI and DSI configurations interleaving DSI frames with SPI frames, giving priority to SPI frames For queued operations, the SPI queues reside in system memory external to the DSPI. Data transfers between the memory and the DSPI FIFOs are accomplished through the use of the eDMA controller or through host software. 1.4.14 Enhanced System Communications Interface (eSCI) The enhanced serial communications interface (eSCI) allows asynchronous serial communications with peripheral devices and other MCUs. It includes special support to interface to local interconnect network (LIN) slave devices. 1.4.15 Flexible Controller Area Network (FlexCAN) The MPC5533 MCU contains two controller area network (FlexCAN) blocks. Each FlexCAN module is a communication controller implementing the CAN protocol according to Bosch Specification version 2.0B. The CAN protocol was designed to be used primarily as a vehicle serial data bus, meeting the specific requirements of this field: real-time processing, reliable operation in the EMI environment of a vehicle, cost-effectiveness and required bandwidth. Each FlexCAN module has 64 message buffers (MB). 1.4.16 Nexus The NDI (Nexus Debug Interface) block provides real-time development support capabilities for the MPC5533 MCU in compliance with the IEEE-ISTO 5001-2003 standard. This development support is MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 1-25 Overview supplied for MCUs without requiring external address and data pins for internal visibility. The NDI block is an integration of several individual Nexus blocks that are selected to provide the development support interface for the MPC5533. The NDI block interfaces to the host processor, eTPU, and internal buses to provide development support as per the IEEE-ISTO 5001-2003 standard. The development support provided includes program trace, data trace, watchpoint trace, ownership trace, run-time access to the MCUs internal memory map and access to the core and eTPU internal registers during halt. The Nexus interface also supports a JTAG only mode using only the JTAG pins. The following features are implemented: • 15 or 23 full duplex pin interface for medium and high visibility throughput: — One of two modes selected by register configuration: full port mode (FPM) and reduced port mode (RPM): FPM comprises 12 MDO pins (324 package only); RPM comprises four MDO pins (208 and 324 packages). — Auxiliary output port • One MCKO (message clock out) pin • Four or 12 MDO (message data out) pins • Two MSEO (message start/end out) pins • One RDY (ready) pin • One EVTO (event out) pin — Auxiliary input port • One EVTI (event in) pin • Five pin JTAG port (JCOMP, TDI, TDO, TMS, and TCK) — Supports JTAG mode • Host processor (e200) development support features — IEEE-ISTO 5001-2003 standard Class 3 compliant — Data trace via data write messaging (DWM) and data read messaging (DRM). This allows the development tool to trace reads and/or writes to selected internal memory resources. — Ownership trace via ownership trace messaging (OTM). OTM facilitates ownership trace by providing visibility of which process ID or operating system task is activated. An ownership trace message is transmitted when a new process/task is activated, allowing development tools to trace ownership flow. — Program trace via branch trace messaging (BTM). Branch trace messaging displays program flow discontinuities (direct branches, indirect branches, exceptions, etc.), allowing the development tool to interpolate what transpires between the discontinuities. Thus, static code can be traced. — Watchpoint messaging (WPM) via the auxiliary port — Watchpoint trigger enable of program and/or data trace messaging — Data tracing of instruction fetches via private opcodes — Subset of PowerPC Architecture Book E software debug facilities with OnCE block (Nexus Class 1 features implemented by OnCE) • eTPU development support features MPC5533 Microcontroller Reference Manual, Rev. 0 1-26 Freescale Semiconductor Overview • • • • — IEEE-ISTO 5001-2003 standard Class 3 compliant for the eTPU — Data trace via data write messaging and data read messaging. This allows the development tool to trace reads and writes to selected shared parameter RAM (SPRAM) address ranges. Four data trace windows are available. — Ownership trace via ownership trace messaging (OTM). OTM facilitates ownership trace by providing visibility of which channel is being serviced. An ownership trace message is transmitted to indicate when a new channel service request is scheduled, allowing the development tools to trace task flow. A special OTM is sent when the engine enters in idle state, meaning that all requests were serviced and no new requests are yet scheduled. — Program trace via branch trace messaging. BTM displays program flow discontinuities (start, repeat, jump, return, etc.), allowing the development tool to interpolate what transpires between the discontinuities. Thus static code can be traced. The branch trace messaging method uses the branch/predicate method to reduce the number of generated messages. — Watchpoint messaging via the auxiliary port. WPM provides visibility of the occurrence of the eTPUs’ watchpoints and breakpoints. — Nexus based breakpoint/watchpoint configuration and single step support. Run-time access to the on-chip memory map via the Nexus read/write access protocol. This feature supports accesses for run-time internal visibility, calibration variable acquisition, calibration constant tuning, and external rapid prototyping for powertrain automotive development systems. All features are independently configurable and controllable via the IEEE 1149.1 I/O port. The NDI block reset is controlled with JCOMP, power-on reset, and the TAP state machine. All these sources are independent of system reset. Power-on-reset status indication during reset via MDO[0] in disabled and reset modes 1.4.17 JTAG The JTAGC (JTAG Controller) block provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode. Testing is performed via a boundary scan technique, as defined in the IEEE 1149.1-2001 standard. All data input to and output from the JTAGC block is communicated in serial format. The JTAGC block is compliant with the IEEE 1149.1-2001 standard. 1.5 Chip Configuration Various functions of the MPC5533 can be implemented at reset, and the following operations can be configured: • Boot mode — Internal memory boot (default) — External memory boot (single master—324 package only) — Boot from serial port (FlexCAN or eSCI) • PLL mode — Normal mode with crystal reference (default) MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 1-27 Overview • — Normal mode with external reference — Bypass mode Watchdog timer enable MPC5533 Microcontroller Reference Manual, Rev. 0 1-28 Freescale Semiconductor Overview 1.6 Related Documentation Table 1-5 lists other documents that provide information related to the MPC5533 and its development support tools. Documentation is available from a local Freescale distributor, a Freescale semiconductor sales office, the Freescale Literature Distribution Center, or through the Freescale world-wide web address at http://www.freescale.com. Table 1-5. MPC5533 and Related Documentation Freescale Document Number Title AN1259/D System Design and Layout Techniques for Noise Reduction in MCU-Based Systems AN2614 Nexus Interface Options for the MPC5500 Family AN2705 Signal Integrity Considerations with MPC5500-base Systems AN2706 EMC Guidelines for MPC5500-based Systems MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 1-29 Overview MPC5533 Microcontroller Reference Manual, Rev. 0 1-30 Freescale Semiconductor Chapter 2 Signals This chapter describes the external device signals, including a table of signal properties, detailed descriptions of the available signals, and the I/O pin power/ground segmentation. 2.1 Block Diagram Figure 2-1 shows the signals that are available on the device in the 324 package: • Signals designated in red are not available on the 208 package due to pin limitations. • Signals shown in blue are primary functions that are not designed into this device. Read the Package column in Table 2-1 for the alpha/numeric code that identifies each ball for a set of muxed signals. You can cross reference this column to the BGA package figures in the Data Sheet to identify the ball location on the device. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 2-1 RESET RSTOUT GPIO[208]_IRQ[4]_PLLCFG[0] RESET/ CONFIGURATION EXTERNAL BUS INTERFACE (EBI) AN[0]_DAN0+ AN[1]_DAN0AN[2]_DAN1+ AN[3]_DAN1AN[4]_DAN2+ AN[5]_DAN2AN[6]_DAN3+ AN[7]_DAN3AN[8]_ANW AN[9]_ANX AN[10]_ANY AN[11]_ANZ AN[12]_MA[0]_SDS AN[13]_MA[1]_SDO AN[14]_MA[2]_SDI AN[15]_FCK AN[16:31] AN[32:39] VRH VRL REFBYPC GPIO[209]_SOUTD_IRQ[5]_PLLCFG[1] GPIO[210]_RSTCFG GPIO[211]_IRQ[2]_BOOTCFG[0] GPIO[212]_IRQ[3]_BOOTCFG[1] GPIO[213]_WKPCFG GPIO[0]_ADDR[8]_CS[0] GPIO[1:3]_ADDR[9:11]_CS[1:3] GPIO[8:27]_ADDR[12:31] GPIO[28:43]_DATA[0:15] GPIO[62]_RD_WR GPIO[63]_BDIP GPIO[64:65]_WE/BE[0:1] GPIO[68]_OE GPIO[69]_TS GPIO[70]_TA EVTI NEXUS EVTO MCKO MDO[0] MDO[3:1] GPIO[82:75]_MDO[11:4] MSEO[1:0] RDY JTAG/TEST TCK TDI TDO TMS JCOMP TEST GPIO[83]_CNTXA GPIO[84]_CNRXA FlexCAN MPC5533 eQADC TCRCLKA_IRQ[7]_GPIO[113] ETPUA[0:3]_ETPUA[12:15]_GPIO[114:117] ETPUA[4:7]_ETPUA[16:19]_GPIO[118:121] ETPUA[8:11]_ETPUA[20:23]_GPIO[122:125] ETPUA[12]_GPIO[126] ETPUA[13]_GPIO[127] ETPUA[14]_GPIO[128] ETPUA[15]_GPIO[129] ETPUA[16]_PCSD[1]_GPIO[130] ETPUA[17]_PCSD[2]_GPIO[131] ETPUA[18]_PCSD[3]_GPIO[132] ETPUA[19]_PCSD[4]_GPIO[133] ETPUA[20:23]_IRQ[8:11]_GPIO[134:137] ETPUA[24:26]_IRQ[12:14]_GPIO[138:140] ETPUA[27]_IRQ[15]_GPIO[141] ETPUA[28]_PCSC[1]_GPIO[142] ETPUA[29]_PCSC[2]_GPIO[143] ETPUA[30]_PCSC[3]_GPIO[144] ETPUA[31]_PCSC[4]_GPIO[145] eTPU GPIO[85]_PCSC[3] GPIO[86]_PCSC[4] GPIO[87]_PCSD[3]_CNTXC GPIO[88]_PCSD[4]_CNRXC GPIO[179:188] PCSD[3]_GPIO[189] PCSD[4]_GPIO[190] SOUTC_GPIO[191] SOUTD_GPIO[192] eSCI GPIO[89]_TXDA GPIO[90]_RXDA GPIO[91]_PCSD[1] GPIO[92]_PCSD[5] GPIO[93]_PCSC[1] GPIO[94]_PCSC[2] GPIO[95]_PCSC[5] GPIO[96]_PCSD[2] GPIO[97]_PCSB[2] GPIO[98]_SCKD GPIO[99]_SIND DSPI NC GPIO[100]_SOUTD GPIO[101] GPIO[102]_PCSC[1] GPIO[103]_PCSC[2] GPIO[104]_PCSC[5] GPIO[105]_PCSD[2] GPIO[106]_PCSD[0] GPIO[107]_SOUTC GPIO[108]_SINC GPIO[109]_SCKC GPIO[110]_PCSC[0] NC IRQ[0:1]_GPIO[193_194] GPIO[195:202] GPIO[203:204] GPIO[206:207] GPIO XTAL EXTCLK_EXTAL CLKOUT ENGCLK CLOCK SYNTHESIZER VRC33 VRCVSS VRCCTL VDDA1 VSSA1 VDDSYN VSSSYN VFLASH POWER/ GROUND VPP VSTBY VDD VDDE VDDEH 3.3V VSS(GND) VDDA0 VSSA0 Figure 2-1. MPC5533 Block Diagram MPC5533 Microcontroller Reference Manual, Rev. 0 2-2 Freescale Semiconductor 2.2 External Signal Descriptions This section summarizes the external signal functions, the electrical characteristics, and pad configuration settings for this device. The signal properties and electrical characteristics are set in the System Integration Unit (SIU) Pad Configuration (PCR) registers. 2.2.1 Multiplexed Signals Signal functions are multiplexed to each ball on the BGA in a function hierarchy: Primary, Main Primary, Alternate, Second Alternate, and General Purpose Input/Output (I/O). For example, in the signal PCSA[3]_SIND_GPIO[99], the primary signal function is PCSA[3], the first alternate signal function is SIND, and the GPIO function is a generic General Purpose I/O signal. Multiplexing signal functions allows for more flexibility when configuring the device, as well as providing compatibility with other devices in the MPC5500 product family. The primary signal function name is used in the Ball Grid Array (BGA) map to identify the location of the ball, however, the primary signal function is not always valid for all devices. As shown in Figure 2-2, when the primary signal function is not available on the device, the Signal Name column contains the primary signal function name, ‘No primary signal’ is shown in the Signal Function column, and a dash appears in the P/A/G, and I/O Type columns. Table footnote Primary function not designed into this device Table 4-1. Signal Properties Primary signal functions are listed first Secondary signal functions 1 are alternate functions and are listed after the primary signal GPIO signal functions are general functions listed last 1 Pin Loc Signal Names 2 PCSA[3]_ SIND_ GPIO[99] Signal Functions No primary signal DSPI D data input GPIO Status P/ A/ G I/O Type — A G — I I/O Voltage Pad Type During Reset After Reset VDDEH6 MH – / Up – / Up 496 R5, P5, R7 Some devices have two alternate signals muxed to the same ball: first alternate (A); second alternate (A2). Figure 2-2. Primary Function Not Available on Device The entries in the P/A/G column designate the position in the signal function hierarchy for multiplexed functions. These symbols correspond to binary values for the Pin Assignment (PA) field in the SIU_PCR registers that determine the active signal function. The PA field length varies from 1- to 3-bits, depending on the PCR register. Figure 2-3 explains the symbol definitions used in the P/A/G column for Table 2-1. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 2-3 Bit 3 in the SUI_PCR registers is bit 0 in the PA field. Register Bits P/A/G Symbol G The main primary function is used for compatibility. PA Signal Type General purpose I/O 3 4 5 – – 0 P Primary – – 1 A Alternate – 1 0 MP Main – 1 1 A2 Second alternate 1 0 0 1 n n All other values reserved for future use. 1 Bit 5 in the SUI_PCR registers is bit 2 in the PA field. PA[0:2] Number of Muxed Signals 1 1-bit 2 muxed signals 2-bits 4 muxed signals 3-bits > 4 muxed signals Two-bit PA fields include the 1-bit muxed signal values; 3-bit PA fields include the 1- and 2-bit muxed signal values. Figure 2-3. Understanding the P/A/G Column Entries 2.2.2 Device Signals Summary Table 2-1 gives a summary of the device’s external signals and properties. See Section 2.3, “Detailed Signal Description,” for detailed descriptions of each signal. The signals shown in red are not available on the 208 package; signals shown in blue are primary functions that are not available in this device. Table 2-1. MPC5533 Signal Properties Status Signal Name 1 Signal Function 2 P/ A/ G I/O Type Voltage3 Package Pad Type4 During Reset5 After Reset6 208 324 Reset / Configuration RESET External reset input P I VDDEH6 SH RESET / Up RESET / Up L16 R22 RSTOUT External reset output P O VDDEH6 SH RSTOUT / Low RSTOUT / High K15 P21 PLLCFG[0]_ IRQ[4]_ GPIO[208] PLLMRFM mode selection External interrupt request GPIO P A G I I I/O VDDEH6 MH PLLCFG / Up – / Up M14 V21 PLLCFG[1]_ IRQ[5]_ SOUTD_ GPIO[209] PLLMRFM reference selection External interrupt request DSPI D data output GPIO P A A2 G I I O I/O VDDEH6 MH PLLCFG / Up – / Up N15 U20 RSTCFG_ GPIO[210] Reset configuration input GPIO P G I I/O VDDEH6 SH RSTCFG / Up – / Up — P22 BOOTCFG[0]_ IRQ[2]_ GPIO[211] Boot configuration input External interrupt request GPIO P A G I I I/O VDDEH6 SH BOOTCFG / Down – / Down — U21 BOOTCFG[1]_ IRQ[3]_ GPIO[212] Boot configuration input External interrupt request GPIO P A G I I I/O VDDEH6 SH BOOTCFG / Down – / Down M15 T20 MPC5533 Microcontroller Reference Manual, Rev. 0 2-4 Freescale Semiconductor Table 2-1. MPC5533 Signal Properties (Continued) Status Signal Name 1 WKPCFG_ GPIO[213] Signal Function 2 Weak pull configuration input GPIO Package P/ A/ G I/O Type Voltage3 Pad Type4 During Reset5 After Reset6 208 324 P G I I/O VDDEH6 SH WKPCFG / Up – / Up L15 R19 VDDE2 F – / Up – / Up9 R1 M4 VDDE2 F – / Up – / Up9 — M3, N2, N1 External Bus Interface (EBI) 7 CS[0]_8 External chip selects ADDR[8]_ External address bus GPIO[0] GPIO CS[1:3]_8, 10 External chip selects ADDR[9:11]_ External address bus GPIO[1:3] GPIO O P A G I/O P A G I/O I/O O I/O ADDR[12:26]_8, 10 External address bus P I/O GPIO[8:22] GPIO G I/O ADDR[27:29]_8, 10 External address bus P I/O GPIO[23:25] GPIO G I/O ADDR[30:31]_8, 10 External address bus P I/O GPIO[26:27] GPIO G I/O DATA[0:15]_8, 10 External data bus P I/O GPIO[28:43] GPIO G I/O RD_WR_ 8, 10 External read/write P I/O GPIO[62] GPIO G I/O BDIP_8, 10 External burst data in progress P O GPIO[63] GPIO G I/O WE/BE[0:1]_8, 10 External write/byte enable P O GPIO[64:65] GPIO G I/O OE_8 External output enable P O GPIO[68] GPIO G I/O TS_8, 10 External transfer start P I/O GPIO[69] GPIO G I/O T3, U3, U4, V3, P1, P2, R1, R2, T1, T2, U1, U2, V1, V2, W1 VDDE2 F – / Up – / Up9 — VDDE2 F – / Up – / Up9 — Y2, Y1, AA1 VDDE2 F – / Up – / Up9 — W3, V4 VDDE3 F – / Up – / Up9 — AB4, AA5, AB5, AB6, AB7, AA8, AB8, AA9, Y6, Y7, Y8, W9, W10, Y10, W11, Y11 VDDE2 F – / Up – / Up9 — P3 VDDE2 F – / Up – / Up9 — M1 VDDE2 F – / Up – / Up9 — N4, N3 VDDE3 F – / Up – / Up9 T3 AB9 VDDE2 F – / Up – / Up9 — T4 MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 2-5 Table 2-1. MPC5533 Signal Properties (Continued) Status Signal Name 1 Signal Function 2 P/ A/ G I/O Type TA_ 8, 10 External transfer acknowledge P I/O GPIO[70] GPIO G I/O Package Voltage3 Pad Type4 During Reset5 After Reset6 208 324 VDDE2 F – / Up – / Up9 — R4 NEXUS EVTI Nexus event in P I VDDE7 F I / Up EVTI / Up E15 F21 EVTO Nexus event out P O VDDE7 F O / Low EVTO / High D15 F22 MCKO Nexus message clock out P O VDDE7 F O / Low MCKO / Enabled11 F15 G20 MDO[0]12 Nexus message data out P O VDDE7 F O / High MDO / Low A14 B20 MDO[3:1] Nexus message data out P O VDDE7 F O / Low MDO / Low B13, A13, B14 D18, C18, C19 VDDE7 F O / Low – / Down — A17:18, B17, A19, B18, D17, C17, B19 O VDDE7 F O / High MSEO / High E16, C15 G22, G21 O VDDE7 F O / High RDY / High — G19 MDO[11:4]_ Nexus message data out P O GPIO[82:75]13 GPIO G I/O MSEO[1:0] Nexus message start/end out P RDY Nexus ready output P JTAG / TEST TCK JTAG test clock input P I VDDE7 F TCK / Down TCK / Down C16 D21 TDI JTAG test data input P I VDDE7 F TDI / Up TDI / Up E14 D22 TDO JTAG test data output P O VDDE7 F TDO / Up TDO / Up F14 E21 TMS JTAG test mode select input P I VDDE7 F TMS / Up TMS / Up D14 E20 JCOMP JTAG TAP controller enable P I VDDE7 F JCOMP / Down JCOMP / Down F16 F20 TEST Test mode select P I VDDE7 F TEST / Up TEST / Up D16 E22 FlexCAN CNTXA_ GPIO[83] FlexCAN A transmit GPIO P G O I/O VDDEH4 SH I / Up – / Up14 P12 Y17 CNRXA_ GPIO[84] FlexCAN A receive GPIO P G I I/O VDDEH4 SH – / Up – / Up17 R12 AA18 CNTXB_ 15 No primary signal DSPI C peripheral chip select GPIO — A G — O I/O VDDEH4 MH – / Up – / Up T12 AB18 No primary signal DSPI C peripheral chip select GPIO — A G — O I/O VDDEH4 MH – / Up – / Up R13 AB19 PCSC[3]_ GPIO[85] CNRXB _15 PCSC[4]_ GPIO[86] MPC5533 Microcontroller Reference Manual, Rev. 0 2-6 Freescale Semiconductor Table 2-1. MPC5533 Signal Properties (Continued) Status Signal Name 1 Signal Function 2 Package P/ A/ G I/O Type Voltage3 Pad Type4 During Reset5 After Reset6 208 324 CNTXC_ PCSD[3]_ GPIO[87] FlexCAN C transmit DSPI D peripheral chip select GPIO P A G O O I/O VDDEH6 MH – / Up – / Up K13 P19 CNRXC_ PCSD[4]_ GPIO[88] FlexCAN C receive DSPI D peripheral chip select GPIO P A G I O I/O VDDEH6 MH – / Up – / Up L14 R20 eSCI TXDA_ GPIO[89] eSCI A transmit GPIO P G O I/O VDDEH6 SH – / Up – / Up J14 N20 RXDA_ GPIO[90] eSCI A receive GPIO P G I I/O VDDEH6 SH – / Up – / Up K14 P20 TXDB_ PCSD[1]_ GPIO[91] No primary signal DSPI D peripheral chip select GPIO — A G — O I/O VDDEH6 MH – / Up – / Up L13 R21 RXDB_ PCSD[5]_ GPIO[92] No primary signal DSPI D peripheral chip select GPIO — A G — O I/O VDDEH6 MH – / Up – / Up M13 T19 DSPI SCKA_15 — A G — O I/O VDDEH6 MH – / Up – / Up — L22 GPIO[93] No primary signal DSPI C peripheral chip select GPIO SINA_15 PCSC[2]_ GPIO[94] No primary signal DSPI C peripheral chip select GPIO — A G — O I/O VDDEH6 MH – / Up – / Up — L21 SOUTA_15 PCSC[5]_ GPIO[95] No primary signal DSPI C peripheral chip select GPIO — A G — O I/O VDDEH6 MH – / Up – / Up — L20 PCSA[0]_15 PCSD[2]_ GPIO[96] No primary signal DSPI D peripheral chip select GPIO — A G — O I/O VDDEH6 MH – / Up – / Up — M20 PCSA[1]_15 PCSB[2]_ 16 GPIO[97] No primary signal No alternate signal GPIO — — G — — I/O VDDEH6 MH – / Up – / Up — M19 PCSA[2]_15 SCKD_ GPIO[98] No primary signal DSPI D clock GPIO — A G — I/O I/O VDDEH6 MH – / Up – / Up J15 M21 PCSA[3]_15 SIND_ GPIO[99] No primary signal DSPI D data input GPIO — A G — I I/O VDDEH6 MH – / Up – / Up H13 K19 PCSA[4]_15 SOUTD_ GPIO[100] No primary signal DSPI D data output GPIO — A G — O I/O VDDEH6 MH – / Up – / Up — N19 PCSC[1]_ MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 2-7 Table 2-1. MPC5533 Signal Properties (Continued) Status Package P/ A/ G I/O Type Voltage3 Pad Type4 During Reset5 After Reset6 208 324 PSCB[3]_ GPIO[101] No primary signal No alternate signal GPIO — A G — O I/O VDDEH6 MH – / Up – / Up — N21 SCKB_15 PCSC[1]_ GPIO[102] No primary signal DSPI C peripheral chip select GPIO — A G — O I/O VDDEH1017 MH – / Up – / Up J16 K21 SINB_15 PCSC[2]_ GPIO[103] No primary signal DSPI C peripheral chip select GPIO — A G — O I/O VDDEH1017 MH – / Up – / Up G15 H22 SOUTB_15 PCSC[5]_ GPIO[104] No primary signal DSPI C peripheral chip select GPIO — A G — O I/O VDDEH1017 MH – / Up – / Up G13 J19 PCSB[0]_15 PCSD[2]_ GPIO[105] No primary signal DSPI D peripheral chip select GPIO — A G — O I/O VDDEH1017 MH – / Up – / Up G16 J21 PCSB[1]_15 PCSD[0]_ GPIO[106] No primary signal DSPI D peripheral chip select GPIO — A G — I/O I/O VDDEH1017 MH – / Up – / Up H16 J22 PCSB[2]_15 SOUTC_ GPIO[107] No primary signal DSPI C data output GPIO — A G — O I/O VDDEH1017 MH – / Up – / Up H15 K22 PCSB[3]_15 SINC_ GPIO[108] No primary signal DSPI C data input GPIO — A G — I I/O VDDEH617 MH – / Up – / Up G14 J20 PCSB[4]_15 SCKC_ GPIO[109] No primary signal DSPI C clock GPIO — A G — I/O I/O VDDEH617 MH – / Up – / Up H14 K20 PCSB[5]_15 PCSC[0]_ GPIO[110] No primary signal DSPI C peripheral chip select GPIO — A G — I/O I/O VDDEH617 MH – / Up – / Up J13 L19 Signal Name 1 PCSA[5]_15 16 Signal Function 2 eQADC AN[0]_ DAN0+ Single-ended analog input Positive terminal differential input P I VDDA118 AE I/– AN[0] / – B5 B8 AN[1]_ DAN0– Single-ended analog input Negative terminal differential input P I VDDA118 AE I/– AN[1] / – A6 A8 AN[2]_ DAN1+ Single-ended analog input Positive terminal differential input P I VDDA118 AE I/– AN[2] / – D6 D10 AN[3]_ DAN1– Single-ended analog input Negative terminal differential input P I VDDA118 AE I/– AN[3] / – C7 C9 AN[4]_ DAN2+ Single-ended analog input Positive terminal differential input P I VDDA118 AE I/– AN[4] / – B6 B9 AN[5]_ DAN2– Single-ended analog input Negative terminal differential input P I VDDA118 AE I/– AN[5] / – A7 A9 AN[6]_ DAN3+ Single-ended analog input Positive terminal differential input P I VDDA118 AE I/– AN[6] / – D7 D11 MPC5533 Microcontroller Reference Manual, Rev. 0 2-8 Freescale Semiconductor Table 2-1. MPC5533 Signal Properties (Continued) Status Signal Name 1 Signal Function 2 Package P/ A/ G I/O Type Voltage3 Pad Type4 During Reset5 After Reset6 208 324 AN[7]_ DAN3– Single-ended analog input Negative terminal differential input P I VDDA118 AE I/– AN[7] / – C8 C10 AN[8]_ ANW Single-ended analog input External multiplexed analog input P I VDDA118 AE I/– AN[8] / – — C5 AN[9]_ ANX Single-ended analog input External multiplexed analog input P I VDDA118 AE I/– AN[9] / – A2 D7 AN[10]_ ANY Single-ended analog input External multiplexed analog input P I VDDA118 AE I/– AN[10] / – — D8 AN[11]_ ANZ Single-ended analog input External multiplexed analog input P I VDDA118 AE I/– AN[11] / – A3 A5 AN[12]_ MA[0]_ SDS Single-ended analog input Mux address eQADC serial data strobe P19 A G20 I O O VDDEH9 MH, A21 I/– AN[12] / – A12 A16 AN[13]_ MA[1]_ SDO Single-ended analog input Mux address eQADC serial data out P19 A G20 I O O VDDEH9 MH, A21 I/– AN[13] / – B12 B16 AN[14]_ MA[2]_ SDI Single-ended analog input Mux address eQADC serial data in P19 A G20 I O I VDDEH9 MH, A21 I/– AN[14] / – C12 C16 AN[15]_ FCK Single-ended analog input eQADC free running clock P19 G20 I O VDDEH9 MH, A21 I/– AN[15] / – C13 D16 AN[16:18] Single-ended analog input P I VDDA118 AE I/– AN[16:18] / C6, C4, – D5 B7, C6, D9 AN[19:20] Single-ended analog input P I VDDA118 AE I/– AN[19:20] / – — B6, C7 AN[21] Single-ended analog input P I VDDA118 AE I/– AN[21] / – B4 C8 AN[22:25] Single-ended analog input P I VDDA018 AE I/– AN[22:25] / B8, C9, – D8, B9 C11, B11, D12, C12 AN[26] Single-ended analog input P I VDDA018 AE I/– AN[26] / – — B12 AN[27:28] Single-ended analog input P I VDDA018 AE I/– AN[27:28] / – A10, B10 A12, A13 AN[29] Single-ended analog input P I VDDA018 AE I/– AN[29] / – — D13 D9, D10, C10, C11, C5, D11 C13, B13, B14, C14, D14, A14 AN[30:35] Single-ended analog input P I VDDA018 AE I/– AN[30:35] / – AN[36:39] Single-ended analog input P I VDDA118 AE I/– AN[36:39] / F4, E3, – B3, D2 VRH Voltage reference high P I – 18 VDDINT –/– VRH A8 A10 I – 18 VSSINT –/– VRL A9 A11 – 18 VDDINT –/– REFBYPC B7 B10 VRL REFBYPC Voltage reference low Reference bypass capacitor input P P I B4, A4, D6, B5 MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 2-9 Table 2-1. MPC5533 Signal Properties (Continued) Status Signal Name 1 Signal Function 2 P/ A/ G I/O Type Package Voltage3 Pad Type4 During Reset5 After Reset6 208 324 eTPU TCRCLKA_ IRQ[7]_ GPIO[113] eTPU A TCR clock External interrupt request GPIO P A G I I I/O VDDEH1 SH – / Up – / Up L4 M2 ETPUA[0:3]_ ETPUA[12:15]_ GPIO[114:117] eTPU A channel eTPU A channels (output only) GPIO P A G I/O O I/O VDDEH1 SH –/ WKPCFG –/ WKPCFG N3, M3, P2, P1 L3, L4, K3, L2 ETPUA[4]_ ETPUA[16]_ GPIO[118] eTPU A channel eTPU A channel (output only) GPIO P A G I/O O I/O VDDEH1 MH –/ WKPCFG –/ WKPCFG N2 L1 ETPUA[5]_ ETPUA[17]_ GPIO[119] eTPU A channel eTPU A channel (output only) GPIO P A G I/O O I/O VDDEH1 MH –/ WKPCFG –/ WKPCFG M4 K4 ETPUA[6]_ ETPUA[18]_ GPIO[120] eTPU A channel eTPU A channel (output only) GPIO P A G I/O O I/O VDDEH1 SH –/ WKPCFG –/ WKPCFG L3 J3 ETPUA[7]_ ETPUA[19]_ GPIO[121] eTPU A channel eTPU A channel (output only) GPIO P A G I/O O I/O VDDEH1 SH –/ WKPCFG –/ WKPCFG K3 K2 ETPUA[8]_ ETPUA[20]_ GPIO[122] eTPU A channel eTPU A channel (output only) GPIO P A G I/O O I/O VDDEH1 SH –/ WKPCFG –/ WKPCFG N1 K1 ETPUA[9]_ ETPUA[21]_ GPIO[123] eTPU A channel eTPU A channel (output only) GPIO P A G I/O O I/O VDDEH1 SH –/ WKPCFG –/ WKPCFG M2 J4 ETPUA[10]_ ETPUA[22]_ GPIO[124] eTPU A channel eTPU A channel (output only) GPIO P A G I/O O I/O VDDEH1 SH –/ WKPCFG –/ WKPCFG M1 H3 ETPUA[11]_ ETPUA[23]_ GPIO[125] eTPU A channel eTPU A channel (output only) GPIO P A G I/O O I/O VDDEH1 SH –/ WKPCFG –/ WKPCFG L2 J2 ETPUA[12]_ GPIO[126] eTPU A channel GPIO P G I/O I/O VDDEH1 MH –/ WKPCFG –/ WKPCFG L1 J1 ETPUA[13]_ GPIO[127] eTPU A channel GPIO P G I/O I/O VDDEH1 MH –/ WKPCFG –/ WKPCFG J4 G4 ETPUA[14]_ GPIO[128] eTPU A channel GPIO P G I/O I/O VDDEH1 MH –/ WKPCFG –/ WKPCFG J3 G3 ETPUA[15]_ GPIO[129] eTPU A channel GPIO P G I/O I/O VDDEH1 MH –/ WKPCFG –/ WKPCFG K2 H2 ETPUA[16]_ PCSD[1]_ GPIO[130] eTPU A channel DSPI D peripheral chip select GPIO P A G I/O O I/O VDDEH1 MH –/ WKPCFG –/ WKPCFG K1 H1 ETPUA[17]_ PCSD[2]_ GPIO[131] eTPU A channel DSPI D peripheral chip select GPIO P A G I/O O I/O VDDEH1 MH –/ WKPCFG –/ WKPCFG H3 F3 MPC5533 Microcontroller Reference Manual, Rev. 0 2-10 Freescale Semiconductor Table 2-1. MPC5533 Signal Properties (Continued) Status Signal Name 1 Signal Function 2 Package P/ A/ G I/O Type Voltage3 Pad Type4 During Reset5 After Reset6 208 324 ETPUA[18]_ PCSD[3]_ GPIO[132] eTPU A channel DSPI D peripheral chip select GPIO P A G I/O O I/O VDDEH1 MH –/ WKPCFG –/ WKPCFG H4 F4 ETPUA[19]_ PCSD[4]_ GPIO[133] eTPU A channel DSPI D peripheral chip select GPIO P A G I/O O I/O VDDEH1 MH –/ WKPCFG –/ WKPCFG J2 G2 ETPUA[20] IRQ[8] GPIO[134] eTPU A channel External interrupt request GPIO P A G I/O I I/O VDDEH1 MH –/ WKPCFG –/ WKPCFG J1 G1 ETPUA[21] IRQ[9] GPIO[135] eTPU A channel External interrupt request GPIO P A G I/O I I/O VDDEH1 MH –/ WKPCFG –/ WKPCFG G4 E4 ETPUA[22] IRQ[10] GPIO[136] eTPU A channel External interrupt request GPIO P A G I/O I I/O VDDEH1 MH –/ WKPCFG –/ WKPCFG H2 F2 ETPUA[23] IRQ[11] GPIO[137] eTPU A channel External interrupt request GPIO P A G I/O I I/O VDDEH1 MH –/ WKPCFG –/ WKPCFG H1 F1 ETPUA[24:26]_ IRQ[12:14]_ GPIO[138:140] eTPU A channel (output only) External Interrupt Request GPIO P A G O I I/O VDDEH1 SH –/ WKPCFG –/ WKPCFG G1, G3, F3 E1, E3, D3 ETPUA[27]_ IRQ[15]_ GPIO[141] eTPU A channel (output only) External Interrupt Request GPIO P A G O I I/O VDDEH1 SH –/ WKPCFG –/ WKPCFG G2 E2 ETPUA[28]_ PCSC[1]_ GPIO[142] eTPU A channel (output only) DSPI C peripheral chip select GPIO P A G O O I/O VDDEH1 MH –/ WKPCFG –/ WKPCFG F1 D1 ETPUA[29]_ PCSC[2]_ GPIO[143] eTPU A channel (output only) DSPI C peripheral chip select GPIO P A G O O I/O VDDEH1 MH –/ WKPCFG –/ WKPCFG F2 D2 ETPUA[30]_ PCSC[3]_ GPIO[144] eTPU A channel DSPI C peripheral chip select GPIO P A G I/O O I/O VDDEH1 MH –/ WKPCFG –/ WKPCFG E1 C1 ETPUA[31]_ PCSC[4]_ GPIO[145] eTPU A channel DSPI C peripheral chip select GPIO P A G I/O O I/O VDDEH1 MH –/ WKPCFG –/ WKPCFG E2 C2 VDDEH4 SH –/ WKPCFG –/ WKPCFG T4, T5, N7 AB10, AB11, W12 VDDEH4 SH –/ WKPCFG –/ WKPCFG R6, R5, T6 AA11, AB12, AA12 eMIOS EMIOS[0:2]_15 No primary signal No alternate signal — — ETPUA[0:2]_16 — — GPIO[179:181] GPIO G I/O EMIOS[3:5]_15 No primary signal No alternate signal — — ETPUA[3:5]_16 — — GPIO[182:184] GPIO G I/O MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 2-11 Table 2-1. MPC5533 Signal Properties (Continued) Status Signal Name 1 Signal Function 2 P/ A/ G I/O Type EMIOS[6:7]_15 No primary signal — — ETPUA[6:7]_16 No alternate signal — — GPIO[185:186] GPIO G I/O EMIOS[8:9]_ No primary signal — — ETPUA[8:9]_16 No alternate signal A O GPIO G I/O No primary signal — — DSPI D peripheral chip select A I/O GPIO G I/O 15 GPIO[187:188] EMIOS[10:11]_ 15 PCSD[3:4]_ GPIO[189:190] 15 EMIOS[12]_ No primary signal — — SOUTC_ DSPI C data output A O GPIO[191] GPIO G I/O EMIOS[13]_15 No primary signal — — SOUTD_ DSPI D data output A O GPIO[192] GPIO G I/O EMIOS[14]_15 No primary signal — — IRQ[0]_ External interrupt request A I GPIO[193] GPIO G I/O EMIOS[15]_15 No primary signal — — IRQ[1]_ External interrupt request A I GPIO[194] GPIO G I/O EMIOS[16:23]_15 No primary signal — — GPIO[195:202] GPIO G O Package Voltage3 Pad Type4 During Reset5 After Reset6 208 324 VDDEH4 SH –/ WKPCFG –/ WKPCFG P7, T7 Y12, AB13 VDDEH4 SH –/ WKPCFG –/ WKPCFG P8, R7 W13, AA13 VDDEH4 SH –/ WKPCFG –/ WKPCFG N8, R8 Y13, AB14 VDDEH4 MH –/ WKPCFG –/ WKPCFG N10 W15 VDDEH4 MH –/ WKPCFG –/ WKPCFG T8 AA14 VDDEH4 SH –/ WKPCFG –/ WKPCFG R9 AB15 VDDEH4 SH –/ WKPCFG –/ WKPCFG T9 Y14 AA15, Y15, AB16, AA16, AB17, W16, Y16, AA17 H20, H21 VDDEH4 SH –/ WKPCFG –/ WKPCFG P9, P10, T10, R10, T11, N11, P11, R11 VDDEH6 SH – / Up – / Up — VDDE3 F – / Up – / Up GPIO EMIOS[14:15]_15 No signal — — GPIO[203:204]22 GPIO G I/O GPIO[206:207]23 GPIO G I/O R4, P5 AA7, Y9 Clock Synthesizer XTAL Crystal oscillator output P O VDDSYN AE O/– XTAL24 / – P16 V22 EXTAL_ Crystal oscillator input P EXTCLK25 External clock input A I I VDDSYN AE I/– EXTAL26 / – N16 U22 CLKOUT System clock output P O VDDE5 F CLKOUT / Enabled CLKOUT / Enabled — AA20 ENGCLK Engineering clock output P O VDDE5 F ENGCLK/ Enabled ENGCLK / Enabled T14 AB21 VDDINT I/– VRC33 P15 W21 Power / Ground VRC3327 Voltage regulator control supply P I 3.3 V MPC5533 Microcontroller Reference Manual, Rev. 0 2-12 Freescale Semiconductor Table 2-1. MPC5533 Signal Properties (Continued) Status Signal Name 1 Signal Function 2 Package P/ A/ G I/O Type Voltage3 Pad Type4 During Reset5 After Reset6 208 324 VRCCTL Voltage regulator control output P O 3.3 V VDDINT O/– VRCCTL N14 V20 VRCVSS Voltage regulator control ground P I — VSSE I/– VRCVSS — T21 Analog power input ADC[0] P I 5.0 V VDDINT I/– VDDA0 B11 C15 VSSA0 Analog ground input ADC[0] P I — VSSINT I/– VSSA0 A11 A15, B15 VDDSYN Clock synthesizer power input P I 3.3 V VDDE I/– VDDSYN R16 W22 VSSSYN Clock synthesizer ground input P I — VSSE I/– VSSSYN M16 T22 VDDA0 28 VFLASH Flash read supply input P I 3.3 V VDDINT I/– VFLASH — N22 VPP29 Flash program/erase supply input P I 5.0 V VDDINT I/– VPP K16 M22 VSTBY30 SRAM standby power input P I 0.8–1.2 V VSTBY I/– VSTBY C1 A3 B1, C2, D3, E4, B16, P13, R14, T15, N5, P4, R3, T2 A2, A20, B3, C4, C22, D5, V19, W5, W20, Y4, Y21, AA3, AA22, AB2 VDD Internal logic supply input P I 1.5 V VDD I/– VDD VDDE2 External I/O supply input P I 1.8–3.3 V — I/– VDDE2 P6 M9:10, N11, P11, R3, W2, W6, W8, Y5, AA4, AA6, AA10, AB3 VDDE5 External I/O supply input P I 1.8–3.3 V — I/– VDDE5 T13 W17, Y18, AA19, AB20, VDDE7 External I/O supply input P I 1.8–3.3 V — I/– VDDE7 E13 B22, C21, D20, E19, F19, J14 VDDEH1 External I/O supply input P I 3.3–5.0 V — I/– VDDEH K4 H4 I 3.3–5.0 V — I/– VDDEH N9 W14 I 3.3–5.0 V — I/– VDDEH F13 U19 I 3.3–5.0 V — I/– VDDEH D12 D15 VDDEH4 External I/O supply input VDDEH6 VDDEH9 External I/O supply input 31 External I/O supply input P P P MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 2-13 Table 2-1. MPC5533 Signal Properties (Continued) Status Signal Name 1 VDDEH10 VDD3332 VSS Signal Function 2 External I/O supply input I/O pad pre-driver and level shifter reference voltage input MCU ground Package P/ A/ G I/O Type Voltage3 Pad Type4 During Reset5 After Reset6 208 324 P I 3.3–5.0 V — I/– VDDEH — H19 3.3 V A15, D1, N6, N12 B1, A21, P4, Y22, W7 A1, A22, B2, B21, C3, C20, D4, D19, J9:13, K9:14, L9:14, M11:14 N9:10 , N12:14 , P9:10, P12:14 , W4, W19, Y3, Y20, AA2, AA21, AB1, AB22 W18, Y19 P I P — 3.3 V — N/A — — N/A VSS A1, B2, C3, D4, D13, C14, B15, A16, N13, P14, R15, T16, N4, P3, R2, T1, G7:10, H7:10, J7:10, K7:10 N/A N/A N/A N/A — No Connect NC33 1 2 3 4 5 6 7 8 No connect N/A N/A Because more than one signal is often multiplexed to one pin, each line in the signal name column is a separate function. For all I/O pins the selection of the primary pin function, alternate function, or GPIO is determined in the SIU_PCR registers. Each line in the signal name column corresponds to a separate signal function on the pin. For all device I/O pins, the primary, alternate, or GPIO signal functions are designated in the PA field of the system integration unit (SIU) PCR registers except where explicitly noted. VDDE (fast I/O) and VDDEH (slow I/O) power supply inputs are grouped into segments. Each segment of VDDEH pins can connect to a separate 3.3–5.0 V (+5% and –10%) power supply input. Each segment of VDDE pins can connect to a separate 1.8–3.3 V (±10%) power supply, with the exception of the VDDE2 and VDDE3 segments that are shorted together and must use the same power supply input. This segment is labeled VDDE2 in the BGA map. The pad type is indicated by one of the abbreviations; F for fast, MH for medium (high voltage), SH for slow (high voltage), A for analog, AE for analog with ESD protection circuitry. Some pads have two types, depending on which pad function is selected. The Status During Reset pin is sampled after the internal POR is negated. Prior to exiting POR, the signal has a high impedance. Terminology is O - output, I - input, Up - weak pullup enabled, Down - weak pulldown enabled, Low - output driven low, High - output driven high. A dash on the left side of the slash denotes that both the input and output buffers for the pin are off. A dash on the right side of the slash denotes that there is no weak pullup/down enabled on the pin. The signal name to the left or right of the slash indicates the pin is enabled. Function after reset of GPI is general purpose input. A dash on the left side of the slash denotes that both the input and output buffers for the pin are off. A dash on the right side of the slash denotes that there is no weak pullup/down enabled on the pin. The EBI is specified and tested at 1.8–3.3 V. When using the EBI functions, select the function in the SIU_PCR register, and then enable the EBI functions in the EBI registers for these pins. Both the SIU and EBI configurations must match to operate correctly. MPC5533 Microcontroller Reference Manual, Rev. 0 2-14 Freescale Semiconductor 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 The function and state of this pin(s) after execution of the BAM program is determined by the BOOTCFG[0:1] pins. See Chapter 15, “Boot Assist Module (BAM) for detail on the External Bus Interface (EBI) configuration after execution of the BAM program. BOOTCFG[0] is not available on the 208 package and is internally asserted (driven to 0). CS[1:3], ADDR[12:31], DATA[0:15], WE/BE[0:1], RD_WR, BDIP, TS, and TA signals are not available on the 208 package due to pin limitations. MCKO is only enabled if debug mode is enabled. Debug mode can be enabled before or after exiting System Reset (RSTOUT deasserted). MDO[0] is driven high following a power-on reset until the system clock achieves lock, at which time it is then deasserted. There is an internal pullup on MDO[0]. The function of the MDO[11:4]_GPIO[82:75] pins is selected during a debug port reset by the EVTI pin or by selecting FPM in the NPC_PCR. When functioning as MDO[11:4] the pad configuration specified by the SIU does not apply. These pins, as well as the RDY pin, are not available on the 208 package. See 2.3.3.4 for more detail on MDO[11:4] pin operation. The function and state of the FlexCAN A pins after execution of the BAM program is determined by the BOOTCFG[0:1] pins. Refer to Table 15-9 for details on the FlexCAN pin configurations after the BAM executes. The primary signal is not available on this device and is listed only for reference to the pin label in the BGA Map. The alternate signal is not available on this device. For compatibility to the MPC5554, always power VDDEH6 and VDDEH10 from the same power supply 3.0–5.25 V. To allow one DSPI to operate at a different operating voltage, connect VDDEH6 and VDDEH10 to separate power supplies, but this configuration is not compatible with the MPC5554, All analog input channels are connected to the ADC block. The supply designation for this pin(s) specifies only the ESD rail used. Because the primary signal function designations for the analog functions AN[12] through AN[15] are internally reserved, the PA field of the corresponding SIU_PCR registers must be set to the main primary function value of 0b011 to use analog functions AN[12] through AN[15]. To use the serial data strobe functions, the PA field in the SIU_PCR registers must be set to 0b00. Because SDS, SDO, SDI, and FCK use the GPIO setting, a G is shown in the P/A/G column. However, these signals do not support GPIO functionality. If analog features are used, tie VDDEH9 to VDDA1. The GPIO[203:204] pins are always pulled up and are not controlled by the WKPCFG field in their SIU registers. These pins are not available on the 208 package. The GPIO[206:207] pins are protect-for-pins for double data rate (DDR) memory data strobes. These pins can be selected as the source for the eQADC trigger in the eQADC Trigger Input Select Register (SIU_ETISR). These pins are not available on the 208 package. The Function After Reset of the XTAL pin is determined by the value of the signal on the PLLCFG[1] pin. Ground the XTAL pin when using bypass mode. When the FMPLL is configured for external reference mode, the VDDE5 supply affects the acceptable signal levels for the external reference. See Section 11.1.4.2, “External Reference Mode.” The function after reset of the EXTAL_EXTCLK pin is determined by the value of the signal on the PLLCFG[1] pin. The operating voltage for the EXTAL function is 3.3 V; the operating voltage for the EXTCLK function is 1.62–3.6 V. VRC33 is the 3.3 V input for the voltage regulator control. The VDDAn and VSSAn supply inputs are split into separate traces in the package substrate. Each trace is bonded to a separate pad location, which provides isolation between the analog and digital sections within each ADC. Can be tied to 5.0 V for both read operation and program / erase. Tie the VSTBY pin to VSSA0 if the battery backed SRAM is not used. The VDDEH9 segment can be powered by 3.0–5.0 V for mux addresses or SSI functions, however the VDDEH9 segment must comply with the VDDA1 specifications (4.5–5.25 V) for analog input functions. All pins with pad type F (pad_fc) are driven to the high state if their VDDE segment is powered before VDD33. The pins are reserved for the clock and inverted clock outputs for the DDR memory interface. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 2-15 2.3 Detailed Signal Description Descriptions of the signals for the device are provided in the following sections. See Table 2-1 for signal properties. 2.3.1 2.3.1.1 Reset and Configuration Signals External Reset Input RESET Assert the RESET signal as an active low input from an external device during a power-on reset or external reset to reset all device modules. See Section 4.2.1, “Reset Input (RESET).” 2.3.1.2 External Reset Output RSTOUT The RSTOUT output is a push/pull output that is asserted during an internal device reset. You can assert RSTOUT via software without causing an internal reset to the device MCU. See Section 4.2.2, “Reset Output (RSTOUT).” NOTE During a power-on-reset (POR), RSTOUT is tri-stated. 2.3.1.3 FMPLL Mode Selection / External Interrupt Request / GPIO PLLCFG[0]_IRQ[4]_GPIO[208] PLLCFG[0]_IRQ[4]_GPIO[208] are sampled on the deassertion of the RESET input pin, if the RSTCFG pin is asserted at that time. The values are used to configure the FMPLL mode of operation. The alternate function is external interrupt request input. 2.3.1.4 FMPLL Mode Selection / External Interrupt Request / DSPI D / GPIO PLLCFG[1]_IRQ[5]_SOUTD_GPIO[209] PLLCFG[1]_IRQ[5]_SOUTD_GPIO[209] are sampled on the deassertion of the RESET input pin, if the RSTCFG pin is asserted at that time. The values are used to configure the FMPLL mode of operation. The alternate functions are external interrupt request input, and data output for the DSPI module D. 2.3.1.5 Reset Configuration Input / GPIO RSTCFG_GPIO[210] The RSTCFG input is used to enable the BOOTCFG[0:1] and PLLCFG[0:1] pins during reset. If RSTCFG is deasserted during reset, the BOOTCFG and PLLCFG pins are not sampled at the deassertion of RSTOUT. In that case, the default values for BOOTCFG and PLLCFG are used. If RSTCFG is asserted during reset, the values on the BOOTCFG and PLLCFG pins are sampled and configure the boot and FMPLL modes. MPC5533 Microcontroller Reference Manual, Rev. 0 2-16 Freescale Semiconductor 208 Package: 2.3.1.6 RSTCFG_GPIO[210] is not available due to pin limitations. The BOOTCFG[0] and the RSTCFG signals are internally asserted (driven to 0). Reset Configuration / External Interrupt Request / GPIO BOOTCFG[0:1]_IRQ[2:3]_GPIO[211:212] The BOOTCFG[0:1]_IRQ[2:3]_GPIO[211:212] are sampled when RSTOUT deasserts, if the RSTCFG pin is asserted at that time. The BOOTCFG[0:1] values are used by the BAM program to determine the boot configuration of the device. Use the alternate function for external interrupt request inputs. 208 Package: 2.3.1.7 BOOTCFG[0]_IRQ[2]_GPIO[211] and RSTCFG_GPIO[210] are not available due to pin limitations, and are internally asserted. Weak Pull Configuration / GPIO WKPCFG_GPIO[213] WKPCFG_GPIO[213] determines whether specific eTPU pins are connected to a weak pullup or weak pulldown during and immediately after reset. 2.3.2 External Bus Interface (EBI) This package has a 16-pin data bus [0:15] on the EBI. 208 Package: 2.3.2.1 This package does not have EBI pins, therefore the external bus signals are not available except for the chip select 0 (CS[0]) and the output enable (OE) pins. External Chip Selects / External Address / GPIO CS[0]_ADDR[8]_GPIO[0] CS[0]_ADDR[8]_GPIO[0] is the external bus interface (EBI) chip select output signal. The alternate function is an EBI address signal. GPIO[0] is available on this device and is the default function after reset. 2.3.2.2 External Chip Selects / External Address / GPIO CS[1:3]_ADDR[9:11]_GPIO[1:3] CS[1:3]_ADDR[9:11]_GPIO[1:3] are the external bus interface (EBI) chip select output signals. The alternate functions are EBI address signals. They can be individually configured as chip selects, address signals or GPIO. GPIO[1:3] are available on this device and are the default functions after reset. 208 Package: 2.3.2.3 The CS[1:3]_ADDR[9:11]_GPIO[1:3] are not available due to pin limitations. External Address / GPIO ADDR[12:31]_GPIO[8:27] ADDR[12:31]_GPIO[8:27] are the EBI address signals. GPIO[8:27] are available on this device and are the default functions after reset. 208 Package: The ADDR[12:31]_GPIO[8:27] are not available due to pin limitations. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 2-17 2.3.2.4 External Data / GPIO DATA[0:15]_GPIO[28:43] DATA[0:15]_GPIO[28:43] are the EBI data signals. GPIO[28:43] are available on this device and are the default functions after reset. 208 Package: 2.3.2.5 DATA[0:15]_GPIO[28:43] are not available due to pin limitations. External Read/Write / GPIO RD_WR_GPIO[62] RD_WR_GPIO[62] indicates whether an external bus transfer is a read or write operation. GPIO[62] is available on this device and is the default functions after reset. 208 Package: 2.3.2.6 The RD_WR_GPIO[62] is not available due to pin limitations. External Burst Data In Progress / GPIO BDIP_GPIO[63] BDIP_GPIO[63] indicates that an EBI burst transfer is in progress. 208 Package: 2.3.2.7 The BDIP_GPIO[63] signal is not available due to pin limitations. External Write/Byte Enable / GPIO WE/BE[0:1]_GPIO[64:65] WE/BE[0:1]_GPIO[64:65] specify which data pins contain valid data for an external bus transfer. GPIO[64:65] are available on this device and are the default functions after reset. 208 Package: 2.3.2.8 The WE/BE[0:1]_GPIO[64:65] are not available due to pin limitations. External Output Enable / GPIO OE_GPIO[68] OE_GPIO[68] indicates that the EBI is ready to accept read data. 2.3.2.9 External Transfer Start / GPIO TS_GPIO[69] TS_GPIO[69] is asserted by the EBI owner to indicate the start of a transfer. 208 Package: 2.3.2.10 The TS_GPIO[69] is not available due to pin limitations. External Transfer Acknowledge TA_GPIO[70] TA_GPIO[70] is asserted by the EBI owner to acknowledge that the slave has completed the current transfer. 208 Package: The TA_GPIO[70] is not available due to pin limitations. MPC5533 Microcontroller Reference Manual, Rev. 0 2-18 Freescale Semiconductor 2.3.3 2.3.3.1 Nexus Controller Nexus Event In EVTI EVTI is an input that is read when TRST asserts to enable or disable the Nexus debug port. After reset, the EVTI pin is used to initiate program and data trace synchronization messages or generate a breakpoint. 2.3.3.2 Nexus Event Out EVTO EVTO is an output that provides timing to a development tool for a single watchpoint or breakpoint occurrence. 2.3.3.3 Nexus Message Clock Out MCKO MCKO is a free running clock output to the development tools which is used for timing of the MDO and MSEO signals. 2.3.3.4 Nexus Message Data Out MDO[3:0] MDO[3:0] are the trace message outputs to the development tools. In addition to being a trace output, MDO[0] indicates the lock status of the system clock following a power-on reset. MDO[0] is driven high following a power-on reset until the system clock achieves lock, at which time it is then deasserted. There is an internal pullup on MDO[0]. 2.3.3.5 Nexus Message Data Out / GPIO MDO[11:4]_GPIO[82:75] MDO[11:4]_GPIO[82:75] are the trace message outputs to the development tools for full port mode. These pins function as GPIO when the Nexus port controller (NPC) operates in reduced port mode. The GPIO functions are available on these pins. GPIO[82:75] are available on this device and are the default functions after reset. 208 Package: 2.3.3.6 MDO[11:4]_GPIO[82:75] signals are not available due to pin limitations. Nexus Message Start/End Out MSEO[1:0] MSEO[1:0] are outputs that indicate when messages start and end on the MDO pins. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 2-19 2.3.3.7 Nexus Ready Output RDY RDY is an output that indicates to the development tools the data is ready to be read from or written to the Nexus read/write access registers. 208 Package: 2.3.4 2.3.4.1 The RDY is not available due to pin limitations. JTAG JTAG Test Clock Input TCK TCK provides the clock input for the on-chip test logic. 2.3.4.2 JTAG Test Data Input TDI TDI provides the serial test instruction and data input for the on-chip test logic. 2.3.4.3 JTAG Test Data Output TDO TDO provides the serial test data output for the on-chip test logic. 2.3.4.4 JTAG Test Mode Select Input TMS TMS controls test mode operations for the on-chip test logic. 2.3.4.5 JTAG Compliance Input JCOMP The JCOMP pin is used to enable the JTAG TAP controller. 2.3.4.6 Test Mode Enable Input TEST The TEST pin is used to place the chip in test mode. Deassert this signal for normal operation. 2.3.5 2.3.5.1 Flexible Controller Area Network (FlexCAN) FlexCAN A Transmit / GPIO CNTXA_GPIO[83] CNTXA_GPIO[83] is the transmit pin for the FlexCAN A module. MPC5533 Microcontroller Reference Manual, Rev. 0 2-20 Freescale Semiconductor 2.3.5.2 FlexCAN A Receive / GPIO CNRXA_GPIO[84] CNRXA_GPIO[84] is the receive pin for the FlexCAN A module. 2.3.5.3 FlexCAN B Transmit / DSPI C Chip Select / GPIO CNTXB_PCSC[3]_GPIO[85] The primary function, CNTXB, is not available on this device. PCSC[3] is the alternate function and is a peripheral chip select output for the DSPI C module. GPIO[85] is the default function after reset and is available on this device. 2.3.5.4 FlexCAN B Receive / DSPI C Chip Select / GPIO CNRXB_PCSC[4]_GPIO[86] The primary function, CNRXB, is not available on this device. PCSC[4]_GPIO[86] is the alternate function and is a peripheral chip select output for the DSPI C module. The GPIO pin is available on this device. 2.3.5.5 FlexCAN C Transmit / DSPI D Chip Select / GPIO CNTXC_PCSD[3]_GPIO[87] CNTXC_PCSD[3]_GPIO[87] is the transmit pin for the FlexCAN C module. The alternate function is a peripheral chip select for the DSPI D module. 2.3.5.6 FlexCAN C Receive / DSPI D Chip Select / GPIO CNRXC_PCSD[4]_GPIO[88] CNRXC_PCSD[4]_GPIO[88] is the receive pin for the FlexCAN C module. The alternate function is a peripheral chip select for the DSPI D module. 2.3.6 2.3.6.1 Enhanced Serial Communications Interface (eSCI) eSCI A Transmit / GPIO TXDA_GPIO[89] TXDA_GPIO[89] is the transmit pin for the eSCI A module. 2.3.6.2 eSCI A Receive / GPIO RXDA_GPIO[90] RXDA_GPIO[90] is the receive pin for the eSCI A module. The pin is an input only for the RXD function, but as GPIO the pin is input or output based on the SIU PCR configuration. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 2-21 2.3.6.3 eSCI B Transmit / DSPI D Chip Select / GPIO TXDB_PCSD[1]_GPIO[91] TXDB_PCSD[1]_GPIO[91] — The transmit pin for the eSCI B module is the primary function, and is not available on this device. The alternate function is a peripheral chip select output for the DSPI D module. 2.3.6.4 eSCI B Receive / DSPI D Chip Select / GPIO RXDB_PCSD[5]_GPIO[92] RXDB_PCSD[5]_GPIO[92] — The receive pin for the eSCI B module, RXDB, is the primary function, and is not available on this device. The alternate function is a peripheral chip select for the DSPI D module. 2.3.7 2.3.7.1 Deserial/Serial Peripheral Interface (DSPI) DSPI A Clock / DSPI C / GPIO SCKA_PCSC[1]_GPIO[93] The primary function, SCKA, is not available on this device. PCSC[1]_GPIO[93] is the peripheral chip select output pin for the DSPI C module. 2.3.7.2 DSPI A Input / DSPI C / GPIO SINA_PCSC[2]_GPIO[94] The primary function, SINA, is not available on this device. PCSC[2]_GPIO[94] is the peripheral chip select output pin for the DSPI C module. 2.3.7.3 DSPI A Output / DSPI C / GPIO SOUTA_PCSC[5]_GPIO[95] The primary function, SOUTA, is not available on this device. PCSC[5]_GPIO[95] is the peripheral chip select output pin for the DSPI C module. 2.3.7.4 DSPI A / DSPI D / GPIO PCSA[0]_PCSD[2]_GPIO[96] The primary function, PCSA[0], is not available on this device. PCSD[2]_GPIO[96] is the peripheral chip select output pin for the DSPI D module. 208 Package: 2.3.7.5 This pin is not available due to pin limitations. DSPI A / DSPI B / GPIO PCSA[1]_PCSB[2]_GPIO[97] The primary function, PCSA[1], is not available on this device. The alternate signal is a peripheral chip select output pins for the DSPI B module PCSB[2], and is not available on this device. Only GPIO[97] is available on this pin. MPC5533 Microcontroller Reference Manual, Rev. 0 2-22 Freescale Semiconductor 208 Package: 2.3.7.6 This pin is not available due to pin limitations in the 208 package. DSPI A / DSPI D Clock / GPIO PCSA[2]_SCKD_GPIO[98] The primary function, PCSA[2], is not available on this device. SCKD_GPIO[98] is the SPI clock pin for the DSPI D module. 2.3.7.7 DSPI A / DSPI D Data Input / GPIO PCSA[3]_SIND_GPIO[99] The primary function, PCSA[3], is not available on this device. SIND_GPIO[99] is the data input pin for the DSPI D module. 2.3.7.8 DSPI A / DSPI D Data Output / GPIO PCSA[4]_SOUTD_GPIO[100] The primary function, PCSA[4], is not available on this device. SOUTD_GPIO[100] is the alternate function is the data output for the DSPI D module. 208 Package: 2.3.7.9 This pin is not available due to pin limitations. DSPI A / DSPI B / GPIO PCSA[5]_PCSB[3]_GPIO[101] The primary function, PCSA[5], is not available on this device. PCSB[3] is the alternate function and is not available on this device. The GPIO[101] signal is the general purpose input/output function and is available. 208 Package: 2.3.7.10 This pin is not available due to pin limitations. DSPI B Clock / DSPI C Chip Select / GPIO SCKB_PCSC[1]_GPIO[102] SCKB_PCSC[1]_GPIO[102] — The SPI clock pin for the DSPI B module is the primary signal, and is not available on this device. The alternate function is a chip select output for the DSPI C module. 2.3.7.11 DSPI B Data Input / DSPI C Chip Select / GPIO SINB_PCSC[2]_GPIO[103] SINB_PCSC[2]_GPIO[103] — The data input pin for the DSPI B module is the primary signal, and is not available on this device. The alternate function is a chip select output for the DSPI C module. 2.3.7.12 DSPI B Data Output / DSPI C Chip Select / GPIO SOUTB_PCSC[5]_GPIO[104] SOUTB_PCSC[5]_GPIO[104] — The data output pin for the DSPI B module is the primary signal, and is not available on this device. The alternate function is a chip select output for the DSPI C module. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 2-23 2.3.7.13 DSPI B Chip Select / DSPI D Chip Select / GPIO PCSB[0]_PCSD[2]_GPIO[105] PCSB[0]_PCSD[2]_GPIO[105] — The peripheral chip select output pin (slave select input pin for slave operation) for the DSPI B module is the primary signal, and is not available on this device. The alternate function is a chip select output for the DSPI D module. 2.3.7.14 DSPI B Chip Select / DSPI D Chip Select / GPIO PCSB[1]_PCSD[0]_GPIO[106] PCSB[1]_PCSD[0]_GPIO[106] — The peripheral chip select output pin for the DSPI B module is the primary signal, and is not available on this device. The alternate function is a chip select output (slave select input pin for slave operation) for the DSPI D module. 2.3.7.15 DSPI B Chip Select / DSPI C Data Output / GPIO PCSB[2]_SOUTC_GPIO[107] PCSB[2]_SOUTC_GPIO[107] — The peripheral chip select output pin for the DSPI B module is the primary signal, and is not available on this device. The alternate function is the data output for the DSPI C module. 2.3.7.16 DSPI B Chip Select / DSPI C Data Input / GPIO PCSB[3]_SINC_GPIO[108] PCSB[3]_SINC_GPIO[108] — The peripheral chip select output pin for the DSPI B module is the primary signal, and is not available on this device. The alternate function, and is the data input for the DSPI C module. The GPIO function is available on this pin. 2.3.7.17 DSPI B Chip Select / DSPI C Clock / GPIO PCSB[4]_SCKC_GPIO[109] PCSB[4]_SCKC_GPIO[109] — The peripheral chip select output pin for the DSPI B module is the primary signal, and is not available on this device. The alternate function is the SPI clock for the DSPI C module. 2.3.7.18 DSPI B Chip Select / DSPI C Chip Select / GPIO PCSB[5]_PCSC[0]_GPIO[110] PCSB[5]_PCSC[0]_GPIO[110] — The peripheral chip select output pin for the DSPI B module is the primary signal, and is not available on this device. The alternate function is a chip select output (slave select input in slave mode) for the DSPI C module. MPC5533 Microcontroller Reference Manual, Rev. 0 2-24 Freescale Semiconductor 2.3.8 Enhanced Queued Analog/Digital Converter (eQADC) NOTE The eQADC has 40 channels in the 324 package; the 208 package has 34 channels due to pin limitations. 2.3.8.1 Analog Input / Differential Analog Input AN[0]_DAN0+ AN[0] is a single-ended analog input to the on-chip ADCs. DAN0+ is the positive terminal of the differential analog input DAN0 (DAN0+ to DAN0–). 2.3.8.2 Analog Input / Differential Analog Input AN[1]_DAN0– AN[1] is a single-ended analog input to the on-chip ADC. DAN0– is the negative terminal of the differential analog input DAN0 (DAN0+ to DAN0–). 2.3.8.3 Analog Input / Differential Analog Input AN[2]_DAN1+ AN[2] is a single-ended analog input to the on-chip ADC. DAN1+ is the positive terminal of the differential analog input DAN1 (DAN1+ to DAN1–). 2.3.8.4 Analog Input / Differential Analog Input AN[3]_DAN1– AN[3] is a single-ended analog input to the on-chip ADC. DAN1– is the negative terminal of the differential analog input DAN1 (DAN1+ to DAN1–). 2.3.8.5 Analog Input / Differential Analog Input AN[4]_DAN2+ AN[4] is a single-ended analog input to the on-chip ADC. DAN2+ is the positive terminal of the differential analog input DAN2 (DAN2+ to DAN2–). 2.3.8.6 Analog Input / Differential Analog Input AN[5]_DAN2– AN[5] is a single-ended analog input to the on-chip ADC. DAN2– is the negative terminal of the differential analog input DAN2 (DAN2+ to DAN2–). 2.3.8.7 Analog Input / Differential Analog Input AN[6]_DAN3+ AN[6] is a single-ended analog input to the on-chip ADC. DAN3+ is the positive terminal of the differential analog input DAN3 (DAN3+ to DAN3–). MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 2-25 2.3.8.8 Analog Input / Differential Analog Input AN[7]_DAN3– AN[7] is a single-ended analog input to the on-chip ADC. DAN3– is the negative terminal of the differential analog input DAN3 (DAN3+ to DAN3–). 2.3.8.9 Analog Input / Multiplexed Analog Input AN[8]_ANW AN[8] is an analog input pin. The alternate function, ANW, is an analog input in external multiplexed mode. This pin has reduced analog to digital conversion accuracy as compared to the AN[0:7] and AN[16:39] analog input pins. 208 Package: 2.3.8.10 The AN[8]_ANW pin is not available due to pin limitations. Analog Input / Multiplexed Analog Input AN[9]_ANX AN[9] is an analog input pin. The alternate function, ANX, is an analog input in external multiplexed mode. This pin has reduced analog to digital conversion accuracy as compared to the AN[0:7] and AN[16:39] analog input pins. 2.3.8.11 Analog Input / Multiplexed Analog Input AN[10]_ANY AN[10] is an analog input pin. The alternate function, ANY, is an analog input in external multiplexed mode. This pin has reduced analog to digital conversion accuracy as compared to the AN[0:7] and AN[16:39] analog input pins. 208 Package: 2.3.8.12 The AN[10]_ANY pin is not available due to pin limitations. Analog Input / Multiplexed Analog Input AN[11]_ANZ AN[11] is an analog input pin. The alternate function, ANZ, is an analog input in external multiplexed mode. This pin has reduced analog to digital conversion accuracy as compared to the AN[0:7] and AN[16:39] analog input pins. 2.3.8.13 Analog Input / Mux Address 0 / eQADC Serial Data Strobe AN[12]_MA[0]_SDS AN[12]_MA[0]_SDS is an analog input pin. The alternate function, MA[0], is a MUX address pin. The second alternate function is the serial data strobe for the eQADC SSI. This pin has reduced analog to digital conversion accuracy as compared to the AN[0:7] and AN[16:39] analog input pins. MPC5533 Microcontroller Reference Manual, Rev. 0 2-26 Freescale Semiconductor 2.3.8.14 Analog Input / Mux Address 1 / eQADC Serial Data Out AN[13]_MA[1]_SDO AN[13]_MA[1]_SDO is an analog input pin. The alternate function, MA[1], is a MUX address pin. The second alternate function is the serial data output for the eQADC SSI. This pin has reduced analog to digital conversion accuracy as compared to the AN[0:7] and AN[16:39] analog input pins. 2.3.8.15 Analog Input / Mux Address 2 / eQADC Serial Data In AN[14]_MA[2]_SDI AN[14]_MA[2]_SDI is an analog input pin. The alternate function, MA[2], is a MUX address pin. The second alternate function is the serial data input for the eQADC SSI. This pin has reduced analog to digital conversion accuracy as compared to the AN[0:7] and AN[16:39] analog input pins. 2.3.8.16 Analog Input / eQADC Free Running Clock AN[15]_FCK AN[15]_FCK is an analog input pin. The alternate function is the free running clock for the eQADC SSI. This pin has reduced analog to digital conversion accuracy as compared to the AN[0:7] and AN[16:39] analog input pins. 2.3.8.17 Analog Input AN[16:39] AN[16:39] are analog input pins. 208 Package: 2.3.8.18 The AN[19:20, 26, 29] pins are not available due to pin limitations. Voltage Reference High VRH VRH is the voltage reference high input pin for the eQADC. 208 Package: 2.3.8.19 The VRH pin is not available due to pin limitations. Voltage Reference Low VRL VRL is the voltage reference low input pin for the eQADC. 208 Package: 2.3.8.20 The VRL pin is not available due to pin limitations. Reference Bypass Capacitor REFBYPC REFBYPC is a bypass capacitor input for the eQADC. Use a 100nF external bias capacitor to connect the REFBYPC pin to the VRL. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 2-27 2.3.9 2.3.9.1 Enhanced Time Processing Unit (eTPU) eTPU A TCR Clock / External Interrupt Request / GPIO TCRCLKA_IRQ[7]_GPIO[113] TCRCLKA_IRQ[7]_GPIO[113] is the TCR A clock input for the eTPU module. The alternate function is an external interrupt request input for the SIU module. 2.3.9.2 eTPU A Channel / eTPU A Channel (Output Only) / GPIO ETPUA[0:11]_ETPUA[12:23]_GPIO[114:125] ETPUA[0:11]_ETPUA[12:23]_GPIO[114:125] are input/output channel pins for the eTPU A module. The alternate functions are output channels only for the eTPU A module; that is, when configured as ETPUA[12:23], the pins function as outputs only. GPIO[114:125] are available on this device and are the default functions after reset. 2.3.9.3 eTPU A Channel / DSPI / GPIO ETPUA[12:19]_PCSDn_GPIO[126:133] ETPUA[12:19]_PCSDn_GPIO[126:133] are input/output channel pins for the eTPU A module muxed with DSPI D pins. The GPIO functions are available on these pins. 2.3.9.4 eTPU A Channel / External Interrupt Request / GPIO ETPUA[20:27]_IRQ[8:15]_GPIO[134:141] ETPUA[20:27]_IRQ[8:15]_GPIO[134:141] are input/output channel pins for the eTPU A module muxed with interrupt request pins. The alternate functions are interrupt request signals. The GPIO functions are available on these pins. 2.3.9.5 eTPU A Channels / DSPI C / GPIO ETPUA[28:31]_PCSC[1:4]_GPIO[142:145] ETPUA[28:31]_PCSC[1:4]_GPIO[142:145] are input/output channel pins for the eTPU A module multiplexed with DSPI C pins. The GPIO functions are available on these pins. 2.3.10 Enhanced Modular Input/Output System (eMIOS) The eMIOS module was not designed into the MPC5533 device, therefore it does not have any EMIOS signals. However, the muxed alternate and GPIO signals are available on the pins. 2.3.10.1 eMIOS Channels / eTPU A Channels (Output Only) / GPIO EMIOS[0:9]_ETPUA[0:9]_GPIO[179:188] EMIOS[0:9]_ETPUA[0:9]_GPIO[179:188] — The primary signals are the input/output channel for the eMIOS module, and are not available on this device. The alternate functions are output channels for the eTPU A module, and are not available on this device. The GPIO functions are available on these pins. MPC5533 Microcontroller Reference Manual, Rev. 0 2-28 Freescale Semiconductor 2.3.10.2 eMIOS Channels / GPIO EMIOS[10:11]_GPIO[189:190] EMIOS[10:11]_GPIO[189:190] — The primary signals are input/output channel pins for the eMIOS module, and are not available on this device. The GPIO functions are available on these pins. 2.3.10.3 eMIOS Channel (Output Only) / DSPI C Data Output / GPIO EMIOS[12]_SOUTC_GPIO[191] EMIOS[12]_SOUTC_GPIO[191] — The primary signal is an output channel pin for the eMIOS module, and is not available on this device. The alternate function is the data output for the DSPI C module. 2.3.10.4 eMIOS Channel (Output Only) / DSPI D Data Output / GPIO EMIOS[13]_SOUTD_GPIO192 EMIOS[13]_SOUTD_GPIO[192] — The primary signal is an output channel pin for the eMIOS module, and is not available on this device. The alternate function is the data output for the DSPI D module. 2.3.10.5 eMIOS Channel (Output Only) / External Interrupt Request / GPIO EMIOS[14:15]_IRQ[0:1]_GPIO[193:194] EMIOS[14:15]_IRQ[0:1]_GPIO[193:194] — The primary signals are output channel pins for the eMIOS module, and are not available on this device. The alternate functions are for external interrupt request inputs. 2.3.10.6 eMIOS Channel (Output Only) / GPIO EMIOS[16:23]_GPIO[195:202] EMIOS[16:23]_GPIO[195:202] — The primary signals are input/output channel pins for the eMIOS module, and are not available on this device. 2.3.11 2.3.11.1 GPIO GPIO EMIOS[14:15]_GPIO[203:204] EMIOS[14:15]_GPIO[203:204] — The primary signals are output channels for the eMIOS module, and are not available on this device. These GPIO functions are the default after reset and available on these pins. 208 Package: The EMIOS[14:15]_GPIO[203:204] signals are not available due to pin limitations. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 2-29 2.3.11.2 GPIO GPIO[206:207] The GPIO[206:207] pins only have GPIO functionality. These pins are reserved for double data rate memory interface support.The pad type for GPIO[206:207] is fast driver and CMOS input buffer (1.62–1.98 V). 2.3.12 2.3.12.1 Clock Synthesizer Crystal Oscillator Output XTAL XTAL is the output pin for an external crystal oscillator. 2.3.12.2 Crystal Oscillator Input / External Clock Input EXTAL_EXTCLK EXTAL is the input pin for an external crystal oscillator or an external clock source. The alternate function is the external clock input. The function of this pin is determined by the PLLCFG configuration pins. 2.3.12.3 System Clock Output CLKOUT CLKOUT is the system clock output. 208 Package: 2.3.12.4 The CLKOUT signal is not available due to pin limitations. Engineering Clock Output ENGCLK ENGCLK is a 50% duty cycle output clock with a maximum frequency of the device’s system clock divided by two. ENGCLK is not synchronous to CLKOUT. 2.3.13 2.3.13.1 Power/Ground Voltage Regulator Control Supply Input VRC33 VRC33 is the 3.3 V supply input pin for the on-chip 1.5 V regulator control circuit. 2.3.13.2 Voltage Regulator Control Ground Input VRCVSS VRCVSS is the ground reference for the on-chip 1.5 V regulator control circuit. 208 Package: The VRCVSS signal is not available due to pin limitations. MPC5533 Microcontroller Reference Manual, Rev. 0 2-30 Freescale Semiconductor 2.3.13.3 Voltage Regulator Control Output VRCCTL VRCCTL is the output pin for the on-chip 1.5 V regulator control circuit. 2.3.13.4 eQADC Analog Supply VDDAn VDDAn is the analog supply input pin for the eQADC. 2.3.13.5 eQADC Analog Ground Reference VSSAn VSSAn is the analog ground reference input pin for the eQADC. 2.3.13.6 Clock Synthesizer Power Input VDDSYN VDDSYN is the power supply input for the FMPLL. 2.3.13.7 Clock Synthesizer Ground Input VSSSYN VSSSYN is the ground reference input for the FMPLL. 2.3.13.8 Flash Read Supply Input VFLASH VFLASH is the on-chip Flash read supply input. 208 Package: 2.3.13.9 The VFLASH signal is not available due to pin limitations. Flash Program/Erase Supply Input VPP VPP is the on-chip Flash program/erase supply input. 2.3.13.10 SRAM Standby Power Input VSTBY VSTBY is the power supply input that is used to maintain a portion of the contents of internal SRAM during power down. If not used, tie VSTBY to VSS. 2.3.13.11 Internal Logic Supply Input VDD VDD is the 1.5 V logic supply input. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 2-31 2.3.13.12 External I/O Supply Input VDDEn VDDEn is the 1.8–3.3 V ±10% external I/O supply input. 2.3.13.13 External I/O Supply Input VDDEHn VDDEHn is the 3.3–5.0 V -10% to +5% external I/O supply input. 2.3.13.14 Fixed 3.3 V Internal Supply Input VDD33 VDD33 is the 3.3 V internal supply input. 2.3.13.15 Ground VSS VSS is the ground reference input. 2.3.14 I/O Power/Ground Segmentation Table 2-2 gives the power/ground segmentation of the device MCU. Each segment provides the power and ground for the given set of I/O pins. Each segment can be powered by either of the allowed voltages regardless of the power on the other segments. The power/ground segmentation applies regardless of whether a particular pin is configured for its primary function or GPIO. See Table 2-1, as not all signals are available on the 324 and 208 packages. The primary signals shown in blue are not available in this device, but are shown to locate the pin on the ball grid array (BGA). The signals shown in red are not available on the 208 package. Table 2-2. MPC5533 Power/Ground Segmentation Power Segment VDDE Voltage Range1 VDDEH1 3.3–5.0 V TCRCLKA_IRQ[7]_GPIO[113], ETPUA[0:11]_ETPUA[12:23]_GPIO[114:125], ETPUA[12]_PCSB[1]_GPIO[126], ETPUA[13:15]_PCSB[3:5]_GPIO[127:129], ETPUA[16:19]_PCSD[1:4]_GPIO[130:133], ETPUA[20:27]_IRQ[8:15]_GPIO[134:141], ETPUA[28:31]_PCSC[1:4]_GPIO[141:145] VDDE22 1.8–3.3 V CS[0]_ADDR[8]_GPIO[0], CS[1:3]_ADDR[9:11]_GPIO[1:3], ADDR[12:31]_GPIO[8:27], DATA[0:15]_GPIO[28:43], RD_WR_GPIO[62], BDIP_GPIO[63], WE/BE[0:1]_GPIO[64:65], OE_GPIO[68], TS_GPIO[69], TA_GPIO[70], GPIO[206:207] VDDEH4 3.3–5.0 V EMIOS[0:9]_ETPUA[0:9]_GPIO[179:188], EMIOS[10:11]_PCSD[3:4]_GPIO[189:190], EMIOS[12]_SOUTC_GPIO[191], EMIOS[13]_SOUTD_GPIO[192], EMIOS[14:15]_IRQ[0:1]_GPIO[193:194], EMOIS[16:23]_GPIO[195:202], CNTXA_GPIO[83], CNRXA_GPIO[84], CNTXB_PCSC[3]_GPIO[85], CNRXB_PCSC[4]_GPIO[86] I/O Pins Powered by Segment MPC5533 Microcontroller Reference Manual, Rev. 0 2-32 Freescale Semiconductor Table 2-2. MPC5533 Power/Ground Segmentation Power Segment VDDE Voltage Range1 VDDE5 1.8–3.3 V CLKOUT, ENGCLK VDDEH6 3.3–5.0 V RESET, RSTOUT, RSTCFG_GPIO[210], WKPCFG_GPIO[213], BOOTCFG[0]_IRQ[2]_GPIO[211], BOOTCFG[1]_IRQ[3]_GPIO[212], PLLCFG[0]_IRQ[4]_GPIO[208], PLLCFG[1]_IRQ[5]_SOUTD_GPIO[209], CNTXC_PCSD[3]_GPIO[87], CNRXC_PCSD[4]_GPIO[88], TXDA_GPIO[89], RXDA_GPIO[90], TXDB_PCSD[1]_GPIO[91], RXDB_PCSD[5]_GPIO[92], SCKA_PCSC[1]_GPIO[93], SINA_PCSC[2]_GPIO[94], SOUTA_PCSC[5]_GPIO[95], PSCA[0]_PCSD[2]_GPIO[96], PSCA[1]_PCSB[2]_GPIO[97], PSCA[2]_SCKD_GPIO[98], PSCA[3]_SIND_GPIO[99], PSCA[4]_SOUTD_GPIO[100], PSCA[5]_PCSB[3]_GPIO[101], PCSB[3]_SINC_GPIO[108], PCSB[4]_SCKC_GPIO[109], PCSB[5]_PCSC[0]_GPIO[110], EMIOS[14:15]_GPIO[203:204] VDDE7 1.8–3.3 V EVTI, EVTO, MCKO, MDO[3:0], MDO[11:4]_GPIO[82:75], MSEO[1:0], RDY, TCK, TDI, TDO, TMS, JCOMP, TEST VDDEH9 3.3–5.0 V AN[12]_MA[0]_SDS, AN[13]_MA[1]_SDO, AN[14]_MA[2]_SDI, AN[15]_FCK VDDEH10 3.3–5.0 V SCKB_PCSC[1]_GPIO[102], SINB_PCSC[2]_GPIO[103], SOUTB_PCSC[5]_GPIO[104], PCSB[0]_PCSD[2]_GPIO[105], PCSB[1]_PCSD[0]_GPIO[106], PCSB[2]_SOUTC_GPIO[107] VDDA0 5.0 V AN[22:35], VRH VDDA1 5.0 V AN[0:11,16:21, 36:39] VDDSYN 3.3 V XTAL, EXTAL_EXTCLK VRC33 3.3 V VRCCTL I/O Pins Powered by Segment 1 These are nominal voltages. All VDDE and VDDEH voltages are ±10% (VDDE 1.62–3.6 V; VDDEH 3.0–5.25 V). VRC33 is ±10%. VDDSYN is ±10%. VDDA is +5%, -10%. 2 V DDE2 and VDDE3 are separate segments in the device pad ring. These segments are shorted together in the package substrate. The following pins are part of the VDDE3 segment: DATA[0:15], GPIO[206:207], OE. 2.4 2.4.1 eTPU Pin Connections and Serialization ETPUA[0:15] The ETPUA[0:15] module channels connect to external pins or can be serialized out through the DSPI C module. A diagram for the ETPUA[0:15] and DSPI C connections is given in Figure 2-4. The full list of connections is given in Table 2-3. Although not shown in Figure 2-4, the output channels of ETPUA[12:15] are connected to the ETPUA[0:3]_ETPUA[12:15]_GPIO[114:117] pins. The eTPU TCRCLKA clock input is connected to an external pin only. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 2-33 eTPU A ETPUA[0]_ ETPUA[12]_ GPIO[114] CH0 IN CH0 OUT EMIOS[0]_1 ETPUA[0]_ • • • • • • GPIO[179] ETPUA[9]_ ETPUA[21]_ GPIO[123] CH9 IN CH9 OUT EMIOS[9]_1 ETPUA[9]_ GPIO[188] ETPUA[10]_ ETPUA[22]_ GPIO[124] CH10 IN CH10 OUT • • • • • • CH15 IN CH15 OUT ETPUA[15]_ GPIO[129] 1 ••• The EMIOS module is not designed into this device. IN 4 ••• IN 13 IN 14 DSPI C IN 3 Figure 2-4. ETPUA[0:15]—DSPI C I/O Connections Table 2-3. ETPUA[0:15]—DSPI C I/O Mapping DSPI C Serialized Input eTPU A Channel Output 15 11 14 10 13 9 12 8 11 7 10 6 9 5 8 4 7 3 6 2 5 1 4 0 MPC5533 Microcontroller Reference Manual, Rev. 0 2-34 Freescale Semiconductor Table 2-3. ETPUA[0:15]—DSPI C I/O Mapping (Continued) 2.4.2 DSPI C Serialized Input eTPU A Channel Output 3 15 2 14 1 13 0 12 ETPUA[16:31] The ETPUA[12:23, 30:31] primary signals connect to external pins for both the input and output functions. The serialized output channels of ETPUA[12:23] are also muxed as alternate signals to the ETPUA[0:11]_ETPUA[12:23]_GPIO[114:125] pins. ETPUA[22:23,30:31] are not serialized out. ETPUA[16:19, 28:31] are serialized out on the DSPI D and DSPI C modules respectively. ETPUA[24:29] connect to external pins for only the output function. Figure 2-5 shows the connections for ETPUA[16] and applies to ETPUA[16:21]. eTPU A ETPUA[16]_ GPIO[130] CH16 IN CH16 OUT IN 7 DSPI C IN 5 DSPI D Figure 2-5. ETPUA[16:21]—DSPI C–DSPI D I/O Connections Figure 2-6 shows the connections for ETPUA[24] and applies to ETPUA[24:29]. eTPU A CH24 IN CH24 OUT ETPUA[24]_ GPIO[138] IN 13 OUT 13 DSPI C IN 15 DSPI D Figure 2-6. ETPU A[24:29]—DSPI C and DSPI D I/O Connections The full ETPUA to DSPI D connections are given in Table 2-4. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 2-35 Table 2-4. ETPUA[16:31]—DSPI D I/O Mapping DSPI D Serialized Inputs eTPU A Channel Output 15 24 14 25 13 26 12 27 11 28 10 29 5 16 4 17 3 18 2 19 1 20 0 21 MPC5533 Microcontroller Reference Manual, Rev. 0 2-36 Freescale Semiconductor Chapter 3 Core Complex (e200z3) The e200z3 integrates a Z3 CPU core, a Memory Management Unit (MMU), a Signal Processing Extension (SPE) Auxiliary Processing Unit (APU), and a Nexus Class 3 real-time Debug unit. Separate Instruction and Data AHB 2.v6 system interfaces are provided. Overviews of the major components are described in this chapter. Additional information: • e200z3 PowerPC Core Reference Manual • EREF: A Programmer's Reference Manual for Freescale Book E Processors • Variable-Length Encoding (VLE) Extension Programming Interface Manual 3.1 Overview The e200 processor family are a set of core devices that implement low-cost versions of the PowerPC Book E architecture. These processors are designed for deeply embedded control applications that require low cost solutions over maximum performance. The initial e200z3 processor integrates an integer execution unit, branch control unit, instruction fetch and load/store units, and a multi-ported register file capable of sustaining three read and two write operations per clock. Most integer instructions execute in a single clock cycle. Branch target prefetching is performed by the branch unit to allow single-cycle branches in many cases. The e200z3 core is a single-issue, 32-bit PowerPC Book E compliant design with 32 general purpose registers (GPRs). PowerPC Book E floating-point instructions are not supported by e200 in hardware, but are trapped and can be emulated by software. All arithmetic instructions that execute in the core operate on data in the general purpose registers (GPRs). A Signal Processing Extension (SPE) APU is provided to support real-time fixed point and single precision, embedded numerics operations using the general-purpose registers. All arithmetic instructions that execute in the core operate on data in the general purpose registers (GPRs). The GPRs have been extended to 64-bits to support vector instructions defined by the SPE APU. These instructions operate on a vector pair of 16-bit or 32-bit data types, and deliver vector and scalar results. In addition to the base PowerPC Book E instruction set, the e200z3 core also implements the VLE (Variable Length Encoding) APU, providing improved code density. In the remainder of this chapter, the e200z3 core is also referred to as “the core.” MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 3-1 3.2 Features The following is a list of some of the key features of the e200z3 core: • 32-bit PowerPC Book E programmer’s model • Single issue, 32-bit PowerPC Book E compliant CPU • Implements the VLE APU for reduced code footprint • In-order execution and retirement • Precise exception handling • Branch processing unit — Dedicated branch address calculation adder — Branch acceleration using Branch Lookahead Instruction Buffer • Load/store unit — 1 cycle load latency — Fully pipelined — Big and Little endian support — Misaligned access support — Zero load-to-use pipeline bubbles • Power management — Low-power design — Dynamic power management of execution units • Testability — Synthesizeable, full MuxD scan design — ABIST/MBIST for optional memory arrays 3.2.1 e200z3 Core Features Not Supported in the Device This device implements a subset of the e200z3 core complex features. The e200z3 core complex features that are not supported in the device are described in Table 4-2. Table 3-1. e200z3 Features Not Supported in the Device Core Function / Category Description Disabled events The external debug event (DEVT2) and unconditional debug event (UDE) are not supported Power management e200z3 core halted state and stopped state are not supported Power management The following low-power modes are not supported: • Doze mode • Nap mode • Sleep mode • Time-base interrupt wake-up from low-power mode is not supported Power management Core wake up is not supported MSR[WE] bit in the machine state register is not supported The OCR[WKUP] bit in the e200z3 OnCE control register (OCR) has no effect MPC5533 Microcontroller Reference Manual, Rev. 0 3-2 Freescale Semiconductor Table 3-1. e200z3 Features Not Supported in the Device Core (Continued) Function / Category Description Machine check The machine check input pin is not supported. HID0 [EMCP] has no effect, and MCSR[MCP] always reads a negated value. PVR value Least significant halfword of processor version register (PVR) is 0x0000, that contains the following bitfields: • MBG Use = 0x00 • MBG Rev = 0x0 • MBG ID = 0x0 The PVR register has two bitfields in the device. Reservation management Reservation management logic external to the e200z3 is not implemented. Verification The system version register (SVR) of the e200z3 is 0x 0000_0000. Time Base The decrement counters are always enabled in the e200z3. The timer external clock is not connected to a clock; Do not select the timer external clock. Context control 3.3 The CTXCR and ALTCXTCR registers are not supported. Microarchitecture Summary The e200 processor utilizes a four stage pipeline for instruction execution. The Instruction Fetch (stage 1), Instruction Decode/Register file Read/Effective Address Calculation (stage 2), Execute/Memory Access (stage 3), and Register Writeback (stage 4) stages operate in an overlapped process, allowing single clock instruction execution for most instructions. The integer execution unit consists of a 32-bit Arithmetic Unit (AU), a Logic Unit (LU), a 32-bit Barrel shifter (Shifter), a Mask-Insertion Unit (MIU), a Condition Register manipulation Unit (CRU), a Count-Leading-Zeros unit (CLZ), a 32x32 Hardware Multiplier array, result feed-forward hardware, and support hardware for division. Most arithmetic and logical operations are executed in a single cycle with the exception of the divide instructions. A Count-Leading-Zeros unit operates in a single clock cycle. The Instruction Unit contains a PC incrementer and a dedicated Branch Address adder to minimize delays during change of flow operations. Sequential prefetching is performed to ensure a supply of instructions into the execution pipeline. Branch target prefetching is performed to accelerate taken branches. Prefetched instructions are placed into an instruction buffer capable of holding six instructions. Branches can also be decoded at the instruction buffer and branch target addresses calculated prior to the branch reaching the instruction decode stage, allowing the branch target to be prefetched early. When a branch is detected at the instruction buffer, a prediction can be made on whether the branch is taken or not. If the branch is predicted to be taken, a target fetch is initiated and its target instructions are placed in the instruction buffer following the branch instruction. Conditional branches which are not taken and not folded execute in a single clock. Branches with successful target prefetching which are not folded have an effective execution time of one clock. All other taken branches have an execution time of two clocks. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 3-3 Memory load and store operations are provided for byte, halfword, and word (32-bit) data with automatic zero or sign extension of byte and halfword load data as well as optional byte reversal of data. These instructions can be pipelined to allow effective single cycle throughput. Load and store multiple word instructions allow low overhead context save and restore operations. The load/store unit contains a dedicated effective address adder to allow effective address generation to be optimized. Also, a load-to-use dependency does not incur any pipeline bubbles for most cases. The Condition Register unit supports the condition register (CR) and condition register operations defined by the PowerPC architecture. The condition register consists of eight 4-bit fields that reflect the results of certain operations, such as move, integer and floating-point compare, arithmetic, and logical instructions, and provide a mechanism for testing and branching. Vectored and autovectored interrupts are supported by the CPU. Vectored interrupt support is provided to allow multiple interrupt sources to have unique interrupt handlers invoked with no software overhead. The SPE APU supports vector instructions operating on 16- and 32-bit fixed-point data types, as well as 32-bit IEEE-754 single-precision floating-point formats, and supports single-precision floating-point operations. The 64-bit general purpose register file is used for source and destination operands, and there is a unified storage model for single-precision floating-point data types of 32-bits and the normal integer type. Low latency fixed-point and floating-point add, subtract, multiply, multiply-add, multiply-subtract, divide, compare, and conversion operations are provided. 3.3.1 Instruction Unit Features The features of the e200 Instruction unit are: • 64-bit instruction fetch path supports fetching of two 32-bit instruction per clock, or up to four 16-bit VLE APU instructions per clock • Instruction buffer holds up to six sequential instructions and two prefetched branch target instructions • Dedicated PC incrementer supporting instruction prefetches • Branch unit with dedicated branch address adder, and small branch target buffer logic supporting single cycle of execution of certain branches, two cycles for all others 3.3.2 Integer Unit Features The e200 integer unit supports single cycle execution of most integer instructions: • 32-bit AU for arithmetic and comparison operations • 32-bit LU for logical operations • 32-bit priority encoder for count leading zero’s function • 32-bit single cycle barrel shifter for static shifts and rotates • 32-bit mask unit for data masking and insertion • Divider logic for signed and unsigned divide in ≤16 clocks with minimized execution timing • 32x32 hardware multiplier array supports single-cycle 32x32→32 multiply MPC5533 Microcontroller Reference Manual, Rev. 0 3-4 Freescale Semiconductor 3.3.3 Load/Store Unit Features The e200 load/store unit supports load, store, and the load multiple / store multiple instructions: • 32-bit effective address adder for data memory address calculations • Pipelined operation supports throughput of one load or store operation per cycle • Dedicated 64-bit interface to memory supports saving and restoring of up to two registers per cycle for load multiple and store multiple word instructions 3.3.4 e200 System Bus Features The features of the e200 System Bus interface are as follows: • Independent Instruction and Data Buses • AMBA AHB2.v6 protocol • 32-bit address bus plus attributes and control on each bus • 64-bit read data bus for Instruction Interface • Separate unidirectional 64-bit read data bus and 64-bit write data bus for Data Interface • Overlapped, in-order accesses 3.3.5 MMU Features The features of the MMU are as follows: • Virtual Memory support • 32-bit Virtual and Physical Addresses • 8-bit Process Identifier • 16-entry Fully associative TLB • Support for multiple page sizes from 4 KB to 256 MB • Entry Flush Protection 3.3.6 Nexus 3 Features The Nexus 3 module is compliant with Class 3 of the IEEE-ISTO 5001-2003 standard. The following features are implemented: • Program Trace via Branch Trace Messaging (BTM). Branch trace messaging displays program flow discontinuities (direct and indirect branches, exceptions, etc.), allowing the development tool to interpolate what transpires between the discontinuities. Thus static code can be traced. • Data Trace via Data Write Messaging (DWM) and Data Read Messaging (DRM). This provides the capability for the development tool to trace reads and/or writes to selected internal memory resources. • Ownership Trace via Ownership Trace Messaging (OTM). OTM facilitates ownership trace by providing visibility of which process ID or operating system task is activated. An Ownership Trace MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 3-5 • • • • • • Message is transmitted when a new process/task is activated, allowing the development tool to trace ownership flow. Run-time access to embedded processor registers and memory map via the JTAG port. This allows for enhanced download/upload capabilities. Watchpoint Messaging via the auxiliary pins Watchpoint Trigger enable of Program and/or Data Trace Messaging Auxiliary interface for higher data input/output — Configurable (min./max) Message Data Out pins (MDO[11:0]) — One or two Message Start/End Out pins (MSEO[1:0]) — One Read/Write Ready pin (RDY) pin — One Watchpoint Event pin (EVTO) — One Event In pin (EVTI) — One Message Clock Out (MCKO) pin Registers for Program Trace, Data Trace, Ownership Trace and Watchpoint Trigger. All features controllable and configurable via the JTAG port MPC5533 Microcontroller Reference Manual, Rev. 0 3-6 Freescale Semiconductor 3.4 Block Diagram Figure 4-1 shows a block diagram of the e200z3 core complex. OnCE/Nexus Control Logic CPU Control Logic Signal Processing Unit (SPE APU) Alternate Contexts Memory Management Unit LR CR CTR XER SPR GPR Integer Execution Unit Instruction Unit Instruction Buffer Address Data Control Multiply Unit 32 64 N Instruction Bus Interface Unit PC Unit External SPR Interface (MTSPR/MFSPR) Branch Unit Load/Store Unit Control Data Data Bus Interface Unit 32 Address 64 Data N Control Figure 3-1. e200z3 Block Diagram 3.5 3.5.1 Memory Management Unit (MMU) Overview The e200z3 Memory Management Unit is a 32-bit PowerPC Book E compliant implementation, with the following feature set: • Freescale Book E MMU architecture compliant • Translates from 32-bit effective to 32-bit real addresses • 16-entry fully associative TLB with support for nine page sizes (4 K, 16 K, 64 K, 256 K, 1 M, 4 M, 16 M, 64 M, 256 M) • Hardware assist for TLB miss exceptions • Software managed by tlbre, tlbwe, tlbsx, tlbsync, and tlbivax instructions MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 3-7 3.5.2 Translation Lookaside Buffer (TLB) The Freescale Book E architecture defines support for zero or more TLBs in an implementation, each with its own characteristics, and provides configuration information for software to query the existence and structure of the TLB(s) through a set of special purpose registers: MMUCFG, TLB0CFG, TLB1CFG, etc. By convention, TLB0 is used for a set associative TLB with fixed page sizes, TLB1 is used for a fully associative TLB with variable page sizes, and TLB2 is arbitrarily defined by an implementation. The e200z3 MMU supports a single TLB which is fully associative and supports variable page sizes, thus it corresponds to TLB1. For the rest of this document, TLB, TLBCAM, and TLB1 are used interchangeably. The TLB consists of a 16-entry, fully associative CAM array with support for nine page sizes. To perform a lookup, the CAM is searched in parallel for a matching TLB entry. The contents of this TLB entry are then concatenated with the page offset of the original effective address. The result is the physical address of the access. A hit to multiple TLB entries is considered to be a programming error. If this occurs, the TLB generates an invalid address and TLB entries can be corrupted (an exception is not reported). Table 4-3 shows the TLB entry bit definitions. Table 3-2. TLB Entry Bit Definitions Field Comments V Valid bit for entry TS Translation address space (compared against AS bit) TID[0:7] Translation ID (compared against PID0 or ‘0’) EPN[0:19] Effective page number (compared against effective address) RPN[0:19] Real page number (translated address) SIZE[0-3] Page size (4 KB, 16 KB, 64 KB, 256 KB, 1 MB, 4 MB, 16 MB, 64 MB, 256 MBs) SX, SW, SR Supervisor execute, write, and read permission bits UX, UW, UR User execute, write, and read permission bits WIMGE Translation attributes (Write-through required, cache-Inhibited, Memory coherence required, Guarded, Endian) U0–U3 Use bits for software IPROT Invalidation protect VLE VLE page indicator The TLB is accessed indirectly through several MMU Assist (MAS) registers. Software can write and read the MMU Assist registers with mtspr and mfspr instructions. These registers contain information related to reading and writing a given entry within the TLB. Data is read from the TLB into the MAS registers with a tlbre (TLB read entry) instruction. Data is written to the TLB from the MAS registers with a tlbwe (TLB write entry) instruction. Certain fields of the MAS registers are also written by hardware when an Instruction TLB Error, Data TLB Error, DSI, or ISI interrupt occurs. MPC5533 Microcontroller Reference Manual, Rev. 0 3-8 Freescale Semiconductor On a TLB Error interrupt, the MAS registers are written by hardware with the proper EA, default attributes (TID, WIMGE, permissions, etc.), and TLB selection information, and an entry in the TLB to replace. Software manages this entry selection information by updating a replacement entry value during TLB miss handling. Software must provide the correct RPN and permission information in one of the MAS registers before executing a tlbwe instruction. On taking a DSI or ISI interrupt, the hardware updates only the search PID (SPID) and search address space (SAS) fields in the MAS registers using PID0, and appropriate MSR[IS] or MSR[DS] values which were used when the DSI or ISI exception was recognized. During the interrupt handler, software can issue a TLB search instruction (tlbsx), which uses the SPID field along with the SAS field, to determine the entry related to the DSI or ISI exception. (It is possible that the entry which caused the DSI or ISI interrupt no longer exists in the TLB by the time the search occurs if a TLB invalidate or replacement removes the entry between the time the exception is recognized and when the tlbsx is executed.) The tlbre, tlbwe, tlbsx, tlbivax, and tlbsync instructions are privileged. 3.5.3 Translation Flow The effective address, concatenated with the address space value of the corresponding MSR bit (MSR[IS] or MSR[DS], is compared to the appropriate number of bits of the EPN field (depending on the page size) and the TS field of TLB entries. If the contents of the effective address plus the address space bit matches the EPN field and TS bit of the TLB entry, that TLB entry is a candidate for a possible translation match. In addition to a match in the EPN field and TS, a matching TLB entry must match with the current Process ID of the access (in PID0), or have a TID value of 0, indicating the entry is globally shared among all processes. Figure 4-2 shows the translation match logic for the effective address plus its attributes, collectively called the virtual address, and how it is compared with the corresponding fields in the TLB entries. TLB_entry[V] TLB_entry[TS] AS (from MSR[IS] or MSR[DS]) Process ID TLB_entry[TID] TLB_entry[EPN] EA page number bits TLB entry Hit =? =? =0? private page shared page =? Figure 3-2. Virtual Address and TLB-Entry Compare Process MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 3-9 The page size for a TLB entry determines how many bits of the effective address are compared with the corresponding EPN field in the TLB entry as shown in Table 3-3. On a TLB hit, the corresponding bits of the Real Page Number (RPN) field are used to form the real address. Table 3-3. Page Size and EPN Field Comparison Page Size (4SIZE KBs) EA to EPN Comparison 0001 4 KB EA[0:19] =? EPN[0:19] 0010 16 KB EA[0:17] =? EPN[0:17] SIZE Field 0011 64 KB EA[0:15] =? EPN[0:15] 0100 256 KB EA[0:13] =? EPN[0:13] 0101 1 MB EA[0:11] =? EPN[0:11] 0110 4 MB EA[0:9] =? EPN[0:9] 0111 16 MB EA[0:7] =? EPN[0:7] 1000 64 MB EA[0:5] =? EPN[0:5] 1001 256 MB EA[0:3] =? EPN[0:3] On a TLB hit, the generation of the physical address occurs as shown in Figure 3-3. NOTE: n = 32 – log2 (page size) n >= 20 n = 20 for 4 KB page size MSR[DS] for data access MSR[IS] for instruction fetch 32-bit Effective Address AS PID Effective Page Address Offset n–1 n 0 31 Virtual Address TLB multiple-entry RPN field of matching entry Real Page Number Offset n–1 n 0 31 32-bit Real Address Figure 3-3. Effective to Real Address Translation Flow 3.5.4 Permissions An operating system can restrict access to virtual pages by selectively granting permissions for user mode read, write, and execute, and supervisor mode read, write, and execute on a per page basis. These permissions can be set up for a particular system (for example, program code might be execute-only, data structures can be mapped as read/write/no-execute) and can also be changed by the operating system based on application requests and operating system policies. MPC5533 Microcontroller Reference Manual, Rev. 0 3-10 Freescale Semiconductor The UX, SX, UW, SW, UR, and SR access control bits are provided to support selective permissions (access control): • SR—Supervisor read permission. Allows loads and load-type cache management instructions to access the page while in supervisor mode (MSR[PR=0]). • SW—Supervisor write permission. Allows stores and store-type cache management instructions to access the page while in supervisor mode (MSR[PR=0]). • SX—Supervisor execute permission. Allows instruction fetches to access the page and instructions to be executed from the page while in supervisor mode (MSR[PR=0]). • UR—User read permission. Allows loads and load-type cache management instructions to access the page while in user mode (MSR[PR=1]). • UW—User write permission. Allows stores and store-type cache management instructions to access the page while in user mode (MSR[PR=1]). • UX—User execute permission. Allows instruction fetches to access the page and instructions to be executed from the page while in user mode (MSR[PR=1]). If the translation match was successful, the permission bits are checked as shown in Figure 3-4. If the access is not allowed by the access permission mechanism, the processor generates an Instruction or Data Storage interrupt (ISI or DSI). TLB MSR[PR] Instruction Fetch TLB_entry[UX] Access Granted TLB_entry[SX] Load-class Data Access TLB_entry[UR] TLB_entry[SR] Store-class Data Access TLB_entry[UW] TLB_entry[SW] Figure 3-4. Granting of Access Permission 3.6 Bus Interface Unit (BIU) The BIU encompasses control and data signals supporting instruction and data transfers. The memory interface supported by the BIU is based on the AMBA AHB-Lite subset of the AMBA 2.0 AHB, with V6 AMBA Extensions. (Ref. documents ARM IHI 0011A, ARM DVI 0044A, and ARM PR022-GENC-001011 0.7). Additional sideband signals have been added to support additional control functions. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 3-11 NOTE The AMBA AHB bit and byte ordering reflect a natural little-endian ordering, as used by the AMBA documentation. The e200z3 BIU automatically performs byte lane conversions for big-endian transfers. Single-beat and misaligned transfers are supported for read and write cycles, and write-buffer writes. 3.7 Core Registers and Programmer’s Models This section describes the registers implemented in the e200z3 core. It includes an overview of registers defined by the PowerPC Book E architecture, highlighting differences in how these registers are implemented in the e200 core, and provides a detailed description of e200-specific registers. Full descriptions of the architecture-defined register set are provided in Book E: Enhanced PowerPCtm Architecture. The PowerPC Book E architecture defines register-to-register operations for all computational instructions. Source data for these instructions are accessed from the on-chip registers or are provided as immediate values embedded in the opcode. The three-register instruction format allows specification of a target register distinct from the two source registers, thus preserving the original data for use by other instructions. Data is transferred between memory and registers with explicit load and store instructions only. e200z3 extends the General Purpose Registers to 64-bits for supporting SPE APU operations. PowerPC Book E instructions operate on the lower 32 bits of the GPRs only, and the upper 32 bits are unaffected by these instructions. SPE vector instructions operate on the entire 64-bit register. The SPE APU defines load and store instructions for transferring 64-bit values to/from memory. NOTE e200z3 is a 32-bit implementation of the PowerPC Book E architecture. In this document, register bits are sometimes numbered from bit 31 (Most Significant Bit) to 0 (Least Significant Bit), rather than the Book E numbering scheme of 32:63, thus register bit numbers for some registers in Book E are 32 higher. Where appropriate, the Book E defined bit numbers are shown in parentheses. MPC5533 Microcontroller Reference Manual, Rev. 0 3-12 Freescale Semiconductor Figure 3-5 and Figure 3-6 show the complete e200 register set. Figure 3-5 shows the registers which are accessible while in supervisor mode. SUPERVISOR MODE PROGRAMMER’S MODEL General Registers Condition Register CR GPR0 GPR1 ••• GPR31 Count Register CTR Exception Handling/Control Registers General Purpose Registers SPR 9 SPRG0 SPRG1 SPRG2 SPRG3 SPRG4 SPRG5 SPRG6 SPRG7 Link Register LR SPR 8 XER XER SPR General SPR 1 SPR 272 SPR 273 SPR 274 SPR 275 SPR 276 SPR 277 SPR 278 SPR 279 SRR0 SRR1 CSRR0 CSRR1 DSRR01 DSRR11 USPRG0 Hardware Implementation Dependent1 Machine State MSR Processor Version HID0 HID1 PVR Context Control1 SPR 287 CTXCR ALTCTXCR Processor ID PIR System SPR 286 Debug Control DBCR0 DBCR1 DBCR2 DBCR31 SPR 308 SPR 309 SPR 310 SPR 561 IAC1 IAC2 IAC3 IAC4 SPR 304 Data Address Compare Debug Counter1 DBCNT 1 2 SPR 562 DAC1 DAC2 Not all e200-specific registers are supported by all PowerPC processors. Optional registers defined by the PowerPC Book-E architecture. SPR 312 SPR 313 SPR 314 SPR 315 IVOR0 IVOR1 ••• IVOR15 SPR 400 SPR 401 ••• SPR 415 IVOR321 ••• IVOR341 SPR 528 ••• SPR 530 SPR 572 SPR 61 BTB Register BTB Control1 Decrementer SPR 284 SPR 285 DEC DECAR SPR 22 SPR 54 BUCSR SPR 1013 Control & Status APU Register TCR TSR SPE APU Status & Control Register SPR 340 SPR 336 SPEFSCR SPR 512 Memory Management Registers MMU Assist1 SPR 316 SPR 317 SPR 62 Timers TBL TBU Instruction Address Compare DBSR DEAR Time Base (Write-Only) Debug Registers2 Debug Status MCSR SPR 63 Data Exception Address SPR 560 SPR 568 SPR 1023 IVPR Interrupt Vector Offset Machine Check Syndrome Register SPR 1008 SPR 1009 Version1 SVR ESR SPR 256 SPR 26 SPR 27 SPR 58 SPR 59 SPR 574 SPR 575 Exception Syndrome User SPR Processor Control Registers Interrupt Vector Prefix Save & Restore Control & Configuration Process ID MAS0 MAS1 MAS2 MAS3 MAS4 SPR 624 SPR 625 SPR 626 SPR 627 SPR 628 MAS6 SPR 630 PID0 SPR 48 MMUCSR0 MMUCFG TLB0CFG TLB1CFG SPR 1012 SPR 1015 SPR 688 SPR 689 Cache Register Cache Configuration (Read-Only) L1CFG0 SPR 515 Figure 3-5. e200z3 Supervisor Mode Programmer’s Model MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 3-13 Figure 3-6 shows the set of registers which are accessible while in user mode. The number to the right of the special-purpose registers (SPRs) is the decimal number used in the instruction syntax to access the register (for example, the integer exception register (XER) is SPR 1). USER MODE PROGRAMMER’S MODEL General Registers Condition Register CR Count Register CTR SPR 9 Timers Cache Register General Purpose Registers Time Base (Read-Only) Cache Configuration (Read-Only) GPR0 GPR1 ••• GPR31 TBL TBU Link Register LR SPR 8 XER SPR 1 L1CFG0 SPR 515 Control Registers APU Register SPR General (Read-Only) SPE APU Status & Control Register SPRG4 SPRG5 SPRG6 SPRG7 XER SPR 268 SPR 269 SPR 260 SPR 261 SPR 262 SPR 263 SPEFSCR SPR 512 User SPR USPRG0 SPR 256 Figure 3-6. e200 User Mode Programmer’s Model General purpose registers (GPRs) are accessed through instruction operands. Access to other registers can be explicit (by using instructions for that purpose such as Move to Special Purpose Register (mtspr) and Move from Special Purpose Register (mfspr) instructions) or implicit as part of the execution of an instruction. Some registers are accessed both explicitly and implicitly. 3.7.1 PowerPC Book E Registers e200 supports most of the registers defined by Book E: Enhanced PowerPC™ Architecture. Notable exceptions are the Floating Point registers FPR0-FPR31 and FPSCR. e200 does not support the Book E Floating Point Architecture in hardware. The General Purpose registers have been extended to 64-bits. The e200 supported PowerPC BookE registers are described as follows: 3.7.1.1 User-level Registers The user-level registers can be accessed by all software with either user or supervisor privileges, and are grouped as follows: • General-purpose registers (GPRs)—The thirty-two 64-bit GPRs (GPR0–GPR31) are data source or destination registers for integer instructions, and provide data to generate addresses. • Condition register (CR)—The 32-bit CR consists of eight 4-bit fields, (CR0–CR7), that reflect the results of arithmetic operations and are used for testing and branching. The remaining user-level registers are SPRs. The PowerPC architecture has the mtspr and mfspr instructions for accessing SPRs. • Integer exception register (XER)—The XER indicates overflow and carries for integer operations. MPC5533 Microcontroller Reference Manual, Rev. 0 3-14 Freescale Semiconductor • • • • • Link register (LR)—The LR provides the branch target address for the Branch Conditional to Link Register (bclr, bclrl) instructions, and is used to hold the address of the instruction that follows a branch and link instruction, typically used for linking to subroutines. Count register (CTR)—The CTR holds a loop count that can be decremented during execution of appropriately coded branch instructions. The CTR also provides the branch target address for the Branch Conditional to Count Register (bcctr, bcctrl) instructions. Time Base facility (TB)— consists of two 32-bit registers—Time Base Upper (TBU) and Time Base Lower (TBL). These two registers are accessible in a read-only access to user-level software. Software-use Special Purpose Registers (SPRGs)—The PowerPC Book E architecture defines how software uses the SPRG4 through SPRG7 (SPRG4–SPRG7). These registers are read-only and are accessed by user-level software. The e200z3 does not allow user mode access to the SPRG3 register (defined as implementation-dependent by Book E). User Software-Use Special Purpose Register (USPRG0)—The PowerPC Book E architecture defines USPRG0 as a read-write register that is accessible by user-level software. 3.7.1.2 Supervisor-level Registers In addition to the registers accessible in user mode, Supervisor-level software has access to additional control and status registers used for configuration, exception handling, and other operating system functions. The PowerPC Book E architecture defines the following supervisor-level registers: • Processor Control registers — Machine State Register (MSR). The MSR defines the state of the processor. The MSR can be modified by the Move to Machine State Register (mtmsr), System Call (sc), and Return from Exception (rfi, rfci, rfdi) instructions. It can be read by the Move from Machine State Register (mfmsr) instruction. When an interrupt occurs, the contents of the MSR are saved to one of the machine state save/restore registers (SRR1, CSRR1, DSRR1). — Processor version register (PVR). This register is a read-only register that identifies the version (model) and revision level of the PowerPC processor. — Processor Identification Register (PIR). This read-only register is provided to distinguish the processor from other processors in the system. • Storage Control register — Process ID Register (PID, also referred to as PID0). This register is provided to indicate the current process or task identifier. It is used by the MMU as an extension to the effective address, and by Nexus 2 module for Ownership Trace message generation. PowerPC Book E allows for multiple PIDs; e200z3 implements only one. • Interrupt Registers — Data Exception Address Register (DEAR). After most Data Storage Interrupt (DSI), or on an Alignment Interrupt, or Data TLB Miss Interrupt, the DEAR is set to the effective address (EA) generated by the faulting instruction. — SPRG0–SPRG7, USPRG0. The SPRG0–SPRG7 and USPRG0 registers are used by thee operating system. e200 does not allow user mode access to the SPRG3 register (defined as implementation dependent by Book E). MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 3-15 • • — Exception Syndrome Register (ESR). The ESR register provides a syndrome to differentiate between the different kinds of exceptions which can generate the same interrupt. — Interrupt Vector Prefix Register (IVPR) and the Interrupt Vector Offset Registers (IVOR0–IVOR15, IVOR32–IVORxx). These registers together provide the address of the interrupt handler for different classes of interrupts. — Save/Restore Register 0 (SRR0). The SRR0 register is used to save machine state on a non-critical interrupt, and contains the address of the instruction at which execution resumes when an rfi instruction is executed at the end of a non-critical class interrupt handler routine. — Critical Save/Restore register 0 (CSRR0). The CSRR0 register is used to save machine state on a critical interrupt, and contains the address of the instruction at which execution resumes when an rfci instruction is executed at the end of a critical class interrupt handler routine. — Save/Restore register 1 (SRR1). The SRR1 register is used to save machine state from the MSR on non-critical interrupts, and to restore machine state when rfi executes. — Critical Save/Restore register 1 (CSRR1). The CSRR1 register is used to save machine state from the MSR on critical interrupts, and to restore machine state when rfci executes. Debug facility registers — Debug Control Registers (DBCR0–DBCR2). These registers provide control for enabling and configuring debug events. — Debug Status Register (DBSR). This register contains debug event status. — Instruction Address Compare registers (IAC1–IAC4). These registers contain addresses and/or masks which are used to specify Instruction Address Compare debug events. — Data address compare registers (DAC1–2). These registers contain addresses and/or masks which are used to specify Data Address Compare debug events. — e200 does not implement the Data Value Compare registers (DVC1 and DVC2). Timer Registers — The clock inputs for the timers are connected to the internal system clock. — Time base (TB). The TB is a 64-bit structure provided for maintaining the time of day and operating interval timers. The TB consists of two 32-bit registers, Time Base Upper (TBU) and Time Base Lower (TBL). The Time Base registers can be written to only by supervisor-level software, but can be read by both user and supervisor-level software. — Decrementer register (DEC). This register is a 32-bit decrementing counter that provides a mechanism for causing a decrementer exception after a programmable delay. — Decrementer Auto-Reload (DECAR). This register is provided to support the auto-reload feature of the Decrementer. — Timer Control Register (TCR). This register controls Decrementer, Fixed-Interval Timer, and Watchdog Timer options. — Timer Status Register (TSR). This register contains status on timer events and the most recent Watchdog Timer-initiated processor reset. More details about these registers can be found in the PowerPC Book E architecture specifications. MPC5533 Microcontroller Reference Manual, Rev. 0 3-16 Freescale Semiconductor 3.7.2 e200-specific Registers The PowerPC Book E architecture allows implementation-specific registers. Those incorporated in the e200 core are described in the following sections. 3.7.2.1 User-level Registers The user-level registers can be accessed by all software with either user or supervisor privileges. They include the following: • Signal Processing Extension APU status and control register (SPEFSCR). The SPEFSCR contains all fixed-point and floating-point exception signal bits, exception summary bits, exception enable bits, and rounding control bits needed for compliance with the IEEE 754 standard. • The L1 Cache Configuration register (L1CFG0). This read-only register allows software to query the configuration of the L1 cache. 3.7.2.2 Supervisor-level Registers The following supervisor-level registers are defined in e200 in addition to the PowerPC Book E registers described above: • Configuration Registers — Hardware implementation-dependent register 0 (HID0). This register controls various processor and system functions. — Hardware implementation-dependent register 1 (HID1). This register controls various processor and system functions. • Exception Handling and Control Registers — Machine Check Syndrome register (MCSR). This register provides a syndrome to differentiate between the different kinds of conditions which can generate a Machine Check. — Debug Save/Restore register 0 (DSRR0). When enabled, the DSRR0 register is used to save the address of the instruction at which execution continues when rfdi executes at the end of a debug interrupt handler routine. — Debug Save/Restore register 1 (DSRR1). When enabled, the DSRR1 register is used to save machine status on debug interrupts and to restore machine status when rfdi executes. • Debug Facility Registers — Debug Control Register 3 (DBCR3)—This register provides control for debug functions not described in PowerPC Book E architecture. — Debug Counter Register (DBCNT)—This register provides counter capability for debug functions. • Branch Unit Control and Status Register (BUCSR) controls operation of the optional BTB. If an optional BTB is not present, this register returns all zeros. • L1 Cache Configuration Register (L1CFG0) is a read-only register that allows software to query the configuration of the L1 Cache. This register returns all zeros. • MMU Configuration Register (MMUCFG) is a read-only register that allows software to query the configuration of the MMU. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 3-17 • • Memory Management Unit Registers — MMU Assist (MAS0-MAS4, MAS6) registers. These registers provide the interface to the core from the Memory Management Unit. — MMU Control and Status Register (MMUCSR0) controls invalidation of the MMU. — TLB Configuration Registers (TLB0CFG, TLB1CFG) are read-only registers that allow software to query the configuration of the TLBs. System version register (SVR). This register is a read-only register that identifies the version (model) and revision level of the System which includes an e200 PowerPC processor. It is not guaranteed that the implementation of e200 core-specific registers is consistent among PowerPC processors, although other processors can implement similar or identical registers. More details about these registers are in the e200z3 PowerPC Core Reference Manual. 3.8 3.8.1 Signal Processing Extension APU (SPE APU) Overview The e200z3 core provides a register file with thirty-two 64-bit registers. The PowerPC 32-bit Book E instructions operate on the lower (least significant) 32 bits of the 64-bit register. New SPE instructions are defined that view the 64-bit register as being composed of a vector of two 32-bit elements, and some of the instructions also read or write 16-bit elements. These new instructions can also be used to perform scalar operations by ignoring the results of the upper 32-bit half of the register file. Some instructions are defined that produce a 64-bit scalar result. Vector fixed-point instructions operate on a vector of two 32-bit or four 16-bit fixed-point numbers resident in the 64-bit GPRs. Vector floating-point instructions operate on a vector of two 32-bit single-precision floating-point numbers resident in the 64-bit GPRs. Scalar floating-point instructions operate on the lower half of GPRs. These single-precision floating-point instructions do not have a separate register file; there is a single shared register file for all instructions. The SPE and Book E instructions issue from a single instruction stream. Figure 3-7 shows two different representations of the 64-bit GPRs. The shaded half is the only region operated on by the 32-bit PowerPC instructions. 0 GPRx 31 Upper/Most Significant Word 0 15 16 32 63 Lower/Least Significant Word 31 32 47 48 63 GPRx Figure 3-7. 64-bit General Purpose Registers 3.8.2 SPE Programming Model Not all SPE instructions record events such as overflow, saturation and negative/positive result. See the description of the individual SPE instruction in the e200z3 PowerPC Core Reference Manual for information on which conditions are recorded and where they are recorded. Most SPE instructions record MPC5533 Microcontroller Reference Manual, Rev. 0 3-18 Freescale Semiconductor conditions to the SPEFSCR. Vector compare instructions store the result of the comparison into the condition register (CR). The e200z3 core has a 64-bit architectural accumulator register that holds the results of the SPE multiply accumulate (MAC) fixed-point instructions. The accumulator allows back-to-back execution of dependent fixed-point MAC instructions, something that is found in the inner loops of DSP code such as filters. The accumulator is partially visible to the programmer in that its results do not have to be explicitly read to use them. Instead, they are always copied into a 64-bit destination GPR specified as part of the instruction. The accumulator however, has to be explicitly cleared when starting a new MAC loop. Based upon the type of instruction, an accumulator can hold either a single 64-bit value or a vector of two 32-bit elements. 3.9 Instruction Summary In addition to the PowerPC Book E instructions, the MPC5533 supports e200 core specific instructions, SPE APU instructions and VLE instructions. See the PowerPC Microprocessor Family: The Programming Environment for 32-bit Microprocessors, the e200z3 PowerPC Core Reference Manual and the Variable-Length Encoding (VLE) Extension Programming Interface Manual documents. 3.9.1 SPE APU Simple and Complex Integer Instructions The SPE APU supports both scalar and vector integer instructions. The instructions are grouped into two categories according to the latency and throughput; Simple Integer Instructions and Complex Integer Instructions. The SPE APU Simple Integer Instructions perform operations such as addition, subtraction, logical operations, rotate, shift, compare, round, merge and swap, and sign or zero-extend. Table 3-4 briefly describes the SPE Simple Integer Instructions. Table 3-4. SPE Simple Integer Instructions Instruction Description brinc Bit Reversed Increment evabs Vector Absolute Value evaddiw Vector Add Immediate Word evaddw Vector Add Word evand Vector AND evandc Vector AND with Complement evcmpeq Vector Compare Equal evcmpgts Vector Compare Greater Than Signed evcmpgtu Vector Compare Greater Than Unsigned evcmplts Vector Compare Less Than Signed evcmpltu Vector Compare Less Than Unsigned MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 3-19 Table 3-4. SPE Simple Integer Instructions (Continued) Instruction Description evcntlsw Vector Count Leading Sign Bits Word evcntlzw Vector Count Leading Zeros Word evdivws Vector Divide Word Signed evdivwu Vector Divide Word Unsigned eveqv Vector Equivalent evextsb Vector Extend Sign Byte evextsh Vector Extend Sign Half Word evmergehi Vector Merge High evmergehilo Vector Merge High/Low evmergelo Vector Merge Low evmergelohi Vector Merge Low/High evnand Vector NAND evneg Vector Negate evnor Vector NOR evor Vector OR evorc Vector OR with Complement evrlw Vector Rotate Left Word evrlwi Vector Rotate Left Word Immediate evrndw Vector Round Word evsel Vector Select evslw Vector Shift Left Word evslwi Vector Shift Left Word Immediate evsplatfi Vector Splat Fractional Immediate evsplati Vector Splat Immediate evsrwis Vector Shift Right Word Immediate Signed evsrwiu Vector Shift Right Word Immediate Unsigned evsrws Vector Shift Right Word Signed evsrwu Vector Shift Right Word Unsigned evsubfw Vector Subtract from Word evsubifw Vector Subtract Immediate from Word evxor Vector XOR MPC5533 Microcontroller Reference Manual, Rev. 0 3-20 Freescale Semiconductor The SPE APU Complex Integer Instructions perform operations such as multiplication, division, and multiply and accumulate. Table 3-5 briefly describes the SPE Complex Integer Instructions. Table 3-5. SPE Complex Integer Instructions Instruction Description evaddsmiaaw Vector Add Signed, Modulo, Integer to Accumulator Word evaddssiaaw Vector Add Signed, Saturate, Integer to Accumulator Word evaddumiaaw Vector Add Unsigned, Modulo, Integer to Accumulator Word evaddusiaaw Vector Add Unsigned, Saturate, Integer to Accumulator Word evdivws Vector Divide Word Signed evdivwu Vector Divide Word Unsigned evmhegsmfaa Vector Multiply Half Words, Even, Guarded, Signed, Modulo, Fractional and Accumulate evmhegsmfan Vector Multiply Half Words, Even, Guarded, Signed, Modulo, Fractional and Accumulate Negative evmhegsmiaa Vector Multiply Half Words, Even, Guarded, Signed, Modulo, Integer and Accumulate evmhegsmian Vector Multiply Half Words, Even, Guarded, Signed, Modulo, Integer and Accumulate Negative evmhegumiaa Vector Multiply Half Words, Even, Guarded, Unsigned, Modulo, Integer and Accumulate evmhegumian Vector Multiply Half Words, Even, Guarded, Unsigned, Modulo, Integer and Accumulate Negative evmhesmf Vector Multiply Half Words, Even, Signed, Modulo, Fractional evmhesmfa Vector Multiply Half Words, Even, Signed, Modulo, Fractional, to Accumulator evmhesmfaaw Vector Multiply Half Words, Even, Signed, Modulo, Fractional and Accumulate into Words evmhesmfanw Vector Multiply Half Words, Even, Signed, Modulo, Fractional and Accumulate Negative into Words evmhesmi Vector Multiply Half Words, Even, Signed, Modulo, Integer evmhesmia Vector Multiply Half Words, Even, Signed, Modulo, Integer, to Accumulator evmhesmiaaw Vector Multiply Half Words, Even, Signed, Modulo, Integer and Accumulate into Words evmhesmianw Vector Multiply Half Words, Even, Signed, Modulo, Integer and Accumulate Negative into Words evmhessf Vector Multiply Half Words, Even, Signed, Saturate, Fractional evmhessfa Vector Multiply Half Words, Even, Signed, Saturate, Fractional, to Accumulator evmhessfaaw Vector Multiply Half Words, Even, Signed, Saturate, Fractional and Accumulate into Words evmhessfanw Vector Multiply Half Words, Even, Signed, Saturate, Fractional and Accumulate Negative into Words evmhessiaaw Vector Multiply Half Words, Even, Signed, Saturate, Integer and Accumulate into Words evmhessianw Vector Multiply Half Words, Even, Signed, Saturate, Integer and Accumulate Negative into Words evmheumi Vector Multiply Half Words, Even, Unsigned, Modulo, Integer evmheumia Vector Multiply Half Words, Even, Unsigned, Modulo, Integer, to Accumulator evmheumiaaw Vector Multiply Half Words, Even, Unsigned, Modulo, Integer and Accumulate into Words evmheumianw Vector Multiply Half Words, Even, Unsigned, Modulo, Integer and Accumulate Negative into Words evmheusiaaw Vector Multiply Half Words, Even, Unsigned, Saturate, Integer and Accumulate into Words MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 3-21 Table 3-5. SPE Complex Integer Instructions (Continued) Instruction Description evmheusianw Vector Multiply Half Words, Even, Unsigned, Saturate, Integer and Accumulate Negative into Words evmhogsmfaa Multiply Half Words, Odd, Guarded, Signed, Modulo, Fractional and Accumulate evmhogsmfan Multiply Half Words, Odd, Guarded, Signed, Modulo, Fractional and Accumulate Negative evmhogsmiaa Multiply Half Words, Odd, Guarded, Signed, Modulo, Integer and Accumulate evmhogsmian Multiply Half Words, Odd, Guarded, Signed, Modulo, Integer and Accumulate Negative evmhogumiaa Multiply Half Words, Odd, Guarded, Unsigned, Modulo, Integer and Accumulate evmhogumian Multiply Half Words, Odd, Guarded, Unsigned, Modulo, Integer and Accumulate Negative evmhosmf Vector Multiply Half Words, Odd, Signed, Modulo, Fractional evmhosmfa Vector Multiply Half Words, Odd, Signed, Modulo, Fractional, to Accumulator evmhosmfaaw Vector Multiply Half Words, Odd, Signed, Saturate, Fractional and Accumulate into Words evmhosmfanw Vector Multiply Half Words, Odd, Signed, Saturate, Fractional and Accumulate Negative into Words evmhosmi Vector Multiply Half Words, Odd, Signed, Modulo, Integer evmhosmia Vector Multiply Half Words, Odd, Signed, Modulo, Integer, to Accumulator evmhosmiaaw Vector Multiply Half Words, Odd, Signed, Modulo, Integer and Accumulate into Words evmhosmianw Vector Multiply Half Words, Odd, Signed, Modulo, Integer and Accumulate Negative into Words evmhossf Vector Multiply Half Words, Odd, Signed, Saturate, Fractional evmhossfa Vector Multiply Half Words, Odd, Signed, Saturate, Fractional, to Accumulator evmhossfaaw Vector Multiply Half Words, Odd, Signed, Saturate, Fractional and Accumulate into Words evmhossfanw Vector Multiply Half Words, Odd, Signed, Saturate, Fractional and Accumulate Negative into Words evmhossiaaw Vector Multiply Half Words, Odd, Signed, Saturate, Integer and Accumulate into Words evmhossianw Vector Multiply Half Words, Odd, Signed, Saturate, Integer and Accumulate Negative into Words evmhoumi Vector Multiply Half Words, Odd, Unsigned, Modulo, Integer evmhoumia Vector Multiply Half Words, Odd, Unsigned, Modulo, Integer, to Accumulator evmhoumiaaw Vector Multiply Half Words, Odd, Unsigned, Modulo, Integer and Accumulate into Words evmhoumianw Vector Multiply Half Words, Odd, Unsigned, Modulo, Integer and Accumulate Negative into Words evmhousiaaw Vector Multiply Half Words, Odd, Unsigned, Saturate, Integer and Accumulate into Words evmhousianw Vector Multiply Half Words, Odd, Unsigned, Saturate, Integer and Accumulate Negative into Words evmra Move Register to Accumulator evmwhsmf Vector Multiply Word High Signed, Modulo, Fractional evmwhsmfa Vector Multiply Word High Signed, Modulo, Fractional, to Accumulator evmwhsmi Vector Multiply Word High Signed, Modulo, Integer evmwhsmia Vector Multiply Word High Signed, Modulo, Integer, to Accumulator evmwhssf Vector Multiply Word High Signed, Saturate, Fractional MPC5533 Microcontroller Reference Manual, Rev. 0 3-22 Freescale Semiconductor Table 3-5. SPE Complex Integer Instructions (Continued) Instruction Description evmwhssfa Vector Multiply Word High Signed, Saturate, Fractional, to Accumulator evmwhumi Vector Multiply Word High Unsigned, Modulo, Integer evmwhumia Vector Multiply Word High Unsigned, Modulo, Integer, to Accumulator evmwlsmf Vector Multiply Word Low Signed, Modulo, Fractional evmwlsmfa Vector Multiply Word Low Signed, Modulo, Fractional, to Accumulator evmwlsmfaaw Vector Multiply Word Low Signed, Modulo, Fractional and Accumulate in Words evmwlsmfanw Vector Multiply Word Low Signed, Modulo, Fractional and Accumulate Negative in Words evmwlsmiaaw Vector Multiply Word Low Signed, Modulo, Integer and Accumulate in Words evmwlsmianw Vector Multiply Word Low Signed, Modulo, Integer and Accumulate Negative in Word evmwlssf Vector Multiply Word Low Signed, Saturate, Fractional evmwlssfa Vector Multiply Word Low Signed, Saturate, Fractional, to Accumulator evmwlssfaaw Vector Multiply Word Low Signed, Saturate, Fractional and Accumulate in Words evmwlssfanw Vector Multiply Word Low Signed, Saturate, Fractional and Accumulate Negative in Words evmwlssiaaw Vector Multiply Word Low Signed, Saturate, Integer and Accumulate in Words evmwlssianw Vector Multiply Word Low Signed, Saturate, Integer and Accumulate Negative in Words evmwlumi Vector Multiply Word Low Unsigned, Modulo, Integer evmwlumia Vector Multiply Word Low Unsigned, Modulo, Integer, to Accumulator evmwlumiaaw Vector Multiply Word Low Unsigned, Modulo, Integer and Accumulate in Words evmwlumianw Vector Multiply Word Low Unsigned, Modulo, Integer and Accumulate Negative in Words evmwlusiaaw Vector Multiply Word Low Unsigned, Saturate, Integer and Accumulate in Words evmwlusianw Vector Multiply Word Low Unsigned, Saturate, Integer and Accumulate Negative in Words evmwsmf Vector Multiply Word Signed, Modulo, Fractional evmwsmfa Vector Multiply Word Signed, Modulo, Fractional, to Accumulator evmwsmfaa Vector Multiply Word Signed, Modulo, Fractional and Accumulate evmwsmfan Vector Multiply Word Signed, Modulo, Fractional and Accumulate Negative evmwsmi Vector Multiply Word Signed, Modulo, Integer evmwsmia Vector Multiply Word Signed, Modulo, Integer, to Accumulator evmwsmiaa Vector Multiply Word Signed, Modulo, Integer and Accumulate evmwsmian Vector Multiply Word Signed, Modulo, Integer and Accumulate Negative evmwssf Vector Multiply Word Signed, Saturate, Fractional evmwssfa Vector Multiply Word Signed, Saturate, Fractional, to Accumulator evmwssfaa Vector Multiply Word Signed, Saturate, Fractional and Accumulate evmwssfan Vector Multiply Word Signed, Saturate, Fractional and Accumulate Negative MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 3-23 Table 3-5. SPE Complex Integer Instructions (Continued) Instruction Description evmwumi Vector Multiply Word Unsigned, Modulo, Integer evmwumia Vector Multiply Word Unsigned, Modulo, Integer, to Accumulator evmwumiaa Vector Multiply Word Unsigned, Modulo, Integer and Accumulate evmwumian Vector Multiply Word Unsigned, Modulo, Integer and Accumulate Negative evsubfsmiaaw Vector Subtract Signed, Modulo, Integer to Accumulator Word evsubfssiaaw Vector Subtract Signed, Saturate, Integer to Accumulator Word evsubfumiaaw Vector Subtract Unsigned, Modulo, Integer to Accumulator Word evsubfusiaaw Vector Subtract Unsigned, Saturate, Integer to Accumulator Word 3.9.2 SPE APU Scalar and Vector Floating Point Instructions Support for a single precision floating point format is implemented in the SPE APU. The single precision format consists of a sign bit, an 8-bit exponent, and a 23-bit fraction. The floating point instructions can operate on both of the 32-bit fields in the 64-bit GPRs e.g. two pairs of single precision floating point numbers can be multiplied simultaneously. The supported floating point operations include: add, subtract, compare/test, multiply, and divide. The SPE unit in the e200 implements several instructions to facilitate converting between floating point and fixed point formats. Various fixed point formats are supported including signed and unsigned, integer and fractional formats. Table 3-6 briefly describes the SPE Scalar Floating Point and Conversion Instructions. Table 3-6. SPE Scalar Floating Point and Conversion Instructions Instruction Description efsabs Floating-Point Absolute Value efsadd Floating-Point Add efscfsf Convert Floating-Point from Signed Fraction efscfsi Convert Floating-Point from Signed Integer efscfuf Convert Floating-Point from Unsigned Fraction efscfui Convert Floating-Point from Unsigned Integer efscmpeq Floating-Point Compare Equal efscmpgt Floating-Point Compare Greater Than efscmplt Floating-Point Compare Less Than efsctsf Convert Floating-Point to Signed Fraction efsctsi Convert Floating-Point to Signed Integer efsctsiz Convert Floating-Point to Signed Integer with Round toward Zero efsctuf Convert Floating-Point to Unsigned Fraction MPC5533 Microcontroller Reference Manual, Rev. 0 3-24 Freescale Semiconductor Table 3-6. SPE Scalar Floating Point and Conversion Instructions (Continued) Instruction Description efsctui Convert Floating-Point to Unsigned Integer efsctuiz Convert Floating-Point to Unsigned Integer with Round toward Zero efsdiv Floating-Point Divide efsmul Floating-Point Multiply efsnabs Floating-Point Negative Absolute Value efsneg Floating-Point Negate efssub Floating-Point Subtract efststeq Floating-Point Test Equal efststgt Floating-Point Test Greater Than efststlt Floating-Point Test Less Than efsabs Floating-Point Absolute Value efsadd Floating-Point Add efscfsf Convert Floating-Point from Signed Fraction efscfsi Convert Floating-Point from Signed Integer efscfuf Convert Floating-Point from Unsigned Fraction efscfui Convert Floating-Point from Unsigned Integer efscmpeq Floating-Point Compare Equal Table 3-7 briefly describes the SPE Vector Floating Point and Conversion Instructions. Table 3-7. SPE Vector Floating Point and Conversion Instructions Instruction Description evfsabs Vector Floating-Point Absolute Value evfsadd Vector Floating-Point Add evfscfsf Vector Convert Floating-Point from Signed Fraction evfscfsi Vector Convert Floating-Point from Signed Integer evfscfuf Vector Convert Floating-Point from Unsigned Fraction evfscfui Vector Convert Floating-Point from Unsigned Integer evfscmpeq Vector Floating-Point Compare Equal evfscmpgt Vector Floating-Point Compare Greater Than evfscmplt Vector Floating-Point Compare Less Than evfsctsf Vector Convert Floating-Point to Signed Fraction evfsctsi Vector Convert Floating-Point to Signed Integer evfsctsiz Vector Convert Floating-Point to Signed Integer with Round toward Zero MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 3-25 Table 3-7. SPE Vector Floating Point and Conversion Instructions (Continued) Instruction 3.9.3 Description evfsctuf Vector Convert Floating-Point to Unsigned Fraction evfsctui Vector Convert Floating-Point to Unsigned Integer evfsctuiz Vector Convert Floating-Point to Unsigned Integer with Round toward Zero evfsdiv Vector Floating-Point Divide evfsmul Vector Floating-Point Multiply evfsnabs Vector Floating-Point Negative Absolute Value evfsneg Vector Floating-Point Negate evfssub Vector Floating-Point Subtract evfststeq Vector Floating-Point Test Equal evfststgt Vector Floating-Point Test Greater Than evfststlt Vector Floating-Point Test Less Than SPE APU Load and Store Instructions To effectively operate on the 64-bit register file, the SPE APU supports load and store instructions that handle up to 64 bits at the time. These 64 bits can be interpreted as two words or four half-words depending on the instruction as shown in Figure 3-7. Every Vector Load/Store instruction has an indexed and a non-indexed version. The mnemonic for the indexed version is appended with an ’x’ to indicate an indexed instruction. For example the indexed version of the evldd instruction is evlddx. Table 3-8 briefly describes the SPE Load and Store Instructions. Table 3-8. SPE Load and Store Instructions Instruction Description evldd Vector Load Double into Double evldh Vector Load Double into Halfwords evldw Vector Load Double into Words evlhhesplat Vector Load Halfword into Halfword Even and Splat evlhhossplat Vector Load Halfword into Halfword Odd Signed and Splat evlhhousplat Vector Load Halfword into Halfword Odd Unsigned and Splat evlwhe Vector Load Word into Halfwords Even evlwhos Vector Load Word into Halfwords Odd Signed (with sign extension) evlwhou Vector Load Word into Halfwords Odd Unsigned (zero-extended) evlwhsplat Vector Load Word into Halfwords and Splat evlwwsplat Vector Load Word into Word and Splat evstdd Vector Store Double of Double MPC5533 Microcontroller Reference Manual, Rev. 0 3-26 Freescale Semiconductor Table 3-8. SPE Load and Store Instructions (Continued) Instruction 3.10 Description evstdh Vector Store Double of Four Halfwords evstdw Vector Store Double of Two Words evstwhe Vector Store Word of Two Halfwords from Even evstwho Vector Store Word of Two Halfwords from Odd evstwwe Vector Store Word of Word from Even evstwwo Vector Store Word of Word from Odd Book E Instruction Extensions—VLE The variable length encoding (VLE) provides an extension to 32-bit PowerPC Book E. There are additional operations defined using an alternate instruction encoding to enable reduced code footprint. This alternate encoding set is selected on an instruction page basis. A single page attribute bit selects between standard PowerPC Book E instruction encodings and VLE instructions for that page of memory. This page attribute is an extension to the PowerPC Book E page attributes. Pages can be freely intermixed, allowing for a mixture of code using both types of encodings. Instruction encodings in pages marked as using the VLE extension are either 16 or 32 bits, and are aligned on 16-bit boundaries. Therefore, all instruction pages marked as VLE are required to use big-endian byte ordering. This section describes the various extensions to Book E instructions to support the VLE extension. rfci, rfdi, rfi—no longer mask bit 62 of CSRR0, DSRR0, or SRR0 respectively. The destination address is [D,C]SRR0[32:62] || 0b0. bclr, bclrl, bcctr, bcctrl—no longer mask bit 62 of the LR or CTR respectively. The destination address is [LR,CTR][32:62] || 0b0. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 3-27 MPC5533 Microcontroller Reference Manual, Rev. 0 3-28 Freescale Semiconductor Chapter 4 Reset 4.1 Introduction The following reset sources are supported in this device: • Power-on reset • External reset (324 package only) • Loss-of-lock reset • Loss-of-clock reset • Watchdog timer/debug reset • JTAG reset • Checkstop reset • Software system reset • Software external reset (324 package only) The reset status register (SIU_RSR) gives the source of the last reset and indicates whether a glitch occurred on the RESET pin. The SIU_RSR is updated for all reset sources. All reset sources are processed by the reset controller, which is located in the SIU module. The reset controller monitors the reset input sources and when a reset event is detected, resets the internal logic and controls the assertion of the RSTOUT pin. All reset sources invoke the boot assist module (BAM) program, except for the software external reset. You can assert the RSTOUT signal by setting the SER bit in the SIU_SRCR to 1. The PLL configuration determines the number of system clocks1 the RSTOUT signal is asserted. This does not reset the MCU. All other reset sources initiate an internal reset of the MCU. For more information, see Section 4.2.2, “Reset Output (RSTOUT)”. For all reset sources, use the BOOTCFG[0:1] signals to determine the boot mode and the PLLCFG[0:1] signals to determine the FMPLL configuration. If the RSTCFG pin is asserted during reset, the values on the BOOTCFG[0:1] pins are latched in the SIU_RSR four clock cycles before the RSTOUT pin deasserts, determining the boot mode. The values on the PLLCFG[0:1] pins are latched when the RSTOUT pin deasserts, determining the configuration of the FMPLL. If the RSTCFG pin deasserts during reset, the FMPLL defaults to normal operation (PLL enabled) with a crystal reference, and the boot mode (latched in the SIU_RSR) defaults to internal boot from flash. 1. Unless noted otherwise, the use of ‘clock’ or ‘clocks’ in this section is a reference to the system clock. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 4-1 208 Package: BOOTCFG[0] and RSTCFG signals are not available due to pin limitations and are internally asserted (driven to 0). Therefore, the BOOTCFG[1] and PLLCFG[0:1] pins are always sampled. The state of the BOOTCFG[0:1] pins specifies the location of the RCHW (internal flash or external memory), or that the MCU is configured to boot from a serial (eSCI) or FlexCAN port. See Chapter 2, “Signals” a complete description of the BOOTCFG[0:1]. The BAM program reads the values of the BOOTCFG[0:1] pins from the SIU_RSR, then reads the RCHW from the specified location and uses the RCHW value to determine and execute the specified boot procedure. See Section 4.4.3, “Reset Configuration and Configuration Pins,” for a complete description. The reset status register (SIU_RSR) gives the source of the last reset and indicates whether a glitch occurred on the RESET pin. The SIU_RSR is updated for all reset sources. The reset configuration half word (RCHW) provides several basic functions at reset: • Locates the boot code • Configures flash memory to either program or erase • Enables or disables the watchdog timer • Configures the MMU to boot: classic PowerPC Book E code or Freescale VLE code • Sets the bus size (external boot only) 208 Package: 4.2 4.2.1 BOOTCFG[0] is not available due to pin limitations and is internally asserted (driven to 0). External Signal Description Reset Input (RESET) Assert the RESET pin as an active low input by an external device during a power-on or external reset. The RESET pin must assert for at least 10 clock cycles to assert the internal reset signal. Assertion of the RESET pin while the device is in reset restarts the reset cycle. The RESET pin has a glitch detector to detect spikes more than two clocks in duration that fall below the switch point of the input buffer logic. 4.2.2 Reset Output (RSTOUT) The RSTOUT pin is an active low output that uses a push/pull configuration. The RSTOUT pin is driven to the low state by the MCU for all internal and external reset sources. After the RESET input deasserts, if the PLL is configured for 1:1 (dual controller) mode or bypass mode, the RSTOUT signal asserts for 16000 clocks, plus four clocks for sampling the configuration pins. If the PLL is configured for another operating mode, the RSTOUT signal asserts for 2400 clocks, plus four clocks for sampling of the configuration pins. See Section 11.1.4, “FMPLL Modes of Operation” for details of PLL configuration. Writing a one to the SER bit of the system reset control register (SIU_SRCR) asserts the RSTOUT pin. MPC5533 Microcontroller Reference Manual, Rev. 0 4-2 Freescale Semiconductor NOTE During a power on reset, RSTOUT is tri-stated. 4.2.3 Reset Configuration (RSTCFG) The RSTCFG input is used to enable the BOOTCFG[0:1] and PLLCFG[0:1] pins during reset. If RSTCFG deasserts during reset, the BOOTCFG and PLLCFG pins are not sampled when RSTOUT deasserts. In that case, the default values for BOOTCFG and PLLCFG are used. If RSTCFG asserts during reset, the values on the BOOTCFG and PLLCFG pins are sampled and used to configure the boot and FMPLL modes. 208 Package: 4.2.4 BOOTCFG[0] and RSTCFG signals are not available due to pin limitations and are internally asserted (driven to 0). Therefore, the BOOTCFG[1] and PLLCFG[0:1] pins are always sampled. Weak Pull Configuration (WKPCFG) WKPCFG determines whether specified eTPU pins are connected to a weak pullup or weak pulldown during and immediately after reset. 4.2.5 Boot Configuration (BOOTCFG[0:1]) BOOTCFG determines the function and state of the following pins after execution of the BAM reset: CS[0, 2:3], ADDR[8:31], DATA[0:15], RD_WR, BDIP, WE/BE[0:1], OE, TS, TA. 208 Package: 4.3 BOOTCFG[0] is not available due to pin limitations and is internally asserted (driven to 0). CS[1:3] are not available due to pin limitations in the 208 package. Memory Map/Register Definition Table 4-1 summarizes the reset controller registers. The base address of the system integration unit is 0xC3F9_0000. Table 4-1. Reset Controller Memory Map Address Register Name Register Description Bits Base (0xC3F9_0000) + 0x000C SIU_RSR Reset status register 32 Base (0xC3F9_0000) + 0x0010 SIU_SRCR System reset control register 32 MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 4-3 4.3.1 Register Descriptions This section describes all the reset controller registers. It includes details about the fields in each register, the number of bits per field, the reset value of the register, and the function of the register. 4.3.1.1 Reset Status Register (SIU_RSR) The reset status register (SIU_RSR) can be read at all times and contains a bit flag for each reset source, as well as the source of the last reset. A reset source bit flag set to 1 indicates that type of reset occurred. Simultaneous reset requests set more than one bit at the same time. Once set, the reset source bits in the SIU_RSR remain set until another reset occurs, except for a software external reset. A software external reset sets the SERF bit, but does not clear any previously set bits in the SIU_RSR. For additional information about the SIU_RSR, see Section 6.4.1.2, “Reset Status Register (SIU_RSR).” The SIU_RSR also contains the values latched at the last reset on the WKPCFG and BOOTCFG[0:1] pins and a RESET input pin glitch flag. The reset glitch flag (RGF) is cleared to 0 by writing a 1 to the bit. A write of 0 has no effect on the bit value. BOOTCFG[0] is not available due to pin limitations and is internally asserted (driven to 0). 208 Package: Address: Base + 0x000C 0 1 Access: User R/W 2 3 4 5 R PORS ERS LLRS LCRS WDRS CRS 6 7 8 9 10 11 12 13 0 0 0 0 0 0 0 0 14 15 SSRS SERF W w1c Reset1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R WKP CFG BOOTCFG W RGF w1c —2 Reset —3, 4 —3 0 1 The RESET values for this register are defined for power-on reset only. The RESET value of this bit or field is determined by the value latched on the associated pin or pins at the deassertion of the last reset. 3 The RESET value of this bit or field is determined by the value latched on the associated pin or pins at the deassertion of the last reset. On the 324 package, when RSTCFG is not asserted, a default value of 0b10 is loaded into BOOTCFG. 4 208 Package: BOOTCFG[0] is not available due to pin limitations and is internally asserted ((driven to 0). 2 Figure 4-1. Reset Status Register (SIU_RSR) MPC5533 Microcontroller Reference Manual, Rev. 0 4-4 Freescale Semiconductor Table 4-2. SIU_RSR Field Descriptions Field 0 PORS Description Power-on reset status 0 No power-on reset has occurred 1 A power-on reset has occurred 1 ERS External reset status 0 No external reset has occurred 1 An external reset has occurred The ERS bit is also set during a POR event 2 LLRS Loss-of-lock reset status 0 No loss-of-lock reset has occurred 1 A loss-of-lock reset has occurred 3 LCRS Loss-of-clock reset status 0 No loss-of-clock reset has occurred 1 A loss-of-clock reset has occurred due to a loss of the reference or failure of the FMPLL 4 WDRS Watchdog timer/debug reset status 0 No watchdog timer or debug reset has occurred 1 A watchdog timer or debug reset has occurred 5 CRS Checkstop reset status 0 No enabled checkstop reset has occurred 1 An enabled checkstop reset has occurred 6–13 Reserved 14 SSRS Software system reset status 0 No software system reset has occurred. 1 A software system reset has occurred. 15 SERF Software external reset flag. Write a 1 to clear this bit. 0 No software external reset has occurred 1 A software external reset has occurred 16 WKPCFG 17–28 Weak pull configuration pin status 0 WKPCFG pin latched during the last reset was logic 0 and weak pull down is the default setting 1 WKPCFG pin latched during the last reset was logic 1 and weak pull up is the default setting Reserved 29–30 Reset configuration pin status. Holds the value of the BOOTCFG[0:1] pins that was latched 4 clocks before BOOTCFG the last deassertion of the RSTOUT pin, if the RSTCFG pin was asserted. If the RSTCFG pin was deasserted at the last deassertion of RSTOUT, the BOOTCFG field is set to the value 0b00. The BOOTCFG field is used by the BAM program to determine the location of the reset configuration half word. See Section 4.4.3.5, “Reset Configuration Half Word (RCHW),” for a translation of the reset configuration half word location from the BOOTCFG field value. 208Package: BOOTCFG[0] and RSTCFG are not available due to pin limitations and are internally asserted (driven to 0) in the 208 package. Therefore, BOOTCFG[1] and PLLCFG[0:1] are always sampled. 31 RGF RESET glitch flag. Set by the MCU when the RESET pin is asserted for more than 2 clocks clock cycles, but less than the minimum RESET assertion time of 10 consecutive clocks to cause a reset. This bit is cleared by the reset controller for a valid assertion of the RESET pin or a power-on reset or a write of 1 to the bit. 0 No glitch was detected on the RESET pin 1 A glitch was detected on the RESET pin MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 4-5 4.3.1.2 System Reset Control Register (SIU_SRCR) The system reset control register (SIU_SRCR) allows software to generate either a software system reset or software external reset. The software system reset causes an internal reset sequence, while the software external reset only causes the external RSTOUT pin to be asserted. When written to 1, the SER bit automatically clears after a predetermined number of clock cycles (see Section 4.2.2, “Reset Output (RSTOUT)”). If the value of the SER bit is 1 and a 0 is written to the bit, the bit is cleared and the RSTOUT pin is deasserted regardless of whether the relevant number of clocks has expired. The CRE bit in the SIU_SRCR allows software to enable a checkstop reset. If enabled, a checkstop reset occurs if the checkstop reset input to the reset controller asserts. The checkstop reset is enabled by default. Address: Base + 0x0010 0 R 1 SSR SER W Reset 0 1 0 Access: User R/W 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 CRE 11 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 The CRE bit is reset to 1 by POR. Other resets sources do not reset the bit value. Figure 4-2. System Reset Control Register (SIU_SRCR) Table 4-3. SIU_SRCR Field Descriptions Field Description 0 SSR Software system reset. Writing a 1 to this bit causes an internal reset and assertion of the RSTOUT pin. The bit is automatically cleared by all reset sources except the software external reset. 0 Do not generate a software system reset 1 Generate a software system reset 1 SER Software external reset. Writing a 1 to this bit causes an software external reset. The RSTOUT pin is asserted for a predetermined number of clock cycles (see Section 4.2.2, “Reset Output (RSTOUT)”), but the MCU is not reset. The bit is automatically cleared when the software external reset completes. 0 Do not generate an software external reset 1 Generate an software external reset 2–15 Reserved 16 CRE Checkstop reset enable Writing a 1 to this bit enables a checkstop reset when the e200z3 core enters a checkstop state. The CRE bit defaults to checkstop reset enabled. This bit is reset at POR. 0 No reset occurs when the e200z3 core enters a checkstop state 1 A reset occurs when the e200z3 core enters a checkstop state 17–31 Reserved MPC5533 Microcontroller Reference Manual, Rev. 0 4-6 Freescale Semiconductor 4.4 4.4.1 Functional Description Reset Vector Locations The reset vector contains a pointer to the instruction where code execution begins after BAM execution. The location of the reset vector is determined by boot mode, as illustrated in Table 4-4. Table 4-4. Reset Vector Locations Boot Mode External Boot 0x0000_0004 (0x0000_0000 must have a valid RCHW) Internal Boot Next word address after the first valid RCHW found. The BAM searches the lowest address of each of the six low address space blocks in flash memory for a valid RCHW. Hence, the possible reset vector locations are: 0x0000_0004 0x0000_4004 0x0001_0004 0x0001_C004 0x0002_0004 0x0003_0004 Serial Boot 4.4.2 4.4.2.1 Reset Vector Location Specified over serial download Reset Sources FMPLL Lock A loss-of-lock of the FMPLL can cause a reset (provided the reset source is enabled by the FMPLL_SYNCR[LOLRE] bit). Regardless of the reset source, RESET remains asserted until the FMPLL locks. 4.4.2.2 Flash High Voltage There is no flash access gating signal implemented in this device. This device remains in RESET to guarantee that high voltage circuits are reset and stabilized and that flash memory is accessible. 4.4.2.3 Reset Source Descriptions For the following reset source descriptions see the reset flow diagrams in Figure 4-5 and Figure 4-6. Figure 4-5 shows the reset flow for assertion of the RESET pin. Figure 4-6 shows the internal processing of reset for all reset sources. 4.4.2.3.1 Power-on Reset The power-on reset (POR) circuit is designed to detect a POR event and ensure that the RESET signal is correctly sensed. Do not use the POR to detect falling power supply voltages. Ensure that the external power supply is monitored. The output signals from the power-on reset circuits are active low signals. All power-on reset output signals are combined into one POR signal at the VDD level and input to the reset controller. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 4-7 NOTE Even though asserting the power-on reset (POR) signal causes a reset, you must also assert the RESET pin at the same time to guarantee the MCU operates correctly. The PLLCFG[0:1] and RSTCFG pins determine the configuration of the FMPLL. • If RSTCFG is asserted when RSTOUT deasserts, the PLLCFG[0:1] pins set the operating mode of the FMPLL. • If RSTCFG is asserted anytime that RSTOUT is asserted, the FMPLL switches to the mode specified by the PLLCFG[0:1] pins. The values on the RSTCFG and the PLLCFG[0:1] pins must be kept constant once RSTCFG asserts to avoid transient mode changes in the FMPLL. If the reset configuration RSTCFG pin is in the deasserted state when RSTOUT deasserts, the FMPLL defaults to enabled with a crystal reference. See Chapter 11, “Frequency Modulated Phase Locked Loop and System Clocks (FMPLL),” for more details on the operation of the FMPLL and the PLLCFG[0:1] pins. The signal on the WKPCFG pin determines whether weak pullup or pulldown devices are enabled after reset on the eTPU pins. The WKPCFG pin is applied when the internal reset signal asserts, as indicated by the assertion of RSTOUT. See Figure 4-4 and Chapter 2, “Signals,” for more information on WKPCFG and RSTOUT. Once the RESET input pin deasserts, the reset controller checks if the FMPLL is locked. The internal reset signal and RSTOUT remain asserted until the FMPLL is locked. After the FMPLL is locked, the reset controller waits a predetermined number of clock cycles (See Section 4.2.2, “Reset Output (RSTOUT)”) before deasserting the RSTOUT pin. The WKPCFG and BOOTCFG[0:1] pins (the BOOTCFG[0:1] pins are sampled only if RSTCFG asserts) are sampled four clock cycles before RSTOUT deasserts, and the reset status register (SIU_RSR) fields are updated. The PORS and ERS bits are set, and all other reset status bits are cleared. 208 Package: 4.4.2.3.2 BOOTCFG[0] and RSTCFG are not available due to pin limitations, and are internally asserted (driven to 0). Therefore, BOOTCFG[1] and PLLCFG[0:1] are always sampled. External Reset The external reset feature is available on this device in the 324 package only, which has a 16-bit external bus interface. The 208 package does not have EBI pins, therefore the external reset feature is not supported. When the reset controller detects assertion of the RESET pin, the internal reset signal and RSTOUT are asserted. Starting at the assertion of the internal reset signal (as indicated by assertion of RSTOUT), the value on the WKPCFG pin is applied; at the same time the PLLCFG[0:1] values are applied if RSTCFG is asserted. Once the RESET pin is deasserted and the FMPLL loss-of-lock request signal is deasserted, the reset controller waits the predetermined number of clock cycles (see Section 4.2.2, “Reset Output (RSTOUT)”). MPC5533 Microcontroller Reference Manual, Rev. 0 4-8 Freescale Semiconductor Once the clock count completes, the WKPCFG and BOOTCFG[0:1] pins are sampled (BOOTCFG[0:1] are sampled only if RSTCFG is asserted). The reset controller then waits four clock cycles before the deasserting RSTOUT, and updates the fields in the SIU_RSR. In addition, the ERS bit is set, and all other reset status bits in the SIU_RSR are cleared. 208 Package: 4.4.2.3.3 There are no external bus interface (EBI) pins on this package. Loss-of-Lock Reset A loss-of-lock reset occurs when the FMPLL loses lock and the loss-of-lock reset enable (LOLRE) bit in the FMPLL synthesizer control register (FMPLL_SYNCR) is set. Beginning when the internal reset asserts, as indicated by the device reset signal (RSTOUT) asserting, the weak pull value is applied on the WKPCFG pin. At the same time, the PLLCFG[0:1] values are applied if RSTCFG is asserted. When the FMPLL locks, the reset controller waits until the predetermined clock count finishes and then the WKPCFG and BOOTCFG[0:1] pins are sampled (BOOTCFG[0:1] pins are only sampled if RSTCFG is asserted). The reset controller then waits four clock cycles before deasserting RSTOUT, and updating the Reset Status Register (SIU_RSR) fields. In addition, the LLRS bit is set, and all other reset status bits in the SIU_RSR are cleared. 208 Package: BOOTCFG[0] is not available due to pin limitations and is internally asserted (driven to 0). For more information, see: • Section 4.2.2, “Reset Output (RSTOUT)” • Chapter 11, “Frequency Modulated Phase Locked Loop and System Clocks (FMPLL)” 4.4.2.3.4 Loss-of-Clock Reset A loss-of-clock reset occurs when the FMPLL detects a failure in either the reference signal or FMPLL output, and the loss-of-clock reset enable (LOCRE) bit in the FMPLL_SYNCR is set. The internal reset signal is asserted (as indicated by assertion of RSTOUT). Starting at the assertion of the internal reset signal (as indicated by assertion of RSTOUT), the value on the WKPCFG pin is applied; at the same time the PLLCFG[0:1] values are applied if RSTCFG is asserted. Once the FMPLL has a clock and is locked, the reset controller waits the predetermined clock cycles (See Section 4.2.2, “Reset Output (RSTOUT)”) before deasserting RSTOUT. When the clock count finishes the WKPCFG and BOOTCFG[0:1] pins are sampled (BOOTCFG[0:1] pins are only sampled if RSTCFG is asserted). The reset controller then waits 4 clock cycles before the deasserting RSTOUT, and the associated bits/fields are updated in the SIU_RSR. In addition, the LCRS bit is set, and all other reset status bits in the SIU_RSR are cleared. See Section 11.4.2.6, “Loss-of-Clock Detection,” for more information on loss-of-clock. 208 Package: BOOTCFG[0] is not available due to pin limitations and is internally asserted (driven to 0). MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 4-9 4.4.2.3.5 Watchdog Timer/Debug Reset The WDRS bit in the reset status register (SIU_RSR) is set when the watchdog timer or a debug request reset occurs. A watchdog timer reset occurs and the WDRS bit is set when all the following conditions occur: • e200z3 core watchdog timer is enabled with the enable next watchdog timer (EWT) • Watchdog timer interrupt status (WIS) bits are set in the timer status register (TSR) • Watchdog reset control (WRC) field in the timer control register (TCR) is configured to reset • Time-out occurs The debug tool can issue a debug reset command by writing 2’b10 to the RST bit {DBCR0[2:3]} register in the e200z3 core, which sets the WDRS bit in the reset status register of the systems integration unit (SIU_RSR). To determine if WDRS was set by a watchdog timer or debug reset, check the WRS field in the e200z3 core TSR. The effect of a watchdog timer or debug reset request is the same on the reset controller. The debug tool can also reset the device using one of the following methods: • Debug tool asserts the RESET signal on the RESET_b pin • Debug tool sets the software system reset (SSR) bit in the system reset control register (SIU_SRCR) The debug tool writes a one to the software external reset (SER) bit in the system reset control register (SIU_SRCR) to generate an external software reset. The device comes out of reset using the following sequence: 1. Starting when the internal reset signal asserts, as indicated by RSTOUT asserting, the value on the WKPCFG pin is applied. At the same time, the PLLCFG[0:1] values are applied only if RSTCFG is asserted. 2. After the FMPLL is locked, the reset controller waits the predetermined number of clock cycles before negating RSTOUT. When the clock count finishes, WKPCFG and BOOTCFG[0:1] are sampled. BOOTCFG[0:1] is only sampled if RSTCFG asserts. 3. The reset controller then waits four clock cycles before the deasserting RSTOUT, and then updates the SIU_RSR. The WTRS bit is set and all other reset status bits in the SIU_RSR are cleared. See the e200z3 Core Guide for more information on the watchdog timer and debug operation. See Section 4.2.2, “Reset Output (RSTOUT).” 208 Package: BOOTCFG[0] is not available due to pin limitations and is internally asserted (driven to 0). MPC5533 Microcontroller Reference Manual, Rev. 0 4-10 Freescale Semiconductor 4.4.2.3.6 Checkstop Reset When the e200z3 core enters a checkstop state, and the checkstop reset is enabled (the CRE bit in the system reset control register (SIU_SRCR) is set), a checkstop reset occurs. Starting at the assertion of the internal reset signal (as indicated by assertion of RSTOUT), the value on the WKPCFG pin is applied; at the same time the PLLCFG[0:1] values are applied if RSTCFG is asserted. Once the FMPLL is locked, the reset controller waits a predetermined number of clock cycles (see Section 4.2.2, “Reset Output (RSTOUT)”) before deasserting RSTOUT.When the clock count finishes the WKPCFG and BOOTCFG[0:1] pins are sampled (the BOOTCFG[0:1] pins are only sampled if RSTCFG is asserted). The reset controller then waits four clock cycles before the deasserting RSTOUT, and the associated bits/fields are updated in the SIU_RSR. In addition, the CRS bit is set, and all other reset status bits in the SIU_RSR are cleared. See e200z3 Core Guide for more information. 208 Package: 4.4.2.3.7 BOOTCFG[0] is not available due to pin limitations and is internally asserted (driven to 0). JTAG Reset A system reset occurs when JTAG is enabled and either the EXTEST, CLAMP, or HIGHZ instructions are executed by the JTAG controller. When the internal reset signal asserts (indicated by RSTOUT asserting), the value on the WKPCFG pin is applied, and at the same time, the PLLCFG[0:1] values are applied (as long as RSTCFG is asserted). When the JTAG reset request deasserts and the FMPLL is locked, the reset controller waits a predetermined number of clock cycles before deasserting RSTOUT. When the clock count completes, the WKPCFG and BOOTCFG[0:1] pins are sampled (BOOTCFG[0:1] is sampled only if RSTCFG is asserted), and the fields in the SIU_RSR are updated. The reset source status bits in the SIU_RSR are unaffected. See Section 4.2.2, “Reset Output (RSTOUT) and Chapter 22, “IEEE 1149.1 Test Access Port Controller (JTAGC),” for more information. 208 Package: 4.4.2.3.8 BOOTCFG[0] is not available due to pin limitations and is internally asserted (driven to 0). Software System Reset A software system reset is caused by a write to the SSR bit in the system reset control register (SIU_SRCR). A write of 1 to the SSR bit causes an internal reset of the MCU. The value on the WKPCFG pin is applied when the internal reset signal asserts (indicated by RSTOUT asserting), and at the same time the PLLCFG[0:1] values are applied (as long as RSTCFG is asserted). Once the FMPLL locks, the reset controller waits a predetermined number of clock cycles before deasserting RSTOUT. When the clock count completes, the WKPCFG and BOOTCFG[0:1] pins are sampled (BOOTCFG[0:1] is sampled only if RSTCFG is asserted). The reset controller then waits four clock cycles before deasserting RSTOUT, and updates the fields in the SIU_RSR. In addition, the SSRS bit is set, and all other reset status bits in the SIU_RSR are cleared. See Section 4.2.2, “Reset Output (RSTOUT) for more information. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 4-11 208 Package: 4.4.2.3.9 BOOTCFG[0] is not available due to pin limitations and is internally asserted (driven to 0). Software External Reset A write of 1 to the SER bit in the SIU_SRCR causes the external RSTOUT pin to be asserted for a predetermined number of clocks (See Section 4.2.2, “Reset Output (RSTOUT)”). The SER bit automatically clears after the clock cycle expires. A software external reset does not cause a reset of the MCU, the BAM program is not executed, the PLLCFG[0:1], BOOTCFG[0:1], and WKPCFG pins are not sampled. The SERF bit in the SIU_RSR is set, but no other status bits are affected. The SERF bit in the SIU_RSR is not automatically cleared after the clock count expires, and remains set until cleared by software or another reset besides the software external reset occurs. For a software external reset, the e200z3 core continues to execute instructions, timers that are enabled continue to operate, and interrupt requests continue to be processed. It is the responsibility of the application to ensure devices connected to RSTOUT are not accessed during a software external reset, and to determine how to manage MCU resources. 208 Package: 4.4.3 BOOTCFG[0] is not available due to pin limitations and is internally asserted (driven to 0). Reset Configuration and Configuration Pins The microcontroller and the BAM perform a reset configuration that allows certain functions of the MCU to be controlled and configured at reset. This reset configuration is defined by: • Configuration pins • A reset configuration half word (RCHW), if present • Serial port, if a serial boot is used The following sections describe these configuration pins and the RCHW. 4.4.3.1 RSTCFG Pin Table 4-5 shows the RSTCFG pin settings for configuring the MCU to use a default or a custom configuration. See Chapter 2, “Signals” for more information about the RSTCFG pin. Table 4-5. RSTCFG Settings RSTCFG Description 1 Use default configuration of: – booting from internal flash – clock source is a crystal on FMPLL 0 Get configuration information from: – BOOTCFG[0:1] – PLLCFG[0:1] MPC5533 Microcontroller Reference Manual, Rev. 0 4-12 Freescale Semiconductor BOOTCFG[0] and RSTCFG are not available due to pin limitations, and are internally asserted (driven to 0). Therefore, BOOTCFG[1] and PLLCFG[0:1] are always sampled. 208 Package: 4.4.3.2 WKPCFG Pin (Reset Weak Pullup/Pulldown Configuration) As shown in Table 4-6, the signal on the WKPCFG pin determines whether specific eTPU pins are connected to weak pullup or weak pulldown devices during and after reset (see Chapter 2, “Signals,” for the eTPU pins that are affected by WKPCFG). For all reset sources except the software external reset, the WKPCFG pin is applied starting at the assertion of the internal reset signal (as indicated by the assertion of RSTOUT). If the WKPCFG signal is logic high at this time, pullup devices are enabled on the eTPU pins. If the WKPCFG signal is logic low at the assertion of the internal reset signal, pulldown devices are enabled on those pins. The value on WKPCFG must be held constant during reset to avoid oscillations on the eTPU pins caused by switching pullup and pulldown states. The final value of WKPCFG is latched four clock cycles before the deassertion of RSTOUT. After reset, software can modify the weak pullup and pulldown selections for all I/O pins through the PCRs in the SIU. Table 4-6. WKPCFG Settings WKPCFG Description 0 Weak pull down applied to eTPU pins at reset 1 Weak pull up applied to eTPU pins at reset Also see Chapter 2, “Signals” for information about the WKPCFG pin. 4.4.3.3 BOOTCFG[0:1] Pins (MCU Configuration) In addition to specifying the RCHW location, the values latched on the BOOTCFG[0:1] pins at reset are used to initialize the internal flash memory enabled/disabled state, and whether no arbitration or external arbitration of the external bus interface is selected. Additionally, the RCHW can determine either directly or indirectly how the MMU is configured, how the external bus is configured, CAN or eSCI module and pin configuration, Nexus enabling, and password selection. Also see Chapter 2, “Signals” for information about the BOOTCFG pins. 208 Package: 4.4.3.3.1 BOOTCFG[0] is not available due to pin limitations and is internally asserted (driven to 0). BOOTCFG[0:1] Configuration in the 208 Package In the 208 BGA package, the BOOTCFG[0] pin is unavailable and BOOTCFG[1] has a constant value based on PLLCFG[0]. The device configuration is mapped based on Table 4-7. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 4-13 Table 4-7. Boot Configuration in the 208 BGA PLLCFG0 BOOTCFG1 Boot Identifier Field (RCHW) Boot Mode Configuration Word Source Valid Internal The lowest address of one of the six low address spaces (LAS) in internal flash memory. Invalid Serial Not applicable — Serial Not applicable 0 0 1 Valid 0 Invalid 1 Valid 1 4.4.3.4 Invalid Reserved The lowest address (0x2000_0000) of an external memory device, enabled by chip select CS[0] using 16-bit data bus. Reserved Not applicable Reserved The lowest address (0x2000_0000) of an external memory device, enabled by chip select CS[0] using 16-bit data bus. Serial boot Not applicable PLLCFG[0:1] Pins The role of PLLCFG pins in PLL configuration is explained in Section 11.1.4, “FMPLL Modes of Operation.” Also see Chapter 2, “Signals” for information about the PLLCFG pins. Table 4-8. PLLCFG[0:1] and RSTCFG in Configuration RSTCFG PLLCFG[0] 1 4.4.3.5 4.4.3.5.1 PLLCFG[1] PLLCFG pins ignored Clock Mode MODE PLLSEL PLLREF Crystal reference (default) 1 1 1 0 0 0 Bypass mode 0 0 0 0 0 1 External reference 1 1 0 0 1 0 Crystal reference 1 1 1 0 1 1 Dual controller (1:1) mode 1 0 0 Reset Configuration Half Word (RCHW) Reset Configuration Half Word (RCHW) Definition The RCHW is read from either external memory or internal flash memory. If a valid RCHW is not found, a CAN/SCI boot is initiated. The RCHW is a collection of control bits that specify a minimum MCU configuration after reset and define the boot mode for the BAM program. At reset the RCHW provides a means to locate the boot code, determines if flash memory is programmed or erased, enables or disables the watchdog timer, configures the MMU to boot as either classic PowerPC Book E code or as Freescale VLE code, and if booting externally, sets the bus size. See the register indicated by the RCHW bit descriptions for a detailed description of each control bit. NOTE Do not configure the RCHW to a 32-bit bus size because the 324 package has a 16-bit data bus. The 208 package does not have an external bus. MPC5533 Microcontroller Reference Manual, Rev. 0 4-14 Freescale Semiconductor If booting from internal flash or external memory, you must ensure that the RCHW is configured for the correct value and memory address. The boot ID of the RCHW must be read as 0x005A. BOOT_BLOCK_ADDRESS is explained in Section 15.3.2.3.4, “Read the Reset Configuration Halfword.” The fields of the RCHW are shown in Figure 4-3. 0 1 2 3 4 5 6 WTE PS[0] 7 8 9 10 11 12 13 14 15 VLE 0 1 0 1 1 0 1 0 Boot Identifier = 0x005A BOOT_BLOCK_ADDRESS + 0x0000_0000 Figure 4-3. RCHW Fields Table 4-9. Internal Boot RCHW Field Descriptions Field Description 0–4 Reserved: These bit values are ignored when the halfword is read. Write to 0 for future compatibility. 5 WTE Watchdog timer enable. This is used to enable or disable the e200z3 watchdog timer through the BAM program. The configuration of the watchdog timer function is managed through the timer control register (TCR). 0 BAM does not write the e200z3 timebase registers (TBU and TBL) nor enable the e200z3 core watchdog timer. 1 BAM writes the e200z3 timebase registers (TBU and TBL) to 0x0000_0000_0000_0000 and enables the e200z3 core watchdog timer with a time-out period of 3 x 217 system clock cycles. (Example: For 8 MHz crystal −> 12MHz system clock−> 32.7mS time-out. For 20 MHz crystal −> 30 MHz system clock −> 13.1mS time-out) 6 PS [0] Port size. Defines the width of the data bus connected to the memory on CS[0]. After system reset, CS[0] is changed to a 16-bit port by the BAM which fetches the RCHW from either 16- or 32-bit external memories. Then the BAM reconfigures the EBI either as a 16-bit bus or a 32-bit bus, according to the settings of this bit. 0 Invalid value 1 16-bit CS[0] port size Note: Used only in external boot mode. Do not set the port to 32-bits because the 324 package only has a 16-bit data bus. 7 VLE VLE Code Indicator. This bit is used to configure the MMU for the boot block to execute as either Classic PowerPC Book E code or as Freescale VLE code. 0 = Boot code executes as Classic PowerPC Book E code 1 = Boot code executes as Freescale VLE code 8–15 BOOTID [0:7] Boot identifier. This field indicates which block in flash memory contains the boot program and identifies whether the flash memory is programmed or invalid. A valid boot identifier is 0x005A (0b01011010). The BAM program checks the first half word of each flash memory block starting at block 0 until a valid boot identifier is found. If all blocks in the low address space of the internal flash are checked and no valid boot identifier is found, boot code is initiated from a FlexCAN or eSCI port. 324 Package Only: For an external boot, only block 0 is checked for a valid boot identifier, and if not found, boot code is initiated from a FlexCAN or eSCI port. 4.4.3.5.2 Invalid Reset Configuration Half Word (RCHW) If the device is configured to boot from internal flash, a valid boot ID must be read at the lowest address of one of the six LAS blocks in internal flash memory. If the device is configured to boot from external MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 4-15 memory, a valid boot ID must be read at 0x00_0000 of CS[0]. See Chapter 15, “Boot Assist Module (BAM)” for more information. If a valid RCHW is not found, a serial boot is initiated which does not use a RCHW. The watchdog timer is enabled. For serial boot entered from a failed external boot, the port size remains configured as 16 bits wide. For serial boot entered from a failed internal boot, the external bus is never configured and remains in the reset state of GPIO inputs. 4.4.3.5.3 Reset Configuration Half Word (RCHW) Source The reset configuration half word (RCHW) specifies a minimal MCU configuration after reset. The RCHW also contains bits that control the BAM program flow. See Section 15.3.2.2.1, “Finding the Reset Configuration Halfword” for information on the BAM using the RCHW. The RCHW is read and applied each time the BAM program executes, which is for every power-on, external, or internal reset event. The only exception to this is the software external reset. See Section 4.4.3.5, “Reset Configuration Half Word (RCHW),” for detailed descriptions of the bits in the RCHW. The RCHW is read from one of the following locations: • The lowest address (0x0000_0000) of an external memory device, enabled by chip select CS[0] using a 16-bit data bus • The lowest address of one of the six low address space (LAS) blocks in the internal flash memory. (2 x 16 KB; 2 x 48 KB; 2 x 64 KB) At the deassertion of the RSTOUT pin, the BOOTCFG field in the RSR has been updated. If BOOTCFG[0] is asserted, then the BAM program reads the RCHW from address 0x0000_0000 in the external memory connected to CS[0] (the BAM first configures the MMU and CS[0] such that address 0x0000_0000 is translated to 0x2000_0000 and then directed to CS[0]). When BOOTCFG[0] is asserted, BOOTCFG[1] determines whether external arbitration must be enabled to fetch the RCHW. If BOOTCFG[0] and BOOTCFG[1] are deasserted at the deassertion of the RSTOUT pin, then the BAM program attempts to read the RCHW from the first address of each of the six blocks in the low address space (LAS) of internal flash. Table 4-10 shows the LAS addresses. Table 4-10. LAS Block Memory Addresses Block Address 0 0x0000_0000 1 0x0000_4000 2 0x0001_0000 3 0x0001_C000 4 0x0002_0000 5 0x0003_0000 If the RCHW stored in either internal or external flash is invalid (boot identifier field of RCHW is not 0x005A), or if BOOTCFG[0] is deasserted and BOOTCFG[1] is asserted at the deassertion of the RSTOUT pin, then RCHW is not applicable, and serial boot mode is performed. Table 4-11 summarizes the RCHW location options. MPC5533 Microcontroller Reference Manual, Rev. 0 4-16 Freescale Semiconductor BOOTCFG[0] is not available due to pin limitations and is internally asserted (driven to 0). 208 Package: Table 4-11. Reset Configuration Half Word Sources RSTCFG BOOTCFG[0] BOOTCFG[1] 1 — 0 Boot Mode Configuration Word Source Valid Internal The lowest address of one of the six low address spaces (LAS) in internal flash memory. Invalid Serial Valid Internal Invalid Serial Not applicable — Serial Not applicable — 0 0 Boot Identifier Field (RCHW) 0 0 1 Valid 0 1 0 Invalid 0 4.4.4 1 1 Not applicable The lowest address of one of the six low address spaces (LAS) in internal flash memory. External Boot, The lowest address (0x00_0000) of an external No Arbitration memory device, enabled by chip select CS[0] using either 16- or 32-bit data bus Serial Not applicable External Arbitration Not Supported Reset Configuration Timing The timing diagram in Figure 4-4 shows the sampling of the BOOTCFG[0:1], WKPCFG, and PLLCFG[0:1] pins for a power-on reset. The timing diagram is also valid for internal/external resets assuming that VDD, VDDSYN, and VDDEH6 are within valid operating ranges. The values of the PLLCFG[0:1] pins are latched at the deassertion of the RSTOUT pin, if the RSTCFG pin is asserted at the deassertion of RSTOUT. The value of the WKPCFG signal is applied at the assertion of the internal reset signal (as indicated by the assertion of RSTOUT). The values of the WKPCFG and BOOTCFG[0:1] pins are latched four clock cycles before the deassertion of RSTOUT and stored in the reset status register (SIU_RSR). BOOTCFG[0:1] are latched only if RSTCFG is asserted. WKPCFG is not dependent on RSTCFG. 208 Package: BOOTCFG[0] is not available due to pin limitations and is internally asserted (driven to 0). MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 4-17 VDD POR RESET 24001 clock cycles All reset signals deasserted (2404 cycles) (4 clock cycles) Internal Reset RSTOUT PLL Crystal powering up or acquiring lock PLL Locked RSTCFG User drives config pins relative to RSTOUT PLLCFG and RSTCFG are ‘Don’t Care’ and WKPCFG is treated as ‘1’ during POR assertion. 1 PLLCFG is latched. RSTCFG is no longer used. PLL Locks WKPCFG and BOOTCFG are latched. PLLCFG and RSTCFG still applied but not latched. PLLCFG, RSTCFG and WKPCFG are applied, but not latched. This clock count is dependent on the configuration of the FMPLL (See Section 4.2.2, “RSTOUT”). If the FMPLL is configured for 1:1 (dual controller) operation or for bypass mode, this clock count is 16000. Figure 4-4. Reset Configuration Timing MPC5533 Microcontroller Reference Manual, Rev. 0 4-18 Freescale Semiconductor 4.4.5 Reset Flow RESET Asserted ? False True Wait 2 Clock Cycles RESET Asserted ? False True Set Latch, Wait 8 Clock Cycles RESET Asserted ? False True A Set RGF Bit To Entry Point in Internal Reset Flow Figure 4-5. External Reset Flow Diagram MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 4-19 Software System Reset Asserted ? True False Internal Reset Asserted ? True False Assert Internal Resets & RSTOUT False Assert RSTOUT Apply WKPCFG Pin RSTCFG Asserted ? Software External Reset Asserted ? True A True Entry Point from External Reset Flow & POR PLLCFG Pins Applied, Not Latched Wait 24001 Clock Cycles Latch WKPCFG Pin False Default PLL Configuration Applied, Not Latched RSTCFG Asserted ? False True Reset Request Deasserted ? Latch BOOTCFG Values Latch Default Boot Configuration Wait 4 Clock Cycles Wait 4 Clock Cycles Latch PLLCFG Values Latch Default PLL Configuration False True Loss of Lock Deasserted ? True Wait 24001 Clock Cycles False Update Reset Status Register Deassert Internal Resets & RSTOUT NOTES: 1 The clock count is dependent on the configuration of the FMPLL (see Section 5.3.1.2, ‘RSTOUT’). If the FMPLL is configured in 1:1 (dual controller) or bypass mode, this clock count is 16000. Figure 4-6. Internal Reset Flow Diagram MPC5533 Microcontroller Reference Manual, Rev. 0 4-20 Freescale Semiconductor Chapter 5 Peripheral Bridge 5.1 Introduction 5.1.1 Block Diagram The PBRIDGE is the interface between the system bus and on-chip peripherals as shown in Figure 5-1. (PBRIDGE_A) (PBRIDGE_B) On-platform Slave Peripheral Bridge B Off-platform Slave Off-platform Slave Peripheral Bridge A System Bus On-platform Slave System Bus System Bus Crossbar Switch (XBAR) Figure 5-1. PBRIDGE Interface 5.1.2 Overview There are two peripheral bridges, PBRIDGE_A and PBRIDGE_B, which act as interfaces between the system bus and lower bandwidth peripherals. In this manual, PBRIDGE refers to either of these bridges, as their functionality is identical. The only difference is the peripherals to which they connect. Accesses that fall within the address space of the PBRIDGE are decoded to provide individual module selects for peripheral devices on the slave bus interface. 5.1.2.1 Access Protections The PBRIDGE provides programmable access protections for masters. It allows the privilege level of a master to be overridden, forcing it to user mode privilege, and allows masters to be designated as trusted or untrusted. More information on access protection can be found in Section 13.3.2.9, “Flash Bus Interface Unit Access Protection Register FLASH_BIUAPR.” MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 5-1 5.1.3 Features The following list summarizes the key features of the PBRIDGE: • Supports the slave interface signals, which is meant for slave peripherals only • Supports 32-bit slave peripherals (byte, halfword, and word reads and writes are supported to each) • Supports a pair of slave accesses for 64-bit instruction fetches • Provides configurable per-master access protections 5.1.4 Modes of Operation The PBRIDGE has only one operating mode. 5.2 External Signal Description The PBRIDGE has no external signals. 5.3 Memory Map and Register Definition The memory map for the program-visible PBRIDGE A and PBRIDGE B registers is shown in Table 5-1. Table 5-1. PBRIDGE A and B Memory Map Address Base1 + 0x0000 1 Register Name Register Description Bits PBRIDGE_x_MPCR Master privilege control register 32 PBRIDGE_A base is 0xC3F0_0000. PBRIDGE_B base is 0xFFF0_0000. 5.3.1 Register Descriptions All registers are 32-bit registers and can only be accessed in supervisor mode by trusted bus masters. Additionally, these registers must only be read from or written to by a 32-bit aligned access. PBRIDGE registers are mapped into the PBRIDGE_A and PBRIDGE_B address spaces. The protection and access fields of the MPCR are 4 bits in width. MPC5533 Microcontroller Reference Manual, Rev. 0 5-2 Freescale Semiconductor 5.3.1.1 Master Privilege Control Register (PBRIDGE_x_MPCR) Each master privilege control register (PBRIDGE_x_MPCR) specifies 4-bit access fields defining the access privilege level associated with a bus master in the platform, as well as specifying whether the write accesses from this master are buffered. The registers provide one field per bus master. Address: Base + 0x0000 0 1 Access: User R/W 2 3 4 Access Field 0 R MBW MTR MTW 0 0 0 W Reset 5 6 7 8 10 11 12 Access Field 2 Access Field 1 MPL MBW MTR MTW 0 1 1 1 9 MPL MBW MTR MTW 1 2 2 2 13 14 15 Access Field 3 MPL MBW MTR MTW 2 3 3 3 MPL 3 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Access Field 5 Access Field 4 Access Field 7 Access Field 6 R W Reset 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 Figure 5-2. Master Privilege Control Registers (PBRIDGE_x_MPCR) Table 5-2. PBRIDGE_x_MPCR Field Descriptions Field Description 0 MBW0 Master buffer writes. Determines whether the PBRIDGE is enabled to buffer writes from the CPU. Writes not able to be buffered by default. 0 Write accesses from the CPU cannot be buffered 1 Write accesses from the CPU can be buffered 1 MTR0 Master trusted for reads. Determines whether the CPU is trusted for read accesses. Trusted by default. 0 The CPU is not trusted for read accesses. 1 The CPU is trusted for read accesses. 2 MTW0 Master trusted for writes. Determines whether the master is trusted for write accesses. Trusted by default. 0 The CPU is not trusted for write accesses. 1 The CPU is trusted for write accesses. 3 MPL0 Master privilege level. Determines how the privilege level of the CPU is determined. Accesses not forced to user mode by default. 0 Accesses from the CPU are forced to user mode. 1 Accesses from the CPU are not forced to user mode. 4 MBW1 Master buffer writes. Determines whether the PBRIDGE is enabled to buffer writes from the Nexus. Writes not able to be buffered by default. 0 Write accesses from the Nexus cannot be buffered 1 Write accesses from the Nexus can be buffered 5 MTR1 Master trusted for reads. Determines whether the Nexus is trusted for read accesses. Trusted by default. 0 The Nexus is not trusted for read accesses. 1 The Nexus is trusted for read accesses. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 5-3 Table 5-2. PBRIDGE_x_MPCR Field Descriptions (Continued) Field Description 6 MTW1 Master trusted for writes. Determines whether the master is trusted for write accesses. Trusted by default. 0 The Nexus is not trusted for write accesses. 1 The Nexus is trusted for write accesses. 7 MPL1 Master privilege level. Determines how the privilege level of the Nexus is determined. Accesses not forced to user mode by default. 0 Accesses from the Nexus are forced to user mode. 1 Accesses from the Nexus are not forced to user mode. 8 MBW2 Master buffer writes. Determines whether the PBRIDGE is enabled to buffer writes from the eDMA. Writes not able to be buffered by default. 0 Write accesses from the eDMA cannot be buffered 1 Write accesses from the eDMA can be buffered 9 MTR2 Master trusted for reads. Determines whether the eDMA is trusted for read accesses. Trusted by default. 0 The eDMA is not trusted for read accesses. 1 The eDMA is trusted for read accesses. 10 MTW2 Master trusted for writes. Determines whether the master is trusted for write accesses. Trusted by default. 0 The eDMA is not trusted for write accesses. 1 The eDMA is trusted for write accesses. 11 MPL2 Master privilege level. Determines how the privilege level of the eDMA is determined. Accesses not forced to user mode by default. 0 Accesses from the eDMA are forced to user mode. 1 Accesses from the eDMA are not forced to user mode. 12 MBW3 Master buffer writes. Determines whether the PBRIDGE is enabled to buffer writes from the EBI. Writes not able to be buffered by default. 0 Write accesses from the EBI cannot be buffered 1 Write accesses from the EBI can be buffered 13 MTR3 Master trusted for reads. Determines whether the EBI is trusted for read accesses. Trusted by default. 0 The EBI is not trusted for read accesses. 1 The EBI is trusted for read accesses. 14 MTW3 Master trusted for writes. Determines whether the master is trusted for write accesses. Trusted by default. 0 The EBI is not trusted for write accesses. 1 The EBI is trusted for write accesses. 15 MPL3 Master privilege level. Determines how the privilege level of the EBI is determined. Accesses not forced to user mode by default. 0 Accesses from the EBI are forced to user mode. 1 Accesses from the EBI are not forced to user mode. 16–31 Reserved MPC5533 Microcontroller Reference Manual, Rev. 0 5-4 Freescale Semiconductor 5.4 Functional Description The PBRIDGE serves as an interface between a system bus and the peripheral (slave) bus. It functions as a protocol translator. Support is provided for generating a pair of 32-bit peripheral instruction accesses (not data accesses) when targeted by a 64-bit system bus access. No other bus-sizing access support is provided. Accesses that fall within the address space of the PBRIDGE are decoded to provide individual module selects for peripheral devices on the slave bus interface. 5.4.1 Peripheral Write Buffering NOTE This device only supports write buffering on a per-master basis, not on a per-peripheral basis. The PBRIDGE provides programmable write buffering capability to allow certain write accesses to be buffered in the PBRIDGE for later completion, while terminating the system bus access early. This provides improved performance in systems where frequent writes to a slow peripheral are performed. Enable write buffering for masters only if: • the slave bus does not generate termination errors • it is safe to ignore termination errors The PBRIDGE controller ignores the error signal on the termination of the buffered writes. When write buffering is enabled, all accesses through the PBRIDGE occur in-order; no bypassing of buffered writes is supported. Write buffering is controllable on a per-master basis. 5.4.1.1 Read Cycles Two-clock read accesses are possible with the PBRIDGE when the requested access size is 32-bits or smaller, and is not misaligned across a 32-bit boundary. If the requested instruction access size is 64-bits, or it is misaligned across a 32-bit boundary (not supported), then a minimum of three clocks are required to complete the access. Misaligned read accesses are not supported. 64-bit data reads (not instruction) are not supported. 5.4.1.2 Write Cycles Three clock write accesses are possible with the PBRIDGE when the requested access size is 32-bits or smaller. Misaligned writes that cross a 32-bit boundary are not supported. 64-bit data writes (not instruction) are not supported. 5.4.1.3 Buffered Write Cycles Single clock write responses to the system bus are possible with the PBRIDGE when the requested write access is bufferable. If the requested access does not violate the permissions check, and if the master is enabled for buffering writes, the PBRIDGE internally buffers the write cycle. The write cycle is terminated MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 5-5 early with zero system bus wait states. The access proceeds normally on the slave interface, but error responses are ignored. All accesses are initiated and completed in order on the slave interface, regardless of buffering. If the buffer is full, the following write cycle waits until it can either be buffered (if bufferable) or can be initiated. If the buffer has valid entries, the following read cycle waits until the buffer is emptied and the read cycle completes. 5.4.2 General Operation NOTE This device supports write buffering on a per-master basis only—not on a per-peripheral basis. Slave peripherals are modules that contain readable/writable control and status registers. The system bus master reads and writes these registers through the PBRIDGE. The PBRIDGE generates module enables, the module address, transfer attributes, byte enables, and write data as inputs to the slave peripherals. The PBRIDGE captures read data from the slave interface and drives it on the system bus. Separate interface ports are provided for on-platform and off-platform peripherals. The distinction between on-platform and off-platform is made to allow platform-based designs incorporating the PBRIDGE to separate the interface ports to allow for ease of timing closure. In addition, module selects and control register storage for on-platform peripherals are allocated at synthesis time, allowing only needed resources to be implemented. Off-platform module selects and control register storage do not have the same degree of configurability. The modules that are on-platform and those that are off-platform are detailed in Table 5-3. Table 5-3. On-Platform and Off-Platform Peripherals On-Platform Off-Platform Enhanced Direct Memory Access (eDMA) Deserial Serial Peripheral Interface (DSPI) PBridge A and B Enhanced Queued Analog-to-Digital Converter (eQADC) Interrupt Controller (INTC) Enhanced Serial Communication Interface (eSCI) Error Correction Status Module (ECSM) FlexCAN Controller Area Network System Bus Crossbar Switch (XBAR) Boot Assist Module (BAM) System Integration Unit (SIU) Frequency Modulated Phase Locked Loop (FMPLL) Enhanced Time Processing Unit (eTPU) External Bus Interface (EBI) Flash Bus Interface Unit (FBIU) The PBRIDGE occupies a 64 MB portion of the address space. A 0.5 MB portion of this space is allocated to on-platform peripherals. The remaining 63.5 MBs are available for off-platform devices. The register maps of the slave peripherals are located on 16-KB boundaries. Each slave peripheral is allocated one MPC5533 Microcontroller Reference Manual, Rev. 0 5-6 Freescale Semiconductor 16-KB block of the memory map, and is activated by one of the module enables from the PBRIDGE. Up to thirty-two 16-KB external slave peripherals can be implemented, occupying contiguous blocks of 16 KBs. Two global external slave module enables are available for the remaining 63 MBs of address space to allow for customization and expansion of addressed peripheral devices. In addition, a single non-global module enable is also asserted whenever any of the 32 non-global module enables is asserted. The PBRIDGE is responsible for indicating to slave peripherals if an access is in supervisor or user mode. The PBRIDGE also supports the notion of trusted masters for security purposes. Masters can be individually designated as trusted for reads, trusted for writes, or trusted for both reads and writes, as well as being forced to look as though all accesses from a master are in user mode privilege level. The PBRIDGE also supports buffered writes, allowing write accesses to be terminated on the system bus in a single clock cycle, and then subsequently performed on the slave interface. Write buffering is controllable on a per-peripheral basis. The PBRIDGE implements a two-entry 32-bit write buffer. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 5-7 MPC5533 Microcontroller Reference Manual, Rev. 0 5-8 Freescale Semiconductor Chapter 6 System Integration Unit (SIU) 6.1 Introduction This chapter describes the device system integration unit (SIU) that configures and initializes the following controls: • MCU reset configuration • System reset operation • Pad configuration • External interrupts (324 package only) • General-purpose I/O (GPIO) • Internal peripheral multiplexing MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 6-1 6.2 Block Diagram Figure 6-1 is a block diagram of the SIU. The signals shown on the right side of the diagram are external pins on the device. The SIU registers are accessed through the crossbar switch. Pad Configuration Power-on Reset Detection RESET Reset Controller RSTOUT 2 RSTCFG External IRQ/ Edge Detects SIU Registers .. . .. . IRQ[0:5, 7:15]1 1 Pad Interface/ Pad Ring Reset Configuration IRQ[6] is not available in this device. IRQ[2] is not available on the 208 package. BOOTCFG[0:1]_GPIO[211:212] 2 2 BOOTCFG[0] and RSTCFG are not available in the 208 package. These signals are internally asserted (driven to 0) in the 208 package. WKPCFG_GPIO[213] GPIO .. . .. . CS[0:3]_GPIO[0:3] 3 3 CS[1:3] are not available due to pin limitations on the 208 package. PLLCFG[0:1]_GPIO[208:209] . .. IRQ Inputs, DSPI Signals, and eQADC Triggers IMUX Peripheral I/O Channels Figure 6-1. SIU Block Diagram NOTE The power-on reset detection module, pad interface/pad ring module, and peripheral I/O channels shown shaded in Figure 6-1 are external to the SIU. MPC5533 Microcontroller Reference Manual, Rev. 0 6-2 Freescale Semiconductor 6.2.1 Overview The system integration unit (SIU) is accessed by the e200z3 core through the system bus crossbar switch (XBAR) and the peripheral bridge A (PBRIDGE_A). Table 6-1 lists the features the SIU configures: : Table 6-1. SIU Features Feature Description MCU reset operations Controls the external pin boot logic System reset operations Monitors internal and external reset sources, and drives the RSTOUT signal • Power-on reset support • Reset status register providing last reset source to software • Glitch detection on reset input • Software controlled reset assertion Pad configuration registers Enables the configuration and initialization of the I/O pin electrical characteristics using software to select the following: • Active function from the set of multiplexed functions • Pullup and pulldown characteristics of the pin • Slew rate for slow and medium pads • Open drain mode for output pins • Hysteresis for input pins • Drive strength of bus signals for fast pads External interrupt operations • 15 interrupt requests • Rising- or falling-edge event detection • Programmable digital filter for glitch rejection General-purpose I/O (GPIO) Provides uniform and discrete I/O control of 150 MCU general-purpose I/O pins, where each GPIO signal has an input register and an output register. The number of GPIO pins varies depending on the package. Internal peripheral multiplexing Provides flexibility to customize signal/pin assignments for application development that allows you to assign IRQs between external pins and the DSPI. 6.2.2 Modes of Operation The MPC5500 family of devices has several operating modes for configuring and testing the device: Table 6-2. SIU Operating Modes Operating Mode Description Normal In normal mode, the SIU provides the register interface and logic that controls the device and system configuration, the reset controller, and GPIO. The SIU continues operation with no changes in stop mode. Debug SIU operation in debug mode is identical to operation in normal mode. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 6-3 6.3 External Signal Description Table 6-3 lists the external pins used by the SIU. Table 6-3. SIU Signal Properties I/O Type Pad Type Pull Up/Down1 Reset Input Input — Up Reset Configuration Input — Up Output Slow — I/O Slow Up/Down Boot Configuration Input General-Purpose I/O Input I/O Slow Down Up/Down BOOTCFG[1]_ GPIO[212] Boot Configuration Input General-Purpose I/O Input I/O Slow Down Up/Down WKPCFG GPIO[213] Weak Pull Configuration Pin General-Purpose I/O Input I/O Slow Up Up/Down PLLCFG[0]_ GPIO[208] Boot Configuration Input General-Purpose I/O Input I/O Slow Down Up/Down PLLCFG[1]_ GPIO[209] Boot Configuration Input General-Purpose I/O Input I/O Slow Down Up/Down Slow —4 Name Function Resets RESET RSTCFG 2 RSTOUT Reset Output System Configuration GPIO[0:210] BOOTCFG[0]_ GPIO[211] General-Purpose I/O 2 External Interrupt (324 package only) IRQ[0:5, 7:15]3 External Interrupt Request Input Input 1 Internal weak pull up/down. The reset weak pull up/down state is given by the pull up/down state for the primary pin function. For example, the reset weak pull up/down state of the BOOTCFG[1]_GPIO[212] pin is weak pullup enabled. 2 RSTCFG and BOOTCFG[0] pins are not available on the 208 package. These signals are internally asserted (driven to 0) in the 208 package. 3 The GPIO and IRQ pins are multiplexed with other functions on the chip. The IRQ[6] function is not available in this device. Not all GPIO pins are available on all packages. See Chapter 2, “Signals” for a list of available IRQ and GPIO signals. 4 The weak pull up/down state at reset for the IRQ[0:5, 7:15] depends on the primary signals with which they are muxed. The weak pull up/down state for these pins is as follows: IRQ[0, 1, 4, 5, 7, 12, 13, 14]: Up, IRQ[2, 3, 15]: Down, IRQ[8:11]: WKPCFG. IRQ[2] is not available on the 208 package. MPC5533 Microcontroller Reference Manual, Rev. 0 6-4 Freescale Semiconductor 6.3.1 6.3.1.1 Detailed Signal Descriptions Reset Input (RESET) RESET is an active-low input signal asserted by an external device during a power-on reset (POR) or external reset. If RESET asserts for ten clock cycles only, the internal reset signal asserts. Asserting the RESET signal while the device is processing a reset restarts the reset process at the beginning. RESET has a glitch detector logic that senses electrical fluctuations on the VDDEH input pins that drop below the switch point value for more than two clock cycles. The switch point value is between the maximum VIL and minimum VIH specifications for the VDDEH input pins. 6.3.1.2 Reset Output (RSTOUT) RSTOUT is an active-low output signal that uses a push/pull configuration. It is driven to the low state by the MCU for all internal and external reset sources. After the RESET input signal deasserts, RSTOUT asserts for: • 16000 clock cycles for devices configured in bypass mode • 16004 clock cycles for devices configured for FMPLL dual-controller mode (1:1) • 2400 clock cycles for all other FMPLL modes To invoke an external software reset, write a 1 to the system external reset (SER) bit in the system reset control register (SIU_SRCR). This asserts RSTOUT for 2400 clock cycles. An external software reset does not execute the BAM module or sample BOOTCFG[0:1]. 208 Package: 6.3.1.3 BOOTCFG[0] is not available due to pin limitations and is internally asserted (driven to 0) in the 208 package. General-Purpose I/O Pins (GPIO[0:213]) 208 Package: Not all GPIO pins are available on all packages. See Chapter 2, “Signals” for more information on the GPIO pins available on this device. The GPIO pins provide general-purpose input and output function. The GPIO pins are generally multiplexed with other I/O pin functions. Each GPIO input and output is separately controlled by an eight-bit input (SIU_GPDI) or output (SIU_GPDO) register. NOTE Not all GPIO pins are available on all packages. See Chapter 2, “Signals” for a listing of available GPIO pins. For more information, see the following sections: Section 6.4.1.13, “GPIO Pin Data Output Registers 0–213 (SIU_GPDOn)” Section 6.4.1.14, “GPIO Pin Data Input Registers 0–213 (SIU_GPDIn)” MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 6-5 6.3.1.4 Boot Configuration Pins (BOOTCFG[0:1]) 208 Package: BOOTCFG[0] and RSTCFG are not available due to pin limitations and are internally asserted (driven to 0) in the 208 package. The BOOTCFG value specifies the location and boot mode used by the boot assist module (BAM). All reset sources can read the boot configuration field, BOOTCFG[0:1], except a debug port reset and a software external reset. The BOOTCFG values are read only if RSTCFG asserts while RSTOUT is asserted. The BOOTCFG signal asserts after RSTCFG to get the boot input information. BOOTCFG[0:1] is sampled four clock cycles before RSTOUT negates, and the latched boot values are stored in the reset status register (SIU_RSR). If RSTCFG asserts while processing a reset, BOOTCFG[0:1] is sampled. Otherwise, if RSTCFG negates while processing a reset, the following occurs: 1. BOOTCFG[0:1] is not sampled 2. BAM module boots from internal flash (default = 0b00) 3. Boot value from internal flash is written to BOOTCFG[0:1] field in the reset status register (SIU_RSR) 4. BOOTCFG[0:1] values are latched and driven as output signals from the SIU The BOOTCFG values are used only if RSTCFG asserts while RSTOUT is asserted. Otherwise, the default values for BOOTCFG (0b00) in the reset status register (SIU_RSR) is used, as shown in Table 6-4. Table 6-4. BOOTCFG[0:1] Configuration Value 6.3.1.5 Meaning 0b00 Boot from internal flash memory (default) 0b01 FlexCAN / eSCI boot 0b10 Boot from external memory (324 package only) 0b11 Invalid value I/O Pin Weak Pull Up Reset Configuration Pin (WKPCFG) The WKPCFG signal is applied when the internal reset signal asserts (indicated by RSTOUT asserting), and is sampled four clock cycles before RSTOUT negates. The WKPCFG value configures the internal weak pullup or weak pulldown pin characteristics after a reset occurs in the eTPU module. The value of WKPCFG is latched at reset, stored in the reset status register (SIU_RSR), and updated for all reset sources except the debug port reset and software external reset. The WKPCFG value must be valid and not change until RSTOUT negates. MPC5533 Microcontroller Reference Manual, Rev. 0 6-6 Freescale Semiconductor 6.3.1.6 External Interrupt Request Input Pins (IRQ[0:5, 7:15]) IRQ[0:5, 7:15] are the external interrupt request (IRQ) inputs connect to the SIU IRQ inputs. The external trigger IRQ select register 1 (SIU_ETISR) specifies the IRQ[0:5, 7:15] signals that are input to the SIU IRQs. NOTE IRQ[6] is not available in this device. 208 Package: IRQ[2] is not available in the 208 package due to pin limitations. External interrupt requests are triggered by rising- and/or falling-edge events that are enabled by setting a bit in: • IRQ rising-edge event enable register (SIU_IREER) • IRQ falling-edge event enable register (SIU_IFEER) If the bit is set in both registers, both rising- and falling-edge events trigger an interrupt request. Each IRQ has a counter that tracks the number of system clock cycles that occur between the rising- and falling-edge events. An IRQ counter exists for each IRQ rising- or falling-edge event enable bit. The digital filter length field in the IRQ digital filter register (SIU_IDFR) specifies the minimum number of system clocks that the IRQ signal must hold a logic value to qualify the edge-triggered event as a valid state change. When the number of system clocks in the IRQ counter equals the value in the digital filter length field, the IRQ state latches and the IRQ counter is cleared. If the previous filtered state of the IRQ does not match the current state, and the rising- or falling-edge event is enabled, the IRQ flag bit is set to 1. For example, the IRQ flag bit is set if a rising-edge event occurs under the following conditions: • Previous filtered IRQ state was a logic 0 • Current latched IRQ state is a logic 1 • Rising-edge event is enabled for the IRQ When the counter for an IRQ is not enabled, the state of the IRQ is held in the current and previous state latches. The IRQ counter operates independently of the IRQ or overrun flag bit. Clearing the IRQ flag or overrun flag bits does not clear or reload the counter. See the following sections for more information: Section 6.4.1.4, “External Interrupt Status Register (SIU_EISR)” Section 6.4.1.9, “IRQ Rising-Edge Event Enable Register (SIU_IREER)” Section 6.4.1.10, “IRQ Falling-Edge Event Enable Register (SIU_IFEER)” Section 6.4.1.11, “IRQ Digital Filter Register (SIU_IDFR)” Rising- or falling-edge events are enabled by setting the bits in SIU_IREER or SIU_IFEER. If the same bit location is set in both registers, both rising- and falling-edge events set the IRQ FLAG bit in Section 6.4.1.4, “External Interrupt Status Register (SIU_EISR).” MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 6-7 6.3.1.6.1 External Interrupts NOTE IRQ[6] is not available in this device. 208 Package: IRQ[2] is not available in the 208 package due to pin limitations. The IRQ signals map to 15 independent interrupt requests output from the SIU. The IRQ flag bit is set when a rising-edge and/or falling-edge event occurs for the IRQ. An external IRQ signal is asserted when all of the following occur: • Enable bit is set in the IRQ rising- and/or falling-edge event registers (SIU_IREER, SIU_IFEER) • IRQ flag bit is set in the external interrupt status register (SIU_EISR) • Enable bit is cleared in the DMA/Interrupt request enable register (SIU_DIRER) • Select bit is cleared in the DMA/Interrupt select register (SIU_DIRSR) See the following sections for more information: Section 6.4.1.5, “Interrupt Request Enable Register (SIU_DIRER)” Section 6.4.1.6, “DMA/Interrupt Request Select Register (SIU_DIRSR)” 6.3.1.6.2 DMA Transfers DMA IRQ signals (IRQ[0] through IRQ[3]) map to four independent DMA transfer or interrupt request outputs configured in the SIU. A DMA transfer or interrupt request asserts when all of the following occur: • IRQ flag bit is set in the external interrupt status register (SIU_EISR) • Enable bit is set in the DMA transfer or interrupt request enable register (SIU_DIRER) • Select bit is set in the DMA transfer or interrupt request select register (SIU_DIRSR) The SIU receives a ‘DMA transfer done’ signal for each DMA or interrupt request transmitted. When the ‘DMA done’ signal asserts, the IRQ flag bit is cleared. 208 Package: IRQ[2] is not available in the 208 package due to pin limitations. See the following sections for more information: Section 6.4.1.5, “Interrupt Request Enable Register (SIU_DIRER)” Section 6.4.1.6, “DMA/Interrupt Request Select Register (SIU_DIRSR)” 6.3.1.6.3 Overruns An overrun IRQ exists for each overrun flag bit in the overrun status register (SIU_OSR). An overrun IRQ asserts when all of the following occur: • Enable bit is set in the IRQ rising- and/or falling-edge event registers (SIU_IREER, SIU_IFEER) • IRQ flag bit is set in the external interrupt status register (SIU_EISR) • Bit is set in the overrun request enable and overrun status registers (SIU_ORER, SIU_OSR) • Rising- or falling-edge event triggers an interrupt request The SIU outputs one overrun IRQ bit that is the logical OR of all of the IRQ overrun bits. MPC5533 Microcontroller Reference Manual, Rev. 0 6-8 Freescale Semiconductor NOTE IRQ[6] is not available in this device. IRQ[2] is not available in the 208 package due to pin limitations. 208 Package: See the following sections for more information: Section 6.4.1.4, “External Interrupt Status Register (SIU_EISR)” Section 6.4.1.7, “Overrun Status Register (SIU_OSR)” Section 6.4.1.8, “Overrun Request Enable Register (SIU_ORER)” 6.3.1.6.4 Edge Detects An IRQ asserts when an: • Edge-detect event is enabled • Edge-detect event occurs To assert an IRQ when an edge-detect event occurs: 1. Set the enable bit in the IRQ rising- and falling-edge event enable registers (SIU_IREER, SIU_IFEER) 2. Clear the enable bits for the DMA/Interrupt request enable register (SIU_DIRER) The IRQ bit is set in the external IRQ status register (SIU_EISR) when an edge-detect event occurs for that IRQ. NOTE IRQ[6] is not available in this device. 208 Package: IRQ[2] is not available in the 208 package due to pin limitations. See the following sections for more information: Section 6.4.1.4, “External Interrupt Status Register (SIU_EISR)” Section 6.4.1.9, “IRQ Rising-Edge Event Enable Register (SIU_IREER)” Section 6.4.1.10, “IRQ Falling-Edge Event Enable Register (SIU_IFEER)” 6.4 Memory Map and Register Definition Table 6-5 is the address map for the SIU registers. All register addresses are given as an offset of the SIU base address. Table 6-5. SIU Address Map Address Base (0xC3F9_0000) Base + 0x0004 Register Name — SIU_MIDR Base + 0x0008 — Base + 0x000C SIU_RSR Register Description Bits Reserved — MCU ID register 32 Reserved — Reset status register 32 MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 6-9 Table 6-5. SIU Address Map (Continued) Address Register Name Register Description Base + 0x0010 SIU_SRCR System reset control register 32 Base + 0x0014 SIU_EISR SIU external interrupt status register 32 Base + 0x0018 SIU_DIRER DMA/interrupt request enable register 32 Base + 0x001C SIU_DIRSR DMA/interrupt request select register 32 Base + 0x0020 SIU_OSR Overrun status register 32 Base + 0x0024 SIU_ORER Overrun request enable register 32 Base + 0x0028 SIU_IREER IRQ rising-edge event enable register 32 Base + 0x002C SIU_IFEER IRQ falling-edge event enable register 32 Base + 0x0030 SIU_IDFR IRQ digital filter register 32 Reserved — Pad configuration registers 0–342 1 16 Reserved — Base + (0x0034–0x003F) Base + (0x0040–0x02EC) Base + (0x02F0–0x005F) Base + (0x0600–0x06D4) Base + (0x06D8–0x07FF) Base + (0x0800–0x08D4) Base + (0x08D8–0x08FF) — SIU_PCR0– SIU_PCR342 — SIU_GPDO0– SIU_GPDO213 — SIU_GPDI0– SIU_GPDI213 — GPIO pin data output registers Bits 0–2132 8 Reserved — GPIO pin data input registers 0–2132 8 Reserved — Base + 0x0900 SIU_ETISR eQADC trigger input select register 32 Base + 0x0904 SIU_EISR External IRQ input select register 32 Base + 0x0908 SIU_DISR DSPI input select register 32 Reserved — Base + (0x090C–0x097) — Base + 0x0980 SIU_CCR Chip configuration register 32 Base + 0x0984 SIU_ECCR External clock control register 32 Base + 0x0988 SIU_CARH Compare A high register 32 Base + 0x098C SIU_CARL Compare A low register 32 Base + 0x0990 SIU_CBRH Compare B high register 32 Base + 0x0994 SIU_CBRL Compare B low register 32 Reserved — Base + (0x0998–0x09FF) 1 2 — Gaps exist in the pad configuration where I/O pins are not available in this package. Gaps exist in this memory space where I/O pins are not available in this package. MPC5533 Microcontroller Reference Manual, Rev. 0 6-10 Freescale Semiconductor 6.4.1 Register Descriptions The register figures use the following notational conventions in this section: w1c Write 1 to clear the bit to 0. — Not applicable. Reserved or unimplemented bit. U Bit value is uninitialized upon reset. u Bit value is unchanged upon reset. 6.4.1.1 MCU ID Register (SIU_MIDR) The SIU_MIDR contains the part identification number and mask revision number specific to the device. The part number is a read-only field that is mask programmed with the part number of the device. The part number is changed if a new module is added to the device or a memory size is changed, for example. It is not changed for bug fixes or process changes. The mask number is a read-only field that is mask programmed with the specific mask revision level of the device. The MCU ID register is 32-bits. Figure 6-2 shows the MCU ID register values. Address: Base + 0x0004 0 1 Access: Read 2 3 4 5 6 R 7 8 9 10 11 12 13 14 15 PARTNUM W Reset R 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MASKNUM_MAJOR MASKNUM_MINOR W Reset 0 0 0 0 0 0 0 0 Figure 6-2. MCU ID Register (SIU_MIDR) Table 6-6. SIU_MIDR Field Descriptions Field Description 0–15 PARTNUM [0:15] MCU part number. Read-only, mask programmed part identification number of the MCU. Reads 0x5533 for the MPC5533. 16–23 Reserved MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 6-11 Table 6-6. SIU_MIDR Field Descriptions (Continued) Field Description 24–27 MASKNUM_MAJOR [0:3] Major revision number of MCU mask. Read-only, mask programmed mask number of the MCU. Reads 0x0000 for the initial mask set, and changes sequentially for each mask set. 28–31 MASKNUM_MINOR [0:3] Minor revision number of MCU mask. Read-only, mask programmed mask number of the MCU. Reads 0x0000 for the initial mask set, and changes sequentially for each mask set. 6.4.1.2 Reset Status Register (SIU_RSR) The SIU_RSR reflects the most recent source, or sources of reset, and the state of configuration pins at reset. This register contains one bit for each reset source, indicating that the last reset was power-on reset (POR), external, software system, software external reset, watchdog, loss of PLL lock, loss of clock or checkstop reset. A reset status bit set to logic one indicates the type of reset that occurred. Once set, the reset source status bits in the SIU_RSR remain set until another reset occurs. In the following cases more than one reset bit is set: • If a power-on reset request has negated and the device is still in the resulting reset, and then an external reset is requested, both the power-on and external reset status bits are set. In this case, the device started the reset sequence due to a power-on reset request, but it ended the reset sequence after an external reset request. • If a software external reset is requested, the SERF flag bit is set, but no previously set bits in the SIU_RSR are cleared. The SERF bit is cleared by writing a 1 to the bit location or when another reset source is asserted. • If any of the loss of clock, loss of lock, watchdog or checkstop reset requests occur on the same clock cycle, and no other higher priority reset source is requesting reset (see Table 6-7), the reset status bits for all of the requesting resets are set. Simultaneous reset requests are prioritized. When reset requests of different priorities occur on the same clock cycle, the lower priority reset request is ignored. Only the highest priority reset request's status bit is set. Except for a power-on reset request and condition above, all reset requests of any priority are ignored until the device exits reset. Table 6-7. Reset Source Priorities Reset Source Priority Power on reset (POR) and external reset (Group 0) Highest Software system reset (Group1) Lowest-high Loss of clock, loss of lock, watchdog, checkstop (Group2) Highest-low Software external reset (Group 3) Lowest MPC5533 Microcontroller Reference Manual, Rev. 0 6-12 Freescale Semiconductor Address: Base + 0x000C 0 1 R PORS ERS Access: R/W 2 3 4 5 LLRS LCRS WDRS CRS 6 7 8 9 10 11 12 13 0 0 0 0 0 0 0 0 14 15 SSRS SERF W W1c Reset1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 0 0 0 0 0 0 0 0 0 0 0 R WKP CFG2 BOOTCFG W RGF W1c 1 Reset U 2 3 U 0 1 The reset status register receives its reset values during power-on reset. The reset value of the WKPCFG bit is determined by the value on the WKPCFG pin at reset. 3 The reset value of the BOOTCFG field is determined by the values on the BOOTCFG[0:1] pins at reset. BOOTCFG[0] is not available due to pin limitations, and is internally asserted (driven to 0) in the 208 package. 2 Figure 6-3. Reset Status Register (SIU_RSR) Table 6-8. SIU_RSR Field Descriptions Field 0 PORS Description Power-on reset status. 0 Another reset source has been acknowledged by the reset controller since the last assertion of the power-on reset input. 1 The power-on reset input to the reset controller has been asserted and no other reset source has been acknowledged since that assertion of the power-on reset input except an external reset. 1 ERS External reset status. 0 The last reset source acknowledged by the reset controller was not a valid assertion of the RESET pin. 1 The last reset source acknowledged by the reset controller was a valid assertion of the RESET pin. 2 LLRS Loss of lock reset status. 0 The last reset source acknowledged by the reset controller was not a loss of PLL lock reset. 1 The last reset source acknowledged by the reset controller was a loss of PLL lock reset. 3 LCRS Loss of clock reset status. 0 The last reset source acknowledged by the reset controller was not a loss of clock reset. 1 The last reset source acknowledged by the reset controller was a loss of clock reset. 4 WDRS Watchdog timer/debug reset status. 0 The last reset source acknowledged by the reset controller was not a watchdog timer or debug reset. 1 The last reset source acknowledged by the reset controller was a watchdog timer or debug reset. 5 CRS Checkstop reset status. 0 The last reset source acknowledged by the reset controller was not an enabled checkstop reset. 1 The last reset source acknowledged by the reset controller was an enabled checkstop reset. 6–13 Reserved 14 SSRS Software system reset status. 0 The last reset source acknowledged by the reset controller was not a software system reset. 1 The last reset source acknowledged by the reset controller was a software system reset. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 6-13 Table 6-8. SIU_RSR Field Descriptions (Continued) Field Description 15 SERF Software external reset flag. 0 This bit has been cleared from a 1 to a 0 by a write of 1 to it when it was a 1 or the software external reset input to the reset controller has not been asserted. 1 The software external reset input to the reset controller has been asserted while this bit was a 0. 16 Weak pull configuration pin status WKPCFG 0 The WKPCFG pin latched during the last reset was a logical 0 and weak pull down is the default setting 1 The WKPCFG pin latched during the last reset was a logical 1 and weak pullup is the default setting 17–28 Reserved 29–30 Reset configuration pin status. Holds the value of the BOOTCFG pins that were latched on the last negation of the BOOTCFG RSTOUT pin, if the RSTCFG pin was asserted. If the RSTCFG pin was not asserted at the last negation of RSTOUT, and the lower half or least significant half word of the censorship control word equals 0xFFFF or 0x0000, the BOOTCFG field is set to the value 0b10. Otherwise, if the RSTCFG pin was negated at the last negation of RSTOUT and the lower half of the censorship control word does not equal 0xFFFF or 0x0000, then the BOOTCFG field is set to the value 0b00. The BOOTCFG field is used by the BAM program to determine the location of the reset configuration half word. See Table 4-11 for a translation of the reset configuration half word location from the BOOTCFG field value. NOTE: BOOTCFG[0] is not available due to pin limitations and is internally asserted (drive to 0) in the 208 package. Reset glitch flag. Set by the reset controller when a glitch is detected on the RESET pin. This bit is cleared by the assertion of the power-on reset input to the reset controller, or a write of 1 to the RGF bit. See Section 6.5.2.1, “RESET Pin Glitch Detect,” for more information on glitch detection. 0 No glitch has been detected on the RESET pin. 1 A glitch has been detected on the RESET pin. 31 RGF 6.4.1.3 System Reset Control Register (SIU_SRCR) The system reset control register allows software to generate either a system or external reset. The software system reset causes an internal reset, while the software external reset only causes the external RSTOUT pin to be asserted. When written to 1, the SER bit automatically clears. Address: Base + 0x0010 0 R 0 W SSR 2 Reset 1 SER 1 Access: R/W 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w1c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R CRE W Reset 13 Figure 6-4. System Reset Control Register (SIU_SRCR) 1 Write 1 to the SER bit to generate a software external reset. A write of 0 to this bit has no effect. When the reset completes, the SER bit is cleared to 0. 2 The SSR bit always reads 0. A write of 0 to this bit has no effect. MPC5533 Microcontroller Reference Manual, Rev. 0 6-14 Freescale Semiconductor 3 The CRE bit is set to 1 by POR. Other reset sources cannot set the CRE bit. Table 6-9. SIU_SRCR Field Descriptions Field Description 0 SSR Software system reset. Used to generate a software system reset. Writing a 1 to this bit causes an internal reset. The software system reset is processed as a synchronous reset. The bit is automatically cleared on the assertion of any other reset source except a software external reset. 0 Do not generate a software system reset. 1 Generate a software system reset. 1 SER Software external reset. Used to generate a software external reset. Writing a 1 to this bit causes the RSTOUT pin to be asserted for 2400 clocks, but the internal reset is not asserted. The bit is automatically cleared when the software external reset completes or any other reset source is asserted. Once a software external reset has been initiated, the RSTOUT pin is negated if this bit is cleared before the 2400 clock period expires. 0 Do not generate a software external reset. 1 Generate a software external reset. Note: If the PLL is configured for dual controller mode writing a 1 to SER causes the RSTOUT pin to be asserted for 16000 clocks. See Section 4.2.2, “Reset Output (RSTOUT).” 2–15 Reserved 16 CRE Checkstop reset enable. Writing a 1 to this bit enables a reset when the checkstop reset request input is asserted. The checkstop reset request input is a synchronous internal reset source. The CRE bit defaults to checkstop reset enabled at POR. If this bit is cleared, it remains cleared until the next POR. 0 No reset occurs when the checkstop reset input to the reset controller is asserted. 1 A reset occurs when the checkstop reset input to the reset controller is asserted. 17–31 6.4.1.4 Reserved External Interrupt Status Register (SIU_EISR) The external interrupt status register is used to record edge triggered events on the IRQ[0:5, 7:15] inputs to the SIU. When an edge triggered event is enabled in the SIU_IREER or SIU_IFEER for an IRQ[n] input and then sensed, the corresponding SIU_EISR flag bit is set. The IRQ flag bit is set regardless of the state of the DMA or interrupt request enable bit in SIU_DIRER. The IRQ flag bit remains set until cleared by software or through the servicing of a DMA request. The IRQ flag bits are cleared by writing a 1 to the bits. A write of 0 has no effect. NOTE IRQ[6] is not available in this device. 208 Package: IRQ[2] is not available in the 208 package due to pin limitations. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 6-15 Address: Base + 0x0014 Access: R/W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R EIF15 EIF14 EIF13 EIF12 EIF11 EIF10 EIF9 EIF8 EIF7 EIF6 EIF5 EIF4 EIF3 EIF2 EIF1 EIF0 W w1c R W Reset Reset w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 6-5. SIU External Interrupt Status Register (SIU_EISR) Table 6-10. SIU_EISR Field Descriptions Field Description 0–15 Reserved 16–31 EIFn External interrupt request flag n. This bit is set when an edge triggered event occurs on the corresponding IRQn input. 0 No edge triggered event has occurred on the corresponding IRQ[n] input. 1 An edge triggered event has occurred on the corresponding IRQ[n] input. 6.4.1.5 Interrupt Request Enable Register (SIU_DIRER) The SIU_DIRER allows the assertion of an interrupt request if the corresponding flag bit is set in the SIU_EISR. The external interrupt request enable bits enable the interrupt requests. There is only one interrupt request from the SIU to the interrupt controller. The EIRE bits determine which external interrupt request flag bits assert the interrupt request signal. NOTE IRQ[6] is not available in this device. 208 Package: IRQ[2] is not available in the 208 package due to pin limitations. MPC5533 Microcontroller Reference Manual, Rev. 0 6-16 Freescale Semiconductor Address: Base + 0x0018 R Access: R/W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 W Reset R EIRE EIRE EIRE EIRE EIRE EIRE EIRE EIRE EIRE EIRE EIRE EIRE EIRE EIRE EIRE EIRE 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 W 15 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 6-6. SIU DMA/Interrupt Request Enable Register (SIU_DIRER) Table 6-11. SIU_DIRER Field Descriptions Field 0–15 16–31 EIREn Description Reserved External interrupt request enable n. Enables the assertion of the interrupt request from the SIU to the interrupt controller when an edge triggered event occurs on the IRQn pin. 0 External interrupt request is disabled. 1 External interrupt request is enabled. 6.4.1.6 DMA/Interrupt Request Select Register (SIU_DIRSR) The SIU_DIRSR allows the selection of a DMA or interrupt request for events on the IRQ[0:3] inputs. Depending on the bits set in the external interrupt status register (SIU_EISR) and the interrupt request enable register (SIU_DIRER), the DMA/interrupt request select bit determines whether a DMA or an interrupt request is asserted. IRQ[2] is not available in the 208 package due to pin limitations. 208 Package: Address: Base + 0x001C R Access: R/W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset R W Reset DIRS DIRS DIRS DIRS 3 2 1 0 0 0 0 0 Figure 6-7. DMA/Interrupt Request Select Register (SIU_DIRSR) MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 6-17 Table 6-12. SIU_DIRSR Field Descriptions Field Description 0–27 Reserved 28–31 DIRSn DMA/interrupt request select n. Selects between a DMA or interrupt request when an edge triggered event occurs on the corresponding IRQn pin. 0 Interrupt request is selected. 1 DMA request is selected. 6.4.1.7 Overrun Status Register (SIU_OSR) The SIU_OSR contains flag bits that record an overrun. NOTE IRQ[6] is not available in this device. IRQ[2] is not available in the 208 package due to pin limitations. 208 Package: Address: Base + 0x0020 R Access: R/W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 OVF 14 OVF 13 OVF 12 OVF 11 OVF 10 OVF 9 OVF 8 OVF 7 OVF 6 OVF 5 OVF 4 OVF 3 OVF 2 OVF 1 OVF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset R OVF W 15 Reset 0 Figure 6-8. Overrun Status Register (SIU_OSR) Table 6-13. SIU_OSR Field Descriptions Field Function 0–15 Reserved 16–31 OVFn Overrun flag n. This bit is set when an overrun occurs on the corresponding IRQn pin. 0 No overrun has occurred on the corresponding IRQn pin. 1 An overrun has occurred on the corresponding IRQn pin. MPC5533 Microcontroller Reference Manual, Rev. 0 6-18 Freescale Semiconductor 6.4.1.8 Overrun Request Enable Register (SIU_ORER) The SIU_ORER contains bits to enable an overrun if the corresponding flag bit is set in the SIU_OSR. If any overrun request enable bit and the corresponding flag bit are set, the single combined overrun request from the SIU to the interrupt controller is asserted. NOTE IRQ[6] is not available in this device. IRQ[2] is not available in the 208 package due to pin limitations. 208 Package: Address: Base + 0x0024 R Access: R/W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 ORE 14 ORE 13 ORE 12 ORE 11 ORE 10 ORE 9 ORE 8 ORE 7 ORE 6 ORE 5 ORE 4 ORE 3 ORE 2 ORE 1 ORE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset R ORE W 15 Reset 0 Figure 6-9. Overrun Request Enable Register (SIU_ORER) Table 6-14. SIU_ORER Field Descriptions Field Function 0–15 Reserved 16–31 OREn Overrun request enable n. Enables the overrun request when an overrun occurs on the IRQ[n] pin. Bit 31 (ORE0) is the enable overrun flag for IRQ[0]; bit 16 (ORE15) is overrun flag for IRQ[15]. 0 Overrun request is disabled. 1 Overrun request is enabled. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 6-19 6.4.1.9 IRQ Rising-Edge Event Enable Register (SIU_IREER) The SIU_IREER allows rising edge triggered events to be enabled on the corresponding IRQ[n] pins. Rising and falling edge events can be enabled by setting the corresponding bits in both the SIU_IREER and SIU_IFEER. NOTE IRQ[6] is not available in this device. IRQ[2] is not available in the 208 package due to pin limitations. 208 Package: Address: Base + 0x0002 R Access: R/W 0 1 2 3 0 0 0 0 0 0 0 0 16 17 18 19 4 5 6 7 8 9 10 11 12 13 14 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 21 22 23 24 25 26 27 28 29 30 31 W Reset R IREE IREE IREE IREE IREE IREE IREE IREE IREE IREE IREE IREE IREE IREE IREE IREE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 6-10. IRQ Rising-Edge Event Enable Register (SIU_IREER) Table 6-15. SIU_IREER Field Descriptions Field 0–15 16–31 IREEn Function Reserved IRQ rising-edge event enable n. Enables rising-edge triggered events on the corresponding IRQn pin. 0 Rising edge event is disabled. 1 Rising edge event is enabled. MPC5533 Microcontroller Reference Manual, Rev. 0 6-20 Freescale Semiconductor 6.4.1.10 IRQ Falling-Edge Event Enable Register (SIU_IFEER) The SIU_IFEER allows falling edge triggered events to be enabled on the corresponding IRQ[n] pins. Rising and falling edge events can be enabled by setting the corresponding bits in both the SIU_IREER and SIU_IFEER. NOTE IRQ[6] is not available in this device. IRQ[2] is not available in the 208 package due to pin limitations. 208 Package: Address: Base + 0x002C R Access: R/W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 IFEE 14 IFEE 13 IFEE 12 IFEE 11 IFEE 10 IFEE 9 IFEE 8 IFEE 7 IFEE 6 IFEE 5 IFEE 4 IFEE 3 IFEE 2 IFEE 1 IFEE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset R IFEE W 15 Reset 0 Figure 6-11. IRQ Falling-Edge Event Enable Register (SIU_IFEER) The following table describes the fields in the IRQ falling-edge event enable register: Table 6-16. SIU_IFEER Field Descriptions Field Function 0–15 Reserved 16–31 IFEEn IRQ falling-edge event enable n. Enables falling-edge triggered events on the corresponding IRQ[n] pin. 0 Falling edge event is disabled. 1 Falling edge event is enabled. 6.4.1.11 IRQ Digital Filter Register (SIU_IDFR) The SIU_IDFR specifies the amount of digital filtering on the IRQ[0:5, 7:15] pins. The digital filter length field specifies the number of system clocks that define the period of the digital filter and the minimum time a signal must be held in the active state on the IRQ pins to be recognized as an edge triggered event. NOTE IRQ[6] is not available in this device. 208 Package: IRQ[2] is not available in the 208 package due to pin limitations. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 6-21 Address: Base + 0x0030 R Access: R/W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset R DFL W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 6-12. External IRQ Digital Filter Register (SIU_IDFR) Table 6-17. SIU_IDFR Field Descriptions Field Function 0–27 Reserved 28–31 DFL Digital filter length. Defines the digital filter period on the IRQn inputs according to the following equation: Filter Period = ( SystemClockPeriod × 2 DFL ) + 1 ( S ystemClockPeriod ) For a 82-MHz system clock, this gives a range of 24ns to 400μs. The minimum time of three clocks accounts for synchronization of the IRQ input pins with the system clock. 6.4.1.12 Pad Configuration Registers (SIU_PCR) The following subsections define the SIU_PCRs for all device pins that allow configuration of the pin function, direction, and static electrical attributes. The information presented pertains to which bits and fields are active for a given pin or group of pins, and the reset state of the register. The reset state of SIU_PCRs given in the following sections is that prior to execution of the BAM program. The BAM program can change certain SIU_PCRs based on the reset configuration. See the BAM section of the manual for more detail. For all PCRs, if the pin is configured as an input, the ODE, SRC, and DSC bits do not apply. If the pin is configured as an output, the HYS bit does not apply. When a pin is configured as an output, the weak internal pull up/down is disabled regardless of the WPE or WPS settings in the PCR. The IBE and OBE bit definitions are specific for each PCR. In cases where an I/O function is input or output only the IBE and OBE bits do not need to be set to enable the input or output. In cases where an I/O function can be either an input and output, the IBE and OBE bits must be set accordingly (IBE = 1 for input, and OBE = 1 for output). For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the IBE and OBE bits have no effect. MPC5533 Microcontroller Reference Manual, Rev. 0 6-22 Freescale Semiconductor For all PCRs where a GPIO function is available on the pin, if the pin is configured as an output and the IBE bit is set, the value of the pin is shown in its GPDIx_x register. Negating the IBE bit when the pin is configured as an output reduces noise and power consumption. The SIU_PCRs are 16-bit registers that can be read or written as 16-bit values aligned on 16-bit boundaries, or as 32-bit values aligned on 32-bit address boundaries. Table 6-18 describes the SIU_PCR fields. NOTE Not all of the fields occur in all SIU_PCRs, depending on the type of pad it controls. See the specific SIU_PCR definition. All pin names begin with the primary function, followed by the alternate function, and then GPIO. The primary function is not available on all MPC5500 devices. In some cases, the third function can be a secondary alternate, which supersedes the GPIO. Those exceptions are noted in the documentation. For example, SIU_PCR85 configures the CNTXB_PCSC[3]_GPIO[85] muxed signal, where CNTXB is the primary function, PCSC[3] is the alternate function. Figure 6-13 shows a sample PCR register with all bit fields displayed: SIU register address Register bit range [3:5] Field bit range [0:2] Bit number Footnotes Access Permissions Field name Address: Base + 0x0014 Read values Write values R Access: R/W 0 1 2 0 0 0 3 4 5 PA1 6 7 OBE IBE 0 0 8 9 10 11 ODE HYS2 DSC 12 13 0 0 14 15 WPE WPS 1 1 W Reset values RESET: 0 0 0 0 0 0 1 1 0 0 0 0 1 Do not configure the PA fields in PCR0–3 and PCR4–7 simultaneously as input. Configure only one set of pins as the address input. 2 If external master operation is enabled, clear the HYS bit to 0. Figure 6-13. Sample PCR Register Description For identification of the source module for primary and alternate functions, and the description of these signals, refer to Chapter 2, “Signals” of this manual. Refer to the chapter for the module that uses the signal for an additional signal description. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 6-23 Table 6-18. SIU_PCR Field Descriptions Field 0–2 3–5 PA[0:2] Description Reserved Pin assignment. Selects the function of a multiplexed pad. A separate port enable output signal from the SIU is asserted for each value of this register. The size of the field can be from 1 to 3 bits, depending on the amount of multiplexing on the pad. PA Bit Field 1-bit2 (2 Functions) 2-bit2 (4 Functions) 3-bit (5 Functions) Pin Function1 0 0 0 0 0 0 0 0 0 GPIO 0 0 1 0 0 1 0 0 1 Primary function 0 1 0 0 1 0 Alternate function 1 0 1 1 0 1 1 Main primary function 3 1 0 0 Alternate function 2 1 0 1 Invalid value 1 1 0 Invalid value 1 1 1 Invalid value The shaded columns indicate invalid bits in 1- and 2-bit PA fields; the shaded rows indicate invalid values for 3-bit PA fields. 1 For all SIU_PCRs that do not comply with these rules, the PA definition is given explicitly with the SIU_PCR definition. 2 For future software compatibility, it is recommended that all PA fields be treated as 3-bit fields, with the unused bits written as 0. 3 The main primary function is used when the primary function is not available on the package or is used for a different purpose. 6 OBE Output buffer enable. Enables the pad as an output and drives the output buffer enable signal. 0 Output buffer for the pad is disabled. 1 Output buffer for the pad is enabled. 7 IBE Input buffer enable. Enables the pad as an input and drives the input buffer enable signal. 0 Input buffer for the pad is disabled. 1 Input buffer for the pad is enabled. 8–9 Drive strength control. Controls the pad drive strength. Drive strength control pertains to pins with the fast I/O pad DSC[0:1] type. 00 10 pF Drive Strength 01 20 pF Drive Strength 10 30 pF Drive Strength 11 50 pF Drive Strength 10 ODE Open drain output enable. Controls output driver configuration for the pads. Either open drain or push/pull driver configurations can be selected. This feature applies to output pins only. 0 Open drain is disabled for the pad (push/pull driver enabled). 1 Open drain is enabled for the pad. 11 HYS Input hysteresis. Controls whether hysteresis is enabled for the pad. 0 Hysteresis is disabled for the pad. 1 Hysteresis is enabled for the pad. MPC5533 Microcontroller Reference Manual, Rev. 0 6-24 Freescale Semiconductor Table 6-18. SIU_PCR Field Descriptions (Continued) Field Description 12–13 Slew rate control. Controls slew rate for the pad. Slew rate control pertains to pins with slow or medium I/O pad types, SRC[0:1] and the output signals are driven according to the value of this field. Actual slew rate is dependent on the pad type and load. See the electrical specification for this information 00 Minimum slew rate (slowest) 01 Medium slew rate 10 Invalid value 11 Maximum slew rate (fastest) 14 WPE Weak pull up/down enable. Controls whether the weak pull up/down devices are enabled/disabled for the pad. Pull up/down devices are enabled by default. 0 Weak pull device is disabled for the pad. 1 Weak pull device is enabled for the pad. 15 WPS Weak pull up/down select. Controls whether weak pull up or weak pull down devices are used for the pad when weak pull up/down devices are enabled. The WKPCFG pin determines whether pull up or pull down devices are enabled at reset. The WPS bit determines whether weak pull up or pull down devices are used after reset, or for pads in which the WKPCFG pin does not determine the reset weak pull up/down state. 0 The pull down value is enabled for the pad. 1 The pull up value is enabled for the pad. 6.4.1.12.1 Pad Configuration Registers 0–3 (SIU_PCR0–SIU_PCR3) The SIU_PCR0–SIU_PCR3 registers control the pin function, direction, and static electrical attributes of the CS[0:3]_ADDR[8:11]_GPIO[0:3] pins. CS[1:3]_ADDR[9:11]_GPIO[1:3] are not available due to pin limitations in the 208 package. 208 Package: Address: SIU_BASE + (0x0040–0x0046) R 0 1 2 3 0 0 0 0 Access: R/W 4 5 6 7 8 OBE1 IBE2 PA 9 10 11 ODE3 HYS DSC 12 13 0 0 0 0 14 15 WPE4 WPS4 W Reset 0 0 0 0 0 0 0 0 1 1 0 0 1 1 1 When configured as CS[0:3], the OBE bit has no effect. When configured as GPO, set the OBE bit to one. When configured as CS[0:3] or GPI, set the IBE bit to one to reflect the pin state in the GPDI register. When configured as GPI, set the IBE bit to one. 3 When configured as CS[0:3], set the ODE bit to zero. 4 See the EBI section for weak pull up settings when configured as CS[0:3]. 2 Figure 6-14. CS[0:3]_ADDR[8:11]_GPIO[0:3] Pad Configuration Registers (SIU_PCR0–SIU_PCR3) MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 6-25 See Table 6-18 for bit field definitions. Table 6-19 lists the PA values for CS[1:3]_ADDR[9:11]_GPIO[1:3]. Table 6-19. PCR0–PCR3 PA Field Descriptions 6.4.1.12.2 PA Field Pin Function 0b00 GPIO[0:3] 0b01 CS[0:3] 0b10 ADDR[8:11] 0b11 CS[0:3] Pad Configuration Registers 8–27 (SIU_PCR8–SIU_PCR27) The SIU_PCR8–SIU_PCR27 registers control the pin function, direction, and static electrical attributes of the ADDR[12:31]_GPIO[8:27] pins. ADDR[12:31]_GPIO[8:27] pins are not available due to pin limitations. 208 Package: Address: SIU_BASE + (0x0048–0x0076) R 0 1 2 3 4 0 0 0 0 0 Access: R/W 5 PA 6 7 8 OBE1 IBE2 9 10 11 ODE3 HYS DSC 12 13 0 0 0 0 14 15 WPE4 WPS4 W Reset 0 0 0 0 0 0 0 0 1 1 0 0 1 1 1 When configured as ADDR[12:31], the OBE bit has no effect. When configured as GPO, set the OBE bit to one. When configured as ADDR[12:31] or GPO, set the IBE bit to one to reflect the pin state in the GPDI register. When configured as GPI, set the IBE bit to one. 3 When configured as ADDR[12:31], set the ODE bit to zero. 4 See the EBI section for weak pull up settings when configured as ADDR[12:31] 2 Figure 6-15. Pad Configuration Registers 8–27 (SIU_PCR8–SIU_PCR27) See Table 6-18 for bit field definitions. 6.4.1.12.3 Pad Configuration Registers 28–43 (SIU_PCR28–SIU_PCR43) The SIU_PCR28–SIU_PCR43 registers control the pin function, direction, and static electrical attributes of the DATA[0:15]_GPIO[28:43] pins. 208 Package: DATA[1:15] pins are not available in the 208 package due to pin limitations. MPC5533 Microcontroller Reference Manual, Rev. 0 6-26 Freescale Semiconductor See Table 6-18 for bit field definitions. Address: SIU_BASE + (0x0078–0x0096) (16) R 0 1 2 3 4 0 0 0 0 0 Access: R/W 5 PA 6 7 8 OBE1 IBE2 9 10 11 ODE3 HYS DSC 12 13 0 0 0 0 14 15 WPE4 WPS4 W Reset 0 0 0 0 0 0 0 0 1 1 0 0 1 1 1 When configured as DATA[0:15], the OBE bit has no effect. When configured as GPO, set the OBE bit to one. When configured as DATA[0:15] or GPO, set the IBE bit to one to reflect the pin state in the GPDI register. When configured as GPI, set the IBE bit to one. 3 When configured as DATA[0:15], set the ODE bit to zero. 4 See the EBI section for weak pull up settings when configured as DATA[0:15]. 2 Figure 6-16. DATA[0:15]_GPIO[28:43] Pad Configuration Registers (SIU_PCR28–SIU_PCR43) 6.4.1.12.4 Pad Configuration Register 62 (SIU_PCR62) The SIU_PCR62 register controls the pin function, direction, and static electrical attributes of the RD_WR_GPIO[62] pin. RD_WR_GPIO[62] pin is not available in the 208 package due to pin limitations. 208 Package: See Table 6-18 for bit field definitions. Address: SIU_BASE + 0x00BC R Access: R/W 0 1 2 3 4 0 0 0 0 0 5 PA 6 7 8 OBE1 IBE2 9 10 11 ODE3 HYS DSC 12 13 0 0 0 0 14 15 WPE4 WPS4 W Reset 0 0 0 0 0 0 0 0 1 1 0 0 1 1 1 When configured as RD_WR, the OBE bit has no effect. When configured as GPO, set the OBE bit to one. When configured as RD_WR or GPO, set the IBE bit to one to reflect the pin state in the GPDI register. When configured as GPI, set the IBE bit to one. 3 When configured as RD_WR, set the ODE bit to zero. 4 See the EBI section for weak pull up settings when configured as RD_WR. 2 Figure 6-17. RD_WR_GPIO[62] Pad Configuration Register (SIU_PCR62) 6.4.1.12.5 Pad Configuration Register 63 (SIU_PCR63) The SIU PCR63 register controls the pin function, direction, and static electrical attributes of the BDIP_GPIO[63] pin. 208 Package: BDIP_GPIO[63] pin is not available in the 208 package due to pin limitations. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 6-27 See Table 6-18 for bit field definitions. Address: SIU_BASE+0x00BE R Access: R/W 0 1 2 3 4 0 0 0 0 0 5 PA 6 7 8 OBE1 IBE2 9 10 11 ODE3 HYS DSC 12 13 0 0 0 0 14 15 WPE4 WPS4 W Reset 0 0 0 0 0 0 0 0 1 1 0 0 1 1 1 When configured as BDIP, the OBE bit has no effect. When configured as GPO, set the OBE bit to one. When configured as BDIP or GPO, set the IBE bit to one to reflect the pin state in the GPDI register. When configured as GPI, set the IBE bit to one. 3 When configured as BDIP, set the ODE bit to zero. 4 See the EBI section for weak pull up settings when configured as BDIP. 2 Figure 6-18. BDIP_GPIO[63] Pad Configuration Register (SIU_PCR63) 6.4.1.12.6 Pad Configuration Registers 64–65 (SIU_PCR64–SIU_PCR65) The SIU_PCR64–SIU_PCR65 registers control the pin function, direction, and static electrical attributes of the WE/BE[0:1]_GPIO[64:65] pins. The PA bit in the PCR64–65 registers selects between the write enable/byte enable and GPIO functions. The WEBS bit in the EBI base registers selects between the write enable and byte enable function. WE/BE[0:1]_GPIO[64:65] pins are not available in the 208 package due to pin limitations. See Table 6-18 for bit field definitions. 208 Package: Address: SIU_BASE + (0x00C0–0x00C6) R 0 1 2 3 4 0 0 0 0 0 Access: R/W 5 PA 6 7 8 OBE1 IBE2 9 10 11 ODE3 HYS DSC 12 13 0 0 0 0 14 15 WPE4 WPS4 W Reset 0 0 0 0 0 0 0 0 1 1 0 0 1 1 1 When configured as WE[0:1] or BE[0:1], the OBE bit has no effect. When configured as GPO, set the OBE bit to one. When configured as WE[0:1] or BE[0:1] or GPO, set the IBE bit to one to reflect the pin state in the GPDI register. When configured as GPI, set the IBE bit to one. 3 When configured as WE[0:1] or BE[0:1], set the ODE bit to zero. 4 See the EBI section for weak pull up settings when configured as WE[0:1] or BE[0:1]. 2 Figure 6-19. WE/BE[0:1]_GPIO[64:65] Pad Configuration Registers (SIU_PCR64–SIU_PCR65) MPC5533 Microcontroller Reference Manual, Rev. 0 6-28 Freescale Semiconductor 6.4.1.12.7 Pad Configuration Register 68 (SIU_PCR68) The SIU_PCR68 register controls the pin function, direction, and static electrical attributes of the OE_GPIO[68] pin. Address: SIU_BASE + 0x00C8 R Access: R/W 0 1 2 3 4 0 0 0 0 0 5 PA 6 7 8 OBE1 IBE2 9 10 11 ODE3 HYS DSC 12 13 0 0 0 0 14 15 WPE4 WPS4 W RESET: 0 0 0 0 0 0 0 0 1 1 0 0 1 1 1 When configured as OE, the OBE bit has no effect. When configured as GPO, set the OBE bit to one. When configured as OE or GPO, set the IBE bit to one to reflect the pin state in the GPDI register. When configured as GPI, set the IBE bit to one. 3 When configured as OE, set the ODE bit to zero. 4 See the EBI section for weak pull up settings when configured as OE. 2 Figure 6-20. OE_GPIO[68] Pad Configuration Register (SIU_PCR68) See Table 6-18 for bit field definitions. 6.4.1.12.8 Pad Configuration Register 69 (SIU_PCR69) The SIU_PCR69 register controls the pin function, direction, and static electrical attributes of the TS_GPIO[69] pin. TS_GPIO[69] pin is not available in the 208 package due to pin limitations. 208 Package: Figure 6-21. TS_GPIO[69] Pad Configuration Register (SIU_PCR69) Address: SIU_BASE + 0x00CA R Access: R/W 0 1 2 3 4 0 0 0 0 0 5 PA 6 7 8 OBE1 IBE2 9 10 11 ODE3 HYS DSC 12 13 0 0 0 0 14 15 WPE4 WPS4 W RESET: 0 0 0 0 0 0 0 0 1 1 0 0 1 1 1 When configured as TS, the OBE bit has no effect. When configured as GPO, set the OBE bit to one. When configured as TS or GPO, set the IBE bit to one to reflect the pin state in the GPDI register. When configured as GPI, set the IBE bit to one. 3 When configured as TS, set the ODE bit to zero. 4 See the EBI section for weak pull up settings when configured as TS. 2 See Table 6-18 for bit field definitions. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 6-29 6.4.1.12.9 Pad Configuration Register 70 (SIU_PCR70) The SIU_PCR70 register controls the pin function, direction, and static electrical attributes of the TA_GPIO[70] pin. TA_GPIO[70] pin is not available in the 208 package due to pin limitations. 208 Package: Figure 6-22. TA_GPIO[70] Pad Configuration Register (SIU_PCR70) Address: SIU_BASE + 0x00CC R Access: R/W 0 1 2 3 4 0 0 0 0 0 5 PA 6 7 8 OBE1 IBE2 9 10 11 ODE3 HYS DSC 12 13 0 0 0 0 14 15 WPE4 WPS4 W RESET: 0 0 0 0 0 0 0 0 1 1 0 0 1 1 1 When configured as TA, the OBE bit has no effect. When configured as GPO, set the OBE bit to one. When configured as TA, or GPIO, set the IBE bit to one to reflect the pin state in the GPDI register. When configured as GPI, set the IBE bit to one. 3 When configured as TA and external master operation is enabled, set the ODE bit to zero. 4 See the EBI section for weak pull up settings when configured as TA. 2 See Table 6-18 for bit field definitions. 6.4.1.12.10 Pad Configuration Register 82–75 (SIU_PCR82–SIU_PCR75) The SIU_PCR82–SIU_PCR75 registers control the pin function, direction, and static electrical attributes of the MDO[11:4]_GPIO[82:75] pins. GPIO is the default function at reset for these pins. The full port mode (FPM) bit in the Nexus port controller (NPC) port configuration register controls whether the pins function as MDO[11:4]_GPIO[82:75]. The pad interface port enable for these pins is driven by the NPC block. When the FPM bit is set, the NPC enables the MDO port enable, and disables GPIO. When the FPM bit is cleared, the NPC disables the MDO port enable, and enables GPIO. MDO[11:4]_GPIO[82:75] pins are not available in the 208 package. 208 Package: Address: SIU_BASE + (0x00E4–0x00D6) R Access: R/W 0 1 2 3 4 5 0 0 0 0 0 0 6 7 8 OBE1 IBE1 9 10 11 ODE2 HYS3 DSC 12 13 0 0 0 0 14 15 WPE4 WPS W RESET: 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 This bit applies only to GPIO operation. Set the ODE bit to zero for MDO operation. 3 The HYS bit has no effect on MDO operation. 4 Set the WPE bit to zero for MDO operation. 2 Figure 6-23. MDO[11:4]_GPIO[82:75] Pad Configuration Register (SIU_PCR82–SIU_PCR75) See Table 6-18 for bit field definitions. MPC5533 Microcontroller Reference Manual, Rev. 0 6-30 Freescale Semiconductor 6.4.1.12.11 Pad Configuration Register 83 (SIU_PCR83) The SIU_PCR83 register controls the pin function, direction, and static electrical attributes of the CNTXA_GPIO[83] pin. Address: SIU_BASE + 0x00E6 R Access: R/W 0 1 2 3 4 0 0 0 0 0 5 PA 6 7 OBE1 IBE2 8 9 0 0 10 11 ODE HYS 0 0 12 13 SRC 14 15 WPE WPS W RESET: 1 2 0 0 0 0 0 0 0 0 0 0 0 0 1 1 When configured as CNTXA, the OBE bit has no effect. When configured as GPO, set the OBE bit to one. When configured as CNTXA or GPO, set the IBE bit to reflect the pin state in the GPDI register. When configured as GPI, set the IBE bit to one. Figure 6-24. CNTXA_GPIO[83] Pad Configuration Register (SIU_PCR83) See Table 6-18 for bit field definitions. 6.4.1.12.12 Pad Configuration Register 84 (SIU_PCR84) The SIU_PCR84 register controls the pin function, direction, and static electrical attributes of the CNRXA_GPIO[84] pin. Address: SIU_BASE + 0x00E8 R Access: R/W 0 1 2 3 4 0 0 0 0 0 5 PA 6 7 OBE1 IBE2 8 9 0 0 10 11 ODE HYS 0 0 12 13 SRC 14 15 WPE WPS W RESET: 1 2 0 0 0 0 0 0 0 0 0 0 0 0 1 1 When configured as CNRXA, the OBE bit has no effect. When configured as GPO, set the OBE bit to one. When configured as CNRXA or GPO, set the IBE bit to one to reflect the pin state in the GPDI register. When configured as GPI, set the IBE bit to one. Figure 6-25. CNRXA_GPIO[84] Pad Configuration Register (SIU_PCR84) See Table 6-18 for bit field definitions. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 6-31 6.4.1.12.13 Pad Configuration Register 85 (SIU_PCR85) The SIU_PCR85 register controls the pin function, direction, and static electrical attributes of the CNTXB_PCSC[3]_GPIO[85] pin. CNTXB is the primary function and is not available in this device. This register allows you to select the PCSC[3] or GPIO[85] function. Address: SIU_BASE + 0x00EA R Access: R/W 0 1 2 3 0 0 0 0 4 5 PA1 6 7 OBE2 IBE3 8 9 0 0 10 11 ODE HYS 0 0 12 13 SRC 14 15 WPE WPS W RESET: 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 The primary function is not available on this device. Do not select 0b01 or 0b11 for the PA field. Valid values are 0b00 for GPIO[85] and 0b10 for PCSC[3]. 2 When configured as PCSC, the OBE bit has no effect. When configured as GPO, set the OBE bit to one. 3 When configured as PCSC or GPO, you can set the IBE bit to one to reflect the pin state in the GPDI register. When configured as GPI, set the IBE bit to one. Figure 6-26. PCSC[3]_GPIO[85] Pad Configuration Register (SIU_PCR85) See Table 6-18 for bit field definitions. 6.4.1.12.14 Pad Configuration Register 86 (SIU_PCR86) The SIU_PCR86 register controls the pin function, direction, and static electrical attributes of the CNRXB_PCSC[4]_GPIO[86] pin. CNRXB is the primary function and is not available in this device. This register allows you to select the PCSC[4] or GPIO[86] function. Address: SIU_BASE + 0x00EC R Access: R/W 0 1 2 3 0 0 0 0 4 5 PA1 6 7 OBE2 IBE3 8 9 0 0 10 11 ODE HYS 0 0 12 13 SRC 14 15 WPE WPS W RESET: 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 The primary function is not available on this device. Do not select 0b01 or 0b11 for the PA field. Valid values are 0b00 for GPIO[86] and 0b10 for PCSC[4]. 2 When configured as PCSC, the OBE bit has no effect. When configured as GPO, set the OBE bit to one. 3 When configured as PCSC or GPO, you can set the IBE bit to one to reflect the pin state in the GPDI register. When configured as GPI, set the IBE bit to one. Figure 6-27. PCSC[4]_GPIO[86] Pad Configuration Register (SIU_PCR86) See Table 6-18 for bit field definitions. MPC5533 Microcontroller Reference Manual, Rev. 0 6-32 Freescale Semiconductor 6.4.1.12.15 Pad Configuration Register 87 (SIU_PCR87) The SIU_PCR87 register controls the pin function, direction, and static electrical attributes of the CNTXC_PCSD[3]_GPIO[87] pin. Address: SIU_BASE + 0x00EE R Access: R/W 0 1 2 3 0 0 0 0 4 5 6 7 OBE1 IBE2 PA 8 9 0 0 10 11 ODE HYS 0 0 12 13 SRC 14 15 WPE WPS W RESET: 1 2 0 0 0 0 0 0 0 0 0 0 0 0 1 1 When configured as CNTXC or PCSD, the OBE bit has no effect. When configured as GPO, set the OBE bit to one. When configured as CNTXC or PCSD or GPO, you can set the IBE bit to one to reflect the pin state in the GPDI register. When configured as GPI, set the IBE bit to one. Figure 6-28. CNTXC_PCSD[3]_GPIO[87] Pad Configuration Register (SIU_PCR87) See Table 6-18 for bit field definitions. 6.4.1.12.16 Pad Configuration Register 88 (SIU_PCR88) The SIU_PCR88 register controls the pin function, direction, and static electrical attributes of the CNRXC_PCSD[4]_GPIO[88] pin. Address: SIU_BASE + 0x00F0 R Access: R/W 0 1 2 3 0 0 0 0 4 5 6 7 OBE1 IBE2 PA 8 9 0 0 10 11 ODE HYS 0 0 12 13 SRC 14 15 WPE WPS W RESET: 1 2 0 0 0 0 0 0 0 0 0 0 0 0 1 1 When configured as CNRXC or PCSD, the OBE bit has no effect. When configured as GPO, set the OBE bit to one. When configured as CNRXC or PCSD or GPO, you can set the IBE bit to one to reflect the pin state in the GPDI register. When configured as GPI, set the IBE bit to one. Figure 6-29. CNRXC_PCSD[4]_GPIO[88] Pad Configuration Register (SIU_PCR88) See Table 6-18 for bit field definitions. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 6-33 6.4.1.12.17 Pad Configuration Register 89 (SIU_PCR89) The SIU_PCR89 register controls the pin function, direction, and static electrical attributes of the TXDA_GPIO[89] pin. Address: SIU_BASE + 0x00F2 R Access: R/W 0 1 2 3 4 0 0 0 0 0 5 PA 6 7 OBE1 IBE2 8 9 0 0 10 11 ODE HYS 0 0 12 13 SRC 14 15 WPE WPS W RESET: 1 2 0 0 0 0 0 0 0 0 0 0 0 0 1 1 When configured as TXDA, the OBE bit has no effect. When configured as GPO, set the OBE bit to one. When configured as TXDA or GPO, you can set the IBE bit to one to reflect the pin state in the GPDI register. For SCI loop back operation, set the IBE bit to one. When configured as GPI, set the IBE bit to one. Figure 6-30. TXDA_GPIO[89] Pad Configuration Register (SIU_PCR89) See Table 6-18 for bit field definitions. 6.4.1.12.18 Pad Configuration Register 90 (SIU_PCR90) The SIU_PCR90 register controls the pin function, direction, and static electrical attributes of the RXDA_GPIO[90] pin. Address: SIU_BASE + 0x00F4 R Access: R/W 0 1 2 3 4 0 0 0 0 0 5 PA 6 7 OBE1 IBE2 8 9 0 0 10 11 ODE HYS 0 0 12 13 SRC 14 15 WPE WPS W RESET: 1 2 0 0 0 0 0 0 0 0 0 0 0 0 1 1 When configured as RXDA, the OBE bit has no effect. When configured as GPO, set the OBE bit to one. When configured as RXDA or GPO, you can set the IBE bit to one to reflect the pin state in the GPDI register. When configured as GPI, set the IBE bit to one. Figure 6-31. RXDA_GPIO[90] Pad Configuration Register (SIU_PCR90) See Table 6-18 for bit field definitions. MPC5533 Microcontroller Reference Manual, Rev. 0 6-34 Freescale Semiconductor 6.4.1.12.19 Pad Configuration Register 91 (SIU_PCR91) The SIU_PCR91 register controls the pin function, direction, and static electrical attributes of the TXDB_PCSD[1]_GPIO[91] pin. TXDB is the primary signal and is not designed into this device. This register allows you to select the PCSD[1] or GPIO[91] function. Address: SIU_BASE + 0x00F6 R Access: R/W 0 1 2 3 0 0 0 0 4 5 PA1 6 7 OBE2 IBE3 8 9 0 0 10 11 ODE HYS 0 0 12 13 SRC 14 15 WPE WPS W RESET: 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 2 3 When configured as PCSD, the OBE bit has no effect. When configured as GPO, set the OBE bit to one. When configured as PCSD or GPO, you can set the IBE bit to one to reflect the pin state in the GPDI register. For SCI loop back operation, set the IBE bit to one. When configured as GPI, set the IBE bit to one. Figure 6-32. PCSD[1]_GPIO[91] Pad Configuration Register (SIU_PCR91) See Table 6-18 for bit field definitions. 6.4.1.12.20 Pad Configuration Register 92 (SIU_PCR92) The SIU_PCR92 register controls the pin function, direction, and static electrical attributes of the RXDB_PCSD[5]_GPIO[92] pin. RXDB is the primary signal and is not designed into this device. This register allows you to select the PCSD[5] or GPIO[92] function. Address: SIU_BASE + 0x00F8 R Access: R/W 0 1 2 3 0 0 0 0 4 5 6 7 OBE1 IBE2 PA 8 9 0 0 10 11 ODE HYS 0 0 12 13 SRC 14 15 WPE WPS W RESET: 1 2 0 0 0 0 0 0 0 0 0 0 0 0 1 1 When configured as PCSD, the OBE bit has no effect. When configured as GPO, set the OBE bit to one. When configured as PCSD or GPO, you can set the IBE bit to one to reflect the pin state in the GPDI register. When configured as GPI, set the IBE bit to one. Figure 6-33. PCSD[5]_GPIO[92] Pad Configuration Register (SIU_PCR92) See Table 6-18 for bit field definitions. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 6-35 6.4.1.12.21 Pad Configuration Register 93 (SIU_PCR93) The SIU_PCR93 register controls the pin function, direction, and static electrical attributes of the SCKA_PCSC[1]_GPIO[93] pin. The SCKA signal is the primary function and is not available in this device. This register allows you to select the PCSC[1] or GPIO[93] function. Address: SIU_BASE + 0x00FA R Access: R/W 0 1 2 3 0 0 0 0 4 5 PA1 6 7 OBE2 IBE3 8 9 0 0 10 11 ODE HYS 0 0 12 13 SRC 14 15 WPE WPS W RESET: 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 The primary function is not available on this device. Do not select 0b01 or 0b11 for the PA field. Valid values are 0b10 for PCSC[1] and 0b00 for GPIO[93]. 2 When configured as PCSC, the OBE bit has no effect. When configured as GPO, set the OBE bit to one. 3 When configured as PCSC or GPO, set the IBE bit to one to reflect the pin state in the GPDI register. When configured as GPI, set the IBE bit to one. Figure 6-34. PCSC[1]_GPIO[93] Pad Configuration Register (SIU_PCR93) See Table 6-18 for bit field definitions. 6.4.1.12.22 Pad Configuration Register 94 (SIU_PCR94) The SIU_PCR94 register controls the pin function, direction, and static electrical attributes of the SINA_PCSC[2]_GPIO[94] pin. SINA is the primary function is not available in this device. This register allows you to select of the PCSC[2] or GPIO[94] function. Address: SIU_BASE + 0x00FC R Access: R/W 0 1 2 3 0 0 0 0 4 5 PA1 6 7 OBE2 IBE3 8 9 0 0 10 11 ODE HYS 0 0 12 13 SRC 14 15 WPE WPS W RESET: 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 The primary function is not available on this device. Do not select 0b01 or 0b11 for the PA field. Valid values are 0b10 for PCSC[2] and 0b00 for GPIO[94]. 2 When configured as PCSC, the OBE bit has no effect. When configured as GPO, set the OBE bit to one. 3 When configured as PCSC or GPO, set the IBE bit to one to reflect the pin state in the GPDI register. When configured as GPI, set the IBE bit to one. Figure 6-35. PCSC[2]_GPIO[94] Pad Configuration Register (SIU_PCR94) See Table 6-18 for bit field definitions. MPC5533 Microcontroller Reference Manual, Rev. 0 6-36 Freescale Semiconductor 6.4.1.12.23 Pad Configuration Register 95 (SIU_PCR95) The SIU_PCR95 register controls the pin function, direction, and static electrical attributes of the SOUTA_PCSC[5]_GPIO[95] pin. SOUTA is the primary function and is not available in the device. This register allows you to select the PCSC[5] or GPIO[95] function. Address: SIU_BASE + 0x00FE R Access: R/W 0 1 2 3 0 0 0 0 4 5 PA1 6 7 OBE2 IBE3 8 9 0 0 10 11 ODE HYS 0 0 12 13 SRC 14 15 WPE WPS W RESET: 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 The primary function is not available on this device. Do not select 0b01 or 0b11 for the PA field. Valid values are 0b10 for PCSC[5] and 0b00 for GPIO[95]. 2 When configured as PCSC, the OBE bit has no effect. When configured as GPO, set the OBE bit to one. 3 When configured as PCSC or GPO, set the IBE bit to one to reflect the pin state in the GPDI register. When configured as GPI, set the IBE bit to one. Figure 6-36. PCSC[5]_GPIO[95] Pad Configuration Register (SIU_PCR95) See Table 6-18 for bit field definitions. 6.4.1.12.24 Pad Configuration Registers 96 (SIU_PCR96) The SIU_PCR96 registers control the pin function, direction, and static electrical attributes of the PCSA[0]_PCSD[2]_GPIO[96] pin. PCSA[0] is the primary function and is not available in this device. This register allows you to select the PCSD[2] or GPIO[96] function. Address: SIU_BASE + 0x0100 R Access: R/W 0 1 2 3 0 0 0 0 4 5 PA1 6 7 OBE2 IBE3 8 9 0 0 10 11 ODE HYS 0 0 12 13 SRC 14 15 WPE WPS W RESET: 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 The primary function is not available on this device. Do not select 0b01 or 0b11 for the PA field. Valid values are 0b10 for PCSD[2] and 0b00 for GPIO[96]. 2 When configured as PCSD[2], the OBE bit has no effect. When configured as GPO, set the OBE bit to one. 3 When configured as PCSD[2] or GPO, set the IBE bit to one to reflect the pin state in the GPDI register. When configured as GPI, set the IBE bit to one. Figure 6-37. PCSD[2]_GPIO[96] Pad Configuration Register (SIU_PCR96) See Table 6-18 for bit field definitions. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 6-37 6.4.1.12.25 Pad Configuration Registers 97 (SIU_PCR97) The SIU_PCR97 registers control the pin function, direction, and static electrical attributes of the PCSA[1]_PCSB[2]_GPIO[97] pin. PCSA[1] is the primary function and is not available in this device. PCSB[2] is not designed into this device. Only the GPIO[97] function is available on this device. Address: SIU_BASE + 0x0102 R Access: R/W 0 1 2 3 0 0 0 0 4 5 PA1 6 7 OBE2 IBE3 8 9 0 0 10 11 ODE HYS 0 0 12 13 SRC 14 15 WPE WPS W RESET: 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 The primary function is not available on this device. Do not select 0b01 or 0b11 for the PA field. Valid value is 0b00 for GPIO[97]. When configured as GPO, set the OBE bit to one. 3 When configured as GPO, set the IBE bit to one to reflect the pin state in the GPDI register. When configured as GPI, set the IBE bit to one. 2 Figure 6-38. GPIO[97] Pad Configuration Register (SIU_PCR97) See Table 6-18 for bit field definitions. 6.4.1.12.26 Pad Configuration Register 98 (SIU_PCR98) The SIU_PCR98 register controls the pin function, direction, and static electrical attributes of the PCSA[2]_SCKD_GPIO[98] pin. PCSA[2] is the primary function and is not available in this device. This register allows you to select the SCKD or GPIO[98] function. Address: SIU_BASE + 0x0104 R Access: R/W 0 1 2 3 0 0 0 0 4 5 PA1 6 7 OBE2 IBE3 8 9 0 0 10 11 ODE HYS 0 0 12 13 SRC 14 15 WPE WPS W RESET: 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 The primary function is not available on this device. Do not select 0b001 or 0b011 for the PA field. Valid values are 0b10 for SCKD and 0b00 for GPIO[98]. 2 When configured as SCKD, set the OBE bit to one for master operation, or set to zero for slave operation. When configured as GPO, set the OBE bit to one. 3 When configured as SCKD in slave operation, set the IBE bit to one. When configured as SCKD in master operation or GPO, set the IBE bit to one to reflect the pin state in the GPDI register. When configured as GPI, set the IBE bit to one. Figure 6-39. SCKD_GPIO[98] Pad Configuration Register (SIU_PCR98) See Table 6-18 for bit field definitions. MPC5533 Microcontroller Reference Manual, Rev. 0 6-38 Freescale Semiconductor 6.4.1.12.27 Pad Configuration Register 99 (SIU_PCR99) The SIU_PCR99 register controls the pin function, direction, and static electrical attributes of the PCSA[3]_SIND_GPIO[99] pin. PCSA[3] is the primary function and is not available in this device. This register allows you to select the SIND or GPIO[99] function. Address: SIU_BASE + 0x0106 R Access: R/W 0 1 2 3 0 0 0 0 4 5 PA1 6 7 OBE2 IBE3 8 9 0 0 10 11 ODE HYS 0 0 12 13 SRC 14 15 WPE WPS W RESET: 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 The primary function is not available on this device. Do not select 0b01 or 0b11 for the PA field. Valid values are 0b10 for SIND and 0b00 for GPIO[99]. 2 When configured as GPO, set the OBE bit to one. 3 When configured as SIND or GPO, set the IBE bit to one to reflect the pin state in the GPDI register. When configured as GPI, set the IBE bit to one. Figure 6-40. SIND_GPIO[99] Pad Configuration Register (SIU_PCR99) See Table 6-18 for bit field definitions. 6.4.1.12.28 Pad Configuration Register 100 (SIU_PCR100) The SIU_PCR100 register controls the pin function, direction, and static electrical attributes of the PCSA[4]_SOUTD_GPIO[100] pin. PCSA[4] is the primary function is not available in this device. This register allows you to select the SOUTD or GPIO[100] function. Address: SIU_BASE + 0x0108 R Access: R/W 0 1 2 3 0 0 0 0 4 5 PA1 6 7 OBE2 IBE3 8 9 0 0 10 11 ODE HYS 0 0 12 13 SRC 14 15 WPE WPS W RESET: 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 The primary function is not available on this device. Do not select 0b01 or 0b11 for the PA field. Valid values are 0b10 for SOUTD and 0b00 for GPIO[100]. 2 When configured as SOUTD, the OBE bit has no effect. When configured as GPO, set the OBE bit to one. 3 When configured as SOUTD or GPO, set the IBE bit to one to reflect the pin state in the GPDI register. When configured as GPI, set the IBE bit to one. Figure 6-41. SOUTD_GPIO[100] Pad Configuration Register (SIU_PCR100) See Table 6-18 for bit field definitions. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 6-39 6.4.1.12.29 Pad Configuration Registers 101 (SIU_PCR101) The SIU_PCR101 register controls the pin function, direction, and static electrical attributes of the PCSA[5]_PCSB[3]_GPIO[101] pin. PCSA[5] is the primary function is not available in this device. PCSB[3] is not available in this device. Only the GPIO[101] function is available on this device. Address: SIU_BASE + 0x010A R Access: R/W 0 1 2 3 0 0 0 0 4 5 PA1 6 7 OBE2 IBE3 8 9 0 0 10 11 ODE HYS 0 0 12 13 SRC 14 15 WPE WPS W RESET: 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 The primary function is not available on this device. Do not select 0b01 or 0b11 for the PA field. Valid value is 0b00 for GPIO[101]. 2 When configured as GPO, set the OBE bit to one. 3 When configured as GPO, set the IBE bit to one to reflect the pin state in the GPDI register. When configured as GPI, set the IBE bit to one. Figure 6-42. PCSB[3]_GPIO[101] Pad Configuration Register (SIU_PCR101) See Table 6-18 for bit field definitions. 6.4.1.12.30 Pad Configuration Register 102 (SIU_PCR102) The SIU_PCR102 register controls the pin function, direction, and static electrical attributes of the SCKB_PCSC[1]_GPIO[102] pin. SCKB is the primary function and is not designed into this device. This register allows you to select the PCSC[1] or GPIO[102]. Address: SIU_BASE + 0x010C R Access: R/W 0 1 2 3 0 0 0 0 4 5 6 7 OBE1 IBE2 PA 8 9 0 0 10 11 ODE HYS 0 0 12 13 SRC 14 15 WPE WPS W RESET: 1 2 0 0 0 0 0 0 0 0 0 0 0 0 1 1 When configured as GPO, set the OBE bit to one. When configured as PCSC or GPO, set the IBE bit to one to reflect the pin state in the GPDI register. When configured as GPI, set the IBE bit to one. Figure 6-43. PCSC[1]_GPIO[102] Pad Configuration Register (SIU_PCR102) See Table 6-18 for bit field definitions. MPC5533 Microcontroller Reference Manual, Rev. 0 6-40 Freescale Semiconductor 6.4.1.12.31 Pad Configuration Register 103 (SIU_PCR103) The SIU_PCR103 register controls the pin function, direction, and static electrical attributes of the SINB_PCSC[2]_GPIO[103] pin. SINB is the primary signal and is not designed into this device. This register allows you to select the PCSC[2] or GPIO[103]. Address: SIU_BASE + 0x010E R Access: R/W 0 1 2 3 0 0 0 0 4 5 6 7 OBE1 IBE2 PA 8 9 0 0 10 11 ODE HYS 0 0 12 13 SRC 14 15 WPE WPS W RESET: 1 2 0 0 0 0 0 0 0 0 0 0 0 0 1 1 When configured as PCSC, set the OBE bit to one. When configured as PCSC, set the IBE bit to one to reflect the pin state in the GPDI register. When configured as GPI, set the IBE bit to one. Figure 6-44. PCSC[2]_GPIO[103] Pad Configuration Register (SIU_PCR103) See Table 6-18 for bit field definitions. 6.4.1.12.32 Pad Configuration Register 104 (SIU_PCR104) The SIU_PCR104 register controls the pin function, direction, and static electrical attributes of the SOUTB_PCSC[5]_GPIO[104] pin. SOUTB is the primary signal and is not designed into this device. This register allows you to select the PCSC[5] or GPIO[104]. Address: SIU_BASE + 0x0110 R Access: R/W 0 1 2 3 0 0 0 0 4 5 6 7 OBE1 IBE2 PA 8 9 0 0 10 11 ODE HYS 0 0 12 13 SRC 14 15 WPE WPS W RESET: 1 2 0 0 0 0 0 0 0 0 0 0 0 0 1 1 When configured as PCSC, the OBE bit has no effect. When configured as GPO, set the OBE bit to one. When configured as PCSC or GPO, set the IBE bit to one to reflect the pin state in the GPDI register. When configured as GPI, set the IBE bit to one. Figure 6-45. PCSC[5]_GPIO[104] Pad Configuration Register (SIU_PCR104) See Table 6-18 for bit field definitions. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 6-41 6.4.1.12.33 Pad Configuration Register 105 (SIU_PCR105) The SIU_PCR105 register controls the pin function, direction, and static electrical attributes of the PCSB[0]_PCSD[2]_GPIO[105] pin. PCSB[0] is the primary signal and is not designed into this device. This register allows you to select the PCSD[2] or GPIO[105]. Address: SIU_BASE + 0x0112 R Access: R/W 0 1 2 3 0 0 0 0 4 5 6 7 OBE1 IBE2 PA 8 9 0 0 10 11 ODE HYS 0 0 12 13 SRC 14 15 WPE WPS W RESET: 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 When configured as PCSD[2], set the OBE bit to one for master operation, and set to zero for slave operation. When configured as GPO, set the OBE bit to one. 2 When configured as PCS or GPO, set the IBE bit to one to reflect the pin state in the GPDI register. When configured as GPI, set the IBE bit to one. Figure 6-46. PCSD[2]_GPIO[105] Pad Configuration Register (SIU_PCR105) See Table 6-18 for bit field definitions. 6.4.1.12.34 Pad Configuration Register 106 (SIU_PCR106) The SIU_PCR106 register controls the pin function, direction, and static electrical attributes of the PCSB[1]_PCSD[0]_GPIO[106] pin. PCSB[1] is the primary signal and is not designed into this device. This register allows you to select the PCSD[0] or GPIO[106]. Address: SIU_BASE + 0x0114 R Access: R/W 0 1 2 3 0 0 0 0 4 5 6 7 OBE1 IBE2 PA 8 9 0 0 10 11 ODE HYS 0 0 12 13 SRC 14 15 WPE WPS W RESET: 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 When configured as PCSD[0], set the OBE bit to one for master operation, and set to zero for slave operation. When configured as GPO, set the OBE bit to one. 2 When configured as PCSD[0] in slave operation, set the IBE bit to one. When configured as PCS in master operation or GPO, set the IBE bit to one to reflect the pin state in the GPDI register. When configured as GPI, set the IBE bit to one. Figure 6-47. PCSD[0]_GPIO[106] Pad Configuration Register (SIU_PCR106) See Table 6-18 for bit field definitions. MPC5533 Microcontroller Reference Manual, Rev. 0 6-42 Freescale Semiconductor 6.4.1.12.35 Pad Configuration Register 107 (SIU_PCR107) The SIU_PCR107 register controls the pin function, direction, and static electrical attributes of the PCSB[2]_SOUTC_GPIO[107] pin. PCSB[2] is the primary signal and is not designed into this device. This register allows you to select the SOUTC or GPIO[107]. Address: SIU_BASE + 0x0116 R Access: R/W 0 1 2 3 0 0 0 0 4 5 6 7 OBE1 IBE2 PA 8 9 0 0 10 11 ODE HYS 0 0 12 13 SRC 14 15 WPE WPS W RESET: 1 2 0 0 0 0 0 0 0 0 0 0 0 0 1 1 When configured as SOUTC, the OBE bit has no effect. When configured as GPO, set the OBE bit to one. When configured as SOUTC or GPO, set the IBE bit to one to reflect the pin state in the GPDI register. When configured as GPI, set the IBE bit to one. Figure 6-48. SOUTC_GPIO[107] Pad Configuration Register (SIU_PCR107) See Table 6-18 for bit field definitions. 6.4.1.12.36 Pad Configuration Register 108 (SIU_PCR108) The SIU_PCR108 register controls the pin function, direction, and static electrical attributes of the PCSB[3]_SINC_GPIO[108] pin. PCSB[3] is the primary signal and is not designed into this device. This register allows you to select the SINC or GPIO[108]. Address: SIU_BASE + 0x0118 R Access: R/W 0 1 2 3 0 0 0 0 4 5 6 7 OBE1 IBE2 PA 8 9 0 0 10 11 ODE HYS 0 0 12 13 SRC 14 15 WPE WPS W RESET: 1 2 0 0 0 0 0 0 0 0 0 0 0 0 1 1 When configured as SINC, the OBE bit has no effect. When configured as GPO, set the OBE bit to one. When configured as SINC or GPO, you can set the IBE bit to one to reflect the pin state in the GPDI register. When configured as GPI, set the IBE bit to one. Figure 6-49. SINC_GPIO[108] Pad Configuration Register (SIU_PCR108) See Table 6-18 for bit field definitions. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 6-43 6.4.1.12.37 Pad Configuration Register 109 (SIU_PCR109) The SIU_PCR109 register controls the pin function, direction, and static electrical attributes of the PCSB[4]_SCKC_GPIO[109] pin. PCSB[4] is the primary signal and is not designed into this device. This register allows you to select the SCKC or GPIO[109]. Address: SIU_BASE + 0x011A R Access: R/W 0 1 2 3 0 0 0 0 4 5 6 7 OBE1 IBE2 PA 8 9 0 0 10 11 ODE HYS 0 0 12 13 SRC 14 15 WPE WPS W RESET: 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 When configured as SCKC, set the OBE bit to one for master operation, and set to zero for slave operation. When configured as GPO, set the OBE bit to one. 2 When configured as SCKC in slave operation, set the IBE bit to one. When configured as SCKC in master operation or GPO, set the IBE bit to one to reflect the pin state in the GPDI register. When configured as GPI, set the IBE bit to one. Figure 6-50. SCKC_GPIO[109] Pad Configuration Register (SIU_PCR109) See Table 6-18 for bit field definitions. 6.4.1.12.38 Pad Configuration Register 110 (SIU_PCR110) The SIU_PCR110 register controls the pin function, direction, and static electrical attributes of the PCSB[5]_PCSC[0]_GPIO[110] pin. PCSB[5] is the primary signal and is not designed into this device. This register allows you to select the PCSC[0] or GPIO[110]. Address: SIU_BASE + 0x011C R Access: R/W 0 1 2 3 0 0 0 0 4 5 6 7 OBE1 IBE2 PA 8 9 0 0 10 11 ODE HYS 0 0 12 13 SRC 14 15 WPE WPS W RESET: 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 When configured as PCSC[0], set the OBE bit to one for master operation, and set to zero for slave operation. When configured as GPO, set the OBE bit to one. 2 When configured as PCSC[0] in slave operation, set the IBE bit to one. When configured as PCSC in master operation or GPO, set the IBE bit to one to reflect the pin state in the GPDI register. When configured as GPI, set the IBE bit to one. Figure 6-51. PCSC[0]_GPIO[110] Pad Configuration Register (SIU_PCR110) See Table 6-18 for bit field definitions. 6.4.1.12.39 Pad Configuration Register 113 (SIU_PCR113) The SIU_PCR113 register controls the pin function, direction, and static electrical attributes of the TCRCLKA_IRQ[7]_GPIO[113] pin. MPC5533 Microcontroller Reference Manual, Rev. 0 6-44 Freescale Semiconductor Address: SIU_BASE + 0x0122 R Access: R/W 0 1 2 3 0 0 0 0 4 5 6 7 OBE1 IBE2 PA 8 9 0 0 10 11 ODE HYS 0 0 12 13 SRC 14 15 WPE WPS W RESET: 1 2 0 0 0 0 0 0 0 0 0 0 0 0 1 1 When configured as TCRCLKA or IRQ, the OBE bit has no effect. When configured as GPO, set the OBE bit to one. When configured as TCRCLKA or IRQ or GPO, set the IBE bit to one to reflect the pin state in the GPDI register. When configured as GPI, set the IBE bit to one. Figure 6-52. TCRCLKA_IRQ[7]_GPIO[113] Pad Configuration Register (SIU_PCR113) See Table 6-18 for bit field definitions. 6.4.1.12.40 Pad Configuration Register 114–125 (SIU_PCR114–SIU_PCR125) The SIU_PCR114–SIU_PCR125 registers control the pin function, direction, and static electrical attributes of the ETPUA[0:11]_ETPUA[12:23]_GPIO[114:125] pins. The ETPUA[12:23] alternate functions are output channels only. ETPUA[0:11] are both input and output channels. Address: SIU_BASE + (0x0124–0x013A) R 0 1 2 3 0 0 0 0 Access: R/W 4 5 6 7 OBE1 IBE2 PA 8 9 0 0 10 11 ODE HYS 0 0 12 13 SRC 14 15 WPE WPS W RESET: 0 0 0 0 0 0 0 0 0 0 0 0 1 U3 1 The OBE bit must be set to one for both ETPUA[0:11] and GPIO[114:125] when configured as outputs. When configured as ETPUA[12:23], the OBE bit has no effect. 2 The IBE bit must be set to one for both ETPUA[0:11] and GPIO[114:125] when configured as inputs. When configured as ETPUA[12:23] or when ETPUA[0:11] or GPIO[114:125] are configured as outputs, you can set the IBE bit to one to reflect the pin state in the GPDI register. 3 The weak pull up/down selection at reset for the ETPUA[0:11] pins is determined by the WKPCFG pin. Figure 6-53. ETPUA[0:11]_ETPUA[12:23]_GPIO[114:125] Pad Configuration Register (SIU_PCR114–SIU_PCR125) See Table 6-18 for bit field definitions. 6.4.1.12.41 Pad Configuration Register 126 (SIU_PCR126) The SIU_PCR126 register controls the pin function, direction, and static electrical attributes of the ETPUA[12]_GPIO[126] pin. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 6-45 Address: SIU_BASE + 0x013C R Access: R/W 0 1 2 3 0 0 0 0 4 5 6 7 OBE1 IBE2 PA 8 9 0 0 10 11 ODE HYS 0 0 12 13 SRC 14 15 WPE WPS W RESET: 0 0 0 0 0 0 0 0 0 0 0 0 1 U3 1 The OBE bit must be set to one for both ETPUA and GPIO when configured as outputs. The IBE bit must be set to one for both ETPUA and GPIO when configured as inputs. When configured as ETPUA or GPO outputs, set the IBE bit to one to reflect the pin state in the GPDI register. 3 The weak pull up/down selection at reset for the ETPUA[12] pin is determined by the WKPCFG pin. 2 Figure 6-54. ETPUA[12]_GPIO[126] Pad Configuration Register (SIU_PCR126) See Table 6-18 for bit field definitions. 6.4.1.12.42 Pad Configuration Register 127 (SIU_PCR127) The SIU_PCR127 register controls the pin function, direction, and static electrical attributes of the ETPUA[13]_GPIO[127] pin. Address: SIU_BASE + 0x013E R Access: R/W 0 1 2 3 0 0 0 0 4 5 6 7 OBE1 IBE2 PA 8 9 0 0 10 11 ODE HYS 0 0 12 13 SRC 14 15 WPE WPS W RESET: 0 0 0 0 0 0 0 0 0 0 0 0 1 U3 1 The OBE bit must be set to one for both ETPUA and GPIO when configured as outputs. The IBE bit must be set to one for both ETPUA and GPIO when configured as inputs. When configured as ETPUA or GPO outputs, set the IBE bit to one to reflect the pin state in the GPDI register. 3 The weak pull up/down selection at reset for the ETPUA[13] pin is determined by the WKPCFG pin. 2 Figure 6-55. ETPUA[13]_GPIO[127] Pad Configuration Register (SIU_PCR127) See Table 6-18 for bit field definitions. 6.4.1.12.43 Pad Configuration Register 128 (SIU_PCR128) The SIU_PCR128 register controls the pin function, direction, and static electrical attributes of the ETPUA[14]_GPIO[128] pin. MPC5533 Microcontroller Reference Manual, Rev. 0 6-46 Freescale Semiconductor Address: SIU_BASE + 0x0140 R Access: R/W 0 1 2 3 0 0 0 0 4 5 6 7 OBE1 IBE2 PA 8 9 0 0 10 11 ODE HYS 0 0 12 13 SRC 14 15 WPE WPS W RESET: 0 0 0 0 0 0 0 0 0 0 0 0 1 U3 1 The OBE bit must be set to one for both ETPUA and GPIO when configured as outputs. The IBE bit must be set to one for both ETPUA and GPIO when configured as inputs. When configured as ETPUA or GPO outputs, set the IBE bit to one to reflect the pin state in the GPDI register. 3 The weak pull up/down selection at reset for the ETPUA[14] pin is determined by the WKPCFG pin. 2 Figure 6-56. ETPUA[14]_GPIO[128] Pad Configuration Register (SIU_PCR128) See Table 6-18 for bit field definitions. 6.4.1.12.44 Pad Configuration Register 129 (SIU_PCR129) The SIU_PCR129 register controls the pin function, direction, and static electrical attributes of the ETPUA[15]_GPIO[129] pin. Address: SIU_BASE + 0x0142 R Access: R/W 0 1 2 3 0 0 0 0 4 5 6 7 OBE1 IBE2 PA 8 9 0 0 10 11 ODE HYS 0 0 12 13 SRC 14 15 WPE WPS W RESET: 0 0 0 0 0 0 0 0 0 0 0 0 1 U3 1 The OBE bit must be set to one for both ETPUA and GPIO when configured as outputs. The IBE bit must be set to one for ETPUA or GPIO when configured as inputs. When configured as ETPUA or GPO outputs, set the IBE bit to one to reflect the pin state in the GPDI register. 3 The weak pull up/down selection at reset for the ETPUA[15] pin is determined by the WKPCFG pin. 2 Figure 6-57. ETPUA[15]_GPIO[129] Pad Configuration Register (SIU_PCR129) See Table 6-18 for bit field definitions. 6.4.1.12.45 Pad Configuration Register 130 (SIU_PCR130) The SIU_PCR130 register controls the pin function, direction, and static electrical attributes of the ETPUA[16]_PCSD[1]_GPIO[130] pin. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 6-47 Address: SIU_BASE + 0x0144 R Access: R/W 0 1 2 3 0 0 0 0 4 5 6 7 OBE1 IBE2 PA 8 9 0 0 10 11 ODE HYS 0 0 12 13 SRC 14 15 WPE WPS W RESET: 0 0 0 0 0 0 0 0 0 0 0 0 1 U3 1 When configured as PCSD, the OBE bit has no effect. The OBE bit must be set to one for both ETPUA and GPIO when configured as outputs. 2 The IBE bit must be set to one for both ETPUA and GPIO when configured as inputs. When configured as PCSD, or ETPUA or GPO outputs, set the IBE bit to one to reflect the pin state in the GPDI register. 3 The weak pull up/down selection at reset for the ETPUA[16] pin is determined by the WKPCFG pin. Figure 6-58. ETPUA[16]_PCSD[1]_GPIO[130] Pad Configuration Register (SIU_PCR130) See Table 6-18 for bit field definitions. 6.4.1.12.46 Pad Configuration Register 131 (SIU_PCR131) The SIU_PCR131 register controls the pin function, direction, and static electrical attributes of the ETPUA[17]_PCSD[2]_GPIO[131] pin. Address: SIU_BASE + 0x0146 R Access: R/W 0 1 2 3 0 0 0 0 4 5 6 7 OBE1 IBE2 PA 8 9 0 0 10 11 ODE HYS 0 0 12 13 SRC 14 15 WPE WPS W RESET: 0 0 0 0 0 0 0 0 0 0 0 0 1 U3 1 When configured as PCSD, the OBE bit has no effect. The OBE bit must be set to one for both ETPUA and GPIO when configured as outputs. 2 The IBE bit must be set to one for both ETPUA and GPIO when configured as inputs. When configured as PCSD, or ETPUA or GPO outputs, set the IBE bit to one to reflect the pin state in the GPDI register. 3 The weak pull up/down selection at reset for the ETPUA[17] pin is determined by the WKPCFG pin. Figure 6-59. ETPUA[17]_PCSD[2]_GPIO[131] Pad Configuration Register (SIU_PCR131) See Table 6-18 for bit field definitions. 6.4.1.12.47 Pad Configuration Register 132 (SIU_PCR132) The SIU_PCR132 register controls the pin function, direction, and static electrical attributes of the ETPUA[18]_PCSD[3]_GPIO[132] pin. MPC5533 Microcontroller Reference Manual, Rev. 0 6-48 Freescale Semiconductor Address: SIU_BASE + 0x0148 R Access: R/W 0 1 2 3 0 0 0 0 4 5 6 7 OBE1 IBE2 PA 8 9 0 0 10 11 ODE HYS 0 0 12 13 SRC 14 15 WPE WPS W RESET: 0 0 0 0 0 0 0 0 0 0 0 0 1 U3 1 When configured as PCSD, the OBE bit has no effect. The OBE bit must be set to one for both ETPUA and GPIO when configured as outputs. 2 The IBE bit must be set to one for both ETPUA and GPIO when configured as inputs. When configured as PCSD, or ETPUA or GPO outputs, you can set the IBE bit to one to reflect the pin state in the GPDI register. 3 The weak pull up/down selection at reset for the ETPUA[18] pin is determined by the WKPCFG pin. Figure 6-60. ETPUA[18]_PCSD[3]_GPIO[132] Pad Configuration Register (SIU_PCR132) See Table 6-18 for bit field definitions. 6.4.1.12.48 Pad Configuration Register 133 (SIU_PCR133) The SIU_PCR133 register controls the pin function, direction, and static electrical attributes of the ETPUA[19]_PCSD[4]_GPIO[133] pin. Address: SIU_BASE + 0x014A R Access: R/W 0 1 2 3 0 0 0 0 4 5 6 7 OBE1 IBE2 PA 8 9 0 0 10 11 ODE HYS 0 0 12 13 SRC 14 15 WPE WPS W RESET: 0 0 0 0 0 0 0 0 0 0 0 0 1 U3 1 When configured as PCSD, the OBE bit has no effect. The OBE bit must be set to one for both ETPUA and GPIO when configured as outputs. 2 The IBE bit must be set to one for both ETPUA and GPIO when configured as inputs. When configured as PCSD, or ETPUA or GPO outputs, you can set the IBE bit to one to reflect the pin state in the GPDI register. 3 The weak pull up/down selection at reset for the ETPUA[19] pin is determined by the WKPCFG pin. Figure 6-61. ETPUA[19]_PCSD[4]_GPIO[133] Pad Configuration Register (SIU_PCR133) See Table 6-18 for bit field definitions. 6.4.1.12.49 Pad Configuration Register 134–141 (SIU_PCR134–SIU_PCR141) The SIU_PCR134–SIU_PCR141 registers control the pin function, direction, and static electrical attributes of the ETPUA[20:27]_IRQ[8:15]_GPIO[134:141] pins. Only the output channels of ETPUA[24:27] are connected to pins. Both the input and output channels of ETPUA[20:23] are connected to pins. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 6-49 Address: SIU_BASE + (0x014C–0x015A) R 0 1 2 3 0 0 0 0 Access: R/W 4 5 6 7 OBE1 IBE2 PA 8 9 0 0 10 11 ODE HYS 0 0 12 13 SRC 14 15 WPE WPS W RESET: 0 0 0 0 0 0 0 0 0 0 0 0 1 U3 1 When configured as ETPUA[24:27] or IRQ, the OBE bit has no effect. The OBE bit must be set to one for both ETPUA[20:23] and GPIO[134:141] when configured as outputs. 2 When configured as ETPUA[24:27] or IRQ or GPO, you can set the IBE bit to one to reflect the pin state in the GPDI register. The IBE bit must be set to one for ETPUA[20:23] or GPIO[134:141] when configured as inputs. 3 The weak pull up/down selection at reset for the ETPUA[20:27] pins is determined by the WKPCFG pin. Figure 6-62. ETPUA[20:27]_IRQ[8:15]_GPIO[134:141] Pad Configuration Register (SIU_PCR134–SIU_PCR141) See Table 6-18 for bit field definitions. 6.4.1.12.50 Pad Configuration Register 142 (SIU_PCR142) The SIU_PCR142 register controls the pin function, direction, and static electrical attributes of the ETPUA[28]_PCSC[1]_GPIO[142] pin. Only the output channel of ETPUA[28] is connected to the pin. Address: SIU_BASE + 0x015C R Access: R/W 0 1 2 3 0 0 0 0 4 5 6 7 OBE1 IBE2 PA 8 9 0 0 10 11 ODE HYS 0 0 12 13 SRC 14 15 WPE WPS W RESET: 0 0 0 0 0 0 0 0 0 0 0 0 1 U3 1 When configured as ETPUA or PCSC, the OBE bit has no effect. When configured as GPO, set the OBE bit to one. When configured as ETPUA, PCSC, or GPO, you can set the IBE bit to one to reflect the pin state in the GPDI register. The IBE bit must be set to one for GPIO when configured as input. 3 The weak pull up/down selection at reset for the ETPUA[28] pin is determined by the WKPCFG pin 2 Figure 6-63. ETPUA[28]_PCSC[1]_GPIO[142] Pad Configuration Register (SIU_PCR142) See Table 6-18 for bit field definitions. MPC5533 Microcontroller Reference Manual, Rev. 0 6-50 Freescale Semiconductor 6.4.1.12.51 Pad Configuration Register 143 (SIU_PCR143) The SIU_PCR143 register controls the pin function, direction, and static electrical attributes of the ETPUA[29]_PCSC[2]_GPIO[143] pin. For ETPUA[29], only the output channel is connected to the pin. Address: SIU_BASE + 0x015E R Access: R/W 0 1 2 3 0 0 0 0 4 5 6 7 OBE1 IBE2 PA 8 9 0 0 10 11 ODE HYS 0 0 12 13 SRC 14 15 WPE WPS W RESET: 0 0 0 0 0 0 0 0 0 0 0 0 1 U3 1 When configured as ETPUA or PCSC, the OBE bit has no effect. When configured as GPO, set the OBE bit to one. When configured as ETPUA, PCSC, or GPO, you can set the IBE bit to one to reflect the pin state in the GPDI register. The IBE bit must be set to one for GPIO when configured as input. 3 The weak pull up/down selection at reset for the ETPUA[29] pin is determined by the WKPCFG pin 2 Figure 6-64. ETPUA[29]_PCSC[2]_GPIO[143] Pad Configuration Register (SIU_PCR143) See Table 6-18 for bit field definitions. 6.4.1.12.52 Pad Configuration Register 144 (SIU_PCR144) The SIU_PCR144 register controls the pin function, direction, and static electrical attributes of the ETPUA[30]_PCSC[3]_GPIO[144] pin. Address: SIU_BASE + 0x0160 R Access: R/W 0 1 2 3 0 0 0 0 4 5 6 7 OBE1 IBE2 PA 8 9 0 0 10 11 ODE HYS 0 0 12 13 SRC 14 15 WPE WPS W RESET: 0 0 0 0 0 0 0 0 0 0 0 0 1 U3 1 When configured as PCSC, the OBE bit has no effect. When configured as ETPUA output or GPO, set the OBE bit to one. When configured as ETPUA output, PCSC, or GPO, you can set the IBE bit to one to reflect the pin state in the GPDI register. The IBE bit must be set to one for ETPUA or GPIO when configured as input. 3 The weak pull up/down selection at reset for the ETPUA[30] pin is determined by the WKPCFG pin 2 Figure 6-65. ETPUA[30]_PCSC[3]_GPIO[144] Pad Configuration Register (SIU_PCR144) See Table 6-18 for bit field definitions. 6.4.1.12.53 Pad Configuration Register 145 (SIU_PCR145) The SIU_PCR145 register controls the pin function, direction, and static electrical attributes of the ETPUA[31]_PCSC[4]_GPIO[145] pin. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 6-51 Address: SIU_BASE + 0x0162 R Access: R/W 0 1 2 3 0 0 0 0 4 5 6 7 OBE1 IBE2 PA 8 9 0 0 10 11 ODE HYS 0 0 12 13 SRC 14 15 WPE WPS W RESET: 0 0 0 0 0 0 0 0 0 0 0 0 1 U3 1 When configured as PCSC, the OBE bit has no effect. When configured as ETPUA output or GPO, set the OBE bit to one. When configured as ETPUA output, PCSC, or GPO, you can set the IBE bit to one to reflect the pin state in the GPDI register. The IBE bit must be set to one for ETPUA or GPIO when configured as input. 3 The weak pull up/down selection at reset for the ETPUA[31] pin is determined by the WKPCFG pin 2 Figure 6-66. ETPUA[31]_PCSC[4]_GPIO[145] Pad Configuration Register (SIU_PCR145) See Table 6-18 for bit field definitions. 6.4.1.12.54 Pad Configuration Register 179–188 (SIU_PCR179–SIU_PCR188) The SIU_PCR179–SIU_PCR188 registers control the pin function, direction, and static electrical attributes of the EMIOS[0:9]_ETPUA[0:9]_GPIO[179:188] pins. EMIOS are the primary signals and are not designed into this device. ETPUA[0:9] are alternate functions and are not designed into this device. Only the GPIO[179:188] pins are available on this device. Address: SIU_BASE + (0x01A6–0x01B8) R 0 1 2 3 0 0 0 0 Access: R/W 4 5 6 7 OBE1 IBE2 PA 8 9 0 0 10 11 ODE HYS 0 0 12 13 SRC 14 15 WPE WPS W RESET: 1 2 0 0 0 0 0 0 0 0 0 0 0 0 1 U The OBE bit must be set to one for GPIO[179:188] when configured as outputs. The IBE bit must be set to one for GPIO[179:188] when configured as inputs. Figure 6-67. GPIO[179:188] Pad Configuration Register (SIU_PCR179–SIU_PCR188) See Table 6-18 for bit field definitions. 6.4.1.12.55 Pad Configuration Register 189–190 (SIU_PCR189–SIU_PCR190) The SIU_PCR189–SIU_PCR190 registers control the pin function, direction, and static electrical attributes of the EMIOS[10:11]_GPIO[189:190] pins. EMIOS are the primary signals and are not designed into this device. MPC5533 Microcontroller Reference Manual, Rev. 0 6-52 Freescale Semiconductor Address: SIU_BASE + (0x01BA–0x01BC) R Access: R/W 0 1 2 3 4 0 0 0 0 0 5 PA 6 7 OBE1 IBE2 8 9 0 0 10 11 ODE HYS 0 0 12 13 SRC 14 15 WPE WPS W RESET: 1 2 0 0 0 0 0 0 0 0 0 0 0 0 1 U The OBE bit must be set to one for GPIO[189:190] when configured as outputs. When configured as GPO, you can set the IBE bit to one to reflect the pin state in the GPDI register. The IBE bit must be set to one for GPIO[189:190] when configured as inputs. Figure 6-68. GPIO[189:190] Pad Configuration Register (SIU_PCR189–SIU_PCR190) See Table 6-18 for bit field definitions. 6.4.1.12.56 Pad Configuration Register 191 (SIU_PCR191) The SIU_PCR191 register controls the pin function, direction, and static electrical attributes of the EMIOS[12]_SOUTC_GPIO[191] pin. EMIOS are the primary signals and are not designed into this device. Address: SIU_BASE + 0x01BE R Access: R/W 0 1 2 3 0 0 0 0 4 5 6 7 OBE1 IBE2 PA 8 9 0 0 10 11 ODE HYS 0 0 12 13 SRC 14 15 WPE WPS W RESET: 1 2 0 0 0 0 0 0 0 0 0 0 0 0 1 U The OBE bit must be set to one for GPIO[191] when configured as an output. When configured as GPO, you can set the IBE bit to one to reflect the pin state in the GPDI register. The IBE bit must be set to one for GPIO[191] when configured as an input. Figure 6-69. SOUTC_GPIO[191] Pad Configuration Register (SIU_PCR191) See Table 6-18 for bit field definitions. 6.4.1.12.57 Pad Configuration Register 192 (SIU_PCR192) The SIU_PCR191 register controls the pin function, direction, and static electrical attributes of the EMIOS[13]_SOUTD_GPIO[192] pin. EMIOS are the primary signals and are not designed into this device. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 6-53 Address: SIU_BASE + 0x01C0 R Access: R/W 0 1 2 3 0 0 0 0 4 5 6 7 OBE1 IBE2 PA 8 9 0 0 10 11 ODE HYS 0 0 12 13 SRC 14 15 WPE WPS W RESET: 1 2 0 0 0 0 0 0 0 0 0 0 0 0 1 U The OBE bit must be set to one for GPIO[192] when configured as an output. When configured as GPO, you can set the IBE bit to one to reflect the pin state in the GPDI register. The IBE bit must be set to one for GPIO[192] when configured as an input. Figure 6-70. SOUTD_GPIO[192] Pad Configuration Register (SIU_PCR192) See Table 6-18 for bit field definitions. 6.4.1.12.58 Pad Configuration Register 193–194 (SIU_PCR193–SIU_PCR194) The SIU_PCR193–SIU_PCR194 registers control the pin function, direction, and static electrical attributes of the EMIOS[14:15]_IRQ[0:1]_GPIO[193:194] pins. EMIOS are the primary signals and are not designed into this device. Address: SIU_BASE + (0x01C2–0x01C4) R 0 1 2 3 0 0 0 0 Access: R/W 4 5 6 7 OBE1 IBE2 PA 8 9 0 0 10 11 ODE HYS 0 0 12 13 SRC 14 15 WPE WPS W RESET: 1 2 0 0 0 0 0 0 0 0 0 0 0 0 1 U The OBE bit must be set to one for GPIO[193:194] when configured as outputs. When configured as IRQ or GPO, you can set the IBE bit to one to reflect the pin state in the GPDI register. The IBE bit must be set to one for GPIO[193:194] when configured as inputs. Figure 6-71. IRQ[0:1]_GPIO[193:194] Pad Configuration Register (SIU_PCR193–SIU_PCR194) See Table 6-18 for bit field definitions. 6.4.1.12.59 Pad Configuration Register 195–202 (SIU_PCR195–SIU_PCR202) The SIU_PCR195–SIU_PCR202 registers control the pin function, direction, and static electrical attributes of the EMIOS[16:23]_GPIO[195:202] pins. EMIOS are the primary signals and are not designed into this device. MPC5533 Microcontroller Reference Manual, Rev. 0 6-54 Freescale Semiconductor Address: SIU_BASE + (0x01C6–0x01D4) R 0 1 2 3 0 0 0 0 Access: R/W 4 5 PA1 6 7 OBE2 IBE3 8 9 0 0 10 11 ODE HYS 0 0 12 13 SRC 14 15 WPE WPS W RESET: 0 0 0 0 0 0 0 0 0 0 0 0 1 U 1 The alternate function is not available on this device. Do not select 0b10. Valid values are 0b00 for GPIO[195:202]. The OBE bit must be set to one for GPIO[195:202] when configured as outputs. 3 The IBE bit must be set to one for GPIO[195:202] when configured as inputs. 2 Figure 6-72. GPIO[195:202] Pad Configuration Register (SIU_PCR195–SIU_PCR202) See Table 6-18 for bit field definitions. 6.4.1.12.60 Pad Configuration Register 203–204 (SIU_PCR203–SIU_PCR204) The SIU_PCR203–SIU_PCR204 registers control the pin function, direction, and static electrical attributes of the EMIOS[14:15]_GPIO[203:204] pins. EMIOS are the primary signals and are not designed into this device. Only the GPIO pins are available on this device. GPIO[203:204] are not available due to pin limitations on the 208 package. 208 Package: Address: SIU_BASE + (0x01D6–0x01D8) R Access: R/W 0 1 2 3 4 0 0 0 0 0 5 PA1 6 7 OBE2 IBE3 8 9 0 0 10 11 ODE HYS 0 0 12 13 SRC 14 15 WPE WPS W RESET: 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 Clear the PA bit to zero when used as GPIO. When configured as GPO, set the OBE bit to one. 3 When configured as GPO, you can set the IBE bit to one to reflect the pin state in the GPDI register. When configured as GPI, set the IBE bit to one. 2 Figure 6-73. GPIO[203:204] Pad Configuration Register (SIU_PCR203–SIU_PCR204) See Table 6-18 for bit field definitions. 6.4.1.12.61 Pad Configuration Registers 206–207 (SIU_PCR206–SIU_PCR207) The SIU_PCR206–SIU_PCR207 registers control the pin function, direction, and static electrical attributes of the GPIO[206:207] pins. The PA bit is not implemented for these PCRs since GPIO is the only pin function. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 6-55 Address: SIU_BASE + (0x01DC–0x01DE) R Access: R/W 0 1 2 3 4 5 0 0 0 0 0 0 6 7 8 OBE1 IBE2 9 DSC 10 11 ODE HYS 0 0 12 13 0 0 14 15 WPE WPS W RESET: 1 2 0 0 0 0 0 0 0 0 0 0 0 0 1 1 When configured as GPO, set the OBE bit to one. When configured as GPO, you can set the IBE to one to reflect the pin state in the GPDI register. When configured as GPI, set the IBE bit to one. Figure 6-74. GPIO[206:207] Pad Configuration Registers (SIU_PCR206–SIU_PCR207) See Table 6-18 for bit field definitions. 6.4.1.12.62 Pad Configuration Register 208 (SIU_PCR208) The SIU_PCR208 register controls the pin function, direction, and static electrical attributes of the PLLCFG[0]_IRQ[4]_GPIO[208] pin. Address: SIU_BASE + 0x01E0 R Access: R/W 0 1 2 3 0 0 0 0 4 5 PA1 6 7 OBE2 IBE3 8 9 0 0 10 11 12 ODE HYS4 13 SRC 14 15 WPE WPS W RESET: 0 0 0 0 1 1 0 0 0 0 0 1 0 0 1 1 1 The PLLCFG function applies only during reset when the RSTCFG pin is asserted during reset. Set the PA field to 0b10 for IRQ[4] and set to 0b00 for GPIO[208]. 2 When configured as IRQ, the OBE bit has no effect. When configured as GPO, set the OBE bit to one. 3 When configured as IRQ or GPO, you can set the IBE bit to one to reflect the pin state in the GPDI register. When configured as GPI, set the IBE bit to one. 4 When configured as IRQ, set the HYS bit to one. Figure 6-75. PLLCFG[0]_IRQ[4]_GPIO[208] Pad Configuration Register (SIU_PCR208) See Table 6-18 for bit field definitions. MPC5533 Microcontroller Reference Manual, Rev. 0 6-56 Freescale Semiconductor 6.4.1.12.63 Pad Configuration Register 209 (SIU_PCR209) The SIU_PCR209 register controls the pin function, direction, and static electrical attributes of the PLLCFG[1]_IRQ[5]_SOUTD_GPIO[209] pins. Address: SIU_BASE + 0x01E2 R 0 1 2 0 0 0 Access: R/W 3 4 5 PA1 6 7 OBE2 IBE3 8 9 0 0 10 11 12 ODE HYS4 13 SRC 14 15 WPE WPS W RESET: 0 0 0 0 1 1 0 0 0 0 0 1 0 0 1 1 1 The PLLCFG function applies only during reset when the RSTCFG pin is asserted during reset. Set the PA field to 0b010 for IRQ[5], 0b100 for SOUTD, or 0b000 for GPIO[209]. 2 When configured as IRQ, the OBE bit has no effect. When configured as GPO, set the OBE bit to one. 3 When configured as IRQ or GPO, you can set the IBE bit to one to reflect the pin state in the GPDI register. When configured as GPI, set the IBE bit to one. 4 When configured as IRQ, set the HYS bit to one. Figure 6-76. PLLCFG[1]_IRQ[5]_SOUTD_GPIO[209] Pad Configuration Register (SIU_PCR209) See Table 6-18 for bit field definitions. 6.4.1.12.64 Pad Configuration Register 210 (SIU_PCR210) The SIU_PCR210 register controls the pin function, direction, and static electrical attributes of the RSTCFG_GPIO[210] pin. RSTCFG_GPIO[210] is not available due to pin limitations on the 208 package. 208 Package: Address: SIU_BASE + 0x01E4 R Access: R/W 0 1 2 3 4 0 0 0 0 0 5 PA1 6 7 OBE2 IBE3 8 9 0 0 10 11 ODE HYS 0 1 12 13 SRC 14 15 WPE WPS W RESET: 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1 RSTCFG function is only applicable during reset. Set the PA bit to zero for GPIO operation When configured as GPO, set the OBE bit to one. 3 When configured as GPO, you can set the IBE bit to one to reflect the pin state in the GPDI register. When configured as GPI, set the IBE bit to one. 2 Figure 6-77. RSTCFG_GPIO[210] Pad Configuration Register (SIU_PCR210) See Table 6-18 for bit field definitions. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 6-57 6.4.1.12.65 Pad Configuration Register 211–212 (SIU_PCR211–SIU_PCR212) The SIU_PCR211–SIU_PCR212 registers control the pin function, direction, and static electrical attributes of the BOOTCFG[0:1]_IRQ[2:3]_GPIO[211:212] pins. BOOTCFG[0]_IRQ[2]_GPIO[211] is not available due to pin limitations on the 208 package. 208 Package: Address: SIU_BASE + (0x01E6–0x01E8) R 0 1 2 3 0 0 0 0 Access: R/W 4 5 PA1 6 7 OBE2 IBE3 8 9 0 0 10 11 12 ODE HYS4 13 SRC 14 15 WPE WPS W RESET: 0 0 0 0 1 1 0 0 0 0 0 1 0 0 1 0 1 The BOOTCFG function applies only during reset when the RSTCFG pin is asserted during reset. Set the PA field to 0b10 for IRQ[2:3] and set to 0b00 for GPIO[211:212]. 2 When configured as IRQ, the OBE bit has no effect. When configured as GPO, set the OBE bit to one. 3 When configured as IRQ or GPO, you can set the IBE bit to one to reflect the pin state in the GPDI register. When configured as GPI, set the IBE bit to one. 4 When configured as IRQ, set the HYS bit to one. Figure 6-78. BOOTCFG[0:1]_IRQ[2:3]_GPIO[211:212] Pad Configuration Register (SIU_PCR211–SIU_PCR212) See Table 6-18 for bit field definitions. 6.4.1.12.66 Pad Configuration Register 213 (SIU_PCR213) The SIU_PCR213 register controls the pin function, direction, and static electrical attributes of the WKPCFG_GPIO[213] pin. Address: SIU_BASE + 0x01EA R Access: R/W 0 1 2 3 4 0 0 0 0 0 5 PA1 6 7 OBE2 IBE3 8 9 0 0 10 11 ODE HYS 0 1 12 13 SRC 14 15 WPE WPS W RESET: 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1 WKPCFG function is only applicable during reset. The PA bit must be set to zero for GPIO operation When configured as GPO, set the OBE bit to one. 3 When configured as GPO, you can set the IBE bit to one to reflect the pin state in the GPDI register. When configured as GPI, set the IBE bit to one. 2 Figure 6-79. WKPCFG_GPIO[213] Pad Configuration Register (SIU_PCR213) See Table 6-18 for bit field definitions. MPC5533 Microcontroller Reference Manual, Rev. 0 6-58 Freescale Semiconductor 6.4.1.12.67 Pad Configuration Register 214 (SIU_PCR214) The SIU_PCR214 register controls the enabling/disabling and drive strength of the ENGCLK pin. The ENGCLK pin is enabled and disabled by setting and clearing the OBE bit. The ENGCLK pin is enabled during reset. Address: SIU_BASE + 0x01EC R Access: R/W 0 1 2 3 4 5 0 0 0 0 0 0 6 7 8 9 10 11 12 13 14 15 0 0 0 0 0 0 0 0 0 0 0 0 0 OBE DSC W RESET: 0 0 0 0 0 0 1 0 1 1 Figure 6-80. ENGLCK Pad Configuration Register (SIU_PCR214) See Table 6-18 for bit field definitions. 6.4.1.12.68 Pad Configuration Register 215 (SIU_PCR215) The SIU_PCR215 register controls the pin function, direction, and static electrical attributes of the AN[12]_MA[0]_SDS pin. Address: SIU_BASE + 0x01EE R Access: R/W 0 1 2 3 0 0 0 0 4 5 PA1 6 7 8 9 0 0 0 0 10 11 12 13 0 ODE 14 15 0 0 0 0 SRC W RESET: 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 The input and output buffers are enabled/disabled based on the PA selection. Both the input and output buffers are disabled for the AN[12] function. The output buffer only is enabled for the MA[0] and SDS functions. Figure 6-81. AN[12]_MA[0]_SDS Pad Configuration Register (SIU_PCR215) See Table 6-18 for bit field definitions. The PA field for PCR215 is given in Table 6-20. Table 6-20. PCR215 PA Field Definition PA Field Pin Function 0b00 SDS 0b01 Reserved 0b10 MA[0] 0b11 AN[12] MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 6-59 6.4.1.12.69 Pad Configuration Register 216 (SIU_PCR216) The SIU_PCR216 register controls the pin function, direction, and static electrical attributes of the AN[13]_MA[1]_SDO pin. Address: SIU_BASE + 0x01F0 R Access: R/W 0 1 2 3 0 0 0 0 4 5 PA1 6 7 8 9 0 0 0 0 10 11 12 13 0 ODE 14 15 0 0 0 0 SRC W RESET: 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 The input and output buffers are enabled/disabled based on the PA selection. Both the input and output buffers are disabled for the AN[13] function. The output buffer only is enabled for the MA[1] and SDO functions. Figure 6-82. AN[13]_MA[1]_SDO Pad Configuration Register (SIU_PCR216) See Table 6-18 for bit field definitions. The PA field for PCR216 is given in Table 6-21. Table 6-21. PCR216 PA Field Definition PA Field Pin Function 0b00 SDO 0b01 Reserved 0b10 MA[1] 0b11 AN[13] 6.4.1.12.70 Pad Configuration Register 217 (SIU_PCR217) The SIU_PCR217 register controls the pin function, direction, and static electrical attributes of the AN[14]_MA[2]_SDI pin. Address: SIU_BASE + 0x01F2 R Access: R/W 0 1 2 3 0 0 0 0 4 5 PA1 6 7 8 9 0 0 0 0 10 11 ODE HYS 0 0 12 13 14 15 WPE2 WPS3 SRC W RESET: 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 The input and output buffers are enabled/disabled based on the PA selection. Both input and output buffers are disabled for the AN[14] function. The output buffer only is enabled for the MA[2] function; the input buffer only is enabled for the SDI function. 2 Set the WPE bit to zero when configured as an analog input or MA[2], and set the WPE bit to one when configured as SDI. 3 Set the WPS bit to one when configured as SDI. Figure 6-83. AN[14]_MA[2]_SDI Pad Configuration Register (SIU_PCR217) See Table 6-18 for bit field definitions. The PA field for PCR217 is given in Table 6-22. MPC5533 Microcontroller Reference Manual, Rev. 0 6-60 Freescale Semiconductor Table 6-22. PCR217 PA Field Definition PA Field Pin Function 0b00 SDI 0b01 Reserved 0b10 MA[2] 0b11 AN[14] 6.4.1.12.71 Pad Configuration Register 218 (SIU_PCR218) The SIU_PCR218 register controls the pin function, direction, and static electrical attributes of the AN[15]_FCK pin. Address: SIU_BASE + 0x01F4 R Access: R/W 0 1 2 3 4 0 0 0 0 0 5 PA1 6 7 8 9 0 0 0 0 10 11 12 13 0 ODE 14 15 0 0 0 0 SRC W RESET: 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 The input and output buffers are enabled/disabled based on the PA selection. Both the input and output buffers are disabled for the AN[15] function. The output buffer only is enabled for the FCK function. Figure 6-84. AN[15]_FCK Pad Configuration Register (SIU_PCR218) See Table 6-18 for bit field definitions. The PA field for PCR218 is given in Table 6-23. Table 6-23. PCR218 PA Field Definition PA Field Pin Function 0b0 FCK 0b1 AN[15] 6.4.1.12.72 Pad Configuration Register 219 (SIU_PCR219) The SIU_PCR219 register controls the drive strength of the MCKO pin. Address: SIU_BASE + 0x01F6 R Access: R/W 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 8 9 10 11 12 13 14 15 0 0 0 0 0 0 0 0 0 0 0 0 DSC W RESET: 0 0 0 0 0 0 0 0 1 1 Figure 6-85. MCKO Pad Configuration Register (SIU_PCR219) See Table 6-18 for bit field definitions. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 6-61 6.4.1.12.73 Pad Configuration Register 223–220 (SIU_PCR223–SIU_PCR220) The SIU_PCR223–SIU_PCR220 registers control the drive strength of the MDO[3:0] pins. Address: SIU_BASE + (0x01FE–0x01F8) R Access: R/W 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 8 9 10 11 12 13 14 15 0 0 0 0 0 0 0 0 0 0 0 0 DSC W RESET: 0 0 0 0 0 0 0 0 1 1 Figure 6-86. MDO[3:0] Pad Configuration Register (SIU_PCR223–SIU_PCR220) See Table 6-18 for bit field definitions. 6.4.1.12.74 Pad Configuration Register 225–224 (SIU_PCR225–SIU_PCR224) The SIU_PCR225–SIU_PCR224 registers control the drive strength of the MSEO[1:0] pins. Address: SIU_BASE + (0x0202–0x0200) R Access: R/W 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 8 9 10 11 12 13 14 15 0 0 0 0 0 0 0 0 0 0 0 0 DSC W RESET: 0 0 0 0 0 0 0 0 1 1 Figure 6-87. MSEO[1:0] Pad Configuration Register (SIU_PCR225–SIU_PCR224) See Table 6-18 for bit field definitions. 6.4.1.12.75 Pad Configuration Register 226 (SIU_PCR226) The SIU_PCR226 register controls the drive strength of the RDY pin. RDY is not available due to pin limitations on the 208 package. 208 Package: Address: SIU_BASE + 0x0204 R Access: R/W 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 8 9 10 11 12 13 14 15 0 0 0 0 0 0 0 0 0 0 0 0 DSC W RESET: 0 0 0 0 0 0 0 0 1 1 Figure 6-88. RDY Pad Configuration Register (SIU_PCR226) See Table 6-18 for bit field definitions. MPC5533 Microcontroller Reference Manual, Rev. 0 6-62 Freescale Semiconductor 6.4.1.12.76 Pad Configuration Register 227 (SIU_PCR227) The SIU_PCR227 register controls the drive strength of the EVTO pin. Address: SIU_BASE + 0x0206 R Access: R/W 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 8 9 10 11 12 13 14 15 0 0 0 0 0 0 0 0 0 0 0 0 DSC W RESET: 0 0 0 0 0 0 0 0 1 1 Figure 6-89. EVTO Pad Configuration Register (SIU_PCR227) See Table 6-18 for bit field definitions. 6.4.1.12.77 Pad Configuration Register 228 (SIU_PCR228) The SIU_PCR228 register controls the drive strength of the TDO pin. Address: SIU_BASE + 0x0208 R Access: R/W 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 8 9 10 11 12 13 14 15 0 0 0 0 0 0 0 0 0 0 0 0 DSC W RESET: 0 0 0 0 0 0 0 0 1 1 Figure 6-90. TDO Pad Configuration Register (SIU_PCR228) See Table 6-18 for bit field definitions. 6.4.1.12.78 Pad Configuration Register 229 (SIU_PCR229) The SIU_PCR229 register controls the enabling/disabling and drive strength of the CLKOUT pin. The CLKOUT pin is enabled and disabled by setting and clearing the OBE bit. The CLKOUT pin is enabled during reset. CLKOUT is not available due to pin limitations in the 208 package. 208 Package: Address: SIU_BASE + 0x020A R Access: R/W 0 1 2 3 4 5 0 0 0 0 0 0 6 7 8 9 0 OBE 10 11 12 13 14 15 0 0 0 0 0 0 0 0 0 0 0 0 DSC W RESET: 0 0 0 0 0 0 1 0 1 1 Figure 6-91. CLKOUT Pad Configuration Register (SIU_PCR229) See Table 6-18 for bit field definitions. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 6-63 6.4.1.12.79 Pad Configuration Register 230 (SIU_PCR230) The SIU_PCR230 register controls the slew rate of the RSTOUT pin. Address: SIU_BASE + 0x020C R Access: R/W 0 1 2 3 4 5 6 7 8 9 10 11 0 0 0 0 0 0 0 0 0 0 0 0 12 13 14 15 0 0 0 0 SRC W RESET: 0 0 0 0 0 0 0 0 0 0 0 0 1 1 Figure 6-92. RSTOUT Pad Configuration Register (SIU_PCR230) See Table 6-18 for bit field definitions. 6.4.1.13 GPIO Pin Data Output Registers 0–213 (SIU_GPDOn) The definition of the 8-bit SIU_GPDOn registers, with each register specifying the drive data for a single GPIO pin, is given in Figure 6-93. The n notation in the name of the SIU_GPDOn registers corresponds to the pins with the same GPIO pin numbers. For example, PDO[213] is the pin data output bit for the WKPCFG_GPIO[213] pin, and you select it in SIU_GPDO213. The GPDO address for a pin is the SIU_BASE + 0x0600 plus the GPIO pin number. The SIU_GPDOn registers are written to by software to drive data out on the external GPIO pin. Each register drives a single external GPIO pin, which allows the state of the pin to be controlled independently from other GPIO pins. Writes to the SIU_GPDOn registers have no effect on pin states if the pins are configured as inputs by the associated Pad Configuration Registers. The SIU_GPDOn register values are automatically driven to the GPIO pins without software update if the direction of the GPIO pins is changed from input to output. When the pins are configured for the primary function, writes to the SIU_GPDOn registers have no effect on the state of these pins. Address: SIU_BASE + (0x0600 + n) R Access: R/W 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 PDOn W Reset 0 0 0 0 0 0 0 0 Figure 6-93. GPIO Pin Data Output Register 0–213 (SIU_GPDOn) Table 6-24. SIU_GPDOn Field Descriptions Name Description PDOn Pin data out. Stores the data to be driven out on the external GPIO pin associated with the register. If the register is read, it returns the value written. 0 VOL is driven on the external GPIO pin when the pin is configured as an output. 1 VOH is driven on the external GPIO pin when the pin is configured as an output. MPC5533 Microcontroller Reference Manual, Rev. 0 6-64 Freescale Semiconductor 6.4.1.14 GPIO Pin Data Input Registers 0–213 (SIU_GPDIn) The definition of the 8-bit SIU_GPDIn registers, with each register specifying the drive data for a single GPIO pin, is given in Figure 6-94. The n notation in the name of the 155 SIU_GPDIn registers corresponds to the pins with the same GPIO pin numbers. For example, PDI0 is the pin data input bit for the CS[0]_GPIO[0] pin and is found in SIU_GPDI0, and PDI213 is the pin data input bit for the WKPCFG_GPIO213 pin and is found in SIU_GPDI213. The GPDI address for a pin is the SIU_BASE + 0x0800 plus the GPIO pin number. Gaps exist in the memory addresses for pins that are not available in the 208 or 324 packages. The SIU_GPDIn registers are read-only registers that allow software to read the input state of an external GPIO pin. Each register represents the input state of a single external GPIO pin. If the GPIO pin is configured as an output, and the input buffer enable (IBE) bit is set in the pad configuration register (PCR), the SIU_GPDIn register reflects the actual state of the output pin. Address: SIU_BASE + (0x0800 + n) R Access: R/O 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 PDIn 0 0 0 0 0 0 0 0 W Reset Figure 6-94. GPIO Pin Data Input Register 0–213 (SIU_GPDIn) Table 6-25. SIU_GPDIn Field Description 1 2 6.4.1.15 Name Description PDIn Pin data in. This bit reflects the input state on the external GPIO pin associated with the register. See the device Data Sheet for VIL and VIH definitions. If PCRn[IBE] = 1, then: 0 Signal on pin is less than or equal to VIL.1 1 Signal on pin is greater than or equal to VIH.2 See the MPC5533 Microcontroller Data Sheet for details on VIL. See the MPC5533 Microcontroller Data Sheet for details on VIH. eQADC Trigger Input Select Register (SIU_ETISR) The SIU_ETISR selects the source for the eQADC trigger inputs. The eQADC trigger numbers 0–5 specified by TSEL(0–5) correspond to CFIFO numbers 0–5. To calculate the CFIFO number that each trigger is connected to, divide the DMA channel number by 2. So, for example, eQADC CFIFO 1 (connected to DMA channel 2) can be triggered by eTPUA[31]. To select a trigger, the TSEL must be initialized. When an eQADC trigger is connected, the timer output is connected to the eQADC CFIFO trigger input. To trigger the eQADC, the eTPU output must change to the state that the eQADC recognizes as a trigger. There are rising- or falling-edges, and low- or high-gated trigger types, so it is possible to trigger the eQADC immediately if desired. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 6-65 Table 6-26. Trigger Interconnections TSEL Field (Trigger Number) eQADC CFIFO EQADC DMA Channel eTPUA Channel 0 0 0 eTPUA30 1 1 2 eTPUA31 2 2 4 eTPUA29 3 3 6 eTPUA28 4 4 8 eTPUA27 5 5 10 eTPUA26 Address: SIU_BASE + 0x0900 0 1 2 Access: R/W 3 4 5 6 7 8 9 10 11 R TSEL5 TSEL4 TSEL3 TSEL2 TSEL1 12 13 14 15 0 0 0 0 TSEL0 W Reset R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset Figure 6-95. eQADC Trigger Input Select Register (SIU_ETISR) Table 6-27. SIU_ETISR Field Descriptions Bits Name Description 0–1 TSEL5 [0:1] eQADC trigger input select 5. Specifies the input for eQADC trigger 5. 00 GPIO[207] 01 ETPUA[26] channel 10 Invalid value 11 Invalid value 2–3 TSEL4 [0:1] eQADC trigger input select 4. Specifies the input for eQADC trigger 4. 00 GPIO[206] 01 ETPUA[27] channel 10 Invalid value 11 Invalid value 4–5 TSEL3 [0:1] eQADC trigger input select 3. Specifies the input for eQADC trigger 3. 00 GPIO[207] 01 ETPUA[28] channel 10 Invalid value 11 Invalid value MPC5533 Microcontroller Reference Manual, Rev. 0 6-66 Freescale Semiconductor Table 6-27. SIU_ETISR Field Descriptions (Continued) Bits Name 6–7 TSEL2 [0:1] eQADC trigger input select 2. Specifies the input for eQADC trigger 2 00 GPIO[206] 01 ETPUA[29] channel 10 Invalid value 11 Invalid value 8–9 TSEL1 [0:1] eQADC trigger input select 1. Specifies the input for eQADC trigger 1 00 GPIO[207] 01 ETPUA[31] channel 10 Invalid value 11 Invalid value 10–11 TSEL0 [0:1] eQADC trigger input select 0. Specifies the input for eQADC trigger 0 00 GPIO[206] 01 ETPUA[30] channel 10 Invalid value 11 Invalid value 12–31 — 6.4.1.16 Description Reserved External IRQ Input Select Register (SIU_EIISR) The SIU_EIISR selects the source for the external interrupt/DMA inputs. Address: SIU_BASE + 0x0904 0 1 2 Access: R/W 3 4 5 6 7 8 9 10 11 12 13 14 15 R ESEL15 ESEL14 ESEL13 ESEL12 ESEL11 ESEL10 ESEL9 ESEL8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 0 W Reset R ESEL7 ESEL5 ESEL4 ESEL3 ESEL2 ESEL1 ESEL0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 6-96. External IRQ Input Select Register 1 (SIU_EIISR) MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 6-67 Table 6-28. SIU_EIISR Field Descriptions Bits Name Description 0–1 ESEL15 [0:1] External IRQ input select 15. Specifies the input for IRQ [15]. 00 IRQ[15] pin 01 Invalid value 10 PCSC[0] serialized input (ETPUA[12] pin) 11 PCSD[1] serialized input (ETPUA[20] pin) 2–3 ESEL14 [0:1] External IRQ input select 14. Specifies the input for IRQ[14]. 00 IRQ[14] pin 01 Invalid value 10 PCSC[15] serialized input (ETPUA[11] pin) 11 PCSD[0] serialized input (ETPUA[21] pin) 4–5 ESEL13 [0:1] External IRQ input select 13. Specifies the input for IRQ[13]. 00 IRQ[13] pin 01 Invalid value 10 PCSC[14] serialized input (ETPUA[10] pin) 11 PCSD[15] serialized input (ETPUA[24] pin) 6–7 ESEL12 [0:1] External IRQ input select 12. Specifies the input for IRQ12]. 00 IRQ[12] pin 01 Invalid value 10 PCSC[13] serialized input (ETPUA[9] pin) 11 PCSD[14] serialized input (ETPUA[25] pin) 8–9 ESEL11 [0:1] External IRQ input select 11. Specifies the input for IRQ[11]. 00 IRQ[11] pin 01 Invalid value 10 PCSC[12] serialized input (ETPUA[8] pin) 11 PCSD[13] serialized input (ETPUA[26] pin) 10–11 ESEL10 [0:1] External IRQ input select 10. Specifies the input for IRQ[10]. 00 IRQ[10] pin 01 Invalid value 10 PCSC[11] serialized input (ETPUA[7] pin) 11 PCSD[12] serialized input (ETPUA[27] pin) 12–13 ESEL9 [0:1] External IRQ input select 9. Specifies the input for IRQ[9]. 00 IRQ[9] pin 01 Invalid value 10 PCSC[10] serialized input (ETPUA[6] pin) 11 PCSD[11] serialized input (ETPUA[28] pin) 14–15 ESEL8 [0:1] External IRQ input select 8. Specifies the input for IRQ[8]. 00 IRQ[8] pin 01 Invalid value 10 PCSC[9] serialized input (ETPUA[5] pin) 11 PCSD[10] serialized input (ETPUA[29] pin) 16–17 ESEL7 [0:1] External IRQ input select 7. Specifies the input for IRQ[7]. 00 IRQ[7] pin 01 Invalid value 10 PCSC[8] serialized input (ETPUA[4] pin) 11 Invalid value MPC5533 Microcontroller Reference Manual, Rev. 0 6-68 Freescale Semiconductor Table 6-28. SIU_EIISR Field Descriptions (Continued) Bits Name 18–19 ESEL6 [0:1] Although the IRQ[6] pin is not available, ESEL6 selects other inputs for the internal IRQ[6] signal. 00 Invalid value 01 Invalid value 10 PCSC[7] serialized input (ETPUA[3] pin) 11 Invalid value 20–21 ESEL5 [0:1] External IRQ input select 5. Specifies the input for IRQ[5]. 00 IRQ[5] 01 Invalid value 10 PCSC[6] serialized input (ETPUA[2] pin) 11 Invalid value 22–23 ESEL4 [0:1] External IRQ input select 4. Specifies the input for IRQ[4]. 00 IRQ[4] pin 01 Invalid value 10 PCSC[5] serialized input (ETPUA[1] pin) 11 Invalid value 24–25 ESEL3 [0:1] External IRQ input select 3. Specifies the input for IRQ[3]. 00 IRQ[3] pin 01 Invalid value 10 PCSC[4] serialized input (ETPUA[0] pin) 11 PCSD[5] serialized input (ETPUA[16] pin) 26–27 ESEL2 [0:1] External IRQ input select 2. Specifies the input for IRQ[2]. 00 IRQ[2] pin 01 Invalid value 10 PCSC[3] serialized input (ETPUA[15] pin) 11 PCSD[4] serialized input (ETPUA[17] pin) 28–29 ESEL1 [0:1] External IRQ input select 1. Specifies the input for IRQ[1]. 00 IRQ[1] pin 01 Invalid value 10 PCSC[2] serialized input (ETPUA[14] pin) 11 Invalid value 30–31 ESEL0 [0:1] External IRQ input select 0. Specifies the input for IRQ[0]. 00 IRQ[0] pin 01 Invalid value 10 PCSC[1] serialized input (ETPUA[5] pin) 11 Invalid value 6.4.1.17 Description DSPI Input Select Register (SIU_DISR) The SIU_DISR specifies the source of each DSPI data input, slave select, clock input, and trigger input to allow serial and parallel chaining of the DSPI modules. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 6-69 Address: SIU_BASE + 0x0908 R Access: R/W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 W Reset R SINSELC SSSELC 0 0 SCKSELC TRIGSELC SINSELD SSSELD 0 0 SCKSELD TRIGSELD W Reset 0 0 0 0 0 0 0 0 0 0 0 0 Figure 6-97. DSPI Input Select Register (SIU_DISR) Table 6-29. SIU_DISR Field Descriptions Bits Name Description 0–15 0 16–17 SINSELC [0:1] SINC data input select. Specifies the source of the SINC data input. 00 SINC_GPIO[108] pin01Invalid value 10 Invalid value 11 SOUTD 18–19 SSSELC [0:1] PCSC slave select input select. Specifies the source of the PCSC slave select input. 00 PCSC[0]_GPIO[110] pin 01 Invalid value 10 Invalid value 11 PCSD[0] (Master) 20–21 SCKSELC [0:1] PCSC clock input select. Specifies the source of the PCSC clock input when in slave mode. 00 SCKC_GPIO[109] pin 01 Invalid value 10 Invalid value 11 SCKD (Master) 22–23 TRIGSELC [0:1] PCSC trigger input select. Specifies the source of the PCSC trigger input for master or slave mode. 00 Invalid value 01 Invalid value 10 Invalid value 11 PCSD[4] 24–25 SINSELD [0:1] Reserved SIND data input select. Specifies the source of the SIND data input. 00 SIND_GPIO[99] pin01Invalid value 10 Invalid value 11 SOUTC MPC5533 Microcontroller Reference Manual, Rev. 0 6-70 Freescale Semiconductor Table 6-29. SIU_DISR Field Descriptions (Continued) Bits Name 26–27 SSSELD [0:1] PCSD slave select input select. Specifies the source of the PCSD slave select input. 00 PCSD[0]_GPIO[106] pin 01 Invalid value 10 Invalid value 11 PCSC[0] (Master) 28–29 SCKSELD [0:1] PCSD clock input select. Specifies the source of the PCSD clock input in slave mode. 00 SCKD_GPIO[98] pin 01 Invalid value 10 Invalid value 11 SCKC (Master) 30–31 TRIGSELD [0:1] PCSD trigger input select. Specifies the source of the PCSD trigger input for master or slave mode. 00 Invalid value 01 Invalid value 10 Invalid value 11 PCSC[4] 6.4.1.18 Description Chip Configuration Register (SIU_CCR) Address: SIU_BASE + 0x0980 R Access: R/W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 U X1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRSE2 TEST2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MATCH DISNEX1 W Reset R W Reset 1 When system reset negates, the value in this bit depends on the censorship control word and the boot configuration bits. In the 208 package, BOOTCFG[0] is not available due to pin limitation and internally asserted (driven to 0). 2 This bit is reset with a power on reset. Figure 6-98. Chip Configuration Register (SIU_CCR) MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 6-71 Table 6-30. SIU_CCR Field Descriptions Bits Name 0–13 — 14 MATCH Compare register match. Holds the value of the match input signal to the SIU. The match input is asserted if the values in the SIU_CARH and SIU_CARL, and SIU_CBRH and SIU_CBRL are equal. The MATCH bit is reset by the synchronous reset signal. 0 The content of SIU_CARH and SIU_CARL does not match the content of SIU_CBRH and SIU_CBRL 1 The content of SIU_CARH and SIU_CARL matches the content of SIU_CBRH and SIU_CBRL 15 DISNEX Disable Nexus. Holds the value of the Nexus disable input signal to the SIU. When system reset negates, the value in this bit depends on the censorship control word and the boot configuration bits. 0 Nexus disable input signal is negated. 1 Nexus disable input signal is asserted. 16–30 — 31 TEST 6.4.1.19 Description Reserved Reserved Test mode enable. Allows reads or writes to undocumented registers used only for production tests. Since these production test registers are undocumented, estimating the impact of errant accesses to them is impossible. The application must not change this bit from its negated state at reset. 0 Undocumented production test registers can not be read or written. 1 Undocumented production test registers can be read or written. External Clock Control Register (SIU_ECCR) The SIU_ECCR controls the timing relationship between the system clock and the external clocks ENGCLK and CLKOUT. All bits and fields in the SIU_ECCR are read/write and are reset by the synchronous reset signal. CLKOUT is not available due to pin limitations. 208 Package: Address: SIU_BASE + 0x0984 R Access: R/W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 0 0 0 0 0 W Reset R ENGDIV 0 EBTS EBDF W Reset 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 Figure 6-99. External Clock Control Register (SIU_ECCR) MPC5533 Microcontroller Reference Manual, Rev. 0 6-72 Freescale Semiconductor Table 6-31. SIU_ECCR Field Descriptions Bits Name 0–17 — 18–23 ENGDIV [0:5] Description Reserved Engineering clock division factor. Specifies the frequency ratio between the system clock and ENGCLK. The ENGCLK frequency is divided from the system clock frequency according to the following equation: System clock frequency Engineering clock frequency = --------------------------------------------------------------ENGDIV × 2 Note: Clearing ENGDIV to 0 is reserved. Synchronization between ENGCLK and CLKOUT cannot be guaranteed. 24–27 — 28 EBTS 29 — 30–31 EBDF [0:1] 6.4.1.20 Reserved External bus tap select. Changes the phase relationship between the system clock and CLKOUT. Changing the phase relationship so that CLKOUT is advanced in relation to the system clock increases the output hold time of the external bus signals to a non-zero value. It also increases the output delay times, increases the input hold times to non-zero values, and decreases the input setup times. See the Electrical Specifications for how the EBTS bit affects the external bus timing. 0 External bus signals have zero output hold times. 1 External bus signals have non-zero output hold times. Note: Do not modify the EBTS bit while an external bus transaction is in progress. Reserved External bus division factor. Specifies the frequency ratio between the system clock and the external clock, CLKOUT. The EBDF field must not be changed during an external bus access or while an access is pending. The CLKOUT frequency is divided from the system clock frequency according to the descriptions below. This divider must be kept as divide-by-2 when operating in dual controller mode. 00 Divide by 1 01 Divide by 2 10 Invalid value 11 Divide by 4 Note: The reset value of the EBDF field is divide-by-2. After reset, if EBDF is changed to divided-by-1, no glitches occur on the CLKOUT signal. If EBDF is changed back to divide-by-2 or divide-by-4, glitches can occur during the switch. Note: CLKOUT is not available in the 208 package due to pin limitations. Compare A High Register (SIU_CARH) The compare registers are not intended for general application use, but are used temporarily by the BAM during boot and intended optionally for communication with calibration tools. After reset, calibration tools can immediately write a non-zero value to these registers. The application code, using the registers then as read only, can read them to determine if a calibration tool is attached and operate appropriately. The compare registers can be used just like 128 bits of memory mapped RAM that is always zero out of reset, or they can perform a 64 bit to 64 bit compare. The compare function is continuous (combinational logic - not requiring a start or stop). The compare result appears in the MATCH bit in the SIU_CCR register. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 6-73 The SIU_CARH holds the 32-bit value that is compared against the value in the SIU_CBRH register. The CMPAH field is read/write and is reset by the synchronous reset signal. Address: SIU_BASE + 0x0988 0 1 2 Access: R/W 3 4 5 6 7 8 9 10 11 12 13 14 15 R CMPAH W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 0 0 0 0 0 0 R CMPAH W Reset 0 0 0 0 0 0 0 0 0 Figure 6-100. Compare A High Register (SIU_CARH) 6.4.1.21 Compare A Low Register (SIU_CARL) The SIU_CARL register holds the 32-bit value that is compared against the value in the SIU_CBRL register. The CMPAL field is read/write and is reset by the synchronous reset signal. Address: SIU_BASE + 0x098C 0 1 2 Access: R/W 3 4 5 6 7 8 9 10 11 12 13 14 15 R CMPAL W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 0 0 0 0 0 0 R CMPAL W Reset 0 0 0 0 0 0 0 0 0 Figure 6-101. Compare A Low Register (SIU_CARL) 6.4.1.22 Compare B High Register (SIU_CBRH) The SIU_CBRH holds the 32-bit value that is compared against the value in the SIU_CARH. The CMPBH field is read/write and is reset by the synchronous reset signal. MPC5533 Microcontroller Reference Manual, Rev. 0 6-74 Freescale Semiconductor Address: SIU_BASE + 0x0990 0 1 2 Access: R/W 3 4 5 6 7 8 9 10 11 12 13 14 15 R CMPBH W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 0 0 0 0 0 0 R CMPBH W Reset 0 0 0 0 0 0 0 0 0 Figure 6-102. Compare B High Register (SIU_CBRH) 6.4.1.23 Compare B Low Register (SIU_CBRL) The SIU_CBRL holds the 32-bit value that is compared against the value in the SIU_CARL. The CMPBL field is read/write and is reset by the synchronous reset signal. Address: SIU_BASE + 0x0994 0 1 2 Access: R/W 3 4 5 6 7 8 9 10 11 12 13 14 15 R CMPBL W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 0 0 0 0 0 0 R CMPBL W Reset 0 0 0 0 0 0 0 0 0 Figure 6-103. Compare B Low Register (SIU_CBRL) 6.5 Functional Description The following sections provide an overview of the SIU operation. 6.5.1 6.5.1.1 System Configuration Boot Configuration The BOOTCFG[0:1] pins are used to determine the boot mode initiated by the BAM program, and whether external arbitration is selected for external booting. The BAM program uses the BOOTCFG field to determine where to read the reset configuration word, and whether to initiate a FlexCAN or eSCI boot. See Section 15.3.2.3.4, “Read the Reset Configuration Halfword” of the BAM chapter for detail on the RCHW. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 6-75 Table 6-32 defines the boot modes specified by the BOOTCFG[0:1] pins. If the RSTCFG pin is asserted during the assertion of RSTOUT, except in the case of a software external reset, the BOOTCFG pins are latched 4 clock cycles prior to the negation of the RSTOUT pin and are used to update the SIU_RSR and the BAM boot mode. Otherwise, if RSTCFG is negated during the assertion of RSTOUT, the BOOTCFG pins are ignored and the device defaults to ‘boot from internal flash memory’ mode. 208 Package: BOOTCFG[0] and RSTCFG are not available due to pin limitations and are internally asserted (driven to 0) in the 208 package. Table 6-32. BOOTCFG[0:1] Configuration 6.5.1.2 Value Meaning 0b00 Boot from internal flash memory 0b01 FlexCAN or eSCI boot 0b10 Boot from external memory (no arbitration) 0b11 Invalid value Pad Configuration The pad configuration registers (SIU_PCR) in the SIU allow software control of the static electrical characteristics of external pins. The pad configuration registers allow control over the following external pin characteristics: • Weak pull up/down enable/disable • Weak pull up/down selection • Slew-rate selection for outputs • Drive strength selection for outputs • Input buffer enable (when direction is configured for output) • Input hysteresis enable/disable • Open drain/push-pull output selection • Multiplexed function selection • Data direction selection The pad configuration registers are provided to allow centralized control over external pins that are shared by more than one module. Each pad configuration register controls a single pin. 6.5.2 Reset Control The reset controller logic is located in the SIU. See Chapter 4, “Reset” for detail on reset operation. 6.5.2.1 RESET Pin Glitch Detect The reset controller provides a glitch detect feature on the RESET pin. If the reset controller detects that the RESET pin is asserted for more than two clock cycles, the event is latched. Once the latch is set, if the RESET pin is negated before 10 clock cycles completes the reset controller sets the RGF bit without affecting any of the other bits in the reset status register. The latch is cleared when the RGF bit is set or a MPC5533 Microcontroller Reference Manual, Rev. 0 6-76 Freescale Semiconductor valid reset is recognized. The RGF bit remains set until cleared by software or the RESET pin is asserted for 10 clock cycles. The reset controller does not respond to assertions of the RESET pin if a reset cycle is already being processed. 6.5.3 External Interrupt There are sixteen external interrupt inputs IRQ[0:15] to the SIU. The IRQ[n] inputs can be configured for rising or falling edge events or both. Each IRQ[n] input has a corresponding flag bit in the external interrupt status register (SIU_EISR). The flag bits for the IRQ[4:15] inputs are ORed together to form one interrupt request to the interrupt controller (OR function performed in the integration glue logic). The flag bits for the IRQ[0:3] inputs can generate either an interrupt request to the interrupt controller or a DMA transfer request to the DMA controller. Table 6-104 shows the DMA and interrupt request connections to the interrupt and DMA controllers. The SIU contains an overrun request for each IRQ and one combined overrun request which is the logical OR of the individual overrun requests. Only the combined overrun request is used in the device, and the individual overrun requests are not connected. Each IRQ pin has a programmable filter for rejecting glitches on the IRQ signals. The filter length for the IRQ pins is specified in the external IRQ digital filter register (SIU_IDFR). NOTE IRQ[2] signal is not available due to pin limitations and is internally asserted (driven to 0) on the 208 package. IRQ[6] signal is not available in this device, however the IRQ[6] signal is available internally. DMA Request SIU SIU_EISR EIRQ Pins or Internal Source • • • IMUX • • • 0 1 2 3 4 • • • 15 SIU_DIRSR DMA/ Interrupt Select Interrupt Request • • • Interrupt Controller • • SIU_OSR 0 1 • • • DMA • • • Interrupt Request • • 15 Overrun Request Figure 6-104. SIU DMA/Interrupt Request Diagram MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 6-77 6.5.4 GPIO Operation All GPIO functionality is provided by the SIU for the device. Each device pin that has GPIO functionality has an associated pin configuration register in the SIU where the GPIO function is selected for the pin. In addition, each device pin with GPIO functionality has an input data register (SIU_GPDIn) and an output data register (SIU_GPDOn). 6.5.5 Internal Multiplexing The internal multiplexing select registers SIU_ETISR, SIU_EIISR, and SIU_DISR provide selection of the source of the input for the eQADC external trigger inputs, the SIU external interrupts, and the DSPI signals that are used in serial and parallel chaining of the DSPI modules. Internal multiplexing allows you to select the input for multiplexed external signals. For each field of each of the select registers, a multiplexor exists in the SIU. The inputs and outputs of the multiplexors are external signals to and from the SIU.A block diagram of the internal multiplexing feature is given in Figure 6-105. The figure shows the multiplexing of four external signals to an output from the SIU. A two bit SEL field from an SIU select register is used to select the input of the multiplexor. SIU From chip-level signals external to the SIU To chip-level signal external to the SIU SIU_ETISR, SIU_EIISR, and SIU_DISR Figure 6-105. Four-to-One Internal Multiplexing Block Diagram 6.5.5.1 eQADC External Trigger Input Multiplexing The eQADC external trigger inputs can be connected to an external pin, eTPU channel. The input source for each eQADC external trigger is individually specified in the eQADC trigger input select register (SIU_ETISR). An example of the multiplexing of an eQADC external trigger input is given in Figure 6-106. As shown in the figure, the GPIO[206] input of the eQADC can be connected to the ETPUA[30] channel. The remaining trigger inputs are multiplexed in the same manner (see Section 6.4.1.15, “eQADC Trigger Input Select Register (SIU_ETISR)” for the SIU_ETISR[TSEL0]–SIU_ETISR[TSEL5] bit definitions). If an external input trigger is connected to an eTPU channel, the external pin used by that channel can be used by the alternate function on that pin. MPC5533 Microcontroller Reference Manual, Rev. 0 6-78 Freescale Semiconductor GPIO[206] EQADC Trigger ETPUA[30] Output Channel SIU_ETISR[TSEL0] Figure 6-106. eQADC External Trigger Input Multiplexing 6.5.5.2 SIU External Interrupt Input Multiplexing The sixteen SIU external interrupt inputs can be connected to either an external pin or to serialized output signals from a DSPI module. The input source for each SIU external interrupt is individually specified in the external IRQ input select register (SIU_EIISR). An example of the multiplexing of an SIU external interrupt input is given in Figure 6-107. As shown in the figure, the IRQ[0] input of the SIU can be connected to either the IRQ[0]_GPIO[193] pin, the PCSC[1] deserialized output signal, or the PCSD[2] deserialized output signal. The remaining IRQ inputs are multiplexed in the same manner. The inputs to the IRQ from each DSPI module are offset by one so that if more than one DSPI module is connected to the same external device type, a separate interrupt can be generated for each device. This also applies to DSPI modules connected to external devices of different type that have status bits in the same bit location of the deserialized information. GPIO[203] 1 IRQ[0] PCSC[1] Serialized Input PCSD[2] Serialized Input 1 GPIO[203] is not available on the 208 package. ESEL0 ESEL1 Figure 6-107. DSPI Serialized Input Multiplexing 6.5.5.3 Multiplexed Inputs for DSPI Multiple Transfer Operation Each DSPI module can be combined in a serial or parallel chain (multiple transfer operation). Serial chaining allows SPI operation with an external device that has more bits than one DSPI module. An example of a serial chain is shown in Figure 6-108. In a serial chain, one DSPI module operates as a master, the second DSPI modules operate as a slave. The data output (SOUT) of the master is connected to the data input (SIN) of the slave. The SOUT of a slave is connected to the SIN of subsequent slaves until the last module in the chain, where the SOUT is connected to an external pin, which connects to the input of an external SPI device. The slave DSPI and external SPI device use the master peripheral chip select (PCS) and clock (SCK). The trigger input of the master allows a slave DSPI to trigger a transfer when a data change occurs in the slave DSPI and the slave DSPI is operating in Change in Data Mode. The trigger input of the master is connected to MTRIG output of the slave. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 6-79 Parallel chaining allows the PCS and SCK from one DSPI to be used by more than one external SPI device, thus reducing pin utilization of the MCU. An example of a parallel chain is shown in Figure 6-109. In this example, the SOUT and SIN of the two DSPIs connect to separate external SPI devices, which share a common PCS and SCK. To support multiple transfer operation of the DSPIs, an input multiplexor is required for the SIN, SS, SCK IN, and trigger signals of each DSPI. The input source for the SIN input of a DSPI can be a pin or the SOUT of the other DSPI. The input source for the SS input of a DSPI can be a pin or the PCS0 of the other DSPI. The input source for the SCK input of a DSPI can be a pin or the SCK output of the other DSPI. The input source for the trigger input can be the PCSS output of the other DSPI. The input source for each DSPI SIN, SS, SCK, and trigger signal is individually specified in the DSPI input select register (SIU_DISR). MPC5533 PCSC (Master) SIND Trigger MTRIG SCKC SS SOUTD SCKD IN SCKC PCSC[0] SINC PCSC0 SOUTC SOUTD SINC PCSD (Slave) SS SOUT SCK IN External SPI Device SIN Figure 6-108. DSPI Serial Chaining MPC5533 Microcontroller Reference Manual, Rev. 0 6-80 Freescale Semiconductor MPC5533 PCSC (Master) SINC PCSD (Slave) SOUT SIN Trigger MTRIG PCSC0 SCK SS SCK IN SOUT SS SIN SOUT SS SCK IN SCK IN SOUT SIN External SPI Device External SPI Device Figure 6-109. DSPI Parallel Chaining MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 6-81 MPC5533 Microcontroller Reference Manual, Rev. 0 6-82 Freescale Semiconductor Chapter 7 Error Correction Status Module (ECSM) This device includes error-correcting code (ECC) implementations to improve the quality and reliability of internal SRAM and internal flash memories. The error correction status module (ECSM) allows the application to collect data on memory errors reported by the ECC or generic access error information. 7.1 Overview The ECSM provides a set of registers that configure and report ECC errors for the device, including accesses to SRAM and flash memory. The types of memory are: • SRAM—32 data bits plus seven check bits for every 32-bit word • Flash—64 data bits plus eight check bits for every 64-bit doubleword The application must: 1. Configure the ECC for the types of memory errors to report. 2. Initialize internal SRAM by performing write operations to the entire SRAM memory before enabling the ECC. Flash memory does not require this step. See Section 7.3, “Initialization and Application Information.” 3. Query a set of read-only status and information registers to identify ECC errors, in response to an enabled ECC error interrupt. 7.1.1 Types of ECC Errors The ECSM is configurable for reporting non-correctable errors, and has registers for capturing ECC information for internal SRAM and flash access errors. The types of ECC errors are: • Correctable error—A correctable ECC error is generated when only one bit is incorrect in the data and ECC check bits. In this case, the bit in error is corrected automatically by hardware, and no flags or other indicators are set by the error that occurred. • Non-correctable error—An ECC non-correctable error is generated when two or more bits in the data and ECC check bits are incorrect. The bus transaction which caused the memory access to produce the non-correctable error terminates with a bus error. If correctly enabled in the ECSM module, non-correctable ECC errors can generate an interrupt and capture additional error details about the access in ECSM registers. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 7-1 7.1.2 ECC Operations ECCs are calculated across the entire width of the data field. The memory controller (flash or SRAM) checks for ECC errors on read accesses, and calculates the ECC check bits on write accesses. ECC operations for system RAM differ depending on the operation and memory: • Read operations are comparable for SRAM and flash memory • Write operations for SRAM and flash memory have major differences Flash memory writes are program events and are managed entirely by the flash memory module. See Chapter 13, “Flash Memory” for information on flash memory write operations. The following write operations apply to SRAM only. Read operation—SRAM and flash memory: 1. Read the data bits that contain the desired byte, halfword, word or doubleword from memory. 2. Calculate the syndrome from the read data and the check bits to determine if a correctable or non-correctable error is present. 3. Return the data bits, error-free or corrected data, to the requesting bus master; or respond with an error termination, and assert an interrupt if necessary. 32-bit write operation—SRAM only: 1. Generate the check bits based on the 32 data bits to be written. 2. Write the 32 data bits plus the check bits to memory. Eight- or 16-bit write operations—SRAM only: 1. Read the data bits that contain the desired byte or halfword from memory. 2. Perform a read ECC check. a) If the read operation is error-free, go to Step 3. b) If a correctable single-bit error is detected, forward the corrected data to Step 3. c) If a non-correctable error is detected, the write operation is not performed and the bus cycle terminates with an error. 3. Merge the write data with the 32-bit read data (error-free or corrected data). 4. Generate the check bits for the destination write data. 5. Write the 32 bits of destination write data plus the check bits to memory. MPC5533 Microcontroller Reference Manual, Rev. 0 7-2 Freescale Semiconductor 7.2 Memory Map and Register Definition Table 7-1 is the memory map for the ECSM registers. Table 7-1. ECSM Memory Map Address Base (0xFFF4_0000) + 0x0016 Base + (0x0018–0x001A) Base + 0x001B Base + (0x001C–0x001E) Base + 0x001F Base + (0x0020–0x0042) Base + 0x0043 Base + (0x0044–0x0046) Base + 0x0047 Base + (0x0048–0x0049) Base + 0x004A Base + (0x004B–0x004F) Base + 0x0050 Base + (0x0054–0x0055) Register Name ECSM_SWTCR Register Description Software watchdog timer control register 1 — ECSM_SWTSR Software watchdog timer service register Software watchdog timer interrupt register Reserved ECC configuration register — ECSM_ESR — ECSM_EEGR — ECSM_FEAR — — 1 8 Reserved — ECSM_ECR 16 Reserved — ECSM_SWTIR Bits Reserved ECC status register — 1 8 — 8 — 8 Reserved ECC error generation register Reserved Flash ECC address register Reserved — 16 — 32 — Base + 0x0056 ECSM_FEMR Flash ECC master register 8 Base + 0x0057 ECSM_FEAT Flash ECC attribute register 8 Base + 0x0058 ECSM_FEDRH Flash ECC data high register 32 Base + 0x005C ECSM_FEDRL Flash ECC data low register 32 Base + 0x0060 ECSM_REAR SRAM ECC address register 32 Base + (0x0064–0x0065) — Reserved — Base + 0x0066 ECSM_REMR SRAM ECC master register 8 Base + 0x0067 ECSM_REAT SRAM ECC attributes register 8 Base + 0x0068 ECSM_REDRH SRAM ECC data high register 32 Base + 0x006C ECSM_REDRL SRAM ECC data low register 32 Base + (0x0070–0x007F) 1 — Reserved — These registers control and configure the software watchdog timer, and are included as part of a standard Freescale ECSM module. Use the core watchdog functions to implement watchdog capabilities rather than these registers. See Section 7.2.1.1, “Software Watchdog Timer Registers: Control, Service, and Interrupt (ECSM_SWTCR, ECSM_SWTSR, and ECSM_SWTIR).” MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 7-3 7.2.1 Register Descriptions The following limitations apply to ECC accesses: • Attempted accesses to reserved addresses result in an error termination. • Attempted writes to read-only registers are ignored and do not terminate with an error. • Writes to the programming model must match the size of the register unless noted otherwise; for example, an n-bit register only supports n-bit writes. Attempted writes greater or less than the register width produce an error termination of the bus cycle and no change to the targeted register. 7.2.1.1 Software Watchdog Timer Registers: Control, Service, and Interrupt (ECSM_SWTCR, ECSM_SWTSR, and ECSM_SWTIR) The core provides watchdog functions for flexible watchdog implementation. Use the core watchdog functions to optimize code portability to other Power Architecture-based products in the MPC5500 family. See the core reference manual for information on the core watchdog timer functions. These ECSM read-only registers control and configure the ESCM software watchdog timer that is included as part of the Freescale standard for this device: Table 7-2. ECSM Register Domains Domain ECSM Register Name Software Watchdog Register Purpose ECSM_SWTCR ECSM Watchdog Timer Control ECSM_SWTSR ECSM Watchdog Timer Service ECSM_SWTIR ECSM Watchdog Timer Interrupt NOTE DO NOT change the reset values in the ECSM software watchdog registers. Any change to the reset values can cause an ECSM_SWTIR_SWTIC interrupt. 7.2.1.2 ECC Registers The ECSM registers in Table 7-3 are visible to application software, and allow you to configure the data reported and log ECC memory failures. Table 7-3. ECSM Register Domains Domain Global Reporting ECSM Register Name Register Purpose ECSM_ECR ECC configuration ECSM_ESR ECC status ECSM_EEGR ECC error generation MPC5533 Microcontroller Reference Manual, Rev. 0 7-4 Freescale Semiconductor Table 7-3. ECSM Register Domains (Continued) Domain ECSM Register Name Register Purpose ECSM_FEAR Flash ECC address ECSM_FEMR Flash ECC master number ECSM_FEAT Flash ECC attributes ECSM_FEDR Flash ECC data ECSM_REAR SRAM ECC address ECSM_REMR SRAM ECC master number ECSM_REAT SRAM ECC attributes ECSM_REDR SRAM ECC data Flash Reporting SRAM Reporting The details of each ECC register are described in the following sections. 7.2.1.3 ECC Configuration Register (ECSM_ECR) ECSM_ECR is an 8-bit control register that enables or disables ECC error reporting during internal SRAM and flash accesses. In addition to the interrupt generation, the ECSM captures specific information (memory address, attributes and data, bus master number, etc.) that is useful for failure analysis. The ECC reporting logic can detect non-correctable memory errors. When a non-correctable error terminates the current access to the memory (flash or SRAM), an error condition is generated. In many cases, the error termination is reported directly by the initiating bus master. Base (0xFFF4_0000) + 0x0043 R Access: R/W 0 1 2 3 4 5 0 0 0 0 0 0 6 7 ERNCR EFNCR 0 0 W Reset 0 0 0 0 0 0 Figure 7-1. ECC Configuration Register (ECSM_ECR) MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 7-5 The following table describes the fields in the error configuration register: Table 7-4. ECSM_ECR Field Definitions Field 0–5 Description Reserved 6 ERNCR Enable internal SRAM non-correctable reporting. When this bit is set (enabled), a non-correctable multi-bit internal SRAM error sets the ECSM_ESR[RNCE] bit in the ECC status register, which generates an ECSM ECC internal SRAM interrupt. The faulting address, attributes and data are also captured in the REAR, REMR, REAT and REDR registers. 0 Reporting of non-correctable internal SRAM errors is disabled. 1 Reporting of non-correctable internal SRAM errors is enabled. 7 EFNCR Enable flash non-correctable reporting. When this bit is set (enabled), a non-correctable multi-bit flash error sets the ECSM_ESR[FNCE] bit in the ECC status register, which generates an ECSM ECC flash interrupt. The faulting address, attributes and data are also captured in the FEAR, FEMR, FEAT and FEDR registers. 0 Reporting of non-correctable flash errors is disabled. 1 Reporting of non-correctable flash errors is enabled. 7.2.1.4 ECC Status Register (ECSM_ESR) The ECC status register (ECSM_ESR) is an 8-bit control register that defines the types of ECC events detected. The ESR indicates the last, correctly-enabled memory event detected. The ECSM ECC interrupt request is generated as defined by the boolean equation: ECSM_ECC_IRQ = ECSM_ECR[ERNCR] & ECSM_ESR[RNCE] | ECSM_ECR[EFNCR] & ECSM_ESR[FNCE] // ram, noncorrectable error // flash, noncorrectable error where the combination of the following criteria generates the interrupt request: • Correctly enabled category in the ECSM_ECR; and • Condition in the ECSM_ESR detected. The ECSM allows a maximum of one bit of the ECSM_ESR to assert at any given time. This preserves the relationship of the ECSM_ESR to the address and attribute registers, which are loaded for each enabled ECC event. If an ECC interrupt is pending and another enabled ECC event occurs, the ECSM hardware automatically performs ECSM_ESR reporting by clearing the previous data, and then loading the new status, which ensures that only a single flag is asserted. To maintain a coherent software view of the reported event, use the following sequence in the ECSM error interrupt service routine: 1. Read the ECSM_ESR and save it. 2. Read and save all the address and attribute reporting registers. 3. Re-read the ECSM_ESR and verify the current contents matches the original contents. If the two values differ, return to step 1 and repeat this sequence. 4. When the values are identical, write a 1 to the asserted ECSM_ESR flag to negate the interrupt request. If multiple status flags are detected simultaneously, the ECSM records the higher priority SRAM non-correctable error (RNCE) events before flash non-correctable error (FNCE) events. MPC5533 Microcontroller Reference Manual, Rev. 0 7-6 Freescale Semiconductor Base + 0x0047 R Access: R/W1c 0 1 2 3 4 5 6 7 0 0 0 0 0 0 RNCE FNCE w1c w1c 0 0 W Reset 0 0 0 0 0 0 Figure 7-2. ECC Status Register (ECSM_ESR) Table 7-5. ECSM_ESR Field Definitions Field 0–5 Description Reserved 6 RNCE SRAM non-correctable error. A non-correctable SRAM error occurs, generates an ECSM ECC interrupt request. The faulting address, attributes and data are also captured in the REAR, REMR, REAT and REDR registers. To clear this interrupt flag, write a 1 to this bit. Writing a 0 has no effect. 0 No reportable non-correctable SRAM error has been detected. 1 A reportable non-correctable SRAM error has been detected. 7 FNCE Flash non-correctable error. The occurrence of a correctly-enabled non-correctable flash error generates an ECSM ECC interrupt request. The faulting address, attributes and data are also captured in the FEAR, FEMR, FEAT and FEDR registers. To clear this interrupt flag, write a 1 to this bit. Writing a 0 has no effect. 0 No reportable non-correctable flash error has been detected. 1 A reportable non-correctable flash error has been detected. 7.2.1.5 ECC Error Generation Register (ECSM_EEGR) The ECSM_EEGR is a 16-bit control register used to generate double-bit data errors in internal SRAM. This allows you to test the software service routines for memory error logging. By generating errors during data write cycles, subsequent reads of the corrupt address locations generate ECC events, such as double-bit noncorrectable errors that are terminated with an error response. If an attempt to force a non-correctable error (by asserting ECSM_EEGR[FRCNCI] or ECSM_EEGR[FRC1NCI]) and the ECSM_EEGR[ERRBIT] equals 64, then no data error is generated. NOTE Only values {0,0}, {1,0} and {0,1} are allowed for the two control bit enables {FRCNCI, FR1NCI}. The value {1,1} causes undefined results. Base + 0x004A R Access: R/W 0 1 2 3 4 5 6 7 8 0 0 0 0 0 0 FRC NCI FR1 NCI 0 0 0 0 W Reset 0 0 0 0 0 0 9 10 11 12 13 14 15 0 0 ERRBIT[0:6] 0 0 0 0 0 Figure 7-3. ECC Error Generation (ECSM_EEGR) Register MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 7-7 Table 7-6. ECSM_EEGR Field Definitions Field 0–5 Description Reserved 6 Force internal SRAM continuous noncorrectable data errors. FRCNCI 0 No internal SRAM continuous 2-bit data errors are generated. 1 2-bit data errors in the internal SRAM are continuously generated. When this bit is cleared: 1. The RAM controller generates a normal ECC 2. The polarity of the bit position specified in ERRBIT plus the overall odd parity bit are inverted to introduce a 2-bit ECC error in internal SRAM. When this bit is set: 1. The internal SRAM controller generates 2-bit data errors, as defined by the bit position specified in ERRBIT[0:6] and the overall odd parity bit, on every write operation. 7 Force internal SRAM one noncorrectable data errors. FR1NCI 0 No internal SRAM single 2-bit data errors are generated. 1 One 2-bit data error in internal SRAM is generated. When this bit is cleared, the RAM controller generates a normal ECC, but then the polarity of the bit position defined by ERRBIT and the overall odd parity bit are inverted to introduce a 2-bit ECC error in the internal SRAM. When this bit is set, the internal SRAM controller generates 2-bit data errors, as defined by the bit position specified in ERRBIT[0:6] and the overall odd parity bit, on every write operation. The assertion of this bit forces the internal SRAM controller to create one 2-bit data error, as defined by the bit position specified in ERRBIT[0:6] and the overall odd parity bit, on the first write operation after this bit is set. The normal ECC generation takes place in the internal SRAM controller, but then the polarity of the bit position defined by ERRBIT and the overall odd parity bit are inverted to introduce a 2-bit ECC error in the internal SRAM. After this bit has been enabled to generate a single 2-bit error, it must be cleared before being set again to correctly re-enable the error generation logic. 8 Reserved 9–15 Error bit position. Defines the bit position which is complemented to create the data error on the write operation. The ERRBIT bit specified by this field plus the odd parity bit of the ECC code are inverted. The internal SRAM controller follows a vector bit ordering scheme where LSB=0. Errors in the ECC check bits can be generated by setting this field to a value greater than the internal SRAM width. The following association between the ERRBIT field and the corrupted memory bit is defined: if ERRBIT = 0, then internal SRAM[0] is inverted if ERRBIT = 1, then internal SRAM[1] is inverted ... if ERRBIT = 31, then internal SRAM[31] is inverted if ERRBIT = 32, then ECC Parity[0] is inverted if ERRBIT = 33, then ECC Parity[1] is inverted ... if ERRBIT = 39, then ECC Parity[7] is inverted For ERRBIT values greater than 39, no bit position is inverted. 7.2.1.6 Flash ECC Address Register (ECSM_FEAR) The ECSM_FEAR is a 32-bit register for capturing the address of the last, correctly-enabled ECC event in the flash memory. Depending on the state of the ECSM_ECR, an ECC event in the flash loads the address, attributes and data of the access into the ECSM_FEAR, ECSM_FEMR, ECSM_FEAT, and ECSM_FEDR registers, and asserts the F1BC or FNCE flag in ECSM_ESR. MPC5533 Microcontroller Reference Manual, Rev. 0 7-8 Freescale Semiconductor The address that is captured in ECSM_FEAR is the flash page address as seen on the system bus. See Section 13.3.2.7, “Address Register FLASH_AR” to retrieve the doubleword address. Base + 0x0050 Access: Read 0 1 2 3 4 5 6 7 R 8 9 10 11 12 13 14 15 FEAR W Reset 1 U U U U U U U U U U U U U U U U 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 U U U U U U U R FEAR W Reset 1 U 1 U U U U U U U U “U” signifies a bit that is uninitialized. Figure 7-4. Flash ECC Address Register (ECSM_FEAR) Table 7-7. ECSM_FEAR Field Descriptions Field Description 0–31 FEAR [0:31] 7.2.1.7 Flash ECC address. Contains the faulting access address of the last, correctly-enabled flash ECC event. Flash ECC Master Number Register (ECSM_FEMR) The FEMR is an 8-bit register for capturing the XBAR bus master number of the last, correctly-enabled ECC event in the flash memory. Depending on the state of the ECSM_ECR, an ECC event in the flash loads the address, attributes and data of the access into the ECSM_FEAR, ECSM_FEMR, ECSM_FEAT and ECSM_FEDR registers, and asserts the FNCE flag in the ECSM_ESR. ECSM Base + 0x0056 R Access: Read 0 1 2 3 0 0 0 0 0 0 0 0 4 5 6 7 U U FEMR W Reset 1 1 U U “U” signifies a bit that is uninitialized. Figure 7-5. Flash ECC Master Number Register (ECSM_FEMR) MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 7-9 Table 7-8. ECSM_FEMR Field Descriptions Field Description 0–3 Reserved 4–7 FEMR [0:3] 7.2.1.8 Flash ECC master number. Contains the XBAR bus master number of the faulting access of the last, correctly-enabled flash ECC event. The reset value of this field is undefined. Flash ECC Attributes Register (ECSM_FEAT) The ECSM_FEAT is an 8-bit register for capturing the XBAR bus master attributes of the last, correctly-enabled ECC event in the flash memory. Depending on the state of the ECSM_ECR register, an ECC event in the flash loads the address, attributes and data of the access into the ECSM_FEAR, ECSM_FEMR, ECSM_FEAT, and ECSM_FEDR registers, and asserts the FNCE flag in ECSM_ESR. Base + 0x0057 Access: Read 0 R 1 2 WRITE 3 SIZE 4 5 6 7 PROT0 PROT1 PROT2 PROT3 U U U U W Reset 1 U 1 U U U “U” signifies a bit that is uninitialized. Figure 7-6. Flash ECC Attributes Register (ECSM_FEAT) Table 7-9. ECSM_FEAT Field Descriptions Field Description 0 WRITE Write. The reset value of this field is undefined. 0 System bus read access 1 System bus write access 1–3 SIZE [0:2] Size. The reset value of this field is undefined. 000 8-bit System bus access 001 16-bit System bus access 010 32-bit System bus access 011 Reserved 1xx Reserved 4 PROT0 Protection: cache. The reset value of this field is undefined. 0 Non-cacheable 1 Cacheable 5 PROT1 Protection: buffer. The reset value of this field is undefined. 0 Non-bufferable 1 Bufferable MPC5533 Microcontroller Reference Manual, Rev. 0 7-10 Freescale Semiconductor Table 7-9. ECSM_FEAT Field Descriptions (Continued) Field Description 6 PROT2 Protection: mode. The reset value of this field is undefined. 0 User mode 1 Supervisor mode 7 PROT3 Protection: type. The reset value of this field is undefined. 0 I-Fetch 1 Data 7.2.1.9 Flash ECC Data High Register (ECSM_FEDRH) The ECSM_FEDRH and ECSM_FEDRL are 32-bit registers for capturing the data of the last, correctly-enabled ECC event in flash memory. Depending on the state of the ECSM_ECR, an ECC event in the flash loads the address, attributes and data of the access into the ECSM_FEAR, ECSM_FEMR, ECSM_FEAT and ECSM_FEDR registers, and asserts the FNCE flag in ECSM_ESR. The data captured on a multi-bit non-correctable ECC error is undefined. Base + 0x0058 0 Access: Read 1 2 3 4 5 6 R 7 8 9 10 11 12 13 14 15 FEDH W Reset 1 U U U U U U U U U U U U U U U U 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 U U U U U U U R FEDH W Reset 1 U 1 U U U U U U U U “U” signifies a bit that is uninitialized. Figure 7-7. Flash ECC Data High Register (ECSM_FEDRH) Table 7-10. ECSM_FEDRH Field Descriptions Field Description 0–31 FEDH [0:31] Flash ECC data. Contains the data associated with the faulting access of the last, correctly-enabled flash ECC event. The register contains the data value taken directly from the data bus. The reset value of this field is undefined. 7.2.1.10 Flash ECC Data Low Registers (ECSM_FEDRL) The ECSM_FEDRH and ECSM_FEDRL are 32-bit registers for capturing the data of the last, correctly-enabled ECC event in the flash memory. Depending on the state of the ECSM_ECR, an ECC event in the flash loads the address, attributes and data of the access into the ECSM_FEAR, ECSM_FEMR, ECSM_FEAT and ECSM_FEDR registers, and asserts the FNCE flag in ECSM_ESR. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 7-11 The data captured on a multi-bit non-correctable ECC error is undefined. Base + 0x005C 0 Access: Read 1 2 3 4 5 6 7 R 8 9 10 11 12 13 14 15 FEDL W Reset 1 U U U U U U U U U U U U U U U U 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 U U U U U U U R FEDL W Reset 1 U 1 U U U U U U U U “U” signifies a bit that is uninitialized. Figure 7-8. Flash ECC Data Low Register (ECSM_FEDRL) Table 7-11. ECSM_FEDRL Field Descriptions Field Description 0–31 FEDL [0:31] Flash ECC data. Contains the data associated with the faulting access of the last, correctly-enabled flash ECC event. The register contains the data value taken directly from the data bus. The reset value of this field is undefined. 7.2.1.11 SRAM ECC Address Register (ECSM_REAR) The ECSM_REAR is a 32-bit register for capturing the address of the last, correctly-enabled ECC event in the RAM memory. Depending on the state of the ECSM_ECR, an ECC event in the RAM loads the address, attributes and data of the access into the ECSM_REAR, ECSM_REMR, ECSM_REAT and ECSM_REDR registers, and asserts the RNCE flag in ECSM_ESR. Base + 0x0060 0 Access: Read 1 2 3 4 5 6 R 7 8 9 10 11 12 13 14 15 REAR W Reset 1 U U U U U U U U U U U U U U U U 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 U U U U U U U R REAR W Reset 1 U 1 U U U U U U U U “U” signifies a bit that is uninitialized. Figure 7-9. RAM ECC Address Register (ECSM_REAR) MPC5533 Microcontroller Reference Manual, Rev. 0 7-12 Freescale Semiconductor Table 7-12. ECSM_REAR Field Descriptions Field Description 0–31 REAR [0:31] SRAM ECC address. Contains the faulting access address of the last, correctly-enabled RAM ECC event. The reset value of this field is undefined. 7.2.1.12 SRAM ECC Master Number Register (ECSM_REMR) The REMR is an 8-bit register for capturing the XBAR bus master number of the last, correctly-enabled ECC event in the RAM memory. Depending on the state of the ECSM_ECR, an ECC event in the SRAM loads the address, attributes and data of the access into the ECSM_REAR, ECSM_REMR, ECSM_REAT and ECSM_REDR registers, and asserts the RNCE flag in ECSM_ESR. Base + 0x0066 R Access: Read 0 1 2 3 0 0 0 0 0 0 0 0 4 5 6 7 U U REMR W Reset 1 1 U U “U” signifies a bit that is uninitialized. Figure 7-10. RAM ECC Master Number Register (ECSM_REMR) Table 7-13. ECSM_REMR Field Descriptions Field 0–3 4–7 REMR [0:3] Description Reserved SRAM ECC master number. Contains the XBAR bus master number of the faulting access of the last, correctly-enabled RAM ECC event. The reset value of this field is undefined. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 7-13 7.2.1.13 SRAM ECC Attributes Register (ECSM_REAT) The ECSM_REAT is an 8-bit register for capturing the XBAR bus master attributes of the last, correctly-enabled ECC event in the RAM memory. Depending on the state of the ECSM_ECR, an ECC event in the RAM loads the address, attributes and data of the access into the ECSM_REAR, ECSM_REMR, ECSM_REAT and ECSM_REDR registers, and asserts the RNCE flag in ECSM_ESR. Base + 0x0067 Access: Read 0 R 1 WRITE 2 3 SIZE 4 5 6 7 PROT0 PROT1 PROT2 PROT3 U U U U W Reset 1 U 1 U U U “U” signifies a bit that is uninitialized. Figure 7-11. SRAM ECC Attributes Register (ECSM_REAT) Table 7-14. ECSM_REAT Field Descriptions Field Description 0 WRITE Write. The reset value of this field is undefined. 0 System bus read access 1 System bus write access 1–3 SIZE [0:2] Size. The reset value of this field is undefined. 000 8-bit system bus access 001 16-bit system bus access 010 32-bit system bus access 011 Reserved 1xx Reserved 4 PROT0 Protection: cache. The reset value of this field is undefined. 0 Non-cacheable 1 Cacheable 5 PROT1 Protection: buffer. The reset value of this field is undefined. 0 Non-bufferable 1 Bufferable 6 PROT2 Protection: mode. The reset value of this field is undefined. 0 User mode 1 Supervisor mode 7 PROT3 Protection: type. The reset value of this field is undefined. 0 Fetch 1 Data MPC5533 Microcontroller Reference Manual, Rev. 0 7-14 Freescale Semiconductor 7.2.1.14 SRAM ECC Data High Register (ECSM_REDRH) The ECSM_REDRH and ECSM_REDRL are 32-bit registers for capturing the data of the last, correctly-enabled ECC event in the RAM memory. Depending on the state of the ECSM_ECR, an ECC event in the RAM loads the address, attributes and data of the access into the ECSM_REAR, ECSM_REMR, ECSM_REAT, ECSM_REDRH and ECSM_REDRL registers, and asserts the RFNCE flag in ECSM_ESR. The data captured on a multi-bit non-correctable ECC error is undefined. Base + 0x0068 0 Access: Read 1 2 3 4 5 6 R 7 8 9 10 11 12 13 14 15 REDH W Reset 1 U U U U U U U U U U U U U U U U 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 U U U U U U U R REDH W Reset 1 U 1 U U U U U U U U “U” signifies a bit that is uninitialized. Figure 7-12. SRAM ECC Data High Register (ECSM_REDRH) Table 7-15. ECSM_REDRH Field Descriptions Field Description 0–31 REDH [0:31] RAM ECC data. Contains the data of the faulting access of the last, correctly-enabled RAM ECC event. The register contains the data value taken directly from the data bus. The reset value of this field is undefined. 7.2.1.15 SRAM ECC Data Low Registers (ECSM_REDRL) The ECSM_REDRH and ECSM_REDRL are 32-bit registers for capturing the data for the last, correctly-enabled ECC event in RAM. Depending on the state of the ECSM_ECR, an ECC event in the RAM loads the address, attributes and data of the access to the following registers: • ECSM_REAR • ECSM_REMR • ECSM_REAT • ECSM_REDRH • ECSM_REDRL and asserts the RFNCE flag in ECSM_ESR. The data captured on a multi-bit non-correctable ECC error is undefined. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 7-15 ECSM Base + 0x006C 0 1 Access: Read 2 3 4 5 6 R 7 8 9 10 11 12 13 14 15 REDL W Reset 1 U U U U U U U U U U U U U U U U 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 U U U U U U U R REDL W Reset 1 U 1 U U U U U U U U “U” signifies a bit that is uninitialized. Figure 7-13. SRAM ECC Data Low Register (ECSM_REDRL) The following table describes the RAM ECC data field in the Table 7-16. ECSM_REDRL Field Descriptions Field Description 0–31 REDL [0:31] RAM ECC data. Contains the data associated with the faulting access of the last, correctly-enabled RAM ECC event. The register contains the data value taken directly from the data bus. The reset value of this field is undefined. 7.3 Initialization and Application Information The Error Correction Code (ECC) is used to verify the contents of the internal SRAM and flash memories. This is done by generating ECC check bits. Typically ECC check bits are calculated on writes and then used on reads to detect and correct errors. • SRAM—Seven ECC check bits for each 32-bit SRAM data word. • Flash—Eight ECC check bits for each 32-bit flash data word. After Power on Reset (POR), the contents of internal SRAM is random and the corresponding ECC check bits are unknown. To prevent generating ECC errors during reads, an initialization routine must perform 32-bit writes to all SRAM locations. Because the flash module is non-volatile, the ECC check bits are calculated and stored when the flash is programmed. Transparent to the application, the ECC uses the check bits to automatically correct single-bit memory errors. Multi-bit memory errors are not correctable. If the ECC detects a multi-bit error, an exception is generated. The type of exception generated by a multi-bit error depends on the settings of the EE and ME in the Machine State Register (MSR), as shown in Table 7-17. When error reporting is enabled, as long as its priority is 0, an interrupt request is generated to the interrupt controller (INTC) even though the INTC request is not serviced. MPC5533 Microcontroller Reference Manual, Rev. 0 7-16 Freescale Semiconductor Table 7-17. MSR[EE] and MSR[ME] Bit Settings Field Description EE External interrupt enable. 0 External input interrupts disabled. 1 External interrupts enabled. ME Machine check enable. 0 Machine check interrupts disabled. Enters machine check. 1 Machine interrupts enabled. A non-correctable data ECC error executes one of the following actions, regardless of whether non-correctable reporting is enabled: Table 7-18. Non-correctable Data ECC States MSR[EE] MSR[ME] Access Type Result 0 0 Instruction or data Enters checkstop state. A reset is required to resume processing. 0 1 Instruction or data Machine check interrupt (IVOR1). 1 X Data Data storage interrupt (IVOR2). External interrupt must be enabled. Machine check can be enabled or disabled. 1 X Instruction Instruction storage interrupt (IVOR3). When the device is in the checkstop state, processing is suspended and cannot resume without a reset. When a debug request is presented to the core while it is in the checkstop state, the core temporarily exits the checkstop state and enters debug mode. When debug mode exits, the core re-enters the checkstop state. If the external interrupt bit in the MSR is enabled, data or instruction stage interrupts are reported when the ECC errors are a result of CPU accesses, regardless of whether non-correctable reporting is enabled. ECC errors generated by other masters (eDMA, etc.) do not generate data or instruction storage exceptions, and the ECSM is used to report these errors. You must initialize the ECSM to enable non-correctable reporting with interrupt generation to detect and report ECC interrupts from the ECSM. Error reporting details can be independently enabled for flash memory and SRAM. To enable non-correctable error reporting and save the error details for: • SRAM—set the ERNCR bit in the ECSM Error Configuration Register (ECSM_ECR). • Flash—set the EFNCR bit in ECSM_ECR. When these bits are set and a non-correctable ECC error occurs, error information is recorded in other ECSM registers and an interrupt request is generated on vector 9 of the interrupt controller (INTC). • CPU data access error—Generates data storage exception (IVOR2). • CPU instruction access error—Generates instruction storage exception (IVOR3). • Vector 9 of INTC enabled—Generates an external exception (IVOR4). MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 7-17 To prevent generating an ECSM interrupt in response to a non-correctable error: • Enable non-correctable reporting in the ECSM. • Ensure the external interrupt is disabled. • Ensure that the INTC_PSR[PRI] value for the ECC error interrupt request is 0. To use the detailed data or instruction storage exception information, design an exception handler that can determine: • The destination that asserted the error, indicated by the value of the ESR[XTE] bit. • The address of the corrupted instruction for an instruction storage exception (SRR0). • The address where the error occurred for a data storage exception, indicated in the data exception address register (DEAR). MPC5533 Microcontroller Reference Manual, Rev. 0 7-18 Freescale Semiconductor Chapter 8 Crossbar Switch (XBAR) 8.1 Introduction This chapter describes the multi-port crossbar switch (XBAR), which supports simultaneous connections between four master ports and five slave ports. XBAR supports a 32-bit address bus width and a 64-bit data bus width at all master and slave ports. 8.1.1 Block Diagram Figure 8-1 shows a block diagram of the crossbar switch. Master Master .... Master Master modules Crossbar Switch Slave modules Slave Slave .... Slave Figure 8-1. XBAR Block Diagram 8.1.2 Overview The XBAR allows for concurrent transactions to occur from any master port to any slave port. It is possible for all master ports and slave ports to be in use at the same time as a result of independent master requests. If a slave port is simultaneously requested by more than one master port, arbitration logic selects the higher priority master and grants it ownership of the slave port. All other masters requesting that slave port are stalled until the higher priority master completes its transactions. By default, requesting masters are granted access based on a fixed priority. A round-robin priority mode also is available. In this mode, requesting masters are treated with equal priority and are granted access to a slave port in round-robin process, based upon the ID of the last master to be granted access. A block diagram of the XBAR is shown in Figure 8-1. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 8-1 The XBAR can place a slave port in a low-power park mode to avoid dissipating power, transitional address, control, or data signals when the master port is not actively accessing the slave port. There is a one-cycle arbitration overhead for exiting low-power park mode. 8.1.3 • Features Four master ports: — core: e200z3 core–CPU data — e200z3 core–CPU instruction — eDMA — EBI Five slave ports — Flash — EBI — Internal SRAM — Peripheral bridge A — Peripheral bridge B 32-bit address, 64-bit internal data paths Fully concurrent transfers between independent master and slave ports • • • 8.1.4 Modes of Operation The following table lists the operating modes for the crossbar switch module. Table 8-1. XBAR Operating Modes Operating Mode Description Normal XBAR provides the register interface and logic that controls crossbar switch configuration. Debug XBAR operation in debug mode is identical to operation in normal mode. MPC5533 Microcontroller Reference Manual, Rev. 0 8-2 Freescale Semiconductor 8.2 Memory Map and Register Definition The memory map for the XBAR registers that are visible to the application is shown in Table 8-2. NOTE Do not read or write to the reserved memory locations in the XBAR register memory map; accessing these areas can cause unpredictable results. Table 8-2. XBAR Register Memory Map Address Base = 0xFFF0_4000 Base + (0x0004–0x000F) Base + 0x0010 Base + (0x0014–0x00FF) Base + 0x0100 Base +(0x0104–0x010F) Base + 0x0110 Base + (0x0114–0x02FF) Base + 0x0300 Base + (0x0304–0x030F) Base + 0x0310 Register Name XBAR_MPR0 — XBAR_SGPCR0 — XBAR_MPR1 — XBAR_SGPCR1 — XBAR_MPR3 — XBAR_SGPCR3 Base + (0x0314–0x05FF) Base + 0x0600 Base + (0x0604–0x060F) Base + 0x0610 Base + (0x0614–0x06FF) Base + 0x0700 Base + (0x0704–0x070F) Base + 0x0710 (Base + 0x0714)–0x0003_FFFF Register Description Bits Master priority register for slave port 0 32 Reserved — General-purpose control register for slave port 0 32 Reserved — Master priority register for slave port 1 32 Reserved — General-purpose control register for slave port 1 32 Reserved — Master priority register for slave port 3 32 Reserved — General-purpose control register for slave port 3 32 Reserved XBAR_MPR6 — XBAR_SGPCR6 — XBAR_MPR7 — XBAR_SGPCR7 — Master priority register for slave port 6 32 Reserved — General-purpose control register for slave port 6 32 Reserved — Master priority register for slave port 7 32 Reserved — General-purpose control register for slave port 7 32 Reserved — MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 8-3 8.2.1 Register Descriptions There are two registers for each slave port of the XBAR. The registers can only be accessed in Supervisor Mode using 32-bit accesses. The slave SGPCR also features a bit (RO), which when written with a 1, prevents all slave registers for that port from being written to again until a reset occurs. The registers remain readable, but future write attempts have no effect on the registers and are terminated with an error response. Table 8-3 lists the crossbar switch master and slave identifiers for each module in the device: • Fixed internal master ID numbers for each master port • XBAR master and slave port ID numbers Shown are the internal master ID numbers as they relate to the crossbar master port ID numbers: Table 8-3. XBAR Switch Ports 8.2.1.1 XBAR Port Internal Master ID Type Number e200z3 core–CPU instruction 0 Master 0 Enhanced direct memory access (eDMA) 2 Master 1 External bus interface (EBI) 3 Master 2 e200z3 core–CPU data 0 Master 4 e200z3–Nexus 1 Master 4 Flash memory — Slave 0 External bus interface (EBI) — Slave 1 Internal SRAM — Slave 3 Peripheral bridge A (PBRIDGE_A) — Slave 6 Peripheral bridge B (PBRIDGE_B) — Slave 7 Module Master Priority Registers (XBAR_MPRn) The XBAR_MPR for a slave port sets the priority of each master port when operating in fixed priority mode. These registers are not used in round-robin priority mode unless more than one master is assigned as high priority by a slave. IMPORTANT Master ports must be assigned unique priority levels. The master priority registers are accessible in Supervisor Mode only using 32-bit accesses. After the read only (RO) bit is set in the slave general-purpose control register, no writes to the master priority register are permitted; only read instructions are allowed. Attempts to write to master priority registers (MPR) have no effect and result in an error. NOTE XBAR_MPR must be written with a read/modify/write for code compatibility. MPC5533 Microcontroller Reference Manual, Rev. 0 8-4 Freescale Semiconductor Address: Base + 0x0000 (XBAR_MPR0) Base + 0x0100 (XBAR_MPR1) Base + 0x0300 (XBAR_MPR3) Base + 0x0700 (XBAR_MPR7) R Access: Supervisor R/W 0 1 2 3 4 5 6 7 8 9 10 11 12 0 0 0 0 0 0 0 0 0 0 0 0 0 13 14 15 MSTR4 W Reset R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 0 0 0 0 0 0 MSTR2 MSTR1 MSTR0 W Reset 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 Table 8-4. XBAR_MPRn Descriptions Field 0–12 13–15 MSTR4 Description Reserved, must be cleared to 0 Master 4 priority. Sets the arbitration priority for the e200z3 core data and Nexus support for the core to master port 4 on the associated slave port. The reset value of 0b011 is the lowest priority. 000This master has the highest priority when accessing the slave port. .... 011This master has the lowest priority when accessing the slave port. 100–111Invalid values 16–20 21–23 MSTR2 Reserved, must be cleared to 0 Master 2 priority. Sets the arbitration priority for the external bus interface (EBI) for master port 2 on the slave port. The MSTR2 reset value of 0b010 is the third highest priority. 000 This master has the highest priority when accessing the slave port. .... 24 25–27 MSTR1 011 This master has the lowest priority when accessing the slave port. 100–111 Invalid values Reserved, must be cleared to 0 Master 1 priority. Sets the arbitration priority for direct memory access (eDMA) for master port 1 on the slave port. The MSTR1 reset value of 0b001 is the second highest priority. 000 This master has the highest priority when accessing the slave port. .... 011 This master has the lowest priority when accessing the slave port. 100–111 Invalid values MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 8-5 Table 8-4. XBAR_MPRn Descriptions (Continued) Field 28 29–31 MSTR0 Description Reserved, must be cleared. Master 0 priority. Sets the arbitration priority for the e200z3 core instruction for master port 0 on the slave port. The MSTR0 reset value of 0b000 is the highest priority. 000 This master has the highest priority when accessing the slave port. .... 8.2.1.2 011 This master has the lowest priority when accessing the slave port. 100–111 Invalid values Slave General-Purpose Control Registers (XBAR_SGPCRn) The XBAR_SGPCRn of a slave port controls several features of the slave port, including the following: • Round-robin or fixed arbitration policy for a particular slave port • Write protection of any slave port registers • Parking algorithm used for a slave port The PARK field indicates which master port this slave port parks on when no active access attempts are being made to the slave and the parking control field is set to park on a specific master. XBAR_SGPCRn[PARK] must only be programmed to select master ports that are actually available on the device, otherwise undefined behavior results. The low-power park feature can result in an overall power savings if the slave port is not saturated; however, an extra clock cycle of latency results whenever any master tries to access a slave (not being accessed by another master) because it is not parked on any master. The XBAR_SGPCR can only be accessed in supervisor mode with 32-bit accesses. After the RO (read only) bit is set in the XBAR_SGPCR, the XBAR_SGPCR and the SBAR_MPR can only be read. Attempts to write to them have no effect and results in an error. NOTE Some of the unused bits in the SGPCRn registers are writeable and readable, but they serve no function. Setting any of these bits has no effect on the operation of this module. MPC5533 Microcontroller Reference Manual, Rev. 0 8-6 Freescale Semiconductor Addess: Base + 0x0010 (XBAR_SGPCR0) Base + 0x0110 (XBAR_SGPCR1) Base + 0x0310 (XBAR_SGPCR3) Base + 0x0610 (XBAR_SGPCR6) Base + 0x0710 (XBAR_SGPCR7) 0 R Access: R/W 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 0 0 0 0 0 0 0 RO1 W Reset R 0 ARB PCTL PARK W Reset 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 After this bit is set, only a hardware reset clears it. Figure 8-2. Slave General-Purpose Control Registers (XBAR_SGPCRn) Table 8-5. XBAR_SGPCRn Field Descriptions Field Description 0 RO Read only. Forces all slave port registers to read only. To clear the read only bit requires a hardware reset. 0 All this slave port’s registers can be written. 1 All this slave port’s registers are read only and cannot be written (attempted writes have no effect and result in an error response). 1–21 Reserved, must be cleared. 22–23 ARB Arbitration mode. Used to select the arbitration policy for the slave port. This field is initialized by hardware reset. 00 Fixed priority using MPR 01 Round-robin priority 10 Invalid value 11 Invalid value 24–25 Reserved, must be cleared. 26–27 PCTL Parking control. Used to select the parking algorithm used by the slave port. This field is initialized by hardware reset. 00 When no master is making a request, the arbiter parks the slave port on the master port defined by the PARK control field. 01 POL—Park on last. When no master is making a request, the arbiter parks the slave port on the last master to own the slave port. 10 LPP—Low-power park. When no master is making a request, the arbiter parks the slave port on no master and drives all slave port outputs to a safe state. 11 Invalid value MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 8-7 Table 8-5. XBAR_SGPCRn Field Descriptions (Continued) Field 28 29–31 PARK 8.3 Description Reserved, must be cleared. Park. Used to determine which master port this slave port parks on when no masters are actively making requests. PCTL must be set to 00. 000 Park on master port 0 001 Park on master port 1 010 Park on master port 2 011 Invalid value 100 Park on master port 4 101 Invalid value 110 Invalid value 111 Invalid value Functional Description This section describes the functionality of the XBAR in more detail. 8.3.1 Overview The main goal of the XBAR is to increase overall system performance by allowing multiple masters to communicate concurrently with multiple slaves. To maximize data throughput, it is essential to keep arbitration delays to a minimum. This section examines data throughput from the point of view of masters and slaves, detailing when the XBAR stalls masters, or inserts bubbles on the slave side. 8.3.2 General Operation When a master accesses the XBAR from an idle master state, the access is taken immediately by the XBAR. If the targeted slave port of the access is available (that is, the requesting master is currently granted ownership of the slave port), the access is immediately presented on the slave port. It is possible to make single clock (zero wait state) accesses through the XBAR by a granted master. If the targeted slave port of the access is busy or parked on a different master port, the requesting master receives wait states until the targeted slave port can service the master request. The latency in servicing the request depends on each master’s priority level and the responding slave’s access time. Because the XBAR appears to be simply another slave to the master device, the master device has no indication that it owns the slave port it is targeting. While the master does not have control of the slave port it is targeting, it is wait-stated. A master is given control of a targeted slave port only after a previous access to a different slave port has completed, regardless of its priority on the newly targeted slave port. This prevents deadlock from occurring when a master has the following conditions: • Outstanding request to slave port A that has a long response time • Pending access to a different slave port B • Lower priority master also makes a request to the different slave port B. MPC5533 Microcontroller Reference Manual, Rev. 0 8-8 Freescale Semiconductor In this case, the lower priority master is granted bus ownership of slave port B after a cycle of arbitration, assuming the higher priority master slave port A access is not terminated. After a master has control of the slave port it is targeting, the master remains in control of that slave port until it gives up the slave port by running an IDLE cycle, leaves that slave port for its next access, or loses control of the slave port to a higher priority master with a request to the same slave port. However, because all masters run a fixed-length burst transfer to a slave port, it retains control of the slave port until that transfer sequence is completed. In round-robin arbitration mode, the current master is forced to hand off bus ownership to an alternately requesting master at the end of its current transfer sequence. When a slave bus is idled by the XBAR, it can be parked on the master port using the PARK bits in the XBAR_SGPCR (slave general-purpose control register), or on the last master to have control of the slave port. This can avoid the initial clock of the arbitration delay if the master must arbitrate to gain control of the slave port. The slave port can also be put into low-power park mode to save power. 8.3.3 Master Ports The XBAR terminates an access and it is not allowed to pass through the XBAR unless the master currently is granted access to the slave port to which the access is targeted. A master access is taken if the slave port to which the access decodes is either currently servicing the master or is parked on the master. In this case, the XBAR is completely transparent and the master access is immediately transmitted on the slave bus and no arbitration delays are incurred. A master access stalls if the access decodes to a slave port that is busy serving another master, parked on another master or is in low-power park mode. If the slave port is currently parked on another master or is in low-power park mode, and no other master is requesting access to the slave port, then only one clock of arbitration is incurred. If the slave port is currently serving another master of a lower priority and the master has a higher priority than all other requesting masters, then the master gains control over the slave port as soon as the data phase of the current access is completed. If the slave port is currently servicing another master of a higher priority, then the master gains control of the slave port after the other master releases control of the slave port if no other higher priority master is also waiting for the slave port. A master access is responded to with an error if the access decodes to a location not occupied by a slave port. This is the only time the XBAR directly responds with an error response. All other error responses received by the master are the result of error responses on the slave ports being passed through the XBAR. 8.3.4 Slave Ports The goal of the XBAR with respect to the slave ports is to keep them 100% saturated when masters are actively making requests. To do this the XBAR must not insert any bubbles onto the slave bus unless absolutely necessary. There is only one instance when the XBAR forces a bubble onto the slave bus when a master is actively making a request. This occurs when a handoff of bus ownership occurs and there are no wait states from the slave port. A requesting master which does not own the slave port is granted access after a one clock delay. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 8-9 The only other time the XBAR has control of the slave port is when no masters are making access requests to the slave port and the XBAR is forced to either park the slave port on a specific master, or place the slave port into low-power park mode. In these cases, the XBAR forces IDLE for the transfer type. 8.3.5 Priority Assignment Each master port must be assigned a unique 2-bit priority level in fixed priority mode. If multiple master ports are assigned the same priority level within a register (XBAR_MPR) undefined behavior results. 8.3.6 Arbitration XBAR supports two arbitration schemes; a simple fixed-priority comparison algorithm, and a round-robin fairness algorithm. The arbitration scheme is independently programmable for each slave port. 8.3.6.1 Fixed Priority Operation When operating in fixed-priority arbitration mode, each master is assigned a unique priority level in the XBAR_MPR. If two masters both request access to a slave port, the master with the highest priority in the selected priority register gains control over the slave port. Any time a master makes a request to a slave port, the slave port checks to see if the new requesting master’s priority level is higher than that of the master that currently has control over the slave port (if any). The slave port does an arbitration check at every clock edge to ensure that the proper master (if any) has control of the slave port. If the new requesting master’s priority level is higher than that of the master that currently has control of the slave port, the higher priority master is granted control at the termination of any currently pending access, assuming the pending transfer is not part of a burst transfer. A new requesting master must wait until the end of the fixed-length burst transfer, before it is granted control of the slave port. But if the new requesting master’s priority level is lower than that of the master that currently has control of the slave port, the new requesting master is forced to wait until the master that currently has control of the slave port is finished accessing the current slave port. 8.3.6.2 Round-Robin Priority Operation When operating in round-robin mode, each master is assigned a relative priority based on the master port number. This relative priority is compared to the port number of the last master to perform a transfer on the slave bus. The highest priority requesting master becomes the owner of the slave bus at the next transfer boundary (accounting for fixed-length burst transfers). Priority is based on how far ahead the port number of the requesting master is to the port number of the last master. After granted access to a slave port, a master can perform as many transfers as desired to that port until another master makes a request to the same slave port. The next master in line is granted access to the slave port when the current transfer is completed, or possibly on the next clock cycle if the current master has no pending access request. MPC5533 Microcontroller Reference Manual, Rev. 0 8-10 Freescale Semiconductor As an example of arbitration in round-robin mode, assume the three masters have ID’s 0, 1, and 2. If the last master of the slave port was master 1, and masters 0 and 2 make simultaneous requests, they are serviced in the order 2 and then 0 assuming no further requests are made. As another example, if master 1 is waiting on a response from a slow slave and has no further pending access to that slave, no other masters are requesting, and master 0 then makes a request, master 0’s request is granted on the next clock (assuming that master 1’s transfer is not a burst transfer), and the request information for master 0 is driven to the slave as a pending access. If master 2 were to make a request after master 0 has been granted access, but prior to master 0’s access being accepted by the slave, master 0 maintains the grant on the slave port, and master 2 is delayed until the next arbitration boundary, which occurs after the transfer is complete. The round-robin pointer is reset to 0, so if master 1 has another request that occurs before master 0’s transfer completes, master 1 is the granted the bus. This implies a worst case latency of N transfers for a system with N masters. Parking can continue to be used in round-robin mode, but affects the round-robin pointer unless the parked master actually performs a transfer. Handoff to the next master in line occurs after one cycle of arbitration. The slave port does an arbitration check at every clock edge to ensure that the proper master (if any) has control of the slave port. A new requesting master must wait until the end of the fixed-length burst transfer, before it is granted control of the slave port. If the new requesting master’s priority level is lower than that of the master that currently has control of the slave port, the new requesting master is forced to wait until the master that currently has control of the slave port completes its access. 8.3.6.2.1 Parking If no master is currently requesting the slave port, the slave port is parked. The slave port parks in one of three places, indicated by the value of the PCTL field in the XBAR_SGPCR. • If park-on-specific master mode is selected, the slave port parks on the master designated by the PARK field. When the master accesses the slave port again, a one clock arbitration penalty is incurred only for an access request made by another master port to the slave port. No other arbitration penalties are incurred. All other masters pay a one clock penalty. • If park-on-last (POL) mode is selected, then the slave port parks on the last master to access it, passing that master’s signals through to the slave bus. When the master accesses the slave port again, no other arbitration penalties are incurred except that a one clock arbitration penalty is incurred for each access request to the slave port made by another master port. All other masters pay a one clock penalty. • If the low-power-park (LPP) mode is selected, then the slave port enters low-power park mode. It is not under control by any master and does not transmit any master signals to the slave bus. All slave bus activity halts because all slave bus signals are not toggling. This saves power if the slave port is not used for some time. However, when a master does make a request to a slave port parked in low-power-park, a one clock arbitration delay is incurred to get ownership of the slave port. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 8-11 MPC5533 Microcontroller Reference Manual, Rev. 0 8-12 Freescale Semiconductor Chapter 9 Enhanced Direct Memory Access (eDMA) 9.1 Introduction This chapter describes the enhanced Direct Memory Access (eDMA) controller, a second-generation module capable of performing complex data transfers with minimal intervention from a host processor. The enhanced direct memory access (eDMA) controller hardware microarchitecture includes a DMA engine which performs source and destination address calculations, and the actual data movement operations, along with SRAM-based local memory containing the transfer control descriptors (TCD) for the channels. Figure 9-1 is a block diagram of the eDMA module. SRAM Transfer Control Descriptor (TCD) eDMA Slave write address Slave write data TCD0 TCDn-1* eDMA Engine Bus read data Slave Interface System Bus SRAM Program model and channel arbitration Data path Address path Control Slave read data Bus write data Bus address *n = 32 channels eDMA peripheral request eDMA done Figure 9-1. eDMA Block Diagram MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 9-1 9.1.1 Features The eDMA is a highly-programmable data transfer engine, which has been optimized to minimize the required intervention from the host processor. It is intended for use in applications where the data size to be transferred is statically known, and is not defined within the data packet itself. The eDMA module features: • • • • All data movement via dual-address transfers: read from source, write to destination Programmable source, destination addresses, transfer size, plus support for enhanced addressing modes 32-channel implementation performs complex data transfers with minimal intervention from a host processor — 32 bytes of data registers, used as temporary storage to support burst transfers (see SSIZE bit) — Connections to the crossbar switch for bus mastering the data movement Transfer control descriptor (TCD) organized to support two-deep, nested transfer operations — 32-byte TCD per channel stored in local memory — An inner data transfer loop defined by a minor byte transfer count — An outer data transfer loop defined by a major iteration count Channel activation via one of three methods: — Explicit software initiation — Initiation via a channel-to-channel linking mechanism for continual transfers — Peripheral-paced hardware requests (one per channel) NOTE For all three methods, one activation per execution of the minor loop is required. • • • • Support for fixed-priority and round-robin channel arbitration Channel completion reported via optional interrupt requests — One interrupt per channel, optionally asserted at completion of major iteration count — Error terminations are enabled per channel, and logically summed together to form a single error interrupt Support for scatter/gather DMA processing Any channel can be programmed so that it can be suspended by a higher priority channel’s activation, before completion of a minor loop Throughout this chapter, n is used to reference the channel number. Additionally, data sizes are defined as byte (8-bit), halfword (16-bit), word (32-bit) and doubleword (64-bit). MPC5533 Microcontroller Reference Manual, Rev. 0 9-2 Freescale Semiconductor 9.1.2 Modes of Operation 9.1.2.1 Normal Mode In normal mode, the eDMA is used to transfer data between a source and a destination. The source and destination can be a memory block or an I/O block capable of operation with the eDMA. 9.1.2.2 Debug Mode If enabled by EDMA_CR[EDBG] and the CPU enters debug mode, the eDMA does not grant a service request when the debug input signal is asserted. If the signal asserts during a data block transfer as described by a minor loop in the current active channel’s TCD, the eDMA continues the operation until the minor loop completes. 9.2 Memory Map and Register Definition 9.2.1 Memory Map The eDMA programming model is partitioned into two regions: Region 1 defines control registers; region 2 defines the local transfer control for the descriptor memory. Table 9-1 is a 32-bit view of the eDMA memory map. Table 9-1. eDMA 32-bit Memory Map Address Register Name Register Description Bits Base (0xFFF4_4000) EDMA_CR eDMA control register 32 Base + 0x0004 EDMA_ESR eDMA error status register 32 Reserved — eDMA enable request low register 32 Reserved — Base + 0x0008 Base + 0x000C Base + 0x0010 — EDMA_ERQRL — Base + 0x0014 EDMA_EEIRL eDMA enable error interrupt low register 32 Base + 0x0018 EDMA_SERQR eDMA set enable request register 8 Base + 0x0019 EDMA_CERQR eDMA clear enable request register 8 Base + 0x001A EDMA_SEEIR eDMA set enable error interrupt register 8 Base + 0x001B EDMA_CEEIR eDMA clear enable error interrupt register 8 Base + 0x001C EDMA_CIRQR eDMA clear interrupt request register 8 Base + 0x001D EDMA_CER eDMA clear error register 8 Base + 0x001E EDMA_SSBR eDMA set start bit register 8 Base + 0x001F EDMA_CDSBR eDMA clear done status bit register 8 Reserved — Base + 0x0020 — MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 9-3 Table 9-1. eDMA 32-bit Memory Map (Continued) Address Base + 0x0024 Base + 0x0028 Register Name EDMA_IRQRL — Register Description Bits eDMA interrupt request low register 32 Reserved — Base + 0x002C EDMA_ERL eDMA error low register 32 Base + 0x0100 EDMA_CPR0 eDMA channel 0 priority register 8 Base + 0x0101 EDMA_CPR1 eDMA channel 1 priority register 8 Base + 0x0102 EDMA_CPR2 eDMA channel 2 priority register 8 Base + 0x0103 EDMA_CPR3 eDMA channel 3 priority register 8 Base + 0x0104 EDMA_CPR4 eDMA channel 4 priority register 8 Base + 0x0105 EDMA_CPR5 eDMA channel 5 priority register 8 Base + 0x0106 EDMA_CPR6 eDMA channel 6 priority register 8 Base + 0x0107 EDMA_CPR7 eDMA channel 7 priority register 8 Base + 0x0108 EDMA_CPR8 eDMA channel 8 priority register 8 Base + 0x0109 EDMA_CPR9 eDMA channel 9 priority register 8 Base + 0x010A EDMA_CPR10 eDMA channel 10 priority register 8 Base + 0x010B EDMA_CPR11 eDMA channel 11 priority register 8 Base + 0x010C EDMA_CPR12 eDMA channel 12 priority register 8 Base + 0x010D EDMA_CPR13 eDMA channel 13 priority register 8 Base + 0x010E EDMA_CPR14 eDMA channel 14 priority register 8 Base + 0x010F EDMA_CPR15 eDMA channel 15 priority register 8 Base + 0x0110 EDMA_CPR16 eDMA channel 16 priority register 8 Base + 0x0111 EDMA_CPR17 eDMA channel 17 priority register 8 Base + 0x0112 EDMA_CPR18 eDMA channel 18 priority register 8 Base + 0x0113 EDMA_CPR19 eDMA channel 19 priority register 8 Base + 0x0114 EDMA_CPR20 eDMA channel 20 priority register 8 Base + 0x0115 EDMA_CPR21 eDMA channel 21 priority register 8 Base + 0x0116 EDMA_CPR22 eDMA channel 22 priority register 8 Base + 0x0117 EDMA_CPR23 eDMA channel 23 priority register 8 Base + 0x0118 EDMA_CPR24 eDMA channel 24 priority register 8 Base + 0x0119 EDMA_CPR25 eDMA channel 25 priority register 8 Base + 0x011A EDMA_CPR26 eDMA channel 26 priority register 8 Base + 0x011B EDMA_CPR27 eDMA channel 27 priority register 8 Base + 0x011C EDMA_CPR28 eDMA channel 28 priority register 8 Base + 0x011D EDMA_CPR29 eDMA channel 29 priority register 8 MPC5533 Microcontroller Reference Manual, Rev. 0 9-4 Freescale Semiconductor Table 9-1. eDMA 32-bit Memory Map (Continued) Address Register Name Register Description Bits Base + 0x011E EDMA_CPR30 eDMA channel 30 priority register 8 Base + 0x011F EDMA_CPR31 eDMA channel 31 priority register 8 Reserved — Base + 0x0120–0x0FFF — Base + 0x1000 TCD00 eDMA transfer control descriptor 00 256 Base + 0x1020 TCD01 eDMA transfer control descriptor 01 256 Base + 0x1040 TCD02 eDMA transfer control descriptor 02 256 Base + 0x1060 TCD03 eDMA transfer control descriptor 03 256 Base + 0x1080 TCD04 eDMA transfer control descriptor 04 256 Base + 0x10A0 TCD05 eDMA transfer control descriptor 05 256 Base + 0x10C0 TCD06 eDMA transfer control descriptor 06 256 Base + 0x10E0 TCD07 eDMA transfer control descriptor 07 256 Base + 0x1100 TCD08 eDMA transfer control descriptor 08 256 Base + 0x1120 TCD09 eDMA transfer control descriptor 09 256 Base + 0x1140 TCD10 eDMA transfer control descriptor 10 256 Base + 0x1160 TCD11 eDMA transfer control descriptor 11 256 Base + 0x1180 TCD12 eDMA transfer control descriptor 12 256 Base + 0x11A0 TCD13 eDMA transfer control descriptor 13 256 Base + 0x11C0 TCD14 eDMA transfer control descriptor 14 256 Base + 0x11E0 TCD15 eDMA transfer control descriptor 15 256 Base + 0x1200 TCD16 eDMA transfer control descriptor 16 256 Base + 0x1220 TCD17 eDMA transfer control descriptor 17 256 Base + 0x1240 TCD18 eDMA transfer control descriptor 18 256 Base + 0x1260 TCD19 eDMA transfer control descriptor 19 256 Base + 0x1280 TCD20 eDMA transfer control descriptor 20 256 Base + 0x12A0 TCD21 eDMA transfer control descriptor 21 256 Base + 0x12C0 TCD22 eDMA transfer control descriptor 22 256 Base + 0x12E0 TCD23 eDMA transfer control descriptor 23 256 Base + 0x1300 TCD24 eDMA transfer control descriptor 24 256 Base + 0x1320 TCD25 eDMA transfer control descriptor 25 256 Base + 0x1340 TCD26 eDMA transfer control descriptor 26 256 Base + 0x1360 TCD27 eDMA transfer control descriptor 27 256 Base + 0x1380 TCD28 eDMA transfer control descriptor 28 256 Base + 0x13A0 TCD29 eDMA transfer control descriptor 29 256 MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 9-5 Table 9-1. eDMA 32-bit Memory Map (Continued) Address Register Name Register Description Bits Base + 0x13C0 TCD30 eDMA transfer control descriptor 30 256 Base + 0x13E0 TCD31 eDMA transfer control descriptor 31 256 Base + 0x1400–0x17FC 9.2.2 — Reserved — Register Descriptions Read operations on reserved bits in a register return undefined data. Do not write operations to reserved bits. Writing to reserved bits in a register can generate errors. The maximum register bit-width for this device is 32-bits wide. 9.2.2.1 eDMA Control Register (EDMA_CR) The 32-bit EDMA_CR defines the basic operating configuration of the eDMA. The eDMA arbitrates channel service requests in two groups (0, 1) of 16 channels each: • Group 0 contains channels 0–15 • Group 1 contains channels 16–31 Arbitration within a group can be configured to use either fixed-priority or round-robin. In fixed-priority arbitration, the highest priority channel requesting service is selected to execute. The priorities are assigned by the channel priority registers. In round-robin arbitration mode, the channel priorities are ignored and the channels within each group are cycled through, from channel 15 down to channel 0, without regard to priority. See Section 9.2.2.15, “eDMA Channel n Priority Registers (EDMA_CPRn).” The group priorities operate in a similar process. In group fixed-priority arbitration mode, channel service requests in the highest priority group are executed first where priority level 1 is the highest and priority level 0 is the lowest. The group priorities are assigned in the GRPnPRI fields of the eDMA control register (EDMA_CR). All group priorities must have unique values prior to any channel service requests occur, otherwise a configuration error is reported. In group round-robin mode, the group priorities are ignored and the groups are cycled through, from group 1 down to group 0, without regard to priority. MPC5533 Microcontroller Reference Manual, Rev. 0 9-6 Freescale Semiconductor Address: Base + 0x0000 Access: User R/W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 0 0 0 0 GRP1 PRI 0 GRP0 PRI 0 0 0 0 1 0 0 0 R W Reset R W Reset 1 1 1 0 0 0 ERGA ERCA EDBG 0 0 0 0 0 0 0 Figure 9-2. eDMA Control Register (EDMA_CR) Table 9-2. EDMA_CR Field Descriptions Field 0–20 21 GRP1PRI 22 23 GRP0PRI Description Reserved Channel group 1 priority. Group 1 priority level when fixed-priority group arbitration is enabled. Reserved Channel group 0 priority. Group 0 priority level when fixed-priority group arbitration is enabled. 24–27 Reserved 28 ERGA Enable round-robin group arbitration. 0 Fixed-priority arbitration is used for selection among the groups. 1 Round-robin arbitration is used for selection among the groups. 29 ERCA Enable round-robin channel arbitration. 0 Fixed-priority arbitration is used for channel selection within each group. 1 Round-robin arbitration is used for channel selection within each group. 30 EDBG Enable debug. 0 The assertion of the system debug control input is ignored. 1 The assertion of the system debug control input causes the eDMA to stall the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when either the system debug control input is negated or the EDBG bit is cleared. 31 Reserved MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 9-7 9.2.2.2 eDMA Error Status Register (EDMA_ESR) The EDMA_ESR provides information concerning the last recorded channel error. Channel errors can be caused by a configuration error (an invalid setting in the transfer control descriptor or an invalid priority register setting in fixed arbitration mode) or an error termination to a bus master read or write cycle. A configuration error is caused when the starting source or destination address, source or destination offsets, minor loop byte count, and the transfer size represent an inconsistent state. The addresses and offsets must be aligned on 0-modulo-transfer_size boundaries, and the minor loop byte count must be a multiple of the source and destination transfer sizes. All source reads and destination writes must be configured to the natural boundary of the programmed transfer size respectively. In fixed arbitration mode, a configuration error is caused by any two channel priorities being equal within a group, or any group priority levels being equal among the groups. For either type of priority configuration error, the ERRCHN field is undefined. All channel priority levels within a group must be unique and all group priority levels among the groups must be unique when fixed arbitration mode is enabled. If a scatter/gather operation is enabled upon channel completion, a configuration error is reported if the scatter/gather address (DLAST_SGA) is not aligned on a 32-byte boundary. If minor loop channel linking is enabled upon channel completion, a configuration error is reported when the link is attempted if the TCD.CITER.E_LINK bit does not equal the TCD.BITER.E_LINK bit. All configuration error conditions except scatter/gather and minor loop link error are reported as the channel is activated and assert an error interrupt request if enabled. When correctly enabled, a scatter/gather configuration error is reported when the scatter/gather operation begins at major loop completion. A minor loop channel link configuration error is reported when the link operation is serviced at minor loop completion. If a system bus read or write is terminated with an error, the data transfer is immediately stopped and the appropriate bus error flag is set. In this case, the state of the channel’s transfer control descriptor is updated by the eDMA engine with the current source address, destination address, and minor loop byte count at the point of the fault. If a bus error occurs on the last read prior to beginning the write sequence, the write executes using the data captured during the bus error. If a bus error occurs on the last write prior to switching to the next read sequence, the read sequence executes before the channel is terminated due to the destination bus error. The occurrence of any type of error causes the eDMA engine to stop the active channel, and the appropriate channel bit in the eDMA error register to be asserted. At the same time, the details of the error condition are loaded into the EDMA_ESR. The major loop complete indicators, setting the transfer control descriptor DONE flag and the possible assertion of an interrupt request, are not affected when an error is detected. After the error status has been updated, the eDMA engine continues to operate by servicing the next appropriate channel. A channel that experiences an error condition is not automatically disabled. If a channel is terminated by an error and then issues another service request before the error is fixed, that channel executes and terminates with the same error condition. MPC5533 Microcontroller Reference Manual, Rev. 0 9-8 Freescale Semiconductor Address: Base + 0x0004 0 Access: User R/O 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SAE SOE DAE DOE NCE SGE SBE DBE 0 0 0 0 0 0 0 0 R VLD W Reset R GPE CPE ERRCHN W Reset 0 0 0 0 0 0 0 0 Figure 9-3. eDMA Error Status Register (EDMA_ESR) Table 9-3. EDMA_ESR Field Descriptions Field Description 0 VLD Logical OR of all EDMA_ERH and EDMA_ERL status bits. 0 No EDMA_ER bits are set. 1 At least one EDMA_ER bit is set indicating a valid error exists that has not been cleared. 1–15 Reserved 16 GPE Group priority error. 0 No group priority error. 1 The last recorded error was a configuration error among the group priorities indicating not all group priorities are unique. 17 CPE Channel priority error. 0 No channel priority error. 1 The last recorded error was a configuration error in the channel priorities within a group, indicating not all channel priorities within a group are unique. 18–23 Error channel number. Channel number of the last recorded error (excluding GPE and CPE errors). ERRCHN[0:5] Note: Do not rely on the number in the ERRCHN field for group and channel priority errors. Group and channel priority errors must be resolved by inspection. The application code must interrogate the priority registers to find groups or channels with duplicate priority level. 24 SAE Source address error. 0 No source address configuration error. 1 The last recorded error was a configuration error detected in the TCD.SADDR field, indicating TCD.SADDR is inconsistent with TCD.SSIZE. 25 SOE Source offset error. 0 No source offset configuration error. 1 The last recorded error was a configuration error detected in the TCD.SOFF field, indicating TCD.SOFF is inconsistent with TCD.SSIZE. 26 DAE Destination address error. 0 No destination address configuration error. 1 The last recorded error was a configuration error detected in the TCD.DADDR field, indicating TCD.DADDR is inconsistent with TCD.DSIZE. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 9-9 Table 9-3. EDMA_ESR Field Descriptions (Continued) Field Description 27 DOE Destination offset error. 0 No destination offset configuration error. 1 The last recorded error was a configuration error detected in the TCD.DOFF field, indicating TCD.DOFF is inconsistent with TCD.DSIZE. 28 NCE NBYTES/CITER configuration error. 0 No NBYTES/CITER configuration error. 1 The last recorded error was a configuration error detected in the TCD.NBYTES or TCD.CITER fields, indicating the following conditions exist: • TCD.NBYTES is not a multiple of TCD.SSIZE and TCD.DSIZE, or • TCD.CITER is equal to zero, or • TCD.CITER.E_LINK is not equal to TCD.BITER.E_LINK. 29 SGE Scatter/gather configuration error. 0 No scatter/gather configuration error. 1 The last recorded error was a configuration error detected in the TCD.DLAST_SGA field, indicating TCD.DLAST_SGA is not on a 32-byte boundary. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCD.E_SG is enabled. 30 SBE Source bus error. 0 No source bus error. 1 The last recorded error was a bus error on a source read. 31 DBE Destination bus error. 0 No destination bus error. 1 The last recorded error was a bus error on a destination write. Address: Base + 0x000C 0 Access: User R/W 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ERQ 30 ERQ 29 ERQ 28 ERQ 27 ERQ 26 ERQ 25 ERQ 24 ERQ 23 ERQ 22 ERQ 21 ERQ 20 ERQ 19 ERQ 18 ERQ 17 ERQ 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 ERQ 14 ERQ 13 ERQ 12 ERQ 11 ERQ 10 ERQ 09 ERQ 08 ERQ 07 ERQ 06 ERQ 05 ERQ 04 ERQ 03 ERQ 02 ERQ 01 ERQ 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R ERQ W 31 Reset R ERQ W 15 Reset 0 Figure 9-4. eDMA Enable Request Low Register (EDMA_ERQRL) Table 9-4. EDMA_ERQRL Field Descriptions Field 0–31 ERQn Description Enable DMA hardware service request n. 0 The DMA request signal for channel n is disabled. 1 The DMA request signal for channel n is enabled. MPC5533 Microcontroller Reference Manual, Rev. 0 9-10 Freescale Semiconductor As a given channel completes the processing of its major iteration count, there is a flag in the transfer control descriptor that can affect the ending state of the EDMA_ERQR bit for that channel. If the TCD.D_REQ bit is set, then the corresponding EDMA_ERQR bit is cleared after the major loop is complete, disabling the DMA hardware request. Otherwise if the D_REQ bit is cleared, the state of the EDMA_ERQR bit is unaffected. 9.2.2.3 eDMA Enable Error Interrupt Register (EDMA_EEIRL) The EDMA_EEIRL provides a bit map for the 32 channels to enable the error interrupt signal for each channel. EDMA_EEIRL maps to channels 31-0. The state of any given channel’s error interrupt enable is directly affected by writes to these registers; it is also affected by writes to the EDMA_SEEIR and EDMA_CEEIR. The EDMA_SEEIR and EDMA_CEEIR are provided so that the error interrupt enable for a single channel can easily be modified without the need to perform a read-modify-write sequence to the EDMA_EEIRL. Both the DMA error indicator and this error interrupt enable flag must be asserted before an error interrupt request for a given channel is asserted. Address: Base + 0x0014 R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 EEI 31 EEI 30 EEI 29 EEI 28 EEI 27 EEI 26 EEI 25 EEI 24 EEI 23 EEI 22 EEI 21 EEI 20 EEI 19 EEI 18 EEI 17 EEI 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 EEI 15 EEI 14 EEI 13 EEI 12 EEI 11 EEI 10 EEI 09 EEI 08 EEI 07 EEI 06 EEI 05 EEI 04 EEI 03 EEI 02 EEI 01 EEI 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset R W Access: User R/W Reset Figure 9-5. eDMA Enable Error Interrupt Low Register (EDMA_EEIRL) Table 9-5. EDMA_EEIRL Field Descriptions Field 0–31 EEIn 9.2.2.4 Description Enable error interrupt n. 0 The error signal for channel n does not generate an error interrupt. 1 The assertion of the error signal for channel n generate an error interrupt request. eDMA Set Enable Request Register (EDMA_SERQR) The EDMA_SERQR is a simple memory-mapped mechanism used to enable the DMA request for a given channel by setting a bit in the EDMA_ERQRL. The data value on a register write sets the bit in the EDMA_ERQRL. Bit 1 (SERQn) is a global set function that asserts the entire contents of EDMA_ERQRL. Reads of this register return all zeroes. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 9-11 Address: Base + 0x0018 R Access: User W/O 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 0 0 0 W Reset SERQ[0:6] 0 0 0 0 0 Figure 9-6. eDMA Set Enable Request Register (EDMA_SERQR) Table 9-6. EDMA_SERQR Field Descriptions Field Descriptions 0 Reserved 1–7 SERQ [0:6] 9.2.2.5 Set enable request. 0–31 Set corresponding bit in EDMA_ERQRL 32–63 Reserved 64–127 Set all bits in EDMA_ERQRH and EDMA_ERQRL Bit 2 (SERQ1) is not used. eDMA Clear Enable Request Register (EDMA_CERQR) The EDMA_CERQR provides a simple memory-mapped mechanism to clear a given bit in the EDMA_ERQRL to disable the DMA request for a given channel. The data value on a register write causes the corresponding bit in the EDMA_ERQRL to be cleared. Setting bit 1 (CERQn) provides a global clear function, forcing the entire contents of the EDMA_ERQRL to be zeroed, disabling all DMA request inputs. Reads of this register return all zeroes. Address: Base + 0x0019 R Access: User W/O 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 0 0 0 W Reset CERQ[0:6] 0 0 0 0 0 Figure 9-7. eDMA Clear Enable Request Register (EDMA_CERQR) Table 9-7. EDMA_CERQR Field Descriptions Field Description 0 Reserved 1–7 CERQ[0:6] Clear enable request. 0–31 Clear corresponding bit in EDMA_ERQRL 32–63 Reserved 64–127 Clear all bits in EDMA_ERQRH and EDMA_ERQRL Bit 2 (CERQ1) is not used. MPC5533 Microcontroller Reference Manual, Rev. 0 9-12 Freescale Semiconductor 9.2.2.6 eDMA Set Enable Error Interrupt Register (EDMA_SEEIR) The EDMA_SEEIR provides a simple memory-mapped mechanism to set a given bit in the EDMA_EEIRL to enable the error interrupt for a given channel. The data value on a register write causes the corresponding bit in the EDMA_EEIRL to be set. Setting bit 1 (SEEIn) provides a global set function, forcing the entire contents of EDMA_EEIRL to be asserted. Reads of this register return all zeroes. Address: Base + 0x001A R Access: User W/O 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 0 0 0 W Reset SEEI[0:6] 0 0 0 0 0 Figure 9-8. eDMA Set Enable Error Interrupt Register (EDMA_SEEIR) Table 9-8. EDMA_SEEIR Field Descriptions Field Description 0 Reserved 1–7 SEEI[0:6] Set enable error interrupt. 0–31 Set corresponding bit in EDMA_EIRRL 32–63 Reserved 64–127 Set all bits in EDMA_EEIRH or EDMA_EEIRL Bit 2 (SEEI1) is not used. 9.2.2.7 eDMA Clear Enable Error Interrupt Register (EDMA_CEEIR) The EDMA_CEEIR provides a simple memory-mapped mechanism to clear a given bit in the EDMA_EEIRL which disables the error interrupt for a given channel. The data value on a register write causes the corresponding bit in the EDMA_EEIRL to be cleared. Setting bit 1 (CEEIn) provides a global clear function, forcing the entire contents of the EDMA_EEIRL to be zeroed, disabling error interrupts for all channels. Reads of this register return all zeroes. Address: Base + 0x001B R Access: User W/O 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 0 0 0 W Reset CEEI[0:6] 0 0 0 0 0 Figure 9-9. eDMA Clear Enable Error Interrupt Register (EDMA_CEEIR) MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 9-13 Table 9-9. EDMA_CEEIR Field Descriptions Field Description 0 Reserved 1–7 CEEI[0:6] Clear enable error interrupt. 0–31 Clear corresponding bit in EDMA_EEIRL 32–63 Reserved 64–127 Clear all bits in EDMA_EEIRH or EDMA_EEIRL Bit 2 (CEEI1) is not used. 9.2.2.8 eDMA Clear Interrupt Request Register (EDMA_CIRQR) The EDMA_CIRQR provides a simple memory-mapped mechanism to clear a given bit in the EDMA_IRQRL to disable the interrupt request for a given channel. The given value on a register write causes the corresponding bit in the EDMA_IRQRL to be cleared. Setting bit 1 (CINTn) provides a global clear function, forcing the entire contents of the EDMA_IRQRL to be zeroed, disabling all DMA interrupt requests. Reads of this register return all zeroes. Address: Base + 0x001C R Access: User W/O 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 0 0 0 W Reset CINT[0:6] 0 0 0 0 0 Figure 9-10. eDMA Clear Interrupt Request (EDMA_CIRQR) Table 9-10. EDMA_CIRQR Field Descriptions Field Description 0 Reserved 1–7 CINT[0:6] Clear interrupt request. 0–31 Clear corresponding bit in EDMA_IRQRL 32–63 Reserved 64–127 Clear all bits in EDMA_IRQRH or EDMA_IRQRL Bit 2 (CINT1) is not used. 9.2.2.9 eDMA Clear Error Register (EDMA_CER) The EDMA_CER provides a simple memory-mapped mechanism to clear a given bit in the EDMA_ERL to disable the error condition flag for a given channel. The given value on a register write causes the corresponding bit in the EDMA_ERL to be cleared. Setting bit 1 (CERRn) provides a global clear function, forcing the entire contents of the EDMA_ERL to be zeroed, clearing all channel error indicators. Reads of this register return all zeroes. MPC5533 Microcontroller Reference Manual, Rev. 0 9-14 Freescale Semiconductor Address: Base + 0x001D R Access:User W/O 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 0 0 0 CERR[0:6] W Reset 0 0 0 0 0 Figure 9-11. eDMA Clear Error Register (EDMA_CER) Table 9-11. EDMA_CER Field Descriptions Field 0 1–7 CERR[0:6] Description Reserved Clear error indicator. 0–31 Clear corresponding bit in EDMA_ERL 32–63 Reserved 64–127 Clear all bits in EDMA_ERH or EDMA_ERL Bit 2 (CERR1) is not used. 9.2.2.10 eDMA Set START Bit Register (EDMA_SSBR) The EDMA_SSBR provides a memory-mapped mechanism to set the START bit in the TCD for a channel. The data value on a register write sets the START bit in the transfer control descriptor. SSBn is a global set function that sets all START bits for a channel. Reads of this register return all zeroes. Address: Base + 0x001E R Access: User W/O 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 0 0 0 W Reset SSB[0:6] 0 0 0 0 0 Figure 9-12. eDMA Set START Bit Register (EDMA_SSBR) Table 9-12. EDMA_SSBR Field Descriptions Field 0 1–7 SSB[0:6] Description Reserved Set START bit (channel service request). 0–31 Set the corresponding channel’s TCD START bit 32–63 Reserved 64–127 Set all TCD START bits Bit 2 (SSB1) is not used. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 9-15 9.2.2.11 eDMA Clear DONE Status Bit Register (EDMA_CDSBR) The EDMA_CDSBR provides a simple memory-mapped mechanism to clear the DONE bit in the TCD of the given channel. The data value on a register write causes the DONE bit in the corresponding transfer control descriptor to be cleared. Setting bit 1 (CDSBn) provides a global clear function, forcing all DONE bits to be cleared. Address: Base + 0x001F R Access: User W/O 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 0 0 0 CDSB[0:6] W Reset 0 0 0 0 0 Figure 9-13. eDMA Clear DONE Status Bit Register (EDMA_CDSBR) Table 9-13. EDMA_CDSBR Field Descriptions Field 0 1–7 CDSB[0:6] Description Reserved Clear DONE status bit. 0–31 Clear the corresponding channel’s DONE bit 32–63 Reserved 64–127 Clear all TCD DONE bits Bit 2 (CDSB1) is not used. 9.2.2.12 eDMA Interrupt Request Register (EDMA_IRQRL) The EDMA_IRQRL provide a bit map for the 32 channels signaling the presence of an interrupt request for each channel. EDMA_IRQRL maps to channels 31–0. The eDMA engine signals the occurrence of a programmed interrupt upon the completion of a data transfer as defined in the transfer control descriptor by setting the appropriate bit in this register. The outputs of this register are directly routed to the interrupt controller (INTC). During the execution of the interrupt service routine associated with any given channel, it is software’s responsibility to clear the appropriate bit, negating the interrupt request. Typically, a write to the EDMA_CIRQR in the interrupt service routine is used for this purpose. The state of any given channel’s interrupt request is directly affected by writes to this register; it is also affected by writes to the EDMA_CIRQR. On writes to the EDMA_IRQRL, a 1 in any bit position clears the corresponding channel’s interrupt request. A zero in any bit position has no affect on the corresponding channel’s current interrupt status. The EDMA_CIRQR is provided so the interrupt request for a single channel can easily be cleared without the need to perform a read-modify-write sequence to the EDMA_IRQRL. MPC5533 Microcontroller Reference Manual, Rev. 0 9-16 Freescale Semiconductor Address: Base + 0x0024 R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 INT 31 INT 30 INT 29 INT 28 INT 27 INT 26 INT 25 INT 24 INT 23 INT 22 INT 21 INT 20 INT 19 INT 18 INT 17 INT 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 INT 15 INT 14 INT 13 INT 12 INT 11 INT 10 INT 09 INT 08 INT 07 INT 06 INT 05 INT 04 INT 03 INT 02 INT 01 INT 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset R W Access: User R/W Reset Figure 9-14. eDMA Interrupt Request Low Register (EDMA_IRQRL) Table 9-14. EDMA_IRQRL Field Descriptions Field 0–31 INTn 9.2.2.13 Description eDMA interrupt request n. 0 The interrupt request for channel n is cleared. 1 The interrupt request for channel n is active. eDMA Error Register (EDMA_ERL) The EDMA_ERL provides a bit map for the 32 channels signaling the presence of an error for each channel. EDMA_ERL maps to channels 31-0. The eDMA engine signals the occurrence of a error condition by setting the appropriate bit in this register. The outputs of this register are enabled by the contents of the EDMA_EEIR, then logically summed across groups of 16 and 32 channels to form several group error interrupt requests which is then routed to the interrupt controller. During the execution of the interrupt service routine associated with any DMA errors, it is software’s responsibility to clear the appropriate bit, negating the error interrupt request. Typically, a write to the EDMA_CER in the interrupt service routine is used for this purpose. Recall the normal DMA channel completion indicators, setting the transfer control descriptor DONE flag and the possible assertion of an interrupt request, are not affected when an error is detected. The contents of this register can also be polled and a non-zero value indicates the presence of a channel error, regardless of the state of the EDMA_EEIR. The EDMA_ESR[VLD] bit is a logical OR of all bits in this register and it provides a single bit indication of any errors. The state of any given channel’s error indicators is affected by writes to this register; it is also affected by writes to the EDMA_CER. On writes to EDMA_ERL, a 1 in any bit position clears the corresponding channel’s error status. A 0 in any bit position has no affect on the corresponding channel’s current error status. The EDMA_CER is provided so the error indicator for a single channel can easily be cleared. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 9-17 Address: Base + 0x002C 0 Access: User R/W 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ERR 30 ERR 29 ERR 28 ERR 27 ERR 26 ERR 25 ERR 24 ERR 23 ERR 22 ERR 21 ERR 20 ERR 19 ERR 18 ERR 17 ERR 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 ERR 14 ERR 13 ERR 12 ERR 11 ERR 10 ERR 09 ERR 08 ERR 07 ERR 06 ERR 05 ERR 04 ERR 03 ERR 02 ERR 01 ERR 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R ERR W 31 Reset R ERR W 15 Reset 0 Figure 9-15. eDMA Error Low Register (EDMA_ERL) Table 9-15. EDMA_ERL Field Descriptions Field Description 0–31 ERRn eDMA Error n. 0 An error in channel n has not occurred. 1 An error in channel n has occurred. 9.2.2.14 DMA Hardware Request Status (EDMA_HRSL) The EDMA_HRSL registers provide a bit map for the implemented channels (16 or 32 channels) to show the current hardware request status for each channel. EDMA_HRSL supports channels 31–0. See Table 9-16 for the EDMA_HRS definition. Address: Base + 0x0034 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 HRS 30 HRS 29 HRS 28 HRS 27 HRS 26 HRS 25 HRS 24 HRS 23 HRS 22 HRS 21 HRS 20 HRS 19 HRS 18 HRS 17 HRS 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 HRS 14 HRS 13 HRS 12 HRS 11 HRS 10 HRS 09 HRS 08 HRS 07 HRS 06 HRS 05 HRS 04 HRS 03 HRS 02 HRS 01 HRS 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R HRS W 31 Reset R HRS W 15 Reset Access: User R/W 0 Figure 9-16. EDMA Hardware Request Status Register Low (EDMA_HRSL) MPC5533 Microcontroller Reference Manual, Rev. 0 9-18 Freescale Semiconductor Table 9-16. EDMA_HRSL Field Descriptions Field 0–31 HRSn 9.2.2.15 Description DMA Hardware Request Status 0 A hardware service request for channel n is not present. 1 A hardware service request for channel n is present. Note: The hardware request status reflects the state of the request as seen by the arbitration logic. Therefore, this status is affected by the EDMA_ERQRL[ERQn] bit. eDMA Channel n Priority Registers (EDMA_CPRn) When the fixed-priority channel arbitration mode is enabled (EDMA_CR[ERCA] = 0), the contents of these registers define the unique priorities associated with each channel within a group. The channel priorities are evaluated by numeric value; that is, 0 is the lowest priority, 1 is the next higher priority, then 2, 3, etc. If software chooses to modify channel priority values, then the software must ensure that the channel priorities contain unique values, otherwise a configuration error is reported. The range of the priority value is limited to the values of 0 through 15. When read, the GRPPRI bits of the EDMA_CPRn register reflect the current priority level of the group of channels in which the corresponding channel resides. GRPPRI bits are not affected by writes to the EDMA_CPRn registers. The group priority is assigned in the EDMA_CR. See Figure 9-2 and Table 9-2 for the EDMA_CR definition. Channel preemption is enabled on a per-channel basis by setting the ECP bit in the EDMA_CPRn register. Channel preemption allows the executing channel’s data transfers to be temporarily suspended in favor of starting a higher priority channel. After the preempting channel has completed all of its minor loop data transfers, the preempted channel is restored and resumes execution. After the restored channel completes one read/write sequence, it is again eligible for preemption. If any higher priority channel is requesting service, the restored channel is suspended and the higher priority channel is serviced. Nested preemption (attempting to preempt a preempting channel) is not supported. After a preempting channel begins execution, it cannot be preempted. Preemption is only available when fixed arbitration is selected for both group and channel arbitration modes. Address: Base + (0x100 + n) 0 R Access: User R/W 1 2 3 0 GRPPRI 4 5 ECP 6 7 CHPRI W Reset 0 1 0 —1 The reset value for the group and channel priority fields, GRPPRI[0–1] and CHPRI[0–3] is the channel number for the priority register; EDMA_CPR31[GRPPRI] = 0b01 and EDMA_CPR31[CHPRI] = 0b1111. Figure 9-17. eDMA Channel n Priority Register (EDMA_CPRn) MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 9-19 The following table describes the fields in the eDMA channel n priority register: Table 9-17. EDMA_CPRn Field Descriptions Field 0 ECP 1 2–3 GRPPRI [0:1] 4–7 CHPRI [0:3] 9.2.2.16 Description Enable channel preemption. 0 Channel n cannot be suspended by a higher priority channel’s service request. 1 Channel n can be temporarily suspended by the service request of a higher priority channel. Reserved Channel n current group priority. Group priority assigned to this channel group when fixed-priority arbitration is enabled. These two bits are read only; writes are ignored. The reset value for the group priority fields, is equal to the corresponding channel number for each priority register; that is, EDMA_CPR31[GRPPRI] = 0b01. Channel n arbitration priority. Channel priority when fixed-priority arbitration is enabled. The reset value for the channel priority fields CHPRI[0–3], is equal to the corresponding channel number for each priority register; that is, EDMA_CPR31[CHPRI] = 0b1111. Transfer Control Descriptor (TCD) Each channel requires a 256-bit transfer control descriptor for defining the desired data movement operation. The channel descriptors are stored in the local memory in sequential order: channel 0, channel 1,... channel 31. The definitions of the TCD are presented as 23 variable-length fields. Table 9-18 defines the fields of the basic TCD structure. Table 9-18. TCDn 32-bit Memory Structure eDMA Bit Offset Bit Length 0x1000 + (32 x n) + 0 32 0x1000 + (32 x n) + 32 TCDn Field Name TCDn Abbreviation Word # Source address SADDR Word 0 5 Source address modulo SMOD 0x1000 + (32 x n) + 37 3 Source data transfer size SSIZE 0x1000 + (32 x n) + 40 5 Destination address modulo DMOD 0x1000 + (32 x n) + 45 3 Destination data transfer size DSIZE 0x1000 + (32 x n) + 48 16 Signed source address offset SOFF 0x1000 + (32 x n) + 64 32 Inner minor byte count NBYTES Word 2 0x1000 + (32 x n) + 96 32 Last source address adjustment SLAST Word 3 0x1000 + (32 x n) + 128 32 Destination address DADDR Word 4 0x1000 + (32 x n) + 160 1 Channel-to-channel linking on minor loop complete CITER.E_LINK 0x1000 + (32 x n) + 161 6 Current major iteration count or Link channel number CITER or CITER.LINKCH 0x1000 + (32 x n) + 167 9 Current major iteration count CITER 0x1000 + (32 x n) + 176 16 Destination address offset (signed) DOFF Word 1 Word 5 MPC5533 Microcontroller Reference Manual, Rev. 0 9-20 Freescale Semiconductor Table 9-18. TCDn 32-bit Memory Structure (Continued) eDMA Bit Offset Bit Length 0x1000 + (32 x n) + 192 32 Last destination address adjustment / scatter gather address 0x1000 + (32 x n) + 224 1 Channel-to-channel Linking on Minor Loop Complete BITER.E_LINK 0x1000 + (32 x n) + 225 6 Starting major iteration count or link channel number BITER or BITER.LINKCH 0x1000 + (32 x n) + 231 9 Starting major iteration count BITER 0x1000 + (32 x n) + 240 2 Bandwidth control BWC 0x1000 + (32 x n) + 242 6 Link channel number MAJOR.LINKCH 0x1000 + (32 x n) + 248 1 Channel done DONE 0x1000 + (32 x n) + 249 1 Channel active ACTIVE 0x1000 + (32 x n) + 250 1 Channel-to-channel linking on major loop complete MAJOR.E_LINK 0x1000 + (32 x n) + 251 1 Enable scatter/gather processing E_SG 0x1000 + (32 x n) + 252 1 Disable request D_REQ 0x1000 + (32 x n) + 253 1 Channel interrupt enable when current major iteration count is half complete INT_HALF 0x1000 + (32 x n) + 254 1 Channel interrupt enable when current major iteration count complete INT_MAJ 0x1000 + (32 x n) + 255 1 Channel start START TCDn Field Name TCDn Abbreviation Word # DLAST_SGA Word 6 Word 7 MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 9-21 Figure 9-18 defines the fields of the TCDn structure. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x0000 SADDR 0x0004 SMOD SSIZE DMOD DSIZE SOFF NBYTES 0x000C SLAST 0x0010 DADDR CITER1 or CITER.LINKCH CITER1 Figure 9-18. TCD Structure 1 If channel linking on minor link completion is disabled, TCD bits [161:175] are used to form a 15-bit CITER field; if channel-to-channel linking is enabled, CITER becomes a 9-bit field. 2 If channel linking on minor link completion is disabled, TCD bits [225:239] are used to form a 15-bit BITER field; if channel-to-channel linking is enabled, BITER becomes a 9-bit field. NOTE The TCD structures for the eDMA channels shown in Figure 9-18 are implemented in internal SRAM. These structures are not initialized at reset. Therefore, all channel TCD parameters must be initialized by the application code before activating that channel. MPC5533 Microcontroller Reference Manual, Rev. 0 9-22 Freescale Semiconductor START INT_MAJ MAJOR LINKCH D_REQ BWC INT_HALF BITER2 E_SG BITER2 or BITER.LINKCH ACTIVE 0x001C DLAST_SGA BITER.E_ LINK 0x0018 DOFF MAJOR.E_LINK 0x0014 CITER.E_ LINK 0x0008 DONE Word Offset The following table gives a detailed description of the TCDn fields: Table 9-19. TCDn Field Descriptions Bits Word Offset [n:n] Field Name Description 0–31 0x0000 [0:31] SADDR [0:31] Source address. Memory address pointing to the source data. Word 0x0, bits 0–31. 32–36 0x0004 [0:4] SMOD [0:4] Source address modulo. 0 Source address modulo feature is disabled. not 0 This value defines a specific address range which is specified to be either the value after SADDR + SOFF calculation is performed or the original register value. The setting of this field provides the ability to easily implement a circular data queue. For data queues requiring power-of-2 “size” bytes, start the queue at a 0-modulo-size address and set the SMOD field to the value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits that are allowed to change. For this circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 37–39 0x0004 [5:7] SSIZE [0:2] Source data transfer size. 000 8-bit 001 16-bit 010 32-bit 011 64-bit 100 32-bit 101 32-byte burst (64-bit x 4) 110 Reserved 111 Reserved The attempted specification of a ‘reserved’ encoding causes a configuration error. 40–44 0x0004 [8:12] DMOD [0:4] Destination address modulo. See the SMOD[0:5] definition. 45–47 0x0004 [13:15] DSIZE [0:2] Destination data transfer size. See the SSIZE[0:2] definition. 48–63 0x0004 [16:31] SOFF [0:15] Source address signed offset. Sign-extended offset applied to the current source address to form the next-state value as each source read is completed. 64–95 0x0008 [0:31] NBYTES [0:31] Inner “minor” byte transfer count. Number of bytes to be transferred in each service request of the channel. As a channel is activated, the contents of the appropriate TCD is loaded into the eDMA engine, and the appropriate reads and writes performed until the complete byte transfer count has been transferred. This is an indivisible operation and cannot be stalled or halted. Once the minor count is exhausted, the current values of the SADDR and DADDR are written back into the local memory, the major iteration count is decremented and restored to the local memory. If the major iteration count is completed, additional processing is performed. Note: The NBYTES value of 0x0000_0000 is interpreted as 0x1_0000_0000, thus specifying a four GB transfer. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 9-23 Table 9-19. TCDn Field Descriptions (Continued) Bits Word Offset [n:n] Field Name Description 96–127 0x000C [0:31] SLAST [0:31] Last source address adjustment. Adjustment value added to the source address at the completion of the outer major iteration count. This value can be applied to “restore” the source address to the initial value, or adjust the address to reference the next data structure. 128–159 0x0010 [0:31] DADDR [0:31] Destination address. Memory address pointing to the destination data. 160 0x0014 [0] CITER.E_LINK Enable channel-to-channel linking on minor loop completion. As the channel completes the inner minor loop, this flag enables the linking to another channel, defined by CITER.LINKCH[0:5]. The link target channel initiates a channel service request via an internal mechanism that sets the TCD.START bit of the specified channel. If channel linking is disabled, the CITER value is extended to 15 bits in place of a link channel number. If the major loop is exhausted, this link mechanism is suppressed in favor of the MAJOR.E_LINK channel linking. 0 The channel-to-channel linking is disabled. 1 The channel-to-channel linking is enabled. Note: This bit must be equal to the BITER.E_LINK bit otherwise a configuration error is reported. 161–166 0x0014 [1:6] CITER [0:5] or CITER.LINKCH [0:5] Current “major” iteration count or link channel number. If channel-to-channel linking is disabled (TCD.CITER.E_LINK = 0), then • No channel-to-channel linking (or chaining) is performed after the inner minor loop is exhausted. TCD bits [161:175] are used to form a 15-bit CITER field. otherwise • After the minor loop is exhausted, the eDMA engine initiates a channel service request at the channel defined by CITER.LINKCH[0:5] by setting that channel’s TCD.START bit. 167–175 0x0014 [7:15] CITER [6:14] Current “major” iteration count. This 9 or 15-bit count represents the current major loop count for the channel. It is decremented each time the minor loop is completed and updated in the transfer control descriptor memory. After the major iteration count is exhausted, the channel performs a number of operations (for example, final source and destination address calculations), optionally generating an interrupt to signal channel completion before reloading the CITER field from the beginning iteration count (BITER) field. Note: When the CITER field is initially loaded by software, it must be set to the same value as that contained in the BITER field. Note: If the channel is configured to execute a single service request, the initial values of BITER and CITER must be 0x0001. 176–191 0x0014 [16:31] DOFF [0:15] Destination address signed offset. Sign-extended offset applied to the current destination address to form the next-state value as each destination write is completed. MPC5533 Microcontroller Reference Manual, Rev. 0 9-24 Freescale Semiconductor Table 9-19. TCDn Field Descriptions (Continued) Bits Word Offset [n:n] Field Name Description 192–223 0x0018 [0:31] DLAST_SGA [0:31] Last destination address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather). If scatter/gather processing for the channel is disabled (TCD.E_SG = 0) then • Adjustment value added to the destination address at the completion of the outer major iteration count. This value can be applied to “restore” the destination address to the initial value, or adjust the address to reference the next data structure. Otherwise • This address points to the beginning of a 0-modulo-32 byte region containing the next transfer control descriptor to be loaded into this channel. This channel reload is performed as the major iteration count completes. The scatter/gather address must be 0-modulo-32 byte, otherwise a configuration error is reported. 224 0x001C [0] BITER.E_LINK Enables channel-to-channel linking on minor loop complete. As the channel completes the inner minor loop, this flag enables the linking to another channel, defined by BITER.LINKCH[0:5]. The link target channel initiates a channel service request via an internal mechanism that sets the TCD.START bit of the specified channel. If channel linking is disabled, the BITER value is extended to 15 bits in place of a link channel number. If the major loop is exhausted, this link mechanism is suppressed in favor of the MAJOR.E_LINK channel linking. 0 The channel-to-channel linking is disabled. 1 The channel-to-channel linking is enabled. Note: When the TCD is first loaded by software, this field must be set equal to the corresponding CITER field, otherwise a configuration error is reported. As the major iteration count is exhausted, the contents of this field is reloaded into the CITER field. 225–230 0x001C [1:6] BITER [0:5] or BITER.LINKCH [0:5] Beginning or starting “major” iteration count or link channel number. If channel-to-channel linking is disabled (TCD.BITER.E_LINK = 0), then • No channel-to-channel linking (or chaining) is performed after the inner minor loop is exhausted. TCD bits [225:239] are used to form a 15-bit BITER field. Otherwise • After the minor loop is exhausted, the eDMA engine initiates a channel service request at the channel, defined by BITER.LINKCH[0:5], by setting that channel’s TCD.START bit. Note: When the TCD is first loaded by software, this field must be set equal to the corresponding CITER field, otherwise a configuration error is reported. As the major iteration count is exhausted, the contents of this field is reloaded into the CITER field. 231–239 0x001C [7:15] BITER [6:14] Beginning or starting major iteration count. As the transfer control descriptor is first loaded by software, this field must be equal to the value in the CITER field. As the major iteration count is exhausted, the contents of this field is reloaded into the CITER field. Note: If the channel is configured to execute a single service request, the initial values of BITER and CITER must be 0x0001. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 9-25 Table 9-19. TCDn Field Descriptions (Continued) Bits Word Offset [n:n] Field Name Description 240–241 0x001C [16:17] BWC [0:1] Bandwidth control. This two-bit field provides a mechanism to effectively throttle the amount of bus bandwidth consumed by the eDMA. In general, as the eDMA processes the inner minor loop, it continuously generates read/write sequences until the minor count is exhausted. This field forces the eDMA to stall after the completion of each read/write access to control the bus request bandwidth seen by the system bus crossbar switch (XBAR). To minimize start-up latency, bandwidth control stalls are suppressed for the first two system bus cycles and after the last write of each minor loop. 00 No eDMA engine stalls 01 Reserved 10 eDMA engine stalls for four cycles after each r/w 11 eDMA engine stalls for eight cycles after each r/w 242–247 0x001C [18:23] MAJOR.LINKCH [0:5] Link channel number. If channel-to-channel linking on major loop complete is disabled (TCD.MAJOR.E_LINK = 0) then: • No channel-to-channel linking (or chaining) is performed after the outer major loop counter is exhausted. Otherwise • After the major loop counter is exhausted, the eDMA engine initiates a channel service request at the channel defined by MAJOR.LINKCH[0:5] by setting that channel’s TCD.START bit. 248 0x001C [24] DONE Channel done. This flag indicates the eDMA has completed the outer major loop. It is set by the eDMA engine as the CITER count reaches zero; it is cleared by software or hardware when the channel is activated (when the channel has begun to be processed by the eDMA engine, not when the first data transfer occurs). Note: This bit must be cleared to write the MAJOR.E_LINK or E_SG bits. 249 0x001C [25] ACTIVE 250 0x001C [26] MAJOR.E_LINK Enable channel-to-channel linking on major loop completion. As the channel completes the outer major loop, this flag enables the linking to another channel, defined by MAJOR.LINKCH[0:5]. The link target channel initiates a channel service request via an internal mechanism that sets the TCD.START bit of the specified channel. NOTE: To support the dynamic linking coherency model, this field is forced to zero when written to while the TCD.DONE bit is set. 0 The channel-to-channel linking is disabled. 1 The channel-to-channel linking is enabled. 251 0x001C [27] E_SG Enable scatter/gather processing. As the channel completes the outer major loop, this flag enables scatter/gather processing in the current channel. If enabled, the eDMA engine uses DLAST_SGA as a memory pointer to a 0-modulo-32 address containing a 32-byte data structure which is loaded as the transfer control descriptor into the local memory. NOTE: To support the dynamic scatter/gather coherency model, this field is forced to zero when written to while the TCD.DONE bit is set. 0 The current channel’s TCD is “normal” format. 1 The current channel’s TCD specifies a scatter gather format. The DLAST_SGA field provides a memory pointer to the next TCD to be loaded into this channel after the outer major loop completes its execution. Channel active. This flag signals the channel is currently in execution. It is set when channel service begins, and is cleared by the eDMA engine as the inner minor loop completes or if any error condition is detected. MPC5533 Microcontroller Reference Manual, Rev. 0 9-26 Freescale Semiconductor Table 9-19. TCDn Field Descriptions (Continued) Bits Word Offset [n:n] Field Name Description 252 0x001C [28] D_REQ Disable hardware request. If this flag is set, the eDMA hardware automatically clears the corresponding EDMA_ERQL bit when the current major iteration count reaches zero. 0 The channel’s EDMA_ERQL bit is not affected. 1 The channel’s EDMA_ERQL bit is cleared when the outer major loop is complete. 253 0x001C [29] INT_HALF Enable an interrupt when major counter is half complete. If this flag is set, the channel generates an interrupt request by setting the bit in the EDMA_ERQL when the current major iteration count reaches the halfway point. The eDMA engine performs the compare (CITER == (BITER >> 1)). This halfway point interrupt request supports double-buffered schemes, or where the processor needs an early indication of the data transfer’s progress during data movement. CITER = BITER = 1 with INT_HALF enabled generates an interrupt as it satisfies the equation (CITER == (BITER >> 1)) after a single activation. 0 The half-point interrupt is disabled. 1 The half-point interrupt is enabled. 254 0x001C [30] INT_MAJ Enable an interrupt when major iteration count completes. If this flag is set, the channel generates an interrupt request by setting the appropriate bit in the EDMA_ERQL when the current major iteration count reaches zero. 0 The end-of-major loop interrupt is disabled. 1 The end-of-major loop interrupt is enabled. 255 0x001C [31] START Channel start. If this flag is set, the channel is requesting service. The eDMA hardware automatically clears this flag after the channel begins execution. 0 The channel is not explicitly started. 1 The channel is explicitly started via a software initiated service request. 9.3 Functional Description This section provides an overview of the microarchitecture and functional operation of the eDMA module. 9.3.1 eDMA Microarchitecture The eDMA module is partitioned into two major modules: the eDMA engine and the transfer control descriptor local memory. Additionally, the eDMA engine is further partitioned into four submodules, which are detailed below. • eDMA engine — Address path: This module implements registered versions of two channel transfer control descriptors: channel ‘x’ and channel ‘y,’ and is responsible for all the master bus address calculations. All the implemented channels provide the exact same functionality. This hardware structure allows the data transfers associated with one channel to be preempted after the completion of a read/write sequence if a higher priority channel service request is asserted while the first channel is active. After a channel is activated, it runs until the minor loop is completed unless preempted by a higher priority channel. This capability provides a mechanism (optionally enabled by EDMA_CPRn[ECP]) where a large data move operation can be preempted to minimize the time another channel is blocked from execution. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 9-27 • When any other channel is activated, the contents of its transfer control descriptor is read from the local memory and loaded into the registers of the other address path channel{x,y}. After the inner minor loop completes execution, the address path hardware writes the new values for the TCDn.{SADDR, DADDR, CITER} back into the local memory. If the major iteration count is exhausted, additional processing is performed, including the final address pointer updates, reloading the TCDn.CITER field, and a possible fetch of the next TCDn from memory as part of a scatter/gather operation. — Data path: This module implements the actual bus master read/write datapath. It includes 32 bytes of register storage (matching the maximum transfer size) and the necessary mux logic to support any required data alignment. The system read data bus is the primary input, and the system write data bus is the primary output. The address and data path modules directly support the 2-stage pipelined system bus. The address path module represents the 1st stage of the bus pipeline (the address phase), while the data path module implements the 2nd stage of the pipeline (the data phase). — Program model/channel arbitration: This module implements the first section of eDMA’s programming model as well as the channel arbitration logic. The programming model registers are connected to the slave bus (not shown). The eDMA peripheral request inputs and eDMA interrupt request outputs are also connected to this module (via the Control logic). — Control: This module provides all the control functions for the eDMA engine. For data transfers where the source and destination sizes are equal, the eDMA engine performs a series of source read, destination write operations until the number of bytes specified in the inner ‘minor loop’ byte count has been moved. A minor loop interaction is defined as the number of bytes to transfer (nbytes) divided by the transfer size. Transfer size is defined as the following: if (SSIZE < DSIZE) transfer size = destination transfer size (# of bytes) else transfer size = source transfer size (# of bytes) Minor loop TCD variables are SOFF, SMOD, DOFF, DMOD, NBYTES, SADDR, DADDR, BWC, ACTIVE, AND START. Major loop TCD variables are DLAST, SLAST, CITER, BITER, DONE, D_REQ, INT_MAJ, MAJOR_LNKCH, and INT_HALF. For descriptors where the sizes are not equal, multiple access of the smaller size data are required for each reference of the larger size. As an example, if the source size references 16-bit data and the destination is 32-bit data, two reads are performed, then one 32-bit write. TCD local memory — Memory controller: This logic implements the required dual-ported controller, handling accesses from both the eDMA engine as well as references from the slave bus. As noted earlier, in the event of simultaneous accesses, the eDMA engine is given priority and the slave transaction is stalled. The hooks to a BIST controller for the local TCD memory are included in this module. — Memory array: The TCD is implemented using a single-ported, synchronous compiled RAM memory array. MPC5533 Microcontroller Reference Manual, Rev. 0 9-28 Freescale Semiconductor 9.3.2 eDMA Basic Data Flow The basic flow of a data transfer can be partitioned into three segments. As shown in Figure 9-19, the first segment involves the channel service request. In the diagram, this example uses the assertion of the eDMA peripheral request signal to request service for channel n. Channel service request via software and the TCDn.START bit follows the same basic flow as an eDMA peripheral request. The eDMA peripheral request input signal is registered internally and then routed to through the eDMA engine, first through the control module, then into the program model/channel arbitration module. In the next cycle, the channel arbitration is performed, either using the fixed-priority or round-robin algorithm. After the arbitration is complete, the activated channel number is sent through the address path and converted into the required address to access the TCD local memory. Next, the TCD memory is accessed and the required descriptor read from the local memory and loaded into the eDMA engine address path channel{x,y} registers. The TCD memory is organized 64-bits in width to minimize the time needed to fetch the activated channel’s descriptor and load it into the eDMA engine address path channel{x,y} registers. eDMA SRAM Transfer Control Descriptor (TCD) Slave Write Address Slave Write Data TCD0 TCDn-1* eDMA Engine Bus Read Data Slave Interface System Bus SRAM Program Model/ Channel Arbitration Data Path Address Path Control Slave Read Data Bus Write Data Bus Address *n = 32 channels eDMA Interrupt Request eDMA Done Handshake eDMA Peripheral Request Figure 9-19. eDMA Operation, Part 1 In the second part of the basic data flow as shown in Figure 9-20, the modules associated with the data transfer (address path, data path and control) sequence through the required source reads and destination writes to perform the actual data movement. The source reads are initiated and the fetched data is temporarily stored in the data path module until it is gated onto the system bus during the destination write. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 9-29 This source read/destination write processing continues until the inner minor byte count has been transferred. The eDMA Done Handshake signal is asserted at the end of the minor byte count transfer. SRAM Transfer Control Descriptor (TCD) eDMA Slave Write Address Slave Write Data TCD0 TCDn-1* eDMA Engine Bus Read Data Slave Interface System Bus SRAM Program Model/ Channel Arbitration Address Path Data Path Control Slave Read Data Bus Write Data Bus Address *n = 32 channels eDMA Peripheral Request eDMA Interrupt Request eDMA Done Handshake Figure 9-20. eDMA Operation, Part 2 After the inner minor byte count has been moved, the final phase of the basic data flow is performed. In this segment, the address path logic performs the required updates to certain fields in the channel’s TCD: for example., SADDR, DADDR, CITER. If the outer major iteration count is exhausted, then there are additional operations which are performed. These include the final address adjustments and reloading of the BITER field into the CITER. Additionally, assertion of an optional interrupt request occurs at this time, as does a possible fetch of a new TCD from memory using the scatter/gather address pointer included in the descriptor. The updates to the TCD memory and the assertion of an interrupt request are shown in Figure 9-21. MPC5533 Microcontroller Reference Manual, Rev. 0 9-30 Freescale Semiconductor eDMA SRAM Transfer Control Descriptor (TCD) Slave Write Address Slave Write Data TCD0 TCDn-1* eDMA Engine Bus Read Data Slave Interface System Bus SRAM Program Model/ Channel Arbitration Address Path Data Path Control Slave Read Data Bus Write Data Bus Address *n = 32 channels eDMA Peripheral Request eDMA Done Figure 9-21. eDMA Operation, Part 3 9.3.3 eDMA Performance This section addresses the performance of the eDMA module, focusing on two separate metrics. In the traditional data movement context, performance is best expressed as the peak data transfer rates achieved using the eDMA. In most implementations, this transfer rate is limited by the speed of the source and destination address spaces. In a second context where device-paced movement of single data values to/from peripherals is dominant, a measure of the requests that can be serviced in a fixed time is a more useful metric. In this environment, the speed of the source and destination address spaces remains important, but the microarchitecture of the eDMA also factors significantly into the resulting metric. The peak transfer rates for several different source and destination transfers are shown in Table 9-20. The following assumptions apply to Table 9-20 and Table 9-21: • Internal SRAM can be accessed with zero wait-states when viewed from the system bus data phase. • All slave reads require two wait-states, and slave writes three wait-states, again viewed from the system bus data phase. • All slave accesses are 32-bits in size. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 9-31 Table 9-20. eDMA Peak Transfer Rates (MB/Sec) System Speed, Transfer Size Internal SRAM-toInternal SRAM 32-Bit Slave-toInternal SRAM Internal SRAM-to32-Bit Slave (buffering disabled) Internal SRAM-to32-Bit Slave (buffering enabled) 66.7 MHz, 32 bit 66.7 66.7 53.3 88.7 66.7 MHz, 64 bit 133.3 66.7 53.3 88.7 66.7 MHz, 256 bit1 213.4 —2 —2 —2 83.3 MHz, 32 bit 83.3 83.3 66.7 110.8 83.3 MHz, 64 bit 166.7 83.3 66.7 110.8 83.3 MHz, 256 bit1 266.6 —2 —2 —2 100.0 MHz, 32 bit 100.0 100.0 80.0 133.0 100.0 MHz, 64 bit 200.0 100.0 80.0 133.0 100.0 MHz, 256 bit1 320.0 —2 —2 —2 132.0 MHz, 32 bit 132.0 132.0 105.6 175.6 132.0 MHz, 64 bit 264.0 132.0 105.6 175.6 132.0 MHz, 256 bit1 422.4 —2 —2 —2 1 2 A 256-bit transfer occurs as a burst of four 64-bit beats. Not applicable: burst access to a slave port is not supported. Table 9-20 presents a peak transfer rate comparison, measured in MBs per second where the internal-SRAM-to-internal-SRAM transfers occur at the core’s datapath width; that is, either 32- or 64-bits per access. For all transfers involving the slave bus, 32-bit transfer sizes are used. In all cases, the transfer rate includes the time to read the source plus the time to write the destination. The second performance metric is a measure of the number of DMA requests that can be serviced in a given amount of time. For this metric, it is assumed the peripheral request causes the channel to move a single slave-mapped operand to/from internal SRAM. The same timing assumptions used in the previous example apply to this calculation. In particular, this metric also reflects the time required to activate the channel. The eDMA design supports the following hardware service request sequence: • Cycle 1: eDMA peripheral request is asserted. • Cycle 2: The eDMA peripheral request is registered locally in the eDMA module and qualified. (TCD.START bit initiated requests start at this point with the registering of the slave write to TCD bit 255). • Cycle 3: Channel arbitration begins. • Cycle 4: Channel arbitration completes. The transfer control descriptor local memory read is initiated. • Cycle 5–6: The first two parts of the activated channel’s TCD is read from the local memory. The memory width to the eDMA engine is 64 bits, so the entire descriptor can be accessed in four cycles. MPC5533 Microcontroller Reference Manual, Rev. 0 9-32 Freescale Semiconductor • • • • • • • Cycle 7: The first system bus read cycle is initiated, as the third part of the channel’s TCD is read from the local memory. Depending on the state of the crossbar switch, arbitration at the system bus can insert an additional cycle of delay here. Cycle 8 – n: The last part of the TCD is read in. This cycle represents the first data phase for the read, and the address phase for the destination write. The exact timing from this point is a function of the response times for the channel’s read and write accesses. In this case of an slave read and internal SRAM write, the combined data phase time is 4 cycles. For an SRAM read and slave write, it is five cycles. Cycle n + 1: This cycle represents the data phase of the last destination write. Cycle n + 2: The eDMA engine completes the execution of the inner minor loop and prepares to write back the required TCDn fields into the local memory. The control and status fields at word offset 0x1C in TCDn are read. If the major loop is complete, the MAJOR.E_LINK and E_SG bits are checked and processed if enabled. Cycle n + 3: The appropriate fields in the first part of the TCDn are written back into the local memory. Cycle n + 4: The fields in the second part of the TCDn are written back into the local memory. This cycle coincides with the next channel arbitration cycle start. Cycle n + 5: The next channel to be activated performs the read of the first part of its TCD from the local memory. This is equivalent to Cycle 4 for the first channel’s service request. Assuming zero wait states on the system bus, DMA requests can be processed every 9 cycles. Assuming an average of the access times associated with slave-to-SRAM (4 cycles) and SRAM-to-slave (5 cycles), DMA requests can be processed every 11.5 cycles (4 + (4+5)/2 + 3). This is the time from Cycle 4 to Cycle “n + 5.” The resulting peak request rate, as a function of the system frequency, is shown in Table 9-21. This metric represents millions of requests per second. Table 9-21. eDMA Peak Request Rate (MReq/Sec) System Frequency (MHz) Request Rate (Zero Wait States) Request Rate (with Wait States) 66.6 7.4 5.8 83.3 9.2 7.2 100.0 11.1 8.7 133.3 14.8 11.6 150.0 16.6 13.0 A general formula to compute the peak request rate (with overlapping requests) is: PEAKreq = freq / [entry + (1 + read_ws) + (1 + write_ws) + exit] where: PEAKreq is the peak request rate freq is the system frequency MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 9-33 entry is the channel startup (four cycles) read_ws is the wait states seen during the system bus read data phase write_ws is the wait states seen during the system bus write data phase exit is the channel shutdown (three cycles) For example, consider a system with the following characteristics: • Internal SRAM can be accessed with one wait-state when viewed from the system bus data phase. • All slave reads require two wait-states, and slave writes three wait-states, again viewed from the system bus data phase. • System operates at 150 MHz. For an SRAM to slave transfer, PEAKreq = 150 MHz / [4 + (1 + 1) + (1 + 3) + 3] cycles = 11.5 Mreq/sec For a slave to SRAM transfer, PEAKreq = 150 MHz / [4 + (1 + 2) + (1 + 1) + 3] cycles = 12.5 Mreq/sec Assuming an even distribution of the two transfer types, the average peak request rate is: PEAKreq = (11.5 Mreq/sec + 12.5 Mreq/sec) / 2 = 12.0 Mreq/sec The minimum number of cycles to perform a single read/write, zero wait states on the system bus, from a cold start (no channel is executing, eDMA is idle) are the following: • 11 cycles for a software (TCD.START bit) request • 12 cycles for a hardware (eDMA peripheral request signal) request Two cycles account for the arbitration pipeline and one extra cycle on the hardware request resulting from the internal registering of the eDMA peripheral request signals. For the peak request rate calculations above, the arbitration and request registering is absorbed in or overlap the previous executing channel. NOTE When channel linking or scatter/gather is enabled, a two-cycle delay is imposed on the next channel selection and startup. This allows the link channel or the scatter/gather channel to be eligible and considered in the arbitration pool for next channel selection. MPC5533 Microcontroller Reference Manual, Rev. 0 9-34 Freescale Semiconductor 9.4 9.4.1 Initialization and Application Information eDMA Initialization A typical initialization of the eDMA has the following sequence: 1. Write the EDMA_CR if a configuration other than the default is desired. 2. Write the channel priority levels into the EDMA_CPRn registers if a configuration other than the default is desired. 3. Enable error interrupts in the EDMA_EEIRL and/or EDMA_EEIRH registers (optional). 4. Write the 32-byte TCD for each channel that can request service. 5. Enable any hardware service requests via the EDMA_ERQRH and/or EDMA_ERQRL registers. 6. Request channel service by either software (setting the TCD.START bit) or by hardware (slave device asserting its eDMA peripheral request signal). After any channel requests service, a channel is selected for execution based on the arbitration and priority levels written into the programmer's model. The eDMA engine reads the entire TCD, including the primary transfer control parameter shown in Table 9-22, for the selected channel into its internal address path module. As the TCD is being read, the first transfer is initiated on the system bus unless a configuration error is detected. Transfers from the source (as defined by the source address, TCD.SADDR) to the destination (as defined by the destination address, TCD.DADDR) continue until the specified number of bytes (TCD.NBYTES) have been transferred. When the transfer is complete, the eDMA engine's local TCD.SADDR, TCD.DADDR, and TCD.CITER are written back to the main TCD memory and any minor loop channel linking is performed, if enabled. If the major loop is exhausted, further post processing is executed: for example, interrupts, major loop channel linking, and scatter/gather operations, if enabled. Table 9-22. TCD Primary Control and Status Fields TCD Field Name Description START Control bit to explicitly start channel when using a software initiated DMA service (Automatically cleared by hardware) ACTIVE Status bit indicating the channel is currently in execution DONE Status bit indicating major loop completion (Cleared by software when using a software initiated DMA service) D_REQ Control bit to disable DMA request at end of major loop completion when using a hardware-initiated DMA service BWC Control bits for “throttling” bandwidth control of a channel E_SG Control bit to enable scatter-gather feature INT_HALF Control bit to enable interrupt when major loop is half complete INT_MAJ Control bit to enable interrupt when major loop completes MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 9-35 Figure 9-22 shows how each DMA request initiates one minor loop transfer (iteration) without CPU intervention. DMA arbitration can occur after each minor loop, and one level of minor loop DMA preemption is allowed. The number of minor loops in a major loop is specified by the beginning iteration count (biter). Current Major Loop Iteration Count (CITER) Example Memory Array DMA Request • • • Minor Loop • • • Minor Loop • • • Minor Loop 3 DMA Request Major Loop 2 DMA Request 1 Figure 9-22. Example of Multiple Loop Iterations Figure 9-23 lists the memory array terms and how the TCD settings interrelate. xADDR: (Starting Address) xSIZE: (Size of one data transfer) • • • • • • xLAST: Number of bytes added to current address after Major Loop • • • • • • Minor Loop (NBYTES in Minor Loop, often the same value as xSIZE) Minor Loop Offset (xOFF): Number of bytes added to current address after each transfer (Often the same value as xSIZE) Each DMA Source (S) and Destination (D) has its own: • Address (xADDR) • Size (xSIZE) • Offset (xOFF) • Modulo (xMOD) • Last Address Adjustment (xLAST) where x = S or D Last Minor Loop (Typically used to loop back) Peripheral queues typically have size and offset equal to NBYTES Figure 9-23. Memory Array Terms MPC5533 Microcontroller Reference Manual, Rev. 0 9-36 Freescale Semiconductor 9.4.2 DMA Programming Errors The eDMA performs various tests on the transfer control descriptor to verify consistency in the descriptor data. Most programming errors are reported on a per channel basis with the exception of two errors: group priority error and channel priority error, or EDMA_ESR[GPE] and EDMA_ESR[CPE], respectively. For all error types other than group or channel priority errors, the channel number causing the error is recorded in the EDMA_ESR. If the error source is not removed before the next activation of the problem channel, the error is detected and recorded again. Channel priority errors are identified within a group after that group has been selected as the active group. For the example that follows, all of the channel priorities in Group 1 are unique, but some of the channel priorities in Group 0 are the same: 1. Configure the eDMA for fixed-group and fixed-channel arbitration modes so that: — Group 1 is the highest priority and all channels are unique in that group. — Group 0 is the next highest priority and two channels have the same priority level. 2. If Group 1 has service requests pending, those requests are executed. 3. After all Group 1 requests have completed, Group 0 becomes the active group. 4. If Group 0 has a service request, the eDMA selects the undefined channel in Group 0 and generates a channel priority error. 5. Repeat Step 4 until the all Group 0 requests are serviced or a higher-priority Group 1 request is received. In step 2, the eDMA acknowledge lines assert only if the selected channel is requesting service via the eDMA peripheral request signal. If interrupts are enabled for all channels, an error interrupt is generated. However, the channel number for the EDMA_ER and the error interrupt request line contain undefined data because the channel is ‘undefined’. A group priority error is global and any request in any group causes a group priority error. If priority levels are not unique, the highest (channel/group) priority that has an active request is selected, but the lowest numbered (channel/group) with that priority is selected by arbitration and executed by the eDMA engine. The hardware service request handshake signals, error interrupts and error reporting are associated with the selected channel. 9.4.3 DMA Request Assignments The assignments between the DMA requests from the modules to the channels of the eDMA are shown in Table 9-23. The source column is written in C language syntax. The syntax is module_instance.register[bit]. Table 9-23. DMA Request Summary for eDMA DMA Request Channel Source Description eQADC_FISR0_CFFF0 0 EQADC.FISR0[CFFF0] eQADC Command FIFO 0 Fill Flag eQADC_FISR0_RFDF0 1 EQADC.FISR0[RFDF0] eQADC Receive FIFO 0 Drain Flag eQADC_FISR1_CFFF1 2 EQADC.FISR1[CFFF1] eQADC Command FIFO 1 Fill Flag MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 9-37 Table 9-23. DMA Request Summary for eDMA (Continued) DMA Request Channel Source Description eQADC_FISR1_RFDF1 3 EQADC.FISR1[RFDF1] eQADC Receive FIFO 1 Drain Flag eQADC_FISR2_CFFF2 4 EQADC.FISR2[CFFF2] eQADC Command FIFO 2 Fill Flag eQADC_FISR2_RFDF2 5 EQADC.FISR2[RFDF2] eQADC Receive FIFO 2 Drain Flag eQADC_FISR3_CFFF3 6 EQADC.FISR3[CFFF3] eQADC Command FIFO 3 Fill Flag eQADC_FISR3_RFDF3 7 EQADC.FISR3[RFDF3] eQADC Receive FIFO 3 Drain Flag eQADC_FISR4_CFFF4 8 EQADC.FISR4[CFFF4] eQADC Command FIFO 4 Fill Flag eQADC_FISR4_RFDF4 9 EQADC.FISR4[RFDF4] eQADC Receive FIFO 4 Drain Flag eQADC_FISR5_CFFF5 10 EQADC.FISR5[CFFF5] eQADC Command FIFO 5 Fill Flag eQADC_FISR5_RFDF5 11 EQADC.FISR5[RFDF5] eQADC Receive FIFO 5 Drain Flag DSPIC_SR_TFFF 14 DSPIC.SR[TFFF] DSPIC Transmit FIFO Fill Flag DSPIC_SR_RFDF 15 DSPIC.SR[RFDF] DSPIC Receive FIFO Drain Flag DSPID_SR_TFFF 16 DSPID.SR[TFFF] DSPID Transmit FIFO Fill Flag DSPID_SR_RFDF 17 DSPID.SR[RFDF] DSPID Receive FIFO Drain Flag eSCIA_COMBTX 18 ESCIA.SR[TDRE] || ESCIA.SR[TC] || ESCIA.SR[TXRDY] eSCIA combined DMA request of the Transmit Data Register Empty, Transmit Complete, and LIN Transmit Data Ready DMA requests eSCIA_COMBRX 19 ESCIA.SR[RDRF] || ESCIA.SR[RXRDY] eSCIA combined DMA request of the Receive Data Register Full and LIN Receive Data Ready DMA requests eTPU_CDTRSR_A_DTRS0 27 ETPU.CDTRSR_A[DTRS0] eTPUA Channel 0 Data Transfer Request Status eTPU_CDTRSR_A_DTRS1 28 ETPU.CDTRSR_A[DTRS1] eTPUA Channel 1 Data Transfer Request Status eTPU_CDTRSR_A_DTRS2 29 ETPU.CDTRSR_A[DTRS2] eTPUA Channel 2 Data Transfer Request Status eTPU_CDTRSR_A_DTRS14 30 ETPU.CDTRSR_A[DTRS14] eTPUA Channel 14 Data Transfer Request Status eTPU_CDTRSR_A_DTRS15 31 ETPU.CDTRSR_A[DTRS15] eTPUA Channel 15 Data Transfer Request Status 9.4.4 9.4.4.1 DMA Arbitration Mode Considerations Fixed-Group Arbitration and Fixed-Channel Arbitration In this mode, the channel service request from the highest priority channel in the highest priority group is selected to execute. If the eDMA is programmed so the channels within one group use ‘fixed’ priorities, and that group is assigned the highest ‘fixed’ priority of all groups, it is possible for that group to take all the bandwidth of the eDMA controller; that is, no other groups is serviced if there is always at least one DMA request pending on a channel in the highest priority group when the controller arbitrates the next DMA request. The advantage of this scenario is that latency can be small for channels that must be serviced quickly. Preemption is available in this scenario only. MPC5533 Microcontroller Reference Manual, Rev. 0 9-38 Freescale Semiconductor 9.4.4.2 Round-Robin Group Arbitration, Fixed-Channel Arbitration The occurrence of one or more DMA requests from one or more groups, the channel with the highest priority from a specific group is serviced first. Groups are serviced starting with the highest group number with a service request and rotating through to the lowest group number containing a service request. After the channel request is serviced, the group round-robin algorithm selects the highest pending request from the next group in the round-robin sequence. Servicing continues using the round-robin method, always servicing the highest priority channel in the next group in the sequence, or just skipping a group if it has no pending requests. If a channel requests service at a rate that equals or exceeds the round-robin service rate, then that channel is always serviced before lower priority channels in the same group, and thus the lower priority channels never are serviced. The advantage of this scenario is that no one group uses all the eDMA bandwidth. The highest priority channel selection latency is potentially greater than fixed/fixed arbitration. Excessive request rates on high priority channels can prevent the servicing of lower priority channels in the same group. 9.4.4.3 Round-Robin Group Arbitration, Round-Robin Channel Arbitration Groups are serviced as described in Section 9.4.4.2, “Round-Robin Group Arbitration, Fixed-Channel Arbitration, but this time channels are serviced in channel number order. Only one channel is serviced from each requesting group for each round-robin pass through the groups. Within each group, channels are serviced starting with the highest channel number and rotating through to the lowest channel number without regard to channel priority levels. Because channels are serviced using a round-robin method, any channel that generates DMA requests faster than a combination of the group round-robin service rate and the channel service rate for its group does not prevent the servicing of other channels in its group. Any DMA requests that are not serviced are simply lost, but at least one channel is serviced. This scenario ensures that all channels are guaranteed service at some point, regardless of the request rates. However, the potential latency can be quite high. All channels are treated equally. Priority levels are not used in round-robin/round-robin mode. 9.4.4.4 Fixed-Group Arbitration, Round-Robin Channel Arbitration The highest priority group with a request is serviced. Lower priority groups are serviced if no pending requests exist in the higher priority groups. Within each group, channels are serviced starting with the highest channel number and rotating through to the lowest channel number without regard to the channel priority levels assigned within the group. This can cause the same bandwidth problem indicated in Section 9.4.4.1, but all the channels in the highest priority group are serviced. Service latency is short on the highest-priority group, but increases as the group priority decreases. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 9-39 9.4.5 9.4.5.1 DMA Transfer Single Request To perform a simple transfer of ‘n’ bytes of data with one activation, set the major loop to 1 (TCD.CITER = TCD.BITER = 1). The data transfer begins after the channel service request is acknowledged and the channel is selected to execute. After the transfer completes, the TCD.DONE bit is set and an interrupt is generated if correctly enabled. For example, the following TCD entry is configured to transfer 16 bytes of data. The eDMA is programmed for one iteration of the major loop transferring 16 bytes per iteration. The source memory has a byte-wide memory port located at 0x1000. The destination memory has a word-wide port located at 0x2000. The address offsets are programmed in increments to match the size of the transfer; one byte for the source and four bytes for the destination. The final source and destination addresses are adjusted to return to their beginning values. TCD.CITER = TCD.BITER = 1 TCD.NBYTES = 16 TCD.SADDR = 0x1000 TCD.SOFF = 1 TCD.SSIZE = 0 TCD.SLAST = –16 TCD.DADDR = 0x2000 TCD.DOFF = 4 TCD.DSIZE = 2 TCD.DLAST_SGA= –16 TCD.INT_MAJ = 1 TCD.START = 1 (Initialize all other fields before writing to this bit) All other TCD fields = 0 MPC5533 Microcontroller Reference Manual, Rev. 0 9-40 Freescale Semiconductor This generates the following sequence of events: 1. Slave write to the TCD.START bit requests channel service. 2. The channel is selected by arbitration for servicing. 3. eDMA engine writes: TCD.DONE = 0, TCD.START = 0, TCD.ACTIVE = 1. 4. eDMA engine reads: channel TCD data from local memory to internal register file. 5. The source to destination transfers are executed as follows: a) read_byte (0x1000), read_byte (0x1001), read_byte (0x1002), read_byte (0x1003) b) write_word (0x2000) –> first iteration of the minor loop c) read_byte (0x1004), read_byte (0x1005), read_byte (0x1006), read_byte (0x1007) d) write_word (0x2004) –> second iteration of the minor loop e) read_byte (0x1008), read_byte (0x1009), read_byte (0x100A), read_byte (0x100B) f) write_word (0x2008) –> third iteration of the minor loop g) read_byte (0x100C), read_byte (0x100D), read_byte (0x100E), read_byte (0x100F) h) write_word (0x200C) –> last iteration of the minor loop –> major loop complete 6. eDMA engine writes: TCD.SADDR = 0x1000, TCD.DADDR = 0x2000, TCD.CITER = 1 (TCD.BITER). 7. eDMA engine writes: TCD.ACTIVE = 0, TCD.DONE = 1, EDMA_IRQRn = 1. 8. The channel retires. The eDMA goes idle or services the next channel. 9.4.5.2 Multiple Requests The next example is similar except it transfers 32 bytes via two hardware requests. The only fields that change are the major loop iteration count and the final address offsets. The eDMA is programmed for two iterations of the major loop transferring 16 bytes per iteration. After the channel’s hardware requests are enabled in the EDMA_ERQR, channel service requests are initiated by the slave device (set ERQR after TCD; TCD.START = 0). TCD.CITER = TCD.BITER = 2 TCD.NBYTES = 16 TCD.SADDR = 0x1000 TCD.SOFF = 1 TCD.SSIZE = 0 TCD.SLAST = –32 TCD.DADDR = 0x2000 TCD.DOFF = 4 TCD.DSIZE = 2 TCD.DLAST_SGA= –32 TCD.INT_MAJ = 1 TCD.START = 0 (Initialize all other fields before writing this bit.) All other TCD fields = 0 MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 9-41 This generates the following sequence of events: 1. First hardware (eDMA peripheral request) request for channel service. 2. The channel is selected by arbitration for servicing. 3. eDMA engine writes: TCD.DONE = 0, TCD.START = 0, TCD.ACTIVE = 1. 4. eDMA engine reads: channel TCD data from local memory to internal register file. 5. The source to destination transfers execute as follows: a) read_byte (0x1000), read_byte (0x1001), read_byte (0x1002), read_byte (0x1003) b) write_word (0x2000) –> first iteration of the minor loop c) read_byte (0x1004), read_byte (0x1005), read_byte (0x1006), read_byte (0x1007) d) write_word (0x2004) –> second iteration of the minor loop e) read_byte (0x1008), read_byte (0x1009), read_byte (0x100A), read_byte (0x100B) f) write_word (0x2008) –> third iteration of the minor loop g) read_byte (0x100C), read_byte (0x100D), read_byte (0x100E), read_byte (0x100F) h) write_word (0x200C) –> last iteration of the minor loop 6. eDMA engine writes: TCD.SADDR = 0x1010, TCD.DADDR = 0x2010, TCD.CITER = 1. 7. eDMA engine writes: TCD.ACTIVE = 0. 8. The channel retires –> one iteration of the major loop. The eDMA goes idle or services the next channel. 9. Second hardware (eDMA peripheral request) requests channel service. 10. The channel is selected by arbitration for servicing. 11. eDMA engine writes: TCD.DONE = 0, TCD.START = 0, TCD.ACTIVE = 1. 12. eDMA engine reads: channel TCD data from local memory to internal register file. 13. The source to destination transfers execute as follows: a) read_byte (0x1010), read_byte (0x1011), read_byte (0x1012), read_byte (0x1013) b) write_word (0x2010) –> first iteration of the minor loop c) read_byte (0x1014), read_byte (0x1015), read_byte (0x1016), read_byte (0x1017) d) write_word (0x2014) –> second iteration of the minor loop e) read_byte (0x1018), read_byte (0x1019), read_byte (0x101A), read_byte (0x101B) f) write_word (0x2018) –> third iteration of the minor loop g) read_byte (0x101C), read_byte (0x101D), read_byte (0x101E), read_byte (0x101F) h) write_word (0x201C) –> last iteration of the minor loop –> major loop complete 14. eDMA engine writes: TCD.SADDR = 0x1000, TCD.DADDR = 0x2000, TCD.CITER = 2 (TCD.BITER). 15. eDMA engine writes: TCD.ACTIVE = 0, TCD.DONE = 1, EDMA_IRQRn = 1. 16. The channel retires –> major loop complete. The eDMA goes idle or services the next channel. MPC5533 Microcontroller Reference Manual, Rev. 0 9-42 Freescale Semiconductor 9.4.5.3 Modulo Feature The modulo feature of the eDMA provides the ability to easily implement a circular data queue in which the size of the queue is a power of two. MOD is a 5-bit field for the source and destination in the TCD, and specifies which lower address bits increment from their original value after the address + offset calculation. All upper address bits remain the same as in the original value. Clearing this field to zero disables the modulo feature. Table 9-24 shows how the transfer addresses are specified based on the setting of the MOD field. Here a circular buffer is created where the address wraps to the original value while the 28 upper address bits (0x1234_567x) retain their original value. In this example the source address is set to 0x1234_5670, the offset is set to 4 bytes and the mod field is set to 4, allowing for a 24 byte (16-byte) size queue. Table 9-24. Modulo Feature Example 9.4.6 9.4.6.1 Transfer Number Address 1 0x1234_5670 2 0x1234_5674 3 0x1234_5678 4 0x1234_567C 5 0x1234_5670 6 0x1234_5674 TCD Status Minor Loop Complete There are two methods to test for minor loop completion when using software initiated service requests. The first method is to read the TCD.CITER field and test for a change. Another method can be extracted from the following sequence. The second method is to test the TCD.START bit AND the TCD.ACTIVE bit. The minor loop complete condition is indicated by both bits reading zero after the TCD.START was written to a one. Polling the TCD.ACTIVE bit can be inconclusive because the active status can be missed if the channel execution is short in duration. The TCD status bits execute the following sequence for a software activated channel: 1. TCD.START = 1, TCD.ACTIVE = 0, TCD.DONE = 0 (issued service request via software) 2. TCD.START = 0, TCD.ACTIVE = 1, TCD.DONE = 0 (executing) 3. TCD.START = 0, TCD.ACTIVE = 0, TCD.DONE = 0 (completed minor loop and is idle) or 4. TCD.START = 0, TCD.ACTIVE = 0, TCD.DONE = 1 (completed major loop and is idle) The best method to test for minor loop completion when using hardware initiated service requests is to read the TCD.CITER field and test for a change. The hardware request and acknowledge handshakes signals are not visible in the programmer’s model. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 9-43 The TCD status bits execute the following sequence for a hardware activated channel: 1. eDMA peripheral request asserts (issued service request via hardware) 2. TCD.START = 0, TCD.ACTIVE = 1, TCD.DONE = 0 (executing) 3. TCD.START = 0, TCD.ACTIVE = 0, TCD.DONE = 0 (completed minor loop and is idle) or 4. TCD.START = 0, TCD.ACTIVE = 0, TCD.DONE = 1 (completed major loop and is idle) For both activation types, the major loop complete status is explicitly indicated via the TCD.DONE bit. The TCD.START bit is cleared automatically when the channel begins execution regardless of how the channel was activated. 9.4.6.2 Active Channel TCD Reads The eDMA reads the true TCD.SADDR, TCD.DADDR, and TCD.NBYTES values if read while a channel is executing. The true values of the SADDR, DADDR, and NBYTES are the values the eDMA engine is currently using in its internal register file and not the values in the TCD local memory for that channel. The addresses (SADDR and DADDR) and NBYTES (decrements to zero as the transfer progresses) can give an indication of the progress of the transfer. All other values are read back from the TCD local memory. 9.4.6.3 Preemption Status Preemption is only available when fixed arbitration is selected for both group and channel arbitration modes. A preempt-able situation is one in which a preempt-enabled channel is running and a higher priority request becomes active. When the eDMA engine is not operating in fixed group, fixed channel arbitration mode, the determination of the relative priority of the actively running and the outstanding requests become undefined. Channel and/or group priorities are treated as equal (or more exactly, constantly rotating) when round-robin arbitration mode is selected. The TCD.ACTIVE bit for the preempted channel remains asserted throughout the preemption. The preempted channel is temporarily suspended while the preempting channel executes one iteration of the major loop. Two TCD.ACTIVE bits set at the same time in the overall TCD map indicates a higher priority channel is actively preempting a lower priority channel. 9.4.7 Channel Linking Channel linking (or chaining) is a mechanism where one channel sets the TCD.START bit of another channel (or itself) thus initiating a service request for that channel. This operation is automatically performed by the eDMA engine at the conclusion of the major or minor loop when correctly enabled. The minor loop channel linking occurs at the completion of the minor loop (or one iteration of the major loop). The TCD.CITER.E_LINK field are used to determine whether a minor loop link is requested. When enabled, the channel link is made after each iteration of the minor loop except for the last. MPC5533 Microcontroller Reference Manual, Rev. 0 9-44 Freescale Semiconductor When the major loop is exhausted, only the major loop channel link fields are used to determine whether to make a channel link. For example, with the initial fields of: TCD.CITER.E_LINK = 1 TCD.CITER.LINKCH = 0x000C TCD.CITER value = 0x0004 TCD.MAJOR.E_LINK = 1 TCD.MAJOR.LINKCH = 0x0007 channel linking executes as: 1. Minor loop done –> set channel 12 TCD.START bit 2. Minor loop done –> set channel 12 TCD.START bit 3. Minor loop done –> set channel 12 TCD.START bit 4. Minor loop done, major loop done –> set channel 7 TCD.START bit When minor loop linking is enabled (TCD.CITER.E_LINK = 1), the TCD.CITER field uses a nine bit vector to form the current iteration count. When minor loop linking is disabled (TCD.CITER.E_LINK = 0), the TCD.CITER field uses a 15-bit vector to form the current iteration count. The bits associated with the TCD.CITER.LINKCH field are concatenated onto the CITER value to increase the range of the CITER. NOTE After configuration, the TCD.CITER.E_LINK bit and the TCD.BITER.E_LINK bit must be equal or a configuration error is reported. The CITER and BITER vector widths must be equal to calculate the major loop, half-way done interrupt point. Table 9-25 summarizes how a DMA channel can “link” to another DMA channel, i.e, use another channel’s TCD, at the end of a loop. Table 9-25. Channel Linking Parameters Desired Link Behavior Link at end of Minor Loop Link at end of Major Loop TCD Control Field Name Description citer.e_link Enable channel-to-channel linking on minor loop completion (current iteration) citer.linkch Link channel number when linking at end of minor loop (current iteration) major.e_link Enable channel-to-channel linking on major loop completion major.linkch Link channel number when linking at end of major loop MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 9-45 9.4.8 Dynamic Programming This section provides recommended methods to change the programming model during channel execution. 9.4.8.1 Dynamic Channel Linking and Dynamic Scatter/Gather Dynamic channel linking and dynamic scatter/gather is the process of changing the TCD.MAJOR.E_LINK or TCD.E_SG bits during channel execution. These bits are read from the TCD local memory at the end of channel execution thus allowing you to enable either feature during channel execution. Because you are allowed to change the configuration during execution, a coherency model is needed. Consider the scenario where you try to execute a dynamic channel link by enabling the TCD.MAJOR.E_LINK bit at the same time the eDMA engine is retiring the channel. The TCD.MAJOR.E_LINK is set in the programmer’s model, but it is unclear whether the link completed before the channel retired. Use the following coherency model when executing a dynamic channel link or dynamic scatter/gather request: 1. Set the TCD.MAJOR.E_LINK bit 2. Read the TCD.MAJOR.E_LINK bit 3. Test the TCD.MAJOR.E_LINK request status: a) If the bit is set, the dynamic link attempt was successful. b) If the bit is cleared, the channel had already retired before the dynamic link completed. This same coherency model is true for dynamic scatter/gather operations. For both dynamic requests, the TCD local memory controller forces the TCD.MAJOR.E_LINK and TCD.E_SG bits to zero on any writes to a channel’s TCD after that channel’s TCD.DONE bit is set indicating the major loop is complete. NOTE You must clear the TCD.DONE bit before writing the TCD.MAJOR.E_LINK or TCD.E_SG bits. The TCD.DONE bit is cleared automatically by the eDMA engine after a channel begins execution. MPC5533 Microcontroller Reference Manual, Rev. 0 9-46 Freescale Semiconductor Chapter 10 Interrupt Controller (INTC) 10.1 Introduction This chapter describes the interrupt controller (INTC), which schedules interrupt requests (IRQs) from software and internal peripherals to the e200z3 core. The INTC provides interrupt prioritization and preemption, interrupt masking, interrupt priority elevation, and protocol support. Interrupts implemented by the MCU are defined in the e200z3 PowerPCtm Core Reference Manual. 10.1.1 Block Diagram Figure 4-1 shows details of the interrupt controller. Software Set/Clear Interrupt Registers Priority Select Registers Highest Priority Interrupt Requests n1 Peripheral Interrupt Requests1 Flag Bits 8 x 4-bits n1 Priority LIFO 4 Popped Priority n1 Priority Arbitrator 4 Pushed 4 Priority End of Interrupt Register Current Priority Register Lowest Vector Interrupt Request Request Selector n1 Module Configuration Register 1 Interrupt Vector Vector Encoder 9 Hardware Vector Enable 1 Vector Table Entry Size Interrupt Vector Interrupt Acknowledge Register 9 Highest Priority New 4 Priority 4 Current Priority Priority Comparator Update Interrupt Vector 1 Interrupt Request to Processor 1 Interrupt Acknowledge 1 Slave Push/Update/Acknowledge 1 Pop 1 Bus Slave Interface Signals for Reads and Writes Memory mapped registers Non-memory mapped logic 1 The total number of interrupt sources is 204, which includes 38 reserved sources, and 8 software sources. Figure 10-1. INTC Block Diagram MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 10-1 10.1.2 Overview The interrupt functions are managed by the e200z3 core and the interrupt controller. The CPU core has 19 exception sources, each of which can interrupt the core. One of those exception sources is the interrupt controller (INTC). The scheduling mechanism in the INTC can be used for statically scheduled hardware real-time systems. INTC allows priority-based preemptive scheduling of interrupt requests for the modules that comprise the SoC. The INTC is optimized for a large number of interrupt requests that work with the core for automotive powertrain applications that need to nest ISRs in multiple levels. Table 10-1 displays the interrupt sources and the number of interrupts available for each module. See Table 10-9 for interrupt source vector details. Table 10-1. Interrupt Sources Available Interrupt Source (IRQs) Number Available Software 8 Watchdog 1 Memory 1 eDMA 33 FMPLL 2 External IRQ Input Pins 6 eTPU Engine A 33 eQADC 31 DSPI 10 eSCI 1 FlexCAN 40 Figure 10-2 shows a general diagram of INTC software vector mode. IRQs Interrupt Controller (INTC) External Interrupt Exception Request e200z3 Core Figure 10-2. INTC Software Vector Mode MPC5533 Microcontroller Reference Manual, Rev. 0 10-2 Freescale Semiconductor Two vector modes are used to determine the interrupt request source: • Software vector mode • Hardware vector mode In software vector mode, the e200z3 branches to a common interrupt exception handler that is located at an address derived from special purpose registers IVPR and IVOR4. The interrupt exception handler reads the INTC_IACKR to automatically determine the address of the interrupt request source. Typical program flow for software vector mode is shown in Figure 10-3. Address IRQn Taken Instructions Prolog (Including Using IACKR to get Vector then bl ISR_n IVPR + IVOR4 Address VTBA IACKR Epilog Instructions ISR_0 address ISR_0 ISR ISR_1 address • • • ISR_n address • • • ISR_N address ISR_1 ISR • • • ISR_n ISR • • • ISR_N ISR N = 203 which includes reserved sources. Figure 10-3. Program Flow–Software Vector Mode In hardware vector mode, the core branches to a unique interrupt exception handler that is unique for each interrupt request source. Typical program flow for hardware vector mode is shown in Figure 10-4. NOTE: ‘b ISR_n’ is technically part of the handler. Address Instructions IVPR + 0x00 b handler_0 • • • b handler_1 • • • b handler_2 • • • b handler_n • • • b handler_N IVPR + 0x10 IVPR + 0x20 IRQn Taken IVPR + n[0x10] see definition of N handler_0 Prolog ISR handler_n Epilog • • • Prolog ISR handler_N Epilog • • • Prolog ISR Epilog N = 203 which includes reserved sources. The address is IVPR + 0x0CB0 Figure 10-4. Program Flow–Hardware Vector Mode For high priority interrupt requests, you must minimize the time from the assertion of the peripheral interrupt request to when the processor begins to service the interrupt request. Using hardware vector mode that has a unique vector for each interrupt request source, you can optimize interrupt handling and minimize the time-to-service an interrupt request. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 10-3 For software and hardware vector modes, the INTC provides 16 priorities so that lower priority ISRs do not delay the execution of higher priority ISRs. Because applications have different priorities for each interrupt request source, the priority of each interrupt request is configurable. When multiple tasks share a resource, the system must support coherent accesses to the shared resource. The INTC supports the priority ceiling protocol for coherent accesses. By providing a modifiable priority mask, the priority level can be raised temporarily so that no task with a priority lower than or equal to the maximum priority can preempt another task that shares the same resource. The software configurable interrupt requests can distribute the processing required to service an interrupt request into high-priority processing and low-priority processing. The high priority processing is initiated by a peripheral interrupt request, and then the ISR can assert a software configurable interrupt request to complete servicing the lower priority ISR. 10.1.3 Features Features include the following: • Total number of interrupt vectors is 204 of which — 8 are software settable sources, and — 38 are reserved sources. • 9-bit unique vector for each interrupt request source in hardware vector mode. • Each interrupt source can be programmed to one of 16 priorities. • Preemption: — Preemptive prioritized interrupt requests to processor. — ISR at a higher priority preempts ISRs or tasks at lower priorities. — Automatic pushing or popping of preempted priority to or from a LIFO. — Ability to modify the ISR or task priority. Modifying the priority can be used to implement the priority ceiling protocol for accessing shared resources. • Low latency: three clocks from receipt of interrupt request from peripheral to interrupt request to processor. 10.1.4 Modes of Operation The interrupt controller has two handshaking modes with the processor: software vector mode and hardware vector mode. The state of the hardware vector enable bit, INTC_MCR[HVEN], determines which mode is used. In debug mode, the interrupt controller operation is not affected. The INTC operates identically in debug mode as it does in normal operation for software vector mode or hardware vector mode. 10.1.4.1 Software Vector Mode In software vector mode, there is a common interrupt exception handler address which is calculated by hardware as shown in Figure 10-5. The upper half of the interrupt vector prefix register (IVPR) is added to the offset contained in the external input interrupt vector offset register (IVOR4). Because bits MPC5533 Microcontroller Reference Manual, Rev. 0 10-4 Freescale Semiconductor IVOR4[28:31] are not part of the offset value, the vector offset must be located on a quad-word (16-byte) aligned location in memory. In software vector mode, the interrupt exception handler software must read the INTC interrupt acknowledge register (INTC_IACKR) to obtain the vector associated with the corresponding peripheral or software interrupt request. The INTC_IACKR contains a 32-bit address composed of a vector table base address (VTBA) plus an offset which is the interrupt vector (INTVEC). The address is then used to branch to the corresponding routine for that peripheral or software interrupt source. CAUTION Do not read the IACKR unless required, because the read instruction pops the value from the stack and cannot be retrieved, which can cause unpredictable results. When in Debug mode, it is important that the memory window which contains the IACKR is not open. IVPR 0 15 16 PREFIX + IVOR4 0 31 0x0000 15 16 0x0000 = Interrupt Exception Handler Address 0 27 28 OFFSET 15 16 PREFIX 0x0000 27 28 OFFSET 31 31 0x0000 Figure 10-5. Software Vector Mode: Interrupt Exception Handler Address Calculation Reading the INTC_IACKR acknowledges the INTC interrupt request and negates the interrupt request to the processor. The interrupt request to the processor does not clear if a higher priority interrupt request arrives. Even in this case, INTVEC does not update to the higher priority request until the lower priority interrupt request is acknowledged by reading the INTC_IACKR. Reading INTC_IACKR pushes the PRI value in the INTC current priority register (INTC_CPR) onto the LIFO and updates PRI in the INTC_CPR with the priority of the interrupt request. The INTC_CPR masks any peripheral or software settable interrupt request at the same or lower priority of the current value of the PRI field in INTC_CPR from generating an interrupt request to the processor. The last actions of the interrupt exception handler must be the write to the end-of-interrupt register (INTC_EOIR). Writing to the INTC_EOIR signals the end of the servicing of the interrupt request. The INTC LIFO is popped into the INTC_CPR's PRI field by writing to the INTC_EOIR, and the size of a write does not affect the operation of the write. Those values and sizes written to this register neither update the INTC_EOIR contents nor affect whether the LIFO pops. For possible future compatibility, write four bytes of all 0s to the INTC_EOIR. The timing relationship between popping the LIFO and disabling recognition of external input has no restriction. The writes can happen in either order. However, disabling recognition of the external input before popping the LIFO eases the calculation of the maximum pipe depth at the cost of postponing the servicing of the next interrupt request. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 10-5 10.1.4.2 Hardware Vector Mode In hardware vector mode, the interrupt exception handler address is specific to the peripheral or software configurable interrupt source rather than being common to all of them. IVOR is not used. The interrupt exception handler address is calculated by hardware as shown in Figure 10-6. The upper half of the interrupt vector prefix register (IVPR) is added to an offset which corresponds to the peripheral or software interrupt source that caused the interrupt request. The offset matches the value in the Interrupt Vector field, INTC_IACKR[INTVEC]. Each interrupt exception handler address is aligned on a quad-word (16-byte) boundary. IVOR4 is unused in this mode, and software does not require read INTC_IACKR to get the interrupt vector number. IVPR 0 15 16 31 PREFIX + Hardware Vector Mode Offset 0 0x0000 15 16 0x0000 = Interrupt Exception Handler Address 0 0b000 15 16 PREFIX 27 28 18 19 INTC_IACKR[INTVEC] 18 19 0b000 31 0b0000 27 28 IRQ SPECIFIC OFFSET 31 0b0000 Figure 10-6. Hardware Vector Mode: Interrupt Exception Handler Address Calculation The processor negates INTC interrupt request when automatically acknowledging the interrupt request. However, the interrupt request to the processor does not negate if a higher priority interrupt request arrives. Even in this case, the interrupt vector number does not update to the higher priority request until the lower priority request is acknowledged by the processor. The assertion of the interrupt acknowledge signal pushes the PRI value in the INTC_CPR onto the LIFO and updates PRI in the INTC_CPR with the new priority. 10.2 External Signal Description The INTC does not have any direct external MCU signals. However, there are fifteen external pins which can be configured in the SIU as external interrupt request input pins. When configured in this function, an interrupt on the pin sets a corresponding SIU external interrupt flag. These flags can cause one of five peripheral interrupt requests to the interrupt controller. See Table 10-2 for a list of the external interrupt pins. See the SIU chapter for more information on these pins. MPC5533 Microcontroller Reference Manual, Rev. 0 10-6 Freescale Semiconductor Table 10-2. External Interrupt Signals Function1 Description P/A/G2 I/O Type EMIOS[14:15]5 No primary signal — — IRQ[0:1] External interrupt request A I GPIO[193:194] GPIO G I/O BOOTCFG[0]6 Boot configuration input P I IRQ[2] External interrupt request A I GPIO[211] GPIO G I/O BOOTCFG[1] Boot configuration input P I IRQ[3] External interrupt request A I GPIO[212] GPIO G I/O PLLCFG[0] FMPLL mode selection P I IRQ[4] External Interrupt Request A I GPIO[208] GPIO G I/O PLLCFG[1] FMPLL mode selection P I IRQ[5] External Interrupt Request A I SOUTD DSPI D Data Output A2 O GPIO[209] GPIO G I/O TCRCLKA eTPU A TCR clock P I IRQ[7] External interrupt request A I GPIO[113] GPIO G I/O ETPUA[20:23] eTPU A channel P I/O IRQ[8:11] External interrupt request A I GPIO[134:137] GPIO G I/O ETPUA[24:26] eTPU A channel (output only) P O IRQ[12:14] External interrupt request A I GPIO[138:140] GPIO G I/O ETPUA[27] eTPU A channel (output only) P O IRQ[15] External interrupt request A I GPIO[141] GPIO G I/O 1 2 3 4 5 Reset Function/ State3 Post Reset Function/ State4 Pin —/ WKPCFG —/ WKPCFG AF19, AD18 BOOTCFG / Down — / Down AA25, Y24 BOOTCFG / Down — / Down AA25, Y24 PLLCFG / Up — / Up AB25 PLLCFG / Up — / Up AA24 — / Up — / Up N4 —/ WKPCFG —/ WKPCFG H1, G4, G2, G1 — /WKPCFG — /WKPCFG F1, G3, F3 — /WKPCFG — /WKPCFG F2 For each pin in the table, each line in the function column is a separate function of the pin. For all device I/O pins the selection of primary, secondary or tertiary function is done in the SIU module except where explicitly noted. Primary, alternate, or GPIO function. Terminology is O - output, I - input, Up - weak pull up enabled, Down - weak pull down enabled, Low - output driven low, High - output driven high. Function after reset of GPI is general-purpose input. This signal is not available on this device. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 10-7 6 10.3 This signal is not available on the 208 package due to pin limitations. Memory Map/Register Definition Table 10-3 is the INTC memory map. 10.3.1 Register Descriptions Table 10-3. INTC Memory Map Address Register Name Register Description Bits INTC_MCR INTC module configuration register 32 Base + 0x0004 — Reserved — Base + 0x0008 INTC_CPR INTC current priority register 32 Base + 0x000C — Reserved — Base + 0x0010 INTC_IACKR INTC interrupt acknowledge register 1 32 Base + 0x0014 — Reserved — Base + 0x0018 INTC_EOIR INTC end-of-interrupt register 32 Base + 0x001C — Reserved — Base + 0x0020 INTC_SSCIR0 INTC software set/clear interrupt register 0 8 Base + 0x0021 INTC_SSCIR1 INTC software set/clear interrupt register 1 8 Base + 0x0022 INTC_SSCIR2 INTC software set/clear interrupt register 2 8 Base + 0x0023 INTC_SSCIR3 INTC software set/clear interrupt register 3 8 Base + 0x0024 INTC_SSCIR4 INTC software set/clear interrupt register 4 8 Base + 0x0025 INTC_SSCIR5 INTC software set/clear interrupt register 5 8 Base + 0x0026 INTC_SSCIR6 INTC software set/clear interrupt register 6 8 Base + 0x0027 INTC_SSCIR7 INTC software set/clear interrupt register 7 8 Base + (0x0028–0x003C) — Reserved — Base + (0x0040–0x0110) INTC_PSRn INTC priority select register2 0–203 8 Base (0xFFF4_8000) 1 2 When the HVEN bit in the INTC_MCR is asserted, a read of the INTC_IACKR has no side effects. The PRI fields are “Reserved” for peripheral interrupt requests whose vectors are labeled as Reserved in Table 10-9. With the exception of the INTC_SSCIn and INTC_PSRn registers, all of the registers are 32 bits in width. Any combination of accessing the 4 bytes of a register with a single access is supported, provided that the access does not cross a register boundary. These supported accesses include types and sizes of 8 bits, aligned 16 bits, and aligned 32 bits. Although INTC_SSCIn and INTC_PSRn and 8 bits wide, they can be accessed with a single 16-bit or 32-bit access, provided that the access does not cross a 32-bit boundary. MPC5533 Microcontroller Reference Manual, Rev. 0 10-8 Freescale Semiconductor In software vector mode, the side effects of a read of the INTC interrupt acknowledge register (INTC_IACKR) are the same regardless of the size of the read. In either software or hardware vector mode, the size of a write to the INTC end-of-interrupt register (INTC_EOIR) does not affect the operation of the write. 10.3.1.1 INTC Module Configuration Register (INTC_MCR) The INTC_MCR is used to configure options of the INTC. Address: Base + 0x0000 Access: User R/W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 26 VTES 0 27 28 29 30 0 0 0 0 0 0 0 0 31 HVEN Figure 10-7. INTC Module Configuration Register (INTC_MCR) Table 10-4. INTC_MCR Field Descriptions Field Description 0–25 Reserved, must be cleared. 26 VTES Vector table entry size. Controls the number of ‘0’s to the right of INTVEC in Section 10.3.1.3, “INTC Interrupt Acknowledge Register (INTC_IACKR). If the contents of INTC_IACKR are used as an address of an entry in a vector table as in software vector mode, then the number of rightmost ‘0’s determines the size of each vector table entry. VTES impacts software vector mode operation but also affects INTC_IACKR[INTVEC] position in both hardware vector mode and software vector mode. 0 4 bytes (Normal expected use) 1 8 bytes 27–30 Reserved, must be cleared. 31 HVEN Hardware vector enable. Controls whether the INTC is in hardware vector mode or software vector mode. See Section 10.1.4, “Modes of Operation”, for the details of the handshaking with the processor in each mode. 0 Software vector mode 1 Hardware vector mode 10.3.1.2 INTC Current Priority Register (INTC_CPR) The INTC_CPR masks any peripheral or software settable interrupt request set at the same or lower priority as the current value of the INTC_CPR[PRI] field from generating an interrupt request to the processor. When the INTC interrupt acknowledge register (INTC_IACKR) is read in software vector mode or the interrupt acknowledge signal from the processor is asserted in hardware vector mode, the value of PRI is pushed onto the LIFO, and PRI is updated with the priority of the preempting interrupt request. When the INTC end-of-interrupt register (INTC_EOIR) is written, the LIFO is popped into the INTC_CPR’s PRI field. The masking priority can be raised or lowered by writing to the PRI field, supporting the PCP. See Section 10.5.5, “Priority Ceiling Protocol.” MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 10-9 0 NOTE On some eSys MCUs, a store to raise the PRI field which closely precedes an access to a shared resource can result in a non-coherent access to that resource unless an MBAR or MSYNC followed by an ISYNC sequence of instructions is executed between the accesses. An MBAR or MSYNC instruction is also necessary after accessing the resource but before lowering the PRI field. See Section 10.5.5.2, “Ensuring Coherency.” Address: Base + 0x0008 (INTC_CPR) Access: User R/W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI W Reset 0 1 1 1 1 Figure 10-8. INTC Current Priority Register (INTC_CPR) Table 10-5. INTC_CPR Field Descriptions Field Description 0–27 Reserved, must be cleared. 28–31 PRI Priority. PRI is the priority of the currently executing ISR according to the field values defined below. 1111 Priority 15 (highest) 1110 Priority 14 ... 0001 Priority 1 0000 Priority 0 (lowest) 10.3.1.3 INTC Interrupt Acknowledge Register (INTC_IACKR) The INTC_IACKR provides a value that can be used to load the address of an ISR from a vector table. The vector table can be composed of addresses of the ISRs specific to their respective interrupt vectors. Also, in software vector mode, the INTC_IACKR has side effects from reads. The side effects are the same regardless of the size of the read. Reading the INTC_IACKR does not have side effects in hardware vector mode. NOTE The INTC_IACKR must not be read speculatively while in software vector mode. Therefore, for future compatibility, the TLB entry covering the INTC_IACKR must be configured to be guarded. In software vector mode, the INTC_IACKR must be read before setting MSR[EE]. No synchronization instruction is needed after reading the INTC_IACKR and before setting MSR[EE]. MPC5533 Microcontroller Reference Manual, Rev. 0 10-10 Freescale Semiconductor However, the time for the processor to recognize the assertion or negation of the external input to it is not defined by the book E architecture and can be greater than 0. Therefore, insert instructions between the reading of the INTC_IACKR and the setting of MSR[EE] that consume at least two processor clock cycles. This length of time allows the negation of the interrupt request to propagate through the processor before MSR[EE] is set. Address: Base + 0x0010 (INTC_IACKR) 0 1 2 3 4 5 6 7 8 Access: User R/W 9 R 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 INTVEC VTBA W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 10-9. INTC Interrupt Acknowledge Register (INTC_IACKR)—INTC_MCR[VTES] = 0 Address: Base + 0x0010 (INTC_IACKR) 0 1 2 3 4 5 6 7 8 R Access: User R/W 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 INTVEC VTBA W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 10-10. INTC Interrupt Acknowledge Register (INTC_IACKR)—INTC_MCR[VTES] = 1 Table 10-6. INTC_IACKR Field Descriptions Field Description 0–20 or 0–19 VTBA Vector table base address. Can be the base address of a vector table of addresses of ISRs. The VTBA only uses the leftmost 20 bits when the VTES bit in INTC_MCR is asserted. 21–29 or 20–28 INTVEC Interrupt vector. Vector of the peripheral or software-settable interrupt request that caused the interrupt request to the processor. When the interrupt request to the processor asserts, the INTVEC is updated, whether the INTC is in software or hardware vector mode. Note: If INTC_MCR[VTES] = 1, then the INTVEC field is shifted left one position to bits 20–28. VTBA is then shortened by one bit to bits 0–19. 30–31 or 29–31 Reserved, must be cleared. 10.3.1.4 INTC End-of-Interrupt Register (INTC_EOIR) Writing to the INTC_EOIR signals the end of the servicing of the interrupt request. When the INTC_EOIR is written, the priority last pushed on the LIFO is popped into INTC_CPR. The values and size of data written to the INTC_EOIR are ignored. Those values and sizes written to this register neither update the INTC_EOIR contents or affect whether the LIFO pops. For possible future compatibility, write four bytes of all 0’s to the INTC_EOIR. Reading the INTC_EOIR has no effect on the LIFO. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 10-11 Address: Base + 0x0018 (INTC_EOIR) Access: User W/O 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EOIR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 10-11. INTC End-of-Interrupt Register (INTC_EOIR) 10.3.1.5 INTC Software Set/Clear Interrupt Registers (INTC_SSCIR[0–7]) The INTC_SSCIRn support the setting or clearing of software settable interrupt requests. These registers contain eight independent sets of bits to set and clear a corresponding flag bit by software. With the exception of being set by software, this flag bit behaves the same as a flag bit set within a peripheral. This flag bit generates an interrupt request within the INTC just like a peripheral interrupt request. Writing a 1 to SETn leaves SETn unchanged at 0, but sets CLRn. Writing a 0 to SETn has no effect. CLRn is the flag bit. Writing a 1 to CLRn clears it. Writing a 0 to CLRn has no effect. If a 1 is written to a pair SETn and CLRn bits at the same time, CLRn is asserted, regardless of whether CLRn was asserted before the write. Although INTC_SSCIn is 8-bits wide, it can be accessed with a single 16-bit or 32-bit access, provided that the access does not cross a 32-bit boundary. Address: Base + 0x0020 + n (INTC_SSCIRn); n = 0–7 R Access: User R/W 0 1 2 3 4 5 6 0 0 0 0 0 0 0 7 CLRn W Reset SETn 0 0 0 0 0 0 0 0 Figure 10-12. INTC Software Set/Clear Interrupt Register (INTC_SSCIRn) Table 10-7. INTC_SSCIRn Field Descriptions Field 0–5 Description Reserved, must be cleared. 6 SETn Set flag bits. Writing a 1 sets the CLRn bit. Writing a 0 has no effect. Each SETn always is read as a 0. 7 CLRn Clear flag bits. CLRn is the flag bit. Writing a 1 to CLRn clear it provided that a 1 is not written simultaneously to its corresponding SETn bit. Writing a 0 to CLRn has no effect. 0 Interrupt request not pending within INTC. 1 Interrupt request pending within INTC. 10.3.1.6 INTC Priority Select Registers (INTC_PSR[0–50, 67–130, 136–146, 152–193]) The INTC_PSRn support the selection of an individual priority for each source of interrupt request. The unique vector of each peripheral or software settable interrupt request determines which INTC_PSRn is assigned to that interrupt request. The software settable interrupt requests 0–7 are assigned vectors 0–7, and their priorities are configured in INTC_PSR0–INTC_PSR7, respectively. The peripheral interrupt MPC5533 Microcontroller Reference Manual, Rev. 0 10-12 Freescale Semiconductor requests are assigned vectors 8–203 and their priorities are configured in INTC_PSR8 through INTC_PSR203, respectively. Although INTC_PSRn is 8 bits wide, it can be accessed with a single 16-bit or 32-bit access, provided that the access does not cross a 32-bit boundary. NOTE Do not modify the PRIn field of an INTC_PSRn while its corresponding peripheral or software settable interrupt request is asserted. Address: Base + 0x0040 + n (INTC_PSRn); n = 0–203 R Access: User R/W 0 1 2 3 0 0 0 0 4 5 6 7 0 0 PRIn W Reset 0 0 0 0 0 0 Figure 10-13. INTC Priority Select Registers (INTC_PSRn) Table 10-8. INTC_SSCIRn Field Descriptions Field Description 0–3 Reserved, must be cleared. 4–7 PRIn Priority select. Selects the priority for corresponding interrupt request. 1111 Priority 15 (highest) 1110 Priority 14 ... 0001 Priority 1 0000 Disabled 10.4 10.4.1 Functional Description Interrupt Request Sources The INTC has two types of interrupt requests, peripheral and software settable. The assignments between the interrupt requests from the modules to the vectors for input to the e200z3 are shown in Table 10-9. The Offset column lists the IRQ specific offsets when using hardware vector mode. The Source column is written in C language syntax. The syntax is ‘module_register[bit].’ Interrupt requests from the same module location or ORed together. The individual interrupt priorities are selected in INTC_PSRn, where the specific select register is assigned according to the vector. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 10-13 Table 10-9. INTC: Interrupt Request Sources Hardware Vector Mode Offset Vector Source1 Description Software 0x0000 0 INTC_SSCIR0[CLR0] INTC software settable Clear flag 0 0x0010 1 INTC_SSCIR1[CLR1] INTC software settable Clear flag 1 0x0020 2 INTC_SSCIR2[CLR2] INTC software settable Clear flag 2 0x0030 3 INTC_SSCIR3[CLR3] INTC software settable Clear flag 3 0x0040 4 INTC_SSCIR4[CLR4] INTC software settable Clear flag 4 0x0050 5 INTC_SSCIR5[CLR5] INTC software settable Clear flag 5 0x0060 6 INTC_SSCIR6[CLR6] INTC software settable Clear flag 6 0x0070 7 INTC_SSCIR7[CLR7] INTC software settable Clear flag 7 Watchdog / ECC 0x0080 8 ECSM_SWTIR[SWTIC] ECSM Software Watchdog Interrupt flag 0x0090 9 ECSM_ESR[RNCE] ECSM_ESR[FNCE] ECSM combined interrupt requests: Internal SRAM Non-Correctable Error and flash Non-Correctable Error eDMA 0x00A0 10 EDMA_ERL[ERR31:ERR0] eDMA channel Error flags 31–0 0x00B0 11 EDMA_IRQRL[INT00] eDMA channel Interrupt 0 0x00C0 12 EDMA_IRQRL[INT01] eDMA channel Interrupt 1 0x00D0 13 EDMA_IRQRL[INT02] eDMA channel Interrupt 2 0x00E0 14 EDMA_IRQRL[INT03] eDMA channel Interrupt 3 0x00F0 15 EDMA_IRQRL[INT04] eDMA channel Interrupt 4 0x0100 16 EDMA_IRQRL[INT05] eDMA channel Interrupt 5 0x0110 17 EDMA_IRQRL[INT06] eDMA channel Interrupt 6 0x0120 18 EDMA_IRQRL[INT07] eDMA channel Interrupt 7 0x0130 19 EDMA_IRQRL[INT08] eDMA channel Interrupt 8 0x0140 20 EDMA_IRQRL[INT09] eDMA channel Interrupt 9 0x0150 21 EDMA_IRQRL[INT10] eDMA channel Interrupt 10 0x0160 22 EDMA_IRQRL[INT11] eDMA channel Interrupt 11 0x0170 23 EDMA_IRQRL[INT12] eDMA channel Interrupt 12 0x0180 24 EDMA_IRQRL[INT13] eDMA channel Interrupt 13 0x0190 25 EDMA_IRQRL[INT14] eDMA channel Interrupt 14 0x01A0 26 EDMA_IRQRL[INT15] eDMA channel Interrupt 15 0x01B0 27 EDMA_IRQRL[INT16] eDMA channel Interrupt 16 MPC5533 Microcontroller Reference Manual, Rev. 0 10-14 Freescale Semiconductor Table 10-9. INTC: Interrupt Request Sources (Continued) Hardware Vector Mode Offset Vector 0x01C0 28 EDMA_IRQRL[INT17] eDMA channel Interrupt 17 0x01D0 29 EDMA_IRQRL[INT18] eDMA channel Interrupt 18 0x01E0 30 EDMA_IRQRL[INT19] eDMA channel Interrupt 19 0x01F0 31 EDMA_IRQRL[INT20] eDMA channel Interrupt 20 0x0200 32 EDMA_IRQRL[INT21] eDMA channel Interrupt 21 0x0210 33 EDMA_IRQRL[INT22] eDMA channel Interrupt 22 0x0220 34 EDMA_IRQRL[INT23] eDMA channel Interrupt 23 0x0230 35 EDMA_IRQRL[INT24] eDMA channel Interrupt 24 0x0240 36 EDMA_IRQRL[INT25] eDMA channel Interrupt 25 0x0250 37 EDMA_IRQRL[INT26] eDMA channel Interrupt 26 0x0260 38 EDMA_IRQRL[INT27] eDMA channel Interrupt 27 0x0270 39 EDMA_IRQRL[INT28] eDMA channel Interrupt 28 0x0280 40 EDMA_IRQRL[INT29] eDMA channel Interrupt 29 0x0290 41 EDMA_IRQRL[INT30] eDMA channel Interrupt 30 0x02A0 42 EDMA_IRQRL[INT31] eDMA channel Interrupt 31 Source1 Description PLL 0x02B0 43 FMPLL_SYNSR[LOCF] FMPLL Loss of Clock Flag 0x02C0 44 FMPLL_SYNSR[LOLF] FMPLL Loss of Lock Flag SIU 0x02D0 45 SIU_OSR[OVF15:OVF0] SIU combined overrun interrupt requests of the external interrupt Overrun Flags 0x02E0 46 SIU_EISR[EIF0] SIU External Interrupt Flag 0 0x02F0 47 SIU_EISR[EIF1] SIU External Interrupt Flag 1 0x0300 48 SIU_EISR[EIF2] SIU External Interrupt Flag 2 0x0310 49 SIU_EISR[EIF3] SIU External Interrupt Flag 3 0x0320 50 SIU_EISR[EIF15:EIF4] SIU External Interrupt Flags 15–4 0x0330–0x0420 51–66 Reserved eTPU A 0x0430 67 ETPU_MCR[MGEA] ETPU_MCR[MGEB] ETPU_MCR[ILFA] ETPU_MCR[ILFB] ETPU_MCR[SCMMISF] eTPU Global Exception 0x0440 68 ETPU_CISR_A[CIS0] eTPU Engine A Channel 0 Interrupt Status MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 10-15 Table 10-9. INTC: Interrupt Request Sources (Continued) Hardware Vector Mode Offset Vector 0x0450 69 ETPU_CISR_A[CIS1] eTPU Engine A Channel 1 Interrupt Status 0x0460 70 ETPU_CISR_A[CIS2] eTPU Engine A Channel 2 Interrupt Status 0x0470 71 ETPU_CISR_A[CIS3] eTPU Engine A Channel 3 Interrupt Status 0x0480 72 ETPU_CISR_A[CIS4] eTPU Engine A Channel 4 Interrupt Status 0x0490 73 ETPU_CISR_A[CIS5] eTPU Engine A Channel 5 Interrupt Status 0x04A0 74 ETPU_CISR_A[CIS6] eTPU Engine A Channel 6 Interrupt Status 0x04B0 75 ETPU_CISR_A[CIS7] eTPU Engine A Channel 7 Interrupt Status 0x04C0 76 ETPU_CISR_A[CIS8] eTPU Engine A Channel 8 Interrupt Status 0x04D0 77 ETPU_CISR_A[CIS9] eTPU Engine A Channel 9 Interrupt Status 0x04E0 78 ETPU_CISR_A[CIS10] eTPU Engine A Channel 10 Interrupt Status 0x04F0 79 ETPU_CISR_A[CIS11] eTPU Engine A Channel 11 Interrupt Status 0x0500 80 ETPU_CISR_A[CIS12] eTPU Engine A Channel 12 Interrupt Status 0x0510 81 ETPU_CISR_A[CIS13] eTPU Engine A Channel 13 Interrupt Status 0x0520 82 ETPU_CISR_A[CIS14] eTPU Engine A Channel 14 Interrupt Status 0x0530 83 ETPU_CISR_A[CIS15] eTPU Engine A Channel 15 Interrupt Status 0x0540 84 ETPU_CISR_A[CIS16] eTPU Engine A Channel 16 Interrupt Status 0x0550 85 ETPU_CISR_A[CIS17] eTPU Engine A Channel 17 Interrupt Status 0x0560 86 ETPU_CISR_A[CIS18] eTPU Engine A Channel 18 Interrupt Status 0x0570 87 ETPU_CISR_A[CIS19] eTPU Engine A Channel 19 Interrupt Status 0x0580 88 ETPU_CISR_A[CIS20] eTPU Engine A Channel 20 Interrupt Status 0x0590 89 ETPU_CISR_A[CIS21] eTPU Engine A Channel 21 Interrupt Status 0x05A0 90 ETPU_CISR_A[CIS22] eTPU Engine A Channel 22 Interrupt Status 0x05B0 91 ETPU_CISR_A[CIS23] eTPU Engine A Channel 23 Interrupt Status 0x05C0 92 ETPU_CISR_A[CIS24] eTPU Engine A Channel 24 Interrupt Status 0x05D0 93 ETPU_CISR_A[CIS25] eTPU Engine A Channel 25 Interrupt Status 0x05E0 94 ETPU_CISR_A[CIS26] eTPU Engine A Channel 26 Interrupt Status 0x05F0 95 ETPU_CISR_A[CIS27] eTPU Engine A Channel 27 Interrupt Status 0x0600 96 ETPU_CISR_A[CIS28] eTPU Engine A Channel 28 Interrupt Status 0x0610 97 ETPU_CISR_A[CIS29] eTPU Engine A Channel 29 Interrupt Status 0x0620 98 ETPU_CISR_A[CIS30] eTPU Engine A Channel 30 Interrupt Status 0x0630 99 ETPU_CISR_A[CIS31] eTPU Engine A Channel 31 Interrupt Status Source1 Description MPC5533 Microcontroller Reference Manual, Rev. 0 10-16 Freescale Semiconductor Table 10-9. INTC: Interrupt Request Sources (Continued) Hardware Vector Mode Offset Vector Source1 Description eQADC 0x0640 100 EQADC_FISRx[TORF] EQADC_FISRx[RFOF] EQADC_FISRx[CFUF] eQADC combined overrun interrupt request s from all of the FIFOs: Trigger Overrun, Receive FIFO Overflow, and command FIFO Underflow 0x0650 101 EQADC_FISR0[NCF] eQADC command FIFO 0 Non-Coherency Flag 0x0660 102 EQADC_FISR0[PF] eQADC command FIFO 0 Pause Flag 0x0670 103 EQADC_FISR0[EOQF] eQADC command FIFO 0 command queue End of Queue Flag 0x0680 104 EQADC_FISR0[CFFF] eQADC Command FIFO 0 Fill Flag 0x0690 105 EQADC_FISR0[RFDF] eQADC Receive FIFO 0 Drain Flag 0x06A0 106 EQADC_FISR1[NCF] eQADC command FIFO 1 Non-Coherency Flag 0x06B0 107 EQADC_FISR1[PF] eQADC command FIFO 1 Pause Flag 0x06C0 108 EQADC_FISR1[EOQF] eQADC command FIFO 1 command queue End of Queue Flag 0x06D0 109 EQADC_FISR1[CFFF] eQADC Command FIFO 1 Fill Flag 0x06E0 110 EQADC_FISR1[RFDF] eQADC Receive FIFO 1 Drain Flag 0x06F0 111 EQADC_FISR2[NCF] eQADC command FIFO 2 Non-Coherency Flag 0x0700 112 EQADC_FISR2[PF] eQADC command FIFO 2 Pause Flag 0x0710 113 EQADC_FISR2[EOQF] eQADC command FIFO 2 command queue End of Queue Flag 0x0720 114 EQADC_FISR2[CFFF] eQADC Command FIFO 2 Fill Flag 0x0730 115 EQADC_FISR2[RFDF] eQADC Receive FIFO 2 Drain Flag 0x0740 116 EQADC_FISR3[NCF] eQADC command FIFO 3 Non-Coherency Flag 0x0750 117 EQADC_FISR3[PF] eQADC command FIFO 3 Pause Flag 0x0760 118 EQADC_FISR3[EOQF] eQADC command FIFO 3 command queue End of Queue Flag 0x0770 119 EQADC_FISR3[CFFF] eQADC Command FIFO 3 Fill Flag 0x0780 120 EQADC_FISR3[RFDF] eQADC Receive FIFO 3 Drain Flag 0x0790 121 EQADC_FISR4[NCF] eQADC command FIFO 4 Non-Coherency Flag 0x07A0 122 EQADC_FISR4[PF] eQADC command FIFO 4 Pause Flag 0x07B0 123 EQADC_FISR4[EOQF] eQADC command FIFO 4 command queue End of Queue Flag 0x07C0 124 EQADC_FISR4[CFFF] eQADC Command FIFO 4 Fill Flag 0x07D0 125 EQADC_FISR4[RFDF] eQADC Receive FIFO 4 Drain Flag MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 10-17 Table 10-9. INTC: Interrupt Request Sources (Continued) Hardware Vector Mode Offset Vector 0x07E0 126 EQADC_FISR5[NCF] eQADC command FIFO 5 Non-Coherency Flag 0x07F0 127 EQADC_FISR5[PF] eQADC command FIFO 5 Pause Flag 0x0800 128 EQADC_FISR5[EOQF] eQADC command FIFO 5 command queue End of Queue Flag 0x0810 129 EQADC_FISR5[CFFF] eQADC Command FIFO 5 Fill Flag 0x0820 130 EQADC_FISR5[RFDF] eQADC Receive FIFO 5 Drain Flag Source1 Description DSPI C, DSPI D 0x0830–0x0870 131–135 Reserved 0x0880 136 DSPI_CSR[TFUF] DSPI_CSR[RFOF] DSPI C combined overrun interrupt requests: Transmit FIFO Underflow and Receive FIFO Overflow 0x0890 137 DSPI_CSR[EOQF] DSPI C transmit FIFO End of Queue Flag 0x08A0 138 DSPI_CSR[TFFF] DSPI C Transmit FIFO Fill Flag 0x08B0 139 DSPI_CSR[TCF] DSPI C Transfer Complete Flag 0x08C0 140 DSPI_CSR[RFDF] DSPI C Receive FIFO Drain Flag 0x08D0 141 DSPI_DSR[TFUF] DSPI_DSR[RFOF] DSPI D combined overrun interrupt requests: Transmit FIFO Underflow and Receive FIFO Overflow 0x08E0 142 DSPI_DSR[EOQF] DSPI D transmit FIFO End of Queue Flag 0x08F0 143 DSPI_DSR[TFFF] DSPI D Transmit FIFO Fill Flag 0x0900 144 DSPI_DSR[TCF] DSPI D Transfer Complete Flag 0x0910 145 DSPI_DSR[RFDF] DSPI D Receive FIFO Drain Flag eSCI 0x0920 146 ESCIA_SR[TDRE] ESCIA_SR[TC] ESCIA_SR[RDRF] ESCIA_SR[IDLE] ESCIA_SR[OR] ESCIA_SR[NF] ESCIA_SR[FE] ESCIA_SR[PF] ESCIA_SR[BERR] ESCIA_SR[RXRDY] ESCIA_SR[TXRDY] ESCIA_SR[LWAKE] ESCIA_SR[STO] ESCIA_SR[PBERR] ESCIA_SR[CERR] ESCIA_SR[CKERR] ESCIA_SR[FRC] ESCIA_SR[OVFL] Combined Interrupt Requests of ESCI Module A: Transmit Data Register Empty, Transmit Complete, Receive Data Register Full, Idle line, Overrun, Noise Flag, Framing Error Flag, and Parity Error Flag interrupt requests, SCI Status Register 2 Bit Error interrupt request, LIN Status Register 1 Receive Data Ready, Transmit Data Ready, Received LIN Wakeup Signal, Slave TimeOut, Physical Bus Error, CRC Error, Checksum Error, Frame Complete interrupts requests, and LIN Status Register 2 Receive Register Overflow MPC5533 Microcontroller Reference Manual, Rev. 0 10-18 Freescale Semiconductor Table 10-9. INTC: Interrupt Request Sources (Continued) Hardware Vector Mode Offset 0x0930–0x0970 Source1 Vector 147–151 Reserved Description Reserved FlexCAN A and FlexCAN C 0x0980 152 CANA_ESR[BOFF_INT] FLEXCAN A Bus Off Interrupt 0x0990 153 CANA_ESR[ERR_INT] FLEXCAN A Error Interrupt 0x09A0 154 Reserved Reserved 0x09B0 155 CANA_IFRL[BUF0] FLEXCAN A Buffer 0 Interrupt 0x09C0 156 CANA_IFRL[BUF1] FLEXCAN A Buffer 1 Interrupt 0x09D0 157 CANA_IFRL[BUF2] FLEXCAN A Buffer 2 Interrupt 0x09E0 158 CANA_IFRL[BUF3] FLEXCAN A Buffer 3 Interrupt 0x09F0 159 CANA_IFRL[BUF4] FLEXCAN A Buffer 4 Interrupt 0x0A00 160 CANA_IFRL[BUF5] FLEXCAN A Buffer 5 Interrupt 0x0A10 161 CANA_IFRL[BUF6] FLEXCAN A Buffer 6 Interrupt 0x0A20 162 CANA_IFRL[BUF7] FLEXCAN A Buffer 7 Interrupt 0x0A30 163 CANA_IFRL[BUF8] FLEXCAN A Buffer 8 Interrupt 0x0A40 164 CANA_IFRL[BUF9] FLEXCAN A Buffer 9 Interrupt 0x0A50 165 CANA_IFRL[BUF10] FLEXCAN A Buffer 10 Interrupt 0x0A60 166 CANA_IFRL[BUF11] FLEXCAN A Buffer 11 Interrupt 0x0A70 167 CANA_IFRL[BUF12] FLEXCAN A Buffer 12 Interrupt 0x0A80 168 CANA_IFRL[BUF13] FLEXCAN A Buffer 13 Interrupt 0x0A90 169 CANA_IFRL[BUF14] FLEXCAN A Buffer 14 Interrupt 0x0AA0 170 CANA_IFRL[BUF15] FLEXCAN A Buffer 15 Interrupt 0x0AB0 171 CANA_IFRL[BUF31I:BUF16] FLEXCAN A Buffers 31–16 Interrupts 0x0AC0 172 CANA_IFRH[BUF63I:BUF32] FLEXCAN A Buffers 63–32 Interrupts 0x0AD0 173 CANC_ESR[BOFF_INT] FLEXCAN C Bus Off Interrupt 0x0AE0 174 CANC_ESR[ERR_INT] FLEXCAN C Error Interrupt 0x0AF0 175 Reserved Reserved 0x0B00 176 CANC_IFRL[BUF0] FLEXCAN C Buffer 0 Interrupt 0x0B10 177 CANC_IFRL[BUF1] FLEXCAN C Buffer 1 Interrupt 0x0B20 178 CANC_IFRL[BUF2] FLEXCAN C Buffer 2 Interrupt 0x0B30 179 CANC_IFRL[BUF3] FLEXCAN C Buffer 3 Interrupt 0x0B40 180 CANC_IFRL[BUF4] FLEXCAN C Buffer 4 Interrupt 0x0B50 181 CANC_IFRL[BUF5] FLEXCAN C Buffer 5 Interrupt MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 10-19 Table 10-9. INTC: Interrupt Request Sources (Continued) Hardware Vector Mode Offset Vector 0x0B60 182 CANC_IFRL[BUF6] FLEXCAN C Buffer 6 Interrupt 0x0B70 183 CANC_IFRL[BUF7] FLEXCAN C Buffer 7 Interrupt 0x0B80 184 CANC_IFRL[BUF8] FLEXCAN C Buffer 8 Interrupt 0x0B90 185 CANC_IFRL[BUF9] FLEXCAN C Buffer 9 Interrupt 0x0BA0 186 CANC_IFRL[BUF10] FLEXCAN C Buffer 10 Interrupt 0x0BB0 187 CANC_IFRL[BUF11] FLEXCAN C Buffer 11 Interrupt 0x0BC0 188 CANC_IFRL[BUF12] FLEXCAN C Buffer 12 Interrupt 0x0BD0 189 CANC_IFRL[BUF13] FLEXCAN C Buffer 13 Interrupt 0x0BE0 190 CANC_IFRL[BUF14] FLEXCAN C Buffer 14 Interrupt 0x0BF0 191 CANC_IFRL[BUF15] FLEXCAN C Buffer 15 Interrupt 0x0C00 192 CANC_IFRL[BUF31:BUF16] FLEXCAN C Buffers 31–16 Interrupts 0x0C10 193 CANC_IFRH[BUF63:BUF32] FLEXCAN C Buffers 63–32 Interrupts 0x0C20–0x0CB0 1 Source1 194–203 Reserved Description Reserved Interrupt requests from the same module location are ORed together. NOTE The INTC has no spurious vector support. If an asserted peripheral or software settable interrupt request: • Has a PRIn value (INTC_PSR0–INTC_PSR203) higher than the PRI value in INTC_CPR; and • Negates before the processor for that interrupt request acknowledges IRQ The IRQ to the processor can assert or remain asserted for that peripheral or software configurable interrupt request. In this case, the interrupt vector for the peripheral or software configurable IRQ remains, and the PRI value in the INTC_CPR is updated to the PRIn value in INTC_PSRn. Clearing the peripheral interrupt request enable bit, or setting its mask bit has the same consequences as clearing its flag bit. Setting its enable bit or clearing its mask bit while its FLAG bit is asserted has the same effect on the INTC as an interrupt event setting the flag bit. 10.4.1.1 Peripheral Interrupt Requests An interrupt event in a peripheral’s hardware sets a flag bit which resides in that peripheral. The interrupt request from the peripheral is driven by that flag bit. The time from when the peripheral starts to drive its peripheral interrupt request to the INTC to the time that the INTC starts to drive the interrupt request to the processor is three clocks. MPC5533 Microcontroller Reference Manual, Rev. 0 10-20 Freescale Semiconductor 10.4.1.2 Software Configurable Interrupt Requests The software set and clear interrupt registers (INTC_SSCIRx_x) support the setting or clearing of software-configurable interrupt requests. These registers contain eight independent sets of bits to set and clear a corresponding flag bit by software. With the exception of being set by software, this flag bit operates the same as a flag bit set within a peripheral. This flag bit generates an interrupt request within the INTC just like a peripheral interrupt request. An interrupt request is triggered by software writing a 1 to the SETn bit in INTC software set/clear interrupt registers (INTC_SSCIR0–INTC_SSCIR7). This write sets the corresponding CLRn bit, which is a flag bit, resulting in the interrupt request. The interrupt request is cleared by writing a 1 to the CLRn bit. Specific operations includes the following: • Writing a 1 to SETn leaves SETn unchanged at '0' but sets the flag bit (which is the CLRn bit). • Writing a 0 to SETn has no effect. • Writing a 1 to CLRn clears the flag (CLRx) bit. • Writing a 0 to CLRn has no effect. • If a 1 is written to a pair of SETn and CLRn bits at the same time, the flag (CLRx) is set, regardless of whether CLRn was asserted before the write. The time from the write to the SETn bit to the time that the INTC starts to drive the interrupt request to the processor is four clocks. 10.4.1.3 Unique Vector for Each Interrupt Request Source Each peripheral and software configurable interrupt request is assigned a hardwired unique 9-bit vector. Software configurable interrupts 0–7 are assigned vectors 0–7, respectively. The peripheral interrupt requests are assigned vectors 8 to as high as needed to cover all of the peripheral interrupt requests. 10.4.2 Priority Management The asserted interrupt requests are compared to each other based on their PRIn values in INTC priority select registers (INTC_PSR0–INTC_PSR203). The result of that comparison also is compared to PRI in INTC current priority register (INTC_CPR). The results of those comparisons are used to manage the priority of the ISR being executed by the processor. The LIFO also assists in managing that priority. 10.4.2.1 Current Priority and Preemption The priority arbitrator, selector, encoder, and comparator submodules shown in Figure 10-1 are used to compare the priority of the asserted interrupt requests to the current priority. If the priority of any asserted peripheral or software configurable interrupt request is higher than the current priority, then the interrupt request to the processor is asserted. Also, a unique vector for the preempting peripheral or software configurable interrupt request is generated for INTC interrupt acknowledge register (INTC_IACKR), and if in hardware vector mode, for the interrupt vector provided to the processor. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 10-21 10.4.2.1.1 Priority Arbitrator Submodule The priority arbitrator submodule compares all the priorities of all of the asserted interrupt requests, both peripheral and software configurable. The output of the priority arbitrator submodule is the highest of those priorities. Also, any interrupt requests which have this highest priority are output as asserted interrupt requests to the request selector submodule. 10.4.2.1.2 Request Selector Submodule If only one interrupt request from the priority arbitrator submodule is asserted, then it is passed as asserted to the vector encoder submodule. If multiple interrupt requests from the priority arbitrator submodule are asserted, then only the one with the lowest vector is passed as asserted to the vector encoder submodule. The lower vector is chosen regardless of the time order of the assertions of the peripheral or software configurable interrupt requests. 10.4.2.1.3 Vector Encoder Submodule The vector encoder submodule generates the unique 9-bit vector for the asserted interrupt request from the request selector submodule. 10.4.2.1.4 Priority Comparator Submodule The priority comparator submodule compares the highest priority output from the priority arbitrator submodule with PRI in INTC_CPR. If the priority comparator submodule detects that this highest priority is higher than the current priority, then it asserts the interrupt request to the processor. This interrupt request to the processor asserts whether this highest priority is raised above the value of PRI in INTC_CPR or the PRI value in INTC_CPR is lowered below this highest priority. This highest priority then becomes the new priority, which is written to PRI in INTC_CPR when the interrupt request to the processor is acknowledged. Interrupt requests with the PRIn in INTC_PSRn set to zero do not cause a preemption because their PRIn are not higher than PRI in INTC_CPR. 10.4.2.2 LIFO The LIFO stores the preempted PRI values from the INTC_CPR. Therefore, because these priorities are stacked within the INTC, if interrupts must be enabled during the ISR, at the beginning of the interrupt exception handler the PRI value in the INTC_CPR does not need to be loaded from the INTC_CPR and stored onto the context stack. Likewise at the end of the interrupt exception handler, the priority does not need to be loaded from the context stack and stored into the INTC_CPR. The PRI value in the INTC_CPR is pushed onto the LIFO when the INTC_IACKR is read in software vector mode or the interrupt acknowledge signal from the processor is asserted in hardware vector mode. The priority is popped into PRI in the INTC_CPR whenever the INTC_EOIR is written. Although the INTC supports 16 priorities, an ISR executing with PRI in the INTC_CPR equal to 15 is not preempted. Therefore, the LIFO supports the stacking of 15 priorities. However, the LIFO is only 14 entries deep. An entry for a priority 0 is not needed because of how pushing onto a full LIFO and popping an empty LIFO operate. MPC5533 Microcontroller Reference Manual, Rev. 0 10-22 Freescale Semiconductor • • If the LIFO is pushed 15 or more times than it is popped, the priorities first pushed are overwritten (priority 0 is overwritten). If the LIFO pops more times than it is pushed, the popped priorities are 0. Therefore, although a priority 0 was overwritten, it is regenerated with the popping of an empty LIFO. The LIFO is not memory mapped. 10.4.3 10.4.3.1 10.4.3.1.1 Details on Handshaking with Processor Software Vector Mode Handshaking Acknowledging Interrupt Request to Processor A timing diagram of the interrupt request and acknowledge handshaking in software vector mode, along with the handshaking near the end of the interrupt exception handler, is shown in Figure 10-14. The INTC examines the peripheral and software settable interrupt requests. When it finds an asserted peripheral or software settable interrupt request with a higher priority than PRI in INTC current priority register (INTC_CPR), it asserts the interrupt request to the processor. The INTVEC field in INTC interrupt acknowledge register (INTC_IACKR) is updated with the preempting interrupt request’s vector when the interrupt request to the processor is asserted. The INTVEC field retains that value until the next time the interrupt request to the processor is asserted. The rest of the handshaking is described in Section 10.1.4.1, “Software Vector Mode.” 10.4.3.1.2 End-of-Interrupt Exception Handler Before the interrupt exception handling completes, INTC end-of-interrupt register (INTC_EOIR) must be written. When it is written, the LIFO is popped so that the preempted priority is restored into PRI of the INTC_CPR. Before it is written, the peripheral or software settable flag bit must be cleared so that the peripheral or software settable interrupt request is negated. NOTE To ensure proper operation across all devices, execute an MBAR or MSYNC instruction between the access to clear the flag bit and the write to the INTC_EOIR. When returning from the preemption, the INTC does not search for the peripheral or software settable interrupt request whose ISR was preempted. Depending on how much the ISR progressed, that interrupt request can be asserted. When PRI in INTC_CPR is decreased to the priority of the preempted ISR, the interrupt request for the preempted ISR or any other asserted peripheral or software settable interrupt request at or less than that priority does not cause a preemption. Instead, after the restoration of the preempted context, the processor returns to the instruction address for the next ISR to execute before it is preempted. This next instruction is part of the preempted ISR or the interrupt exception handler’s prolog or epilog. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 10-23 Clock Interrupt Request to Processor Hardware Vector Enable Interrupt Vector 0 Interrupt Acknowledge Read INTC_IACKR Write INTC_EOIR INTVEC in INTC_IACKR PRI in INTC_CPR 0 108 0 1 0 Peripheral Interrupt Request 100 Figure 10-14. Software Vector Mode Handshaking Timing Diagram 10.4.3.2 Hardware Vector Mode Handshaking A timing diagram of the interrupt request and acknowledge handshaking in hardware vector mode, along with the handshaking near the end of the interrupt exception handler, is shown in Figure 10-15. As in software vector mode, the INTC examines the peripheral and software settable interrupt requests, and when it finds an asserted one with a higher priority than PRI in INTC_CPR, it asserts the interrupt request to the processor. The INTVEC field in the INTC_IACKR is updated with the preempting peripheral or software settable interrupt request’s vector when the interrupt request to the processor is asserted. The INTVEC field retains that value until the next time the interrupt request to the processor is asserted. In addition, the value of the interrupt vector to the processor matches the value of the INTVEC field in the INTC_IACKR. The rest of the handshaking is described in Section 10.1.4.2, “Hardware Vector Mode.” The handshaking near the end of the interrupt exception handler, that is the writing to the INTC_EOIR, is the same as in software vector mode. See Section 10.4.3.1.2, “End-of-Interrupt Exception Handler.” MPC5533 Microcontroller Reference Manual, Rev. 0 10-24 Freescale Semiconductor Clock Interrupt Request to Processor Hardware Vector Enable Interrupt Vector 0 108 Interrupt Acknowledge Read INTC_IACKR Write INTC_EOIR INTVEC in INTC_IACKR 0 PRI in INTC_CPR 108 0 1 0 Peripheral Interrupt Request 100 Figure 10-15. Hardware Vector Mode Handshaking Timing Diagram 10.5 10.5.1 Initialization/Application Information Initialization Flow After exiting reset, all of the PRIn fields in INTC priority select registers (INTC_PSR0–INTC_PSR203) are zero, and PRI in INTC current priority register (INTC_CPR) is 15. These reset values prevent INTC from asserting the interrupt request to the processor. The enable or mask bits in the peripherals are reset such that the peripheral interrupt requests are negated. An initialization sequence that allows peripheral and software settable interrupt requests to generate an interrupt request to the processor follows: Interrupt request initialization 1. Configure the VTES and HVEN fields in the master control register INTC_MCR 2. Configure the VTBA field in INTC_IACKR 3. Raise the PRIn fields in INTC_PSRn 4. Set the enable bits or clear the mask bits for the peripheral interrupt requests 5. Clear the PRI field in INTC_CPR to zero 6. Enable processor recognition of interrupts MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 10-25 10.5.2 Interrupt Exception Handler These example interrupt exception handlers use PowerPC Book E assembly code. 10.5.2.1 Software Vector Mode interrupt_exception_handler: code to create stack frame, save working register, and save SRR0 and SRR1 lis lwz lwz wrteei r3,INTC_IACKR@ha r3,INTC_IACKR@l(r3) r3,0x0(r3) 1 # # # # form adjusted upper half of INTC_IACKR address load INTC_IACKR, which clears request to processor load address of ISR from vector table enable processor recognition of interrupts code to save rest of context required by e500 EABI mtlr blrl r3 # move address of ISR into link register # branch to ISR; link register updated with epilog # address epilog: code to restore most of context required by e500 EABI # Popping the LIFO after the restoration of most of the context and the disabling of processor # recognition of interrupts eases the calculation of the maximum stack depth at the cost of # postponing the servicing of the next interrupt request. mbar # ensure store to clear flag bit has completed lis r3,INTC_EOIR@ha # form adjusted upper half of INTC_EOIR address li r4,0x0 # form 0 to write to INTC_EOIR wrteei 0 # disable processor recognition of interrupts stw r4,INTC_EOIR@l(r3) # store to INTC_EOIR, informing INTC to lower priority code to restore SRR0 and SRR1, restore working registers, and delete stack frame rfi vector_table_base_address: address of ISR for interrupt address of ISR for interrupt . . . address of ISR for interrupt address of ISR for interrupt with vector 0 with vector 1 with vector 510 with vector 511 ISRx: code to service the interrupt event code to clear flag bit which drives interrupt request to INTC blr # return to epilog MPC5533 Microcontroller Reference Manual, Rev. 0 10-26 Freescale Semiconductor 10.5.2.2 Hardware Vector Mode This interrupt exception handler is useful with processor and system bus implementations that support a hardware vector. This example assumes that each interrupt_exception_handlerx only has space for four instructions, and therefore a branch to interrupt_exception_handler_continuedx is needed. interrupt_exception_handlerx: b interrupt_exception_handler_continuedx# 4 instructions available, branch to continue interrupt_exception_handler_continuedx: code to create stack frame, save working register, and save SRR0 and SRR1 wrteei 1 # enable processor recognition of interrupts code to save rest of context required by e500 EABI bl ISRx # branch to ISR for interrupt with vector x epilog: code to restore most of context required by e500 EABI # Popping the LIFO after the restoration of most of the context and the disabling of processor # recognition of interrupts eases the calculation of the maximum stack depth at the cost of # postponing the servicing of the next interrupt request. mbar # ensure store to clear flag bit has completed lis r3,INTC_EOIR@ha # form adjusted upper half of INTC_EOIR address li r4,0x0 # form 0 to write to INTC_EOIR wrteei 0 # disable processor recognition of interrupts stw r4,INTC_EOIR@l(r3) # store to INTC_EOIR, informing INTC to lower priority code to restore SRR0 and SRR1, restore working registers, and delete stack frame rfi ISRx: code to service the interrupt event code to clear flag bit which drives interrupt request to INTC blr 10.5.3 # branch to epilog ISR, RTOS, and Task Hierarchy The RTOS and all of the tasks under its control typically execute with PRI in INTC current priority register (INTC_CPR) having a value of 0. The RTOS executes the tasks according to the its current priority scheme, but that priority scheme is independent and has a lower priority of execution than the priority scheme of the INTC. In other words, the ISRs execute above INTC_CPR priority 0 and outside the control of the RTOS, the RTOS executes at INTC_CPR priority 0, and while the tasks execute at different priorities under the control of the RTOS, they also execute at INTC_CPR priority 0. If a task shares a resource with an ISR and the PCP is being used to manage that shared resource, then the task’s priority can be elevated in the INTC_CPR while the shared resource is being accessed. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 10-27 An ISR whose PRIn in INTC priority select registers (INTC_PSR0–INTC_PSR203) has a value of 0 does not cause an interrupt request to the processor, even if its peripheral or software settable interrupt request is asserted. For a peripheral interrupt request, not setting its enable bit or disabling the mask bit causes it to remain deasserted, which does not cause an interrupt request to the processor. Since the ISRs are outside the control of the RTOS, this ISR is not run unless called by another ISR or the interrupt exception handler, perhaps after executing another ISR. 10.5.4 Order of Execution An ISR with a higher priority can preempt an ISR with a lower priority, regardless of the unique vectors associated with each of their peripheral or software settable interrupt requests. However, if multiple peripheral or software settable interrupt requests are asserted, more than one has the highest priority, and that priority is high enough to cause preemption, the INTC selects the one with the lowest unique vector regardless of the order in time that they asserted. However, the ability to meet deadlines with this scheduling scheme is no less than if the ISRs execute in the time order that their peripheral or software settable interrupt requests asserted. The example in Table 10-10 shows the order of execution of both ISRs with different priorities and the same priority. Table 10-10. Order of ISR Execution Example Code Executing At End of Step Step Step Description RTOS ISR1081 ISR208 ISR308 ISR408 PRI in INTC_CPR Interrupt at End of Exception Step Handler 1 RTOS at priority 0 is executing. X 0 2 Peripheral interrupt request 100 at priority 1 asserts. Interrupt taken. 3 Peripheral interrupt request 400 at priority 4 is asserts. Interrupt taken. X 4 4 Peripheral interrupt request 300 at priority 3 is asserts. X 4 5 Peripheral interrupt request 200 at priority 3 is asserts. X 4 6 ISR408 completes. Interrupt exception handler writes to INTC_EOIR. 7 Interrupt taken. ISR208 starts to execute, even though peripheral interrupt request 300 asserted first. 8 ISR208 completes. Interrupt exception handler writes to INTC_EOIR. 9 Interrupt taken. ISR308 starts to execute. X 1 X X 1 3 X X 1 3 MPC5533 Microcontroller Reference Manual, Rev. 0 10-28 Freescale Semiconductor Table 10-10. Order of ISR Execution Example (Continued) Code Executing At End of Step Step Step Description RTOS 1 ISR1081 ISR208 ISR308 ISR408 PRI in INTC_CPR Interrupt at End of Exception Step Handler 10 ISR308 completes. Interrupt exception handler writes to INTC_EOIR. X 1 11 ISR108 completes. Interrupt exception handler writes to INTC_EOIR. X 0 12 RTOS continues execution. X 0 ISR108 executes for peripheral interrupt request 100 because the first eight ISRs are for software settable interrupt requests. 10.5.5 10.5.5.1 Priority Ceiling Protocol Elevating Priority The PRI field in INTC current priority register (INTC_CPR) is elevated in the OSEK PCP to the ceiling of all of the priorities of the ISRs that share a resource. This protocol therefore allows coherent accesses of the ISRs to that shared resource. For example, ISR1 has a priority of 1, ISR2 has a priority of 2, and ISR3 has a priority of 3. They all share the same resource. Before ISR1 or ISR2 can access that resource, they must raise the PRI value in INTC_CPR to 3, the ceiling of all of the ISR priorities. After they release the resource, they must lower the PRI value in INTC_CPR to prevent further scheduling inefficiencies. If they do not raise their priority, then ISR2 can preempt ISR1, and ISR3 can preempt ISR1 or ISR2, possibly corrupting the shared resource. Another possible failure mechanism is deadlock if the higher priority ISR needs the lower priority ISR to release the resource before it can continue, but the lower priority ISR can not release the resource until the higher priority ISR completes and execution returns to the lower priority ISR. Using the PCP instead of disabling processor recognition of all interrupts reduces the time used by scheduling inefficiencies when accessing a shared resource. For example, while ISR3 can not preempt ISR1 while it is accessing the shared resource, all of the ISRs with a priority higher than 3 can preempt ISR1. 10.5.5.2 Ensuring Coherency A scenario can exist that can cause non-coherent accesses to the shared resource. As an example, ISR1 and ISR2 both share a resource. ISR1 has a lower priority than ISR2. ISR1 is executing, and it writes to the INTC_CPR. The instruction following this store is a store to a value in a shared coherent data block. Either just before or at the same time as the first store, the INTC asserts the interrupt request to the processor because the peripheral interrupt request for ISR2 has asserted. As the processor is responding to the interrupt request from the INTC, and as it is terminating transactions and flushing its pipeline, it is possible MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 10-29 for both of these stores to execute. ISR2 attempts to access the data block coherently, but the data block has been corrupted. OSEK uses the GetResource and ReleaseResource system services to manage access to a shared resource. To prevent corrupting a coherent data block, use these same system services with the following code to modify the PRI in INTC_CPR. Interrupts must be enabled before executing the following the GetResource code sequence. GetResource: raise PRI mbar isync ReleaseResource: mbar lower PRI 10.5.6 Selecting Priorities According to Request Rates and Deadlines The selection of the priorities for the ISRs can be made using rate monotonic scheduling (RMS) or a superset of it, deadline monotonic scheduling (DMS). In RMS, the ISRs with the higher request rates have higher priorities. In DMS, if the ISR deadline is set to occur before the next request for the ISR, then the ISR priority is assigned according to the time from the request for the IRS to the deadline, not from the time of the ISR request to the next ISR request for it. For example, ISR1 executes every 100 μs, ISR2 executes every 200 μs, and ISR3 executes every 300 μs. ISR1 has a higher priority than ISR2, which has a higher priority than ISR3. However, if ISR3 has a deadline of 150 μs, then its priority is higher than ISR2. The INTC has 16 priorities, which can be less than the number of ISRs. In this case, group the priority ISRs with other ISRs that have similar deadlines. For example, a priority can be allocated every time the request rate doubles. ISRs with the same approximate request rates can share a priority: • ISRs with request rates of approximately 1 ms • ISRs with request rates of approximately 500 μs • ISRs with request rates of approximately 250 μs Using this approach, a 216 range of ISR request rates can be prioritized, regardless of the number of ISRs. Reducing the number of priorities can cause scheduling inefficiencies which reduces the processor’s ability to meet its deadlines. It also allows easier management of ISRs with similar deadlines that share a resource. They can be placed at the same priority without any further scheduling inefficiencies, and they do not need to use the PCP to access the shared resource. 10.5.7 Software Settable Interrupt Requests The software settable interrupt requests can be used in two ways. They can be used to schedule a lower priority portion of an ISR and for processors to interrupt other processors in a multiple processor system. MPC5533 Microcontroller Reference Manual, Rev. 0 10-30 Freescale Semiconductor 10.5.7.1 Scheduling a Lower Priority Portion of an ISR A portion of an ISR needs to be executed at the PRIn value in INTC priority select registers (INTC_PSR0–INTC_PSR203), which becomes the PRI value in INTC current priority register (INTC_CPR) with the interrupt acknowledgement. The ISR, however, can have a portion of it which does not need to be executed at this higher priority. Therefore, executing this later portion which does not need to be executed at this higher priority can block the execution of ISRs which do not have a higher priority than the earlier portion of the ISR but do have a higher priority than what the later portion of the ISR needs. These scheduling inefficiencies reduce the processor’s ability to meet its deadlines. One option is for the ISR to complete the earlier higher priority portion, but then schedule through the RTOS a task to execute the later lower priority portion. However, some RTOSs can require a large amount of time for an ISR to schedule a task. Therefore, a second option is for the ISR, after completing the higher priority portion, to set a SETn bit in INTC software set/clear interrupt registers (INTC_SSCIR0–INTC_SSCIR7). Writing a 1 to SETn causes a software settable interrupt request. This software settable interrupt request, which usually has a lower PRIn value in the INTC_PSRn, does not cause scheduling inefficiencies. 10.5.7.2 Scheduling an ISR on Another Processor Since the SETn bits in the INTC_SSCIRn are memory mapped, processors in multiple processor systems can schedule ISRs on the other processors. One application is that one processor simply wants to command another processor to perform a piece of work, and the initiating processor does not need to use the results of that work. If the initiating processor is concerned that processor executing the software settable ISR has not completed the work before asking it to again execute that ISR, it can check if the corresponding CLRn bit in INTC_SSCIRn is asserted before again writing a 1 to the SETn bit. Another application is the sharing of a block of data. For example, a first processor has completed accessing a block of data and wants a second processor to then access it. Furthermore, after the second processor has completed accessing the block of data, the first processor again wants to access it. The accesses to the block of data must be done coherently. The procedure is that the first processor writes a 1 to a SETn bit on the second processor. The second processor, after accessing the block of data, clears the corresponding CLRn bit and then writes 1 to a SETn bit on the first processor, informing it that it now can access the block of data. 10.5.8 Lowering Priority Within an ISR In implementations without the software-settable interrupt requests in the INTC software set/clear interrupt registers (INTC_SSCIR0–INTC_SSCIR7), the only way—besides scheduling a task through an RTOS—to prevent scheduling inefficiencies with an ISR whose work spans multiple priorities (as described in Section 10.5.7.1, “Scheduling a Lower Priority Portion of an ISR,”) is to lower the current priority. However, the INTC has a LIFO whose depth is determined by the number of priorities. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 10-31 NOTE Lowering the PRI value in INTC current priority register (INTC_CPR) within an ISR to less than the ISR corresponding PRI value in INTC priority select registers (INTC_PSR0–INTC_PSR203) allows more preemptions than the depth of the LIFO can support. Therefore, the INTC does not support lowering the current priority within an ISR as a way to avoid scheduling inefficiencies. 10.5.9 10.5.9.1 Negating an Interrupt Request Outside of its ISR Negating an Interrupt Request as a Side Effect of an ISR Some peripherals have flag bits which can be cleared as a side effect of servicing a peripheral interrupt request. For example, reading a specific register can clear the flag bits, and consequently their corresponding interrupt requests too. This clearing as a side effect of servicing a peripheral interrupt request can cause the negation of other peripheral interrupt requests besides the peripheral interrupt request whose ISR presently is executing. This negating of a peripheral interrupt request outside of its ISR can be a desired effect. 10.5.9.2 Negating Multiple Interrupt Requests in One ISR An ISR can clear other flag bits besides its own flag bit. One reason that an ISR clears multiple flag bits is because it serviced those other flag bits, and therefore the ISRs for these other flag bits do not need to be executed. 10.5.9.3 Proper Setting of Interrupt Request Priority Whether an interrupt request negates outside of its own ISR due to the side effect of an ISR execution or the intentional clearing a flag bit, the priorities of the peripheral or software settable interrupt requests for these other flag bits must be selected correctly. Their PRIn values in INTC priority select registers (INTC_PSR0–INTC_PSR203) must be selected to be at or lower than the priority of the ISR that cleared their flag bits. Otherwise, those flag bits still can cause the interrupt request to the processor to assert. Furthermore, the clearing of these other flag bits also has the same timing relationship to the writing to INTC end-of-interrupt register (INTC_EOIR) as the clearing of the flag bit that caused the present ISR to be executed. See Section 10.4.3.1.2, “End-of-Interrupt Exception Handler,” for more information. A flag bit whose enable bit or mask bit is negating its peripheral interrupt request can be cleared at any time, regardless of the peripheral interrupt request’s PRIn value in INTC_PSRn. MPC5533 Microcontroller Reference Manual, Rev. 0 10-32 Freescale Semiconductor 10.5.10 Examining LIFO Contents Normally you do not need to know the contents of the LIFO, or even how deep the LIFO is nested. Although the LIFO contents are not memory mapped, you can read the contents by popping the LIFO and reading the PRI field in the INTC current priority register (INTC_CPR). Disabling processor recognition of interrupts while examining the LIFO contents provides a coherent view of the preempted priorities. The code sequence is: pop_lifo: store to INTC_EOIR load INTC_CPR, examine PRI, and store onto stack if PRI is not zero or value when interrupts were enabled, branch to pop_lifo When you are finished examining the LIFO contents, you can restore it in software vector mode using the following code sequence. In hardware vector mode, reading the INTC_IACKR does not push the INTC_CPR[PRI] onto the LIFO, therefore the LIFO contents cannot be restored in hardware vector mode. push_lifo: load stacked PRI value and store to INTC_CPR load INTC_IACKR if stacked PRI values are not depleted, branch to push_lifo NOTE Reading the INTC_IACKR acknowledges the interrupt request to the processor and updates the INTC_CPR[PRI] with the priority of the preempting interrupt request. If the processor recognition of interrupts is disabled during the LIFO restoration, interrupt requests to the processor can go undetected. However, since the peripheral or software settable interrupt requests are not cleared, the peripheral interrupt request to the processor re-asserts when INTC_CPR[PRI] is lower than the priorities of those peripheral or software settable interrupt requests. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 10-33 MPC5533 Microcontroller Reference Manual, Rev. 0 10-34 Freescale Semiconductor Chapter 11 Frequency Modulated Phase Locked Loop and System Clocks (FMPLL) 11.1 Introduction This section describes the features and function of the FMPLL module. 11.1.1 Block Diagrams This section contains block diagrams that illustrate the FMPLL, the clock architecture, and the various FMPLL and clock configurations that are available. The following diagrams are provided: • Figure 11-1, “FMPLL and Clock Architecture” • Figure 11-2, “FMPLL Bypass Mode” • Figure 11-3, “FMPLL External Reference Mode” • Figure 11-4, “FMPLL Crystal Reference Mode Without FM” • Figure 11-5, “FMPLL Crystal Reference Mode With FM” • Figure 11-6, “FMPLL Dual-Controller (1:1) Mode” MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 11-1 11.1.1.1 FMPLL and Clock Architecture PLL MFD 1 PFD/ charge pumps 0 EXTAL_EXTCLK OSC XTAL Filter PREDIV Successive approximation frequency PLLSEL PLLREF Control/status registers PLLCFG[0:1] Current controlled oscillator (ICO) 0 System clock 1 RFD FM control MODE Bus interface SIU Oscillator clock 1 CLKOUT divider CLKOUT1 0 ENGCLK divider ENGCLK NPC MCKO_EN MCKO_GT MCKO divider MCKO DSPI MDIS NOTE: The clock mode selection and associated package pin settings and FMPLL_SYNSR settings are displayed in Table 11-1. 1 EBI MDIS eTPU engine The 208 package does not have a CLKOUT pin. MDIS CAN interface CLK Message buffer CLK Core, INTC, eDMA, SIU, BAM, RAMs, eQADC, flash, XBAR, PBRIDGE_A, PBRIDGE_B FlexCAN MDIS CLK_SRC eSCI MDIS Figure 11-1. FMPLL Block and Clock Architecture MPC5533 Microcontroller Reference Manual, Rev. 0 11-2 Freescale Semiconductor 11.1.1.2 FMPLL Bypass Mode PLL MFD 1 PFD/ charge pumps 0 EXTAL_EXTCLK OSC XTAL Filter PREDIV Successive approximation frequency PLLSEL PLLREF Control/status registers PLLCFG[0:1] Current controlled oscillator (ICO) 0 RFD System clock 1 FM control MODE Bus interface SIU Oscillator clock 1 CLKOUT divider CLKOUT1 0 ENGCLK divider ENGCLK NPC MCKO_EN MCKO_GT MCKO divider MCKO DSPI MDIS NOTE: The clock mode selection and associated package pin settings and FMPLL_SYNSR settings are displayed in Table 11-1. 1 EBI MDIS eTPU engine The 208 package does not have a CLKOUT pin. MDIS CAN interface CLK Message buffer CLK Core, INTC, eDMA, SIU, BAM, RAMs, eQADC, flash, XBAR, PBRIDGE_A, PBRIDGE_B FlexCAN MDIS CLK_SRC eSCI MDIS Figure 11-2. FMPLL Bypass Mode MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 11-3 11.1.1.3 FMPLL External Reference Mode PLL MFD 1 PFD/ charge pumps 0 EXTAL_EXTCLK OSC XTAL Filter PREDIV Successive approximation frequency PLLSEL PLLREF Control/status registers PLLCFG[0:1] Current controlled oscillator (ICO) 0 System clock 1 RFD FM control MODE Bus interface SIU Oscillator clock 1 CLKOUT divider CLKOUT1 0 ENGCLK divider ENGCLK NPC MCKO_EN MCKO_GT MCKO divider MCKO DSPI MDIS NOTE: The clock mode selection and associated package pin settings and FMPLL_SYNSR settings are displayed in Table 11-1. 1 EBI MDIS eTPU engine The 208 package does not have a CLKOUT pin. MDIS CAN interface CLK Message buffer CLK Core, INTC, eDMA, SIU, BAM, RAMs, eQADC, flash, XBAR, PBRIDGE_A, PBRIDGE_B FlexCAN MDIS CLK_SRC eSCI MDIS Figure 11-3. FMPLL External Reference Mode MPC5533 Microcontroller Reference Manual, Rev. 0 11-4 Freescale Semiconductor 11.1.1.4 FMPLL Crystal Reference Mode Without FM PLL MFD 1 PFD/ charge pumps 0 EXTAL_EXTCLK OSC XTAL Filter PREDIV Successive approximation frequency PLLSEL PLLREF Control/status registers PLLCFG[0:1] 0 Current controlled oscillator (ICO) RFD (Not enabled) System clock 1 FM control MODE Bus interface SIU Oscillator clock 1 CLKOUT divider CLKOUT1 0 ENGCLK divider ENGCLK NPC MCKO_EN MCKO_GT MCKO divider MCKO DSPI MDIS NOTE: The clock mode selection and associated package pin settings and FMPLL_SYNSR settings are displayed in Table 11-1. 1 EBI MDIS eTPU engine The 208 package does not have a CLKOUT pin. MDIS CAN interface CLK FlexCAN MDIS Message buffer CLK Core, INTC, eDMA, SIU, BAM, RAMs, eQADC, flash, XBAR, PBRIDGE_A, PBRIDGE_B CLK_SRC eSCI MDIS Figure 11-4. FMPLL Crystal Reference Mode without FM MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 11-5 11.1.1.5 FMPLL Crystal Reference Mode With FM PLL MFD 1 PFD/ charge pumps 0 EXTAL_EXTCLK OSC XTAL Filter PREDIV Successive approximation frequency PLLSEL PLLREF Control/status registers PLLCFG[0:1] 0 Current controlled oscillator (ICO) 1 RFD (Enabled) System clock FM control MODE Bus interface SIU Oscillator clock 1 CLKOUT divider CLKOUT1 0 ENGCLK divider ENGCLK NPC MCKO_EN MCKO_GT MCKO divider MCKO DSPI MDIS NOTE: The clock mode selection and associated package pin settings and FMPLL_SYNSR settings are displayed in Table 11-1. 1 EBI MDIS eTPU engine The 208 package does not have a CLKOUT pin. MDIS CAN interface CLK Message buffer CLK Core, INTC, eDMA, SIU, BAM, RAMs, eQADC, flash, XBAR, PBRIDGE_A, PBRIDGE_B FlexCAN MDIS CLK_SRC eSCI MDIS Figure 11-5. FMPLL Crystal Reference Mode with FM MPC5533 Microcontroller Reference Manual, Rev. 0 11-6 Freescale Semiconductor 11.1.1.6 FMPLL Dual-Controller Mode (1:1) PLL MFD 1 PFD/ charge pumps 0 EXTAL_EXTCLK OSC XTAL Filter PREDIV Successive approximation frequency PLLSEL PLLREF Control/status registers PLLCFG[0:1] Current controlled oscillator (ICO) 0 RFD System clock 1 FM control MODE Bus interface SIU Oscillator clock 1 CLKOUT divider CLKOUT1 0 ENGCLK divider ENGCLK NPC MCKO_EN MCKO_GT MCKO divider MCKO DSPI MDIS NOTE: The clock mode selection and associated package pin settings and FMPLL_SYNSR settings are displayed in Table 11-1. 1 EBI MDIS eTPU engine The 208 package does not have a CLKOUT pin. MDIS CAN interface CLK Message buffer CLK Core, INTC, eDMA, SIU, BAM, RAMs, eQADC, flash, XBAR, PBRIDGE_A, PBRIDGE_B FlexCAN MDIS CLK_SRC eSCI MDIS Figure 11-6. FMPLL Dual Controller (1:1) Mode MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 11-7 11.1.2 Overview The frequency modulated phase locked loop (FMPLL) allows you to generate high-speed system clocks from an 8–20 MHz crystal oscillator, or from an external clock generator. Further, the FMPLL supports programmable frequency modulation of the system clock. The FMPLL multiplication factor, reference clock pre-divider factor, output clock divider ratio, modulation depth, and modulation rate are all controllable through a bus interface. 11.1.3 Features The FMPLL has the following major features: • Input clock frequency from 8–20 MHz • Current controlled oscillator (ICO) range from 48 MHz to maximum device frequency • Reference frequency pre-divider (PREDIV) for finer frequency synthesis resolution • Reduced frequency divider (RFD) for reduced frequency operation without forcing the FMPLL to re-lock • Four modes of operation: — Bypass mode. — Crystal reference mode. This is the default mode for the 324 package. See Section 11.1.4.1, “Crystal Reference.” — External reference mode. See Section 11.1.4.2, “External Reference Mode.” — PLL dual-controller (1:1) mode for EXTAL_EXTCLK to CLKOUT skew minimization. • Programmable frequency modulation — Modulation enabled/disabled via bus interface — Triangle wave modulation — Register programmable modulation depth (±1% to ±2% deviation from center frequency) — Register programmable modulation frequency dependent on reference frequency; limited to 100–250 MHz. • Lock detect circuitry reports when the FMPLL has achieved frequency lock and continuously monitors lock status to report loss of lock conditions — User-selectable ability to generate an interrupt request upon loss of lock. See Chapter 10, “Interrupt Controller (INTC),” for details. — User-selectable ability to generate a system reset upon loss of lock. See Chapter 4, “Reset,” for details. • Loss-of-clock (LOC) detection for reference and feedback clocks — User-selectable ability to generate an interrupt request upon loss of clock. See Chapter 10, “Interrupt Controller (INTC),” for details. — User-selectable ability to generate a system reset upon loss of clock See Chapter 4, “Reset,” for details. • Self-clocked mode (SCM) operation in event of input clock failure MPC5533 Microcontroller Reference Manual, Rev. 0 11-8 Freescale Semiconductor 11.1.4 FMPLL Modes of Operation The FMPLL operational mode is configured during reset. Table 11-2 shows clock mode selection during reset configuration. Additional information on reset configuration options for the FMPLL are in Chapter 4, “Reset.” Table 11-1. Clock Mode Selection Synthesizer Status Register (FMPLL_SYNSR)1 Bits Package Pins Clock Mode RSTCFG2 PLLCFG[0] PLLCFG[1] MODE PLLSEL PLLREF 1 1 1 Crystal reference (324 package only) 1 0 1 0 External reference 0 0 1 1 1 0 Bypass 0 0 0 0 0 0 Dual-controller 0 1 1 1 0 0 1 2 11.1.4.1 PLLCFG pins ignored. See Section 11.3.1.2, “Synthesizer Status Register (FMPLL_SYNSR)” for more information. Because the 208 package has no RSTCFG pin, the signal is internally asserted (driven to 0), therefore the PLLCFG pins are always used to configure the FMPLL. After the device resets, the PLLCFG values remain the same as before the reset. The device does not reset to the crystal reference mode. Bypass mode is not enabled in the 208 package. Crystal Reference In crystal reference mode, the FMPLL receives an input clock frequency (Fref_crystal) from the crystal oscillator circuit (EXTAL_EXTCLK) and the pre-divider, and multiplies the frequency to create the FMPLL output clock. You must supply a crystal oscillator that is within the device input frequency range, the crystal manufacturer’s recommended external support circuitry, and a short signal route from the MCU to the crystal. The external support circuitry for the crystal oscillator is shown in Figure 11-7. Example component values are shown as well. Review the actual circuit with the crystal manufacturer. A block diagram illustrating crystal reference mode is shown in Figure 11-4. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 11-9 Crystal C1 C2 VSSSYN EXTAL XTAL VSSSYN RF1 On chip Oscillator 1 For an 8–20 MHz crystal, the resistor must be zero ohms. Figure 11-7. Crystal Oscillator Network In crystal reference mode, the FMPLL can generate a frequency modulated clock or a non-modulated clock (locked on a single frequency). The modulation rate, modulation depth, output clock divide ratio (RFD), and whether the FMPLL is modulating or not can be programmed by writing to the FMPLL registers. Crystal reference is the default clock mode for the 324 pin package. It is not necessary to force PLLCFG[0:1] to enter this mode. In the 208 package size, because it has no RSTCFG pin, the crystal reference mode can only be selected through the PLLCFG pins. MPC5533 Microcontroller Reference Manual, Rev. 0 11-10 Freescale Semiconductor 11.1.4.2 External Reference Mode The external reference mode functions the same as crystal reference mode except that EXTAL_EXTCLK is driven by an external clock generator rather than a crystal oscillator. The input frequency range (Fref_ext) in external reference mode is the same as the input frequency reference range (Fref-crystal) in the crystal reference mode, and frequency modulation is also available. To enter external reference mode, follow the procedure outlined in Section 11.1.4, “FMPLL Modes of Operation.” A block diagram illustrating external reference mode is shown in Figure 11-3. NOTE In addition to supplying power for the CLKOUT signal, when the FMPLL is configured for external reference mode of operation, the VDDE5 supply voltage also controls the voltage level at which the signal presented to the EXTAL_EXTCLK pin causes a switch in the clock logic levels. The EXTAL_EXTCLK accepts a clock source with a voltage range of 1.6–3.6 V, however the transition voltage is determined by VDDE5 supply voltage divided by two. As an example, if VDDE5 is 3.3 V, then the clock transitions at approximately 1.6 V. The VDDE5 supply voltage and the voltage level of the external clock reference must be compatible, or the device does not clock correctly. 11.1.4.3 Bypass Mode In FMPLL bypass mode, the FMPLL is completely bypassed and you must supply an external clock on the EXTAL_EXTCLK pin. The external clock is used directly to produce the internal system clocks. In bypass mode, the analog portion of the FMPLL is disabled and no clocks are generated at the FMPLL output. Consequently, frequency modulation is not available. In bypass mode the pre-divider is bypassed and has no effect on the system clock. The frequency in bypass mode is Fref_ext. To enter bypass mode, follow the procedure outlined in Section 11.1.4, “FMPLL Modes of Operation.” A block diagram illustrating bypass mode is shown in Figure 11-2. 11.1.4.4 Dual-Controller Mode (1:1) FMPLL dual-controller mode is used by the slave MCU device of a dual-controller system. The slave FMPLL facilitates skew reduction between the input and output clock signals. To enter dual-controller mode, follow the procedure outlined in Section 11.1.4, “FMPLL Modes of Operation.” In this mode, the system clock runs at twice the frequency of the EXTAL_EXTCLK input pin and is phase aligned. Crystal operation is not supported in dual-controller mode and an external clock must be provided. In this mode, the frequency and phase of the signal at the EXTAL_EXTCLK pin and the CLKOUT pin of the slave MCU are matched. A block diagram illustrating dual-controller mode (1:1) is shown in Figure 11-6. Frequency modulation is not available when configured for dual-controller mode for both the master and slave devices. Enabling frequency modulation on the device supplying the reference clock to the slave in dual-controller mode produces unreliable clocks on the slave. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 11-11 NOTE When using dual-controller mode, do not change the CLKOUT clock divider on the slave device from its reset state of divide-by-two. Increasing or decreasing this divide ratio can produce unpredictable results from the FMPLL. 11.2 External Signal Description Table 11-2 lists external signals used by the FMPLL during normal operation. Table 11-2. PLL External Pin Interface Name I/O Type Function Pull RSTCFG_GPIO[210]1 I/O Determines the configuration to use during reset. GPIO used otherwise. Up PLLCFG[0]_GPIO[208] I/O Configures the mode during reset. GPIO used otherwise. Up PLLCFG[1]_GPIO[209] I/O Configures the mode during reset. GPIO used otherwise. Up Output drive for external crystal — XTAL Output EXTAL_EXTCLK Input Crystal external clock input — VDDSYN Power Analog power supply (3.3 V ±10%) — VSSSYN Ground Analog ground — 1 The 208 package does not have a RSTCFG pin, therefore the signal is internally asserted (driven to 0). 11.3 Memory Map/Register Definition Table 11-3 shows the FMPLL memory map locations. Table 11-3. FMPLL Module Memory Map Address Register Name Register Description Bits Base (0xC3F8_0000) FMPLL_SYNCR Synthesizer control register 32 Base + 0x0004 FMPLL_SYNSR Synthesizer status register 32 — Reserved — (Base + 0x0008)–0xC3F8_3FFF 11.3.1 Register Descriptions The clock operation is controlled by the synthesizer control register (FMPLL_SYNCR) and status is reported in the synthesizer status register (FMPLL_SYNSR). The following sections describe these registers in detail. 11.3.1.1 Synthesizer Control Register (FMPLL_SYNCR) The synthesizer control register (FMPLL_SYNCR) contains bits for defining the clock operation for the system. MPC5533 Microcontroller Reference Manual, Rev. 0 11-12 Freescale Semiconductor NOTE To ensure proper operation for all MPC5500s, execute an mbar or msync instruction between: the write to change the FMPLL_SYNCR[MFD], and the read to check the lock status shown by FMPLL_SYNSR[LOCK]. Buffered writes to the FMPLL, as controlled by PBRIDGE_A_OPACR[BW0], must be disabled. Address: Base + 0x0000 0 R 1 0 0 16 R DIS CLK W Reset 0 2 3 4 5 PREDIV W Reset Access: User R/W 0 17 LOL IRQ 7 8 9 10 11 0 MFD 12 RFD 13 14 15 LOC EN LOL RE LOC RE 0 0 0 0 0 1 0 0 0 1 0 0 0 0 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 0 0 0 0 LOC RATE IRQ 0 6 0 0 DEPTH 0 0 EXP 0 0 0 0 0 Figure 11-8. Synthesizer Control Register (FMPLL_SYNCR) Table 11-4. FMPLL_SYNCR Field Descriptions Field 0 1–3 PREDIV [0:2] Description Reserved The PREDIV bits control the value of the divider on the input clock. The output of the pre-divider circuit generates the reference clock (Fprediv) to the FMPLL analog loop. When the PREDIV bits are changed, the FMPLL immediately loses lock. To prevent an immediate reset, the LOLRE bit must be cleared before writing the PREDIV bits. In 1:1 (dual-controller) mode, the PREDIV bits are ignored and the input clock is fed directly to the analog loop. 000 Divide by 1 001 Divide by 2 010 Divide by 3 011 Divide by 4 100 Divide by 5 101–111 Invalid values Note: Programming a PREDIV value such that the ICO operates outside its specified range causes unpredictable results and the FMPLL does not lock. See the device Data Sheet for details on the ICO range. Note: To avoid unintentional interrupt requests, disable LOLIRQ before changing PREDIV and then reenable it after acquiring lock. Note: When using crystal reference mode or external reference mode, The PREDIV value must not be set to any value that causes the phase/frequency detector to go below 4 MHz. That is, the crystal (Fref_crystal) or external clock (Fref_ext) frequency divided by the PREDIV value creates the Fprediv frequency that must be greater than or equal to 4 MHz. See the device Data Sheet for Fprediv values. Note: To use the 8–20 MHz OSC, the PLL predivider must be configured for divide-by-two operation by tying PLLCFG[2] low (set PREDIV to 0b000). MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 11-13 Table 11-4. FMPLL_SYNCR Field Descriptions (Continued) Field Description 4–8 MFD [0:4] Multiplication factor divider. The MFD bits control the value of the divider in the FMPLL feedback loop. The value specified by the MFD bits establish the multiplication factor applied to the reference frequency. The decimal equivalent of the MFD binary number is substituted into the equation from Table 11-9 for Fsys to determine the equivalent multiplication factor. When the MFD bits are changed, the FMPLL loses lock. At this point, if modulation is enabled, the calibration sequence is reinitialized. To prevent an immediate reset, the LOLRE bit must be cleared before writing the MFD bits. In dual-controller mode, the MFD bits are ignored and the multiplication factor is equivalent to 2X. In bypass mode the MFD bits have no effect. Note: Programming an MFD value such that the ICO operates outside its specified range causes unpredictable results and the FMPLL does not lock. See the device Data Sheet for details on the ICO range. Note: To avoid unintentional interrupt requests, disable LOLIRQ before changing MFD and then reenable it after acquiring lock. 9 10–12 RFD [0:2] Reserved Reduced frequency divider. The RFD bits control a divider at the output of the FMPLL. The value specified by the RFD bits establish the divisor applied to the FMPLL frequency. RFD[0:2] Output Clock Divide Ratio 000 Divide by 1 001 Divide by 2 010 Divide by 4 011 Divide by 8 100 Divide by 16 101 Divide by 32 110 Divide by 64 111 Divide by 128 Changing the RFD bits does not affect the FMPLL; hence, no re-lock delay is incurred. Resulting changes in clock frequency are synchronized to the next falling edge of the current system clock. However these bits must only be written when the lock bit (LOCK) is set, to avoid exceeding the allowable system operating frequency. In bypass mode, the RFD bits have no effect. 13 LOCEN Loss-of-clock enable. The LOCEN bit determines whether the loss of clock function is operational. See Section 11.4.2.6, “Loss-of-Clock Detection” and Section 11.4.2.6.1, “Alternate and Backup Clock Selection” for more information. In bypass mode, this bit has no effect. LOCEN does not affect the loss of lock circuitry. 0 Loss of clock disabled. 1 Loss of clock enabled. MPC5533 Microcontroller Reference Manual, Rev. 0 11-14 Freescale Semiconductor Table 11-4. FMPLL_SYNCR Field Descriptions (Continued) Field Description 14 LOLRE Loss-of-lock reset enable. The LOLRE bit determines how the system integration module (the SIU) handles a loss of lock indication. When operating in crystal reference, external reference, or dual-controller mode, the FMPLL must be locked before setting the LOLRE bit. Otherwise reset is immediately asserted. The LOLRE bit has no effect in bypass mode. 0 Ignore loss of lock, reset not asserted. 1 Assert reset on loss of lock. Reset remains asserted, regardless of the source of reset, until after the FMPLL has locked. 15 LOCRE Loss-of-clock reset enable. The LOCRE bit determines how the system integration module (the SIU) handles a loss of clock condition when LOCEN = 1. LOCRE has no effect when LOCEN = 0. If the LOCF bit in the SYNSR indicates a loss of clock condition, setting the LOCRE bit causes an immediate reset. In bypass mode LOCRE has no effect. 0 Ignore loss of clock, reset not asserted. 1 Assert reset on loss of clock. 16 DISCLK Disable CLKOUT. The DISCLK bit determines whether CLKOUT is active. When CLKOUT is disabled it is driven low. 0 CLKOUT driven normally 1 CLKOUT driven low 17 LOLIRQ Loss-of-lock interrupt request. The LOLIRQ bit enables an interrupt request for LOLF when it (LOLIRQ) is asserted and when LOLF is asserted. If either LOLF or LOLIRQ is negated, the interrupt request is negated. When operating in crystal reference, external reference, or dual-controller mode, the FMPLL must be locked before setting the LOLIRQ bit. Otherwise an interrupt is immediately requested. The LOLIRQ bit has no effect in bypass mode. 0 Ignore loss of lock, interrupt not requested 1 Request interrupt 18 LOCIRQ Loss-of-clock interrupt request. The LOCIRQ bit determines how the system integration module (the SIU) handles a loss of clock condition when LOCEN = 1. LOCIRQ has no effect when LOCEN = 0. If the LOCF bit in the SYNSR indicates a loss of clock condition, setting (or having previously set) the LOCIRQ bit causes an interrupt request. In bypass mode LOCIRQ has no effect. 0 Ignore loss of clock, interrupt not requested 1 Request interrupt on loss of clock. 19 RATE Modulation rate. Controls the rate of frequency modulation applied to the system frequency. The allowable modulation rates are shown below. Changing the rate by writing to the RATE bit initiates the FM calibration sequence. RATE Modulation Rate (Hz) Fmod = Fref_crystal ÷ [(PREDIV +1) × 80] 0 Fmod = Fref_ext ÷ [(PREDIV +1) × 80] Fmod = Fref_crystal ÷ [(PREDIV +1) × 40] 1 Fmod = Fref_ext ÷ [(PREDIV +1) × 40] Note: To prevent unintentional interrupt requests, clear LOLIRQ before changing RATE. Note: Fmod must be between 100–250 MHz. See Section 11.4.2.3, “Programmable Frequency Modulation.” MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 11-15 Table 11-4. FMPLL_SYNCR Field Descriptions (Continued) Field Description 20–21 DEPTH [0:1] Controls the frequency modulation depth and enables the frequency modulation. When programmed to a value other than 0x0000, the frequency modulation is automatically enabled. The programmable frequency deviations from the system frequency are shown below. If the depth is changed to a value other than 0x0000, the calibration sequence is reinitialized. DEPTH[1] DEPTH[0] Modulation Depth (% of Fsys) 0 0 0 0 1 1.0 ± 0.2 1 0 2.0 ± 0.2 1 1 Invalid value Note: To prevent unintentional interrupt requests, clear LOLIRQ before changing DEPTH. 22–31 EXP [0:9] Expected difference value. Holds the expected value of the difference of the reference and the feedback counters. See Section 11.4.3.3, “FM Calibration Routine” to determine the value of these bits. This field is written by the application before entering calibration mode. 11.3.1.2 Synthesizer Status Register (FMPLL_SYNSR) The synthesizer status register (FMPLL_SYNSR) is a 32-bit register. Only the LOLF and LOCF flag bits are writable in this register. Writes to bits other than the LOLF and LOCF have no effect. Address: Base + 0x0004 R Access: User R/W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 W Reset R 0 0 0 0 0 0 W PLL LOLF LOC MODE SEL PLL CALD CAL LOCKS LOCK LOCF REF ONE PASS w1c Reset 0 0 0 0 0 0 0 w1c 0 1 — — 1 1 — 1 — 2 — 0 0 0 1 Reset state determined during reset configuration. (See Section 11.1.4, “FMPLL Modes of Operation,” for more information.) 2 Reset state determined during reset. Note: “w1c” signifies that this bit is cleared by writing a 1 to it. Figure 11-9. Synthesizer Status Register (FMPLL_SYNSR) MPC5533 Microcontroller Reference Manual, Rev. 0 11-16 Freescale Semiconductor Table 11-5. FMPLL_SYNSR Field Descriptions Field Description 0–21 Reserved 22 LOLF Loss-of-lock flag. Provides the interrupt request flag. This is a write 1 to clear (w1c) bit; to clear the flag, you must write a 1 to the bit. Writing 0 has no effect. This flag is not set and an interrupt is not requested, if the loss-of-lock condition was caused by: • a system reset • a write to the FMPLL_SYNCR which modifies the MFD bits • enabling frequency modulation If the flag is set due to a system failure, writing the MFD bits or enabling FM does not clear the flag. Asserting reset clears the flag. This flag bit is sticky; if lock is reacquired, the bit remains set until either a write of 1 or reset is asserted. 0 Interrupt service not requested 1 Interrupt service requested Note: Upon a loss-of-lock that is not generated by: •System reset •Write to the FMPLL_SYNCR that modifies the MFD or PREDIV bits •Enabling of frequency modulation the LOLF is set only if LOLIRQ is set. If the FMPLL reacquires lock and any of the previous conditions in the bulleted list occurs, the LOLF is set again. To avoid generating an unintentional interrupt, clear LOLIRQ before changing MFD or PREDIV, or before enabling FM after a previous interrupt and relock occurred. 23 LOC Loss-of-clock status. Indicates whether a loss-of-clock condition is present when operating in crystal reference, external reference, or dual-controller mode, If LOC = 0, the system clocks are operating normally. If LOC = 1, the system clocks have failed due to a reference failure or a FMPLL failure. If the read of the LOC bit and the loss-of-clock condition occur simultaneously, the bit does not reflect the current loss of clock condition. If a loss-of-clock condition occurs which sets this bit and the clocks later return to normal, this bit is cleared. A loss of clock condition can only be detected if LOCEN = 1. LOC is always 0 in bypass mode. 0 Clocks are operating normally 1 Clocks are not operating normally. 24 MODE Clock mode. This bit is read only and the value is determined at reset. The value of this bit combined with the values of the PLLSEL and PLLREF bits, set the system clocking mode used. See Chapter 4, “Reset,” for details on how to configure the system clock mode during reset. 0 PLL bypass mode used. 1 PLL clock mode used. 25 PLLSEL PLL mode select. This bit is read only and the value is determined at reset. The value of this bit combined with the values of the MODE and PLLREF bits, indicates the system clocking mode used. This bit indicates the FMPLL operating mode used: dual controller or reference mode. This bit is cleared in dual-controller and bypass mode. See Chapter 4, “Reset,” for details on how to configure the system clock mode during reset. See Table 11-2 for more information. 0 Dual-controller mode used. 1 Crystal reference or external reference mode used. 26 PLLREF PLL clock reference source. This bit is read only and the value is determined at reset. The value of this bit combined with the values of the MODE and PLLSEL bits, indicates the system clocking mode used. This bit determines whether an external clock or a crystal reference is used as a the PLL reference source. This bit is cleared in dual controller mode and bypass mode. See Chapter 4, “Reset,” for details on how to configure the system clock mode during reset. 0 External clock reference used. 1 Crystal clock reference used. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 11-17 Table 11-5. FMPLL_SYNSR Field Descriptions (Continued) Field Description 27 LOCKS Sticky FMPLL lock status bit. This bit is a read-only sticky bit that indicates the FMPLL lock status. LOCKS is set by the lock detect circuitry when the FMPLL acquires lock after one of the following: • System reset • Write to the FMPLL_SYNCR that modifies the MFD and PREDIV bits • Enable frequency modulation Whenever the FMPLL loses lock, LOCKS is cleared. LOCKS remains cleared even after the FMPLL relocks, until one of the three previously-stated conditions occurs. Furthermore, if the LOCKS bit is read when the FMPLL simultaneously loses lock, the bit does not reflect the current loss of lock condition. If operating in bypass mode, LOCKS remains cleared after reset. In crystal reference, external reference, and dual-controller mode, LOCKS is set after reset. 0 PLL has lost lock since last system reset, a write to FMPLL_SYNCR to modify the MFD and PREDIV bit fields, or frequency modulation enabled. 1 PLL has not lost lock since last system reset, a write to FMPLL_SYNCR to modify the MFD and PREDIV bit fields, or frequency modulation enabled. 28 LOCK PLL lock status bit. This bit is a read-only bit that indicates whether the FMPLL has acquired lock. If the LOCK bit is read when the FMPLL simultaneously loses lock or acquires lock, the bit does not reflect the current condition of the FMPLL. If operating in bypass mode, LOCK remains cleared after reset. See the frequency as defined in the MPC5533 Microcontroller Data Sheet for the lock/unlock range. 0 PLL is unlocked. 1 PLL is locked. 29 LOCF Loss-of-clock flag. This bit provides the interrupt request flag. This is a write 1 to clear (w1c) bit; to clear the flag, you must write a 1 to the bit. Writing 0 has no effect. Asserting reset clears the flag. This flag is sticky in the sense that if clocks return to normal after the flag has been set, the bit remains set until cleared by either writing 1 or asserting reset. 0 Interrupt service not requested 1 Interrupt service requested 30 Calibration complete. Indicates whether the calibration sequence has been completed since the last time CALDONE modulation was enabled. If CALDONE = 0 then the calibration sequence is either in progress or modulation is disabled. If CALDONE = 1 then the calibration sequence has been completed, and frequency modulation is operating. 0 Calibration not complete. 1 Calibration complete. Note: FM relocking does not start until calibration is complete. 31 CALPASS Calibration passed. Indicates whether the calibration routine was successful. If CALPASS = 1 and CALDONE = 1 then the routine was successful. If CALPASS = 0 and CALDONE = 1, then the routine was unsuccessful. When the calibration routine is initiated the CALPASS is asserted. CALPASS remains asserted until either modulation is disabled by clearing the DEPTH bits in the FMPLL_SYNCR or a failure occurs within the FMPLL calibration sequence. 0 Calibration unsuccessful. 1 Calibration successful. If calibration is unsuccessful, then actual depth is not guaranteed to match the desired depth. MPC5533 Microcontroller Reference Manual, Rev. 0 11-18 Freescale Semiconductor 11.4 Functional Description This section explains clock architecture, clock operation, and clock configuration. 11.4.1 Clock Architecture This section describes the clocks and clock architecture in the MCU. The system clocks are generated from one of four FMPLL modes: crystal reference mode, external reference mode, dual-controller (1:1) mode, and bypass mode. See Section 11.1, “Introduction” for information on the different clocking modes available in the FMPLL. The MCU has three clock output pins that are driven by programmable clock dividers. The clock dividers divide the system clock down by even integer values. The three clock output pins are the following: • CLKOUT – External address/data bus clock • MCKO – Nexus auxiliary port clock • ENGCLK – Engineering clock The MCU has been designed so that the oscillator clock can be selected as the clock source for the CAN interface in the FlexCAN blocks resulting in very low jitter performance. Figure 11-1 shows a block diagram of the FMPLL and the system clock architecture. 11.4.1.1 Software Controlled Power Management/Clock Gating The peripheral IP modules are designed to let software gate the clocks to the non-memory-mapped logic of the modules. Some of the IP modules on this device support software controlled power management/clock gating whereby the application software can disable the non-memory-mapped portions of the modules by writing to module disable (MDIS) bits in registers within the modules. The memory-mapped portions of the modules are clocked by the system clock when they are being accessed. The Nexus Port Controller (NPC) can be configured to disable the MCKO signal when there are no Nexus messages pending. The flash array can be disabled by writing to a bit in the flash register map. The modules that implement software controlled power management and clock gating are listed in Table 11-6 along with the registers and bits that disable each module. The software controlled clocks are enabled when the MCU comes out of reset. Table 11-6. Software Controlled Power Management/Clock Gating Support Module Name Register Name Bit Names DSPI C DSPI_C_MCR MDIS DSPI D DSPI_D_MCR MDIS EBI EBI_MCR MDIS eTPU engine A ETPU_ECR_1 MDIS FlexCAN A CAN_A_MCR MDIS MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 11-19 Table 11-6. Software Controlled Power Management/Clock Gating Support (Continued) Module Name Bit Names FlexCAN C CAN_C_MCR MDIS eSCI A ESCI_A_CR2 MDIS Nexus port controller (NPC) NPC_PCR Flash array FLASH_MCR 1 2 11.4.1.2 Register Name MCKO_EN, MCKO_GT 1 STOP 2 See Chapter 23, “Nexus Development Interface.” See Chapter 13, “Flash Memory.” Clock Dividers Each of the CLKOUT, MCKO, and ENGCLK dividers provides a nominal 50% duty cycle clock to an output pin. There is no guaranteed phase relationship between CLKOUT, MCKO, and ENGCLK. ENGCLK is not synchronized to any I/O pins. 11.4.1.2.1 External Bus Clock (CLKOUT) The external bus clock (CLKOUT) divider can be programmed to divide the system clock by two or four based on the settings of the EBDF bit field in the SIU external clock control register (SIU_ECCR). The reset value of the EBDF selects a CLKOUT frequency of one half of the system clock frequency. The EBI supports gating of the CLKOUT signal when there are no external bus accesses in progress. See the Chapter 6, “System Integration Unit (SIU)” for more information on CLKOUT. The hold-time for the external bus pins can be changed by writing to the external bus tap select (EBTS) bit in the SIU_ECCR. See Chapter 6, “System Integration Unit (SIU)” for more information. 11.4.1.2.2 Nexus Message Clock (MCKO) The Nexus message clock (MCKO) divider can be programmed to divide the system clock by two, four or eight based on the MCKO_DIV bit field in the port configuration register (PCR) in the Nexus port controller (NPC). The reset value of the MCKO_DIV selects an MCKO clock frequency one half of the system clock frequency. The MCKO divider is configured by writing to the NPC through the JTAG port. See Chapter 23, “Nexus Development Interface” for more information. 11.4.1.2.3 Engineering Clock (ENGCLK) The engineering clock (ENGCLK) divider can be programmed to divide the system clock by factors from 2 to 126 in increments of two. The ENGDIV bit field in the SIU_ECCR determines the divide factor. The reset value of ENGDIV selects an ENGCLK frequency of system clock divided by 32. 11.4.1.2.4 FlexCAN_x Clock Domains The FlexCAN modules have two distinct software controlled clock domains. One of the clock domains is always derived from the system clock. This clock domain includes the message buffer logic. The source for the second clock domain can be either the system clock or a direct feed from the oscillator pin EXTAL_EXTCLK. The logic in the second clock domain controls the CAN interface pins. The CLK_SRC MPC5533 Microcontroller Reference Manual, Rev. 0 11-20 Freescale Semiconductor bit in the FlexCAN CTRL register selects between the system clock and the oscillator clock as the clock source for the second domain. Selecting the oscillator as the clock source ensures very low jitter on the CAN bus. System software can gate both clocks by writing to the MDIS bit in the FlexCAN MCR register. Figure 11-1 shows the two clock domains in the FlexCAN modules. See Chapter 20, “FlexCAN2 Controller Area Network” for more information on the FlexCAN modules. 11.4.2 11.4.2.1 Clock Operation Input Clock Frequency The FMPLL is designed to operate over an input clock frequency range as determined by the operating mode. The operating ranges for each mode are given in Table 11-7. Co Table 11-7. Input Clock Frequency Mode Crystal reference External reference Bypass Dual-controller (1:1) 11.4.2.2 Symbol Input Frequency Range Fref_crystal Fref_ext 8–20 MHz Fextal 0–132 MHz Fref_1:1 25–66 MHz Reduced Frequency Divider (RFD) The RFD can be used for reducing the FMPLL system clock frequency. To protect the system from frequency overshoot during the PLL lock detect phase, the RFD must be programmed to be greater than or equal to 1 when changing MFD or PREDIV or when enabling frequency modulation. 11.4.2.3 Programmable Frequency Modulation The FMPLL provides for frequency modulation of the system clock. The modulation is applied as a triangular waveform with modulation depth and rate controlled by fields in the FMPLL_SYNCR. The modulation depth can be set to ±1% or ±2% of the system frequency. The modulation rate is dependent on the reference clock frequency. Complete details for configuring the programmable frequency modulation is given in Section 11.4.3, “Clock Configuration.” Changing the MFD or PREDIV values causes the FMPLL to perform a search for the lock frequency that results in the system clock frequency changing rapidly across the complete frequency range. All MCU peripherals, including the external bus are subjected to this frequency sweep. Operation of timers and serial communications during this search sequence produces unpredictable results. 11.4.2.4 FMPLL Lock Detection A pair of counters monitor the reference and feedback clocks to determine when the system has acquired frequency lock. After the FMPLL has locked, the counters continue to monitor the reference and feedback clocks and reports if/when the FMPLL has lost lock. The FMPLL_SYNCR provides the flexibility to MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 11-21 select whether to generate an interrupt, assert system reset, or do nothing in the event that the FMPLL loses lock. See Section 11.3.1.1, “Synthesizer Control Register (FMPLL_SYNCR) for details. When the frequency modulation is enabled, the loss of lock continues to function as described but with the lock and loss of lock criteria reduced to ensure that false loss of lock conditions are not detected. In bypass mode, the FMPLL cannot lock since the FMPLL is disabled. 11.4.2.5 FMPLL Loss-of-Lock Conditions After the FMPLL acquires lock after reset, the FMPLL_SYNSR[LOCK] and FMPLL_SYNSR[LOCKS] status bits are set. If the MFD is changed or if an unexpected loss of lock condition occurs, the LOCK and LOCKS status bits are negated. While the FMPLL is in an unlocked condition, the system clocks continue to be sourced from the FMPLL as the FMPLL attempts to re-lock. Consequently, during the re-locking process, the system clock frequency is not well defined and can exceed the maximum system frequency thereby violating the system clock timing specifications (when changing MFD and PREDIV, this is avoided by following the procedure detailed in Section 11.4.3, “Clock Configuration”). Because this condition can arise during unexpected loss of lock events, it is recommended to use the loss of lock reset functionality, See Section 11.4.2.5.1, “FMPLL Loss-of-Lock Reset,” below. However, LOLRE must be cleared while changing the MFD otherwise a reset occurs. After the FMPLL has relocked, the LOCK bit is set. The LOCKS bit remains cleared if the loss of lock was unexpected. The LOCKS bit is set to 1 when the loss of lock was caused by changing the MFD. 11.4.2.5.1 FMPLL Loss-of-Lock Reset The FMPLL provides the ability to assert reset when a loss of lock condition occurs by programming the FMPLL_SYNCR[LOLRE] bit. Reset is asserted if LOLRE is set and loss-of-lock occurs. Because the FMPLL_SYNSR[LOCK] and FMPLL_SYNSR[LOCKS] bits are reinitialized after reset, the system reset status register (SIU_RSR) must be read to determine that a loss of lock condition occurred. To exit reset, the reference must be present and the FMPLL must acquire lock. In bypass mode, the FMPLL cannot lock. Therefore a loss of lock condition cannot occur, and LOLRE has no effect. 11.4.2.5.2 FMPLL Loss-of-Lock Interrupt Request The FMPLL provides the ability to request an interrupt when a loss of lock condition occurs by programming the FMPLL_SYNCR[LOLIRQ] bit. An interrupt is requested by the FMPLL if LOLIRQ is set and loss-of-lock occurs. In bypass mode, the FMPLL cannot lock. Therefore a loss of lock condition cannot occur, and the LOLIRQ bit has no effect. 11.4.2.6 Loss-of-Clock Detection The FMPLL continuously monitors the reference and feedback clocks. In the event either of the clocks fall below a threshold frequency, the system reports a loss of clock condition. You can enable a feature to have the FMPLL switch the system clocks to a backup clock in the event of such a failure. Additionally, you can enter a system RESET, assert an interrupt request, or do nothing if the FMPLL reports this condition. MPC5533 Microcontroller Reference Manual, Rev. 0 11-22 Freescale Semiconductor 11.4.2.6.1 Alternate and Backup Clock Selection If you enable loss-of-clock by setting FMPLL.SYNCR[LOCEN] = 1, then the FMPLL transitions system clocks to a backup clock source in the event of a clock failure as per Table 11-8. If loss of clock is enabled and the reference clock is the source of the failure, the FMPLL enters self-clock mode (SCM). The exact frequency during self-clock mode operation is indeterminate due to process, voltage, and temperature variation but is guaranteed to be below the maximum system frequency. If the FMPLL clocks have failed, the FMPLL transitions the system clock source to the reference clock. The FMPLL remains in SCM until the next reset. If the FMPLL is operated in SCM, writes to FMPLL_SYNCR[RFD] have no effect on clock frequency. The SCM system frequency stated in the device Data Sheet is calculated with RFD programmed to 0x0. If loss-of-clock is enabled, and the loss-of-clock is from a FMPLL failure (for example, loss of feedback clock), the FMPLL reference becomes the system clock’s source until the next reset, even if the FMPLL regains itself and re-locks. Table 11-8. Loss-of-Clock Summary Clock Mode Crystal Reference External Reference Bypass System Clock Source before Failure REFERENCE FAILURE Alternate Clock Selected by LOC Circuitry until Reset PLL FAILURE Alternate Clock Selected by LOC Circuitry until Reset PLL PLL self-clocked mode PLL reference External clock(s) None — A special loss of clock condition occurs when both the reference and the FMPLL fail. The failures can be simultaneous or the FMPLL can fail first. In either case, the reference clock failure takes priority and the FMPLL attempts to operate in SCM. If successful, the FMPLL remains in SCM until the next reset. During SCM, modulation is always disabled. If the FMPLL cannot operate in SCM, the system remains static until the next reset. Both the reference and the FMPLL must be functioning correctly to exit reset. 11.4.2.6.2 Loss-of-Clock Reset When a loss-of-clock condition is recognized, reset is asserted if the FMPLL_SYNCR[LOCRE] bit is set. The LOCF and LOC bits in FMPLL_SYNSR are cleared after reset, therefore, the SIU_RSR must be read to determine that a loss of clock condition occurred. LOCRE has no effect in bypass mode. To exit reset, the reference must be present and the FMPLL must acquire lock. 11.4.2.6.3 Loss-of-Clock Interrupt Request When a loss-of-clock condition is recognized, the FMPLL requests an interrupt if the FMPLL_SYNCR[LOCIRQ] bit is set. The LOCIRQ bit has no effect in bypass mode or if FMPLL_SYNCR[LOCEN] = 0. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 11-23 11.4.3 Clock Configuration In crystal reference and external reference clock mode, the default system frequency is determined by the MFD, RFD, and PREDIV reset values. See Section 11.3.1.1, “Synthesizer Control Register (FMPLL_SYNCR).” The frequency multiplier is determined by the RFD, PREDIV, and multiplication frequency divisor (MFD) bits in FMPLL_SYNCR. Table 11-9 shows the clock-out to clock-in frequency relationships for the possible clock modes. Table 11-9. Clock-out vs. Clock-in Relationships Clock Mode PLL Option Crystal Reference Mode Fsys = Fref_crystal × External Reference Mode Fsys = Fref_ext × Dual Controller (1:1) Mode (MFD + 4) [(PREDIV + 1) × 2 RFD] (MFD + 4) [(PREDIV + 1) × 2 RFD] Fsys = 2 × Fref_1:1 Bypass Mode Fsys = Fref_ext NOTES: Fsys = system frequency Fprediv = clock frequency after PREDIV. Fref_crystal and Fref_ext = clock frequencies at the EXTAL_EXTCLK signal. (See Figure 11-1). MFD ranges from 0–31. RFD ranges from 0–7. PREDIV normal reset value is 0. Caution: Programming a PREDIV value such that the ICO operates outside its specified range causes unpredictable results and the FMPLL does not lock. See the device Data Sheet for details on the ICO range. When programming the FMPLL, do not violate the maximum system clocks frequency, or maximum and minimum ICO frequency specifications. For determining the MFD value, use a value of zero for the RFD (translates to divide-by-one). This ensures that the FMPLL does not try to synthesize a frequency out of its range. See the device Data Sheet for more information. 11.4.3.1 Programming System Clock Frequency Without Frequency Modulation The following steps are required to accommodate the frequency overshoot that can occur when the PREDIV or MFD bits are changed. If frequency modulation is going to be enabled, the maximum allowable frequency must be reduced by the programmed ΔFm. NOTE Following these steps produces immediate changes in supply current, therefore make sure the power supply is decoupled with low ESR capacitors. MPC5533 Microcontroller Reference Manual, Rev. 0 11-24 Freescale Semiconductor The following steps program the clock frequency without frequency modulation: 1. Determine the value for the PREDIV, MFD, and RFD fields in the synthesizer control register (FMPLL_SYNCR). Remember to include the ΔFm if frequency modulation is enabled. The amount of jitter in the system clocks can be minimized by selecting the maximum MFD factor that can be paired with an RFD factor to provide the desired frequency. The maximum MFD value that can be used is determined by the ICO range. See the Data Sheet for the maximum frequency of the ICO. 2. Change the following in FMPLL_SYNCR: a) Make sure frequency modulation is disabled (FMPLL_SYNCR[DEPTH] = 00). A change to PREDIV, MFD, or RATE while modulation is enabled invalidates the previous calibration results. b) Clear FMPLL_SYNCR[LOLRE]. If this bit is set, the MCU goes into reset when MFD is written. c) Initialize the FMPLL for less than the desired final system frequency (done in one single write to FMPLL_SYNCR): – Disable LOLIRQ. – Write FMPLL_SYNCR[PREDIV] to a desired final value. – Write FMPLL_SYNCR[MFD] to a desired final value. – Write the RFD control field value to a desired final RFD value plus one. RFD must be set to greater than one to protect from overshoot. 3. Wait for the FMPLL to lock by monitoring the FMPLL_SYNSR[LOCK] bit. See Section 11.3.1.1, “Synthesizer Control Register (FMPLL_SYNCR),” for memory synchronization between changing FMPLL_SYNCR[MFD] and monitoring the lock status. 4. Initialize the FMPLL to the desired final system frequency by changing FMPLL_SYNCR[RFD]. The FMPLL does not need to re-lock if only the RFD changes. 5. Re-enable LOLIRQ. When using crystal reference mode or external reference mode, do not set the PREDIV value to any value that causes the phase and frequency detector to go below 4 MHz. That is, the crystal or external clock frequency divided by the PREDIV value must be in the range of 4–20 MHz. This first register write causes the FMPLL to switch to an initial system frequency which is less than the final one. Keeping the change of frequency to a lower initial value helps minimize the current surge to the external power supply caused by the change in frequency. The last step changes the RFD to get the desired final frequency. Changing the MFD or PREDIV values causes the FMPLL to perform a search for the lock frequency that results in the system clock frequency changing rapidly across the complete frequency range. All MCU peripherals, including the external bus are subjected to this frequency sweep. Operation of timers and serial communications during this search sequence produces unpredictable results. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 11-25 11.4.3.2 Programming System Clock Frequency with Frequency Modulation In crystal reference and external reference clock modes, the default mode is without frequency modulation enabled. When frequency modulation is enabled, however, three parameters must be set to generate the desired level of modulation: the RATE, DEPTH, and EXP bit fields of the FMPLL_SYNCR. RATE and DEPTH determine the modulation rate and the modulation depth. The EXP field controls the FM calibration routine. Section 11.4.3.3, “FM Calibration Routine,” shows how to obtain the values to be programmed for EXP. Figure 11-10 illustrates the effects of the parameters and the modulation waveform built into the modulation hardware. The modulation waveform is always a triangle wave and its shape is not programmable. The modulation rates given are specific to a reference frequency of 8 MHz. Fprediv is the frequency after the predivider. Fmod = Fref_crystal or Fref_ext ÷ [(PREDIV + 1) x Q] where: Q = 40 or 80. This gives modulation rates of 200 kHz and 100 kHz, respectively. NOTE The following relationship between Fmod and modulation rates must be maintained: 100 KHz ≤ Fmod ≤ 250 KHz Therefore, the use of a non 8 MHz reference results in scaled modulation rates. The steps to program the clock frequency with frequency modulation ensure the calibration routine operates correctly and prevents frequency overshoot: 1. Change the following in FMPLL_SYNCR: a) Make sure frequency modulation is disabled (FMPLL_SYNCR[DEPTH] = 00). A change to PREDIV, MFD, or RATE while modulation is enabled invalidates the previous calibration results. b) Clear FMPLL_SYNCR[LOLRE]. If this bit is set, the MCU goes into reset when MFD is written. c) Initialize the FMPLL for less than the desired final frequency: — Disable LOLIRQ. — Write FMPLL_SYNCR[PREDIV] to the desired final value. — Write FMPLL_SYNCR[MFD] to the desired final value. — Write FMPLL_SYNCR[EXP] to the desired final value. — Write FMPLL_SYNCR[RATE] to the desired final value. — Write the RFD control field to 1 plus the desired final RFD value (RFD must be greater than one to protect from overshoot). MPC5533 Microcontroller Reference Manual, Rev. 0 11-26 Freescale Semiconductor 2. Wait for the FMPLL to lock by monitoring the FMPLL_SYNSR[LOCK] bit. See Section 11.3.1.1, “Synthesizer Control Register (FMPLL_SYNCR),” for memory synchronization between changing FMPLL_SYNCR[MFD] and monitoring the lock status. 3. If using the frequency modulation feature, then: a) Enable FM by setting FMPLL_SYNCR[DEPTH] = 1 or 2. b) Also set FMPLL_SYNCR[RATE] if not done previously in step 2. 4. Calibration starts. After calibration is done, then the FMPLL re-locks. Wait for the FMPLL to re-lock by monitoring the FMPLL_SYNSR[LOCK] bit. 5. Verify FM calibration completed and was successful by testing the FMPLL_SYNSR[CALDONE] and FMPLL_SYNSR[CALPASS] bitfields. 6. If FM calibration did not complete or was not successful, attempt again by going back to step 1. 7. Initialize the FMPLL to the desired final system frequency by changing FMPLL_SYNCR[RFD]. The FMPLL does not need to re-lock when only changing the RFD. 8. Re-enable LOLIRQ. NOTE This first register write causes the FMPLL to switch to an initial frequency which is less than the final one. Keeping the change of frequency to a lower initial value helps minimize the current surge to the external power supply caused by change of frequency. The last step changes the RFD to get the final frequency. NOTE Changing the MFD or PREDIV values causes the FMPLL to perform a search for the lock frequency that results in the system clock frequency changing rapidly across the complete frequency range. All MCU peripherals, including the external bus, are subjected to this frequency sweep. Operation of timers and serial communications during this search sequence produces unpredictable results. The frequency modulation system is dependent upon several the accuracies of these factors: • VDDSYN and VSSSYN voltages • Crystal oscillator frequency • Manufacturing variation For example, if a 5% accurate supply voltage is used, then a 5% modulation depth error results. If the crystal oscillator frequency is skewed from 8 MHz, the resulting modulation frequency is proportionally skewed. Finally, the error due to the manufacturing and environment variation alone can cause the frequency modulation depth error to be greater than 20%. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 11-27 f Fmax ΔFm t ΔFm Fmin Δt = 1 Fmod Fmax = Fsys + {1%, 2%} Fmin = Fsys – {1%, 2%} Fmod = Fref_crystal or Fref_ext ÷ [(PREDIV + 1) × Q] where Q = 40 or 80 Figure 11-10. Frequency Modulation Waveform 11.4.3.3 FM Calibration Routine Upon enabling frequency modulation, a new calibration routine is performed. This routine tunes a reference current into the modulation D/A so that the modulation depth (Fmax and Fmin) remains within specification. Entering the FM calibration mode requires you to program SYNCR[EXP]. The EXP is the expected value of the difference between the reference and feedback counters used in the calibration of the FM equation: ( ( MFD + 4 ) × M × P ) EXP = -----------------------------------------------------100 For example, if 80 MHz is the desired final frequency and an 8 MHz crystal is used, the final values of MFD = 6 and RFD = 0 produces the desired 80 MHz. For a desired frequency modulation with a 1% depth, then EXP is calculated using P = 1, MFD = 6 and M = 480. See Table 11-10 for a complete list of values to be used for the variable (M) based on MFD setting. To obtain a percent modulation (P) of 1%, the EXP field must be set at: EXP = ( ( 6 + 4 ) × 480 × 1 ) ÷ 100 = 48 Rounding this value to the closest integer yields 48, which is entered into the EXP field for this example. Table 11-10. Multiplied Factor Dividers with M Values MFD M 0–2 960 3–5 640 MPC5533 Microcontroller Reference Manual, Rev. 0 11-28 Freescale Semiconductor Table 11-10. Multiplied Factor Dividers with M Values (Continued) MFD M 6–8 480 9–14 320 15–20 240 21–31 160 This routine corrects for process variations, but because temperature can change after calibration is performed, the variation caused by temperature drift remains. This frequency modulation calibration system is also voltage dependent, so if the supply changes after the sequence occurs, errors incurred are not corrected. The calibration system reuses the two counters in the lock detect circuit, and the reference and feedback counters. The reference counter remains clocked by the reference clock, but the feedback counter is clocked by the ICO clock. When the calibration routine is initiated by writing to the DEPTH bits, the CALPASS status bit is immediately set and the CALDONE status bit is immediately cleared. When calibration is induced, the ICO is given time to settle. Then both the feedback and reference counters start counting. Full ICO clock cycles are counted by the feedback counter during this time to give the initial center frequency count. When the reference counter has counted to the programmed number of reference count cycles, the input to the feedback counter is disabled and the result is placed in the COUNT0 register. The calibration system then enables modulation at programmed ΔFm. The ICO is given time to settle. Both counters are reset and restarted. The feedback counter begins to count full ICO clock cycles again to obtain the delta-frequency count. When the reference counter has counted to the new programmed number of reference count cycles, the feedback counter is stopped again. The delta-frequency count minus the center frequency count (COUNT0) results in a delta count proportional to the reference current into the modulation D/A. That delta count is subtracted from the expected value given in the EXP field of the FMPLL_SYNCR resulting in an error count. The sign of this error count determines the direction taken by the calibration D/A to update the calibration current. After obtaining the error count for the present iteration, both counters are cleared. The stored count of COUNT0 is preserved while a new feedback count is obtained, and the process to determine the error count is repeated. The calibration system repeats this process eight times, once for each bit of the calibration D/A. After the last decision is made, the CALDONE bit of the SYNSR is written to a one. If an error occurs during the calibration routine, then CALPASS is immediately written to a zero. If the routine completed successfully then CALPASS remains a one. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 11-29 Figure 11-11 shows a block diagram of the calibration circuitry and its associated registers. Figure 11-12 shows a flow chart showing the steps taken by the calibration circuit. Expected (EXP) Count 0 Error (ERR) Reference counter 13 Control ICO counter 13 10 10 13 A B 10 A – B = Delta count C 10 D C – D = Error count Figure 11-11. FM Auto-Calibration Data Flow MPC5533 Microcontroller Reference Manual, Rev. 0 11-30 Freescale Semiconductor Enter calibration mode; Set PCALPASS = 1 A Count M reference clock cycles. Store value of feedback Counter in CAL[0] N=0 ? Yes No N=N Enable FM where N = 7 -1 CAL[N] = 1 CALDONE = 1 Allow system 3 x 384 reference counts to settle DONE Count M reference clock cycles. CALX = value in feedback counter Let DIFF = CALX - CAL0 DIFF > 0 ? No For MFD = 0 to 2: M = 960 For MFD = 3 to 5: M = 640 For MFD = 6 to 8: M = 480 For MFD = 9 to 14: M = 320 For MFD = 15 to 20: M = 240 For MFD = 21 to 31: M = 160 PCALPASS = 0 Yes Let ERR = DIFF - EXP ERR > 0 ? Yes CAL[N] = 0 No A Figure 11-12. FM Auto-Calibration Flow Chart MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 11-31 MPC5533 Microcontroller Reference Manual, Rev. 0 11-32 Freescale Semiconductor Chapter 12 External Bus Interface (EBI) NOTE The 208 package does not have an external bus interface. This chapter pertains to devices in the 324 package. 12.1 Introduction This chapter describes the external bus interface (EBI) that manages the transfer of information between the internal buses and the memories or peripherals in the external address space and enables an external master to access internal address space. This device has a 16-bit data bus only—it does not have a 32-bit data bus (internally or externally). The EBI includes a memory controller that generates interface signals to support a variety of external memories. This includes single data rate (SDR) burst mode flash, external SRAM, and asynchronous memories. It supports up to four regions (via chip selects), each with its own programmed attributes. See Section 12.5.6, “Summary of Differences from MPC500,” for an overview of how the MPC5500 EBI differs from the EBI used in MPC500 devices. 12.1.1 Block Diagram Figure 12-1 is a block diagram of the EBI. The signals shown are external pins to the MCU. NOTE See Chapter 2, “Signals,” as not all signals are implemented in all device packages. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 12-1 CLKOUT Driver CLKOUT External Bus Interface Slave Interface/ System Bus Crossbar Switch (XBAR) ADDR[12:31] Memory Controller BDIP CS[0]_ADDR[8]_GPIO[0] Master Interface/ System Bus Crossbar Switch (XBAR) External Master Controller CS[1:3]_ADDR[9:11]_GPIO_[1:3] DATA[0:15] OE Bus Monitor RD_WR TA Peripheral Bridge (PBridge_A) TS Registers WE/BE[0:1] Arbiter Figure 12-1. MPC5533 EBI Block Diagram MPC5533 Microcontroller Reference Manual, Rev. 0 12-2 Freescale Semiconductor 12.1.2 Features The device is designed with the following features: • 1.8–3.3 V I/O • Address bus—32-bit internal address bus with transfer size indication — 20 bits is the default EBI size for the 324 package (ADDR[12:31]). — 24 bits available: ADDR[12:31] is the default pin set, then CS[0:3]_ADDR[8:11]_GPIO [0:3] must be configured by PCR to ADDR[8:11] to attain the 24-bit size. • Data bus—16-bit data bus for both external memory accesses and transactions involving an external master. Although the device is designed to support a 32-bit internal data bus, the 324 package only supplies 16 balls for the external (EBI) data bus (DATA[0:15]). • Support for external master accesses to internal addresses • Memory controller with support for various memory types: — Standard SRAM — Synchronous burst SDR (flash or SRAM) — Asynchronous/legacy memory (flash or SRAM) • Burst support (this device has no cache, therefore only the DMA can generate a burst transfer to the EBI—the core cannot.) • Bus monitor • Configurable wait states • Four chip select (CS[0:3]) signals in the 324 package • Two WE/BE signals (WE/BE[0:1]) • Configurable bus speed modes (½ or ¼ of system clock frequency) • Optional automatic CLKOUT gating to save power and reduce EMI • Compatible with MPC500 external bus See Section 12.4.1.12, “Compatible with MPC500 External Bus (with Some Limitations).” MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 12-3 12.1.3 Modes of Operation The mode of the EBI is determined by the MDIS and EXTM bits in the EBI_MCR. Configurable bus speed modes and debug mode are modes that the MCU can enter, in parallel to the EBI being configured in one of its module-specific modes. See Section 12.3.1.3, “EBI Module Configuration Register (EBI_MCR)” for details. 12.1.3.1 Single Master Mode In single master mode, the EBI responds to internal requests matching one of its regions, but ignores all externally-initiated bus requests. The MCU is the only master allowed to initiate transactions on the external bus in this mode; therefore, it acts as a parked master and does not have to arbitrate for the bus before starting each cycle. Single master mode is entered when EXTM = 0 and MDIS = 0 in the EBI_MCR. 12.1.3.2 External Master Mode When the MCU is in external master mode, the EBI responds to internal requests matching one of its regions, and to external master accesses to internal address space. External master mode is entered when EXTM = 1 and MDIS = 0 in the EBI_MCR register. Dual-master operation (multiple masters initiating external bus cycles) is not supported. A multi-MCU system with one master and one slave is supported. In a dual-controller system, the EBI is configured to internal arbitration (EARB=0 in EBI_MCR) and must be the system master. Use the SIZEN and SIZE fields in the EBI_MCR for MCU-to-MCU transfers to indicate transfer size. See Section 12.5.5, “Dual-MCU Operations,” and Section 12.4.2.10, “Bus Operation in External Master Mode” describes external master mode operation. 12.1.3.3 Module Disable Mode The module disable mode is used for MCU power management. The clock to the non-memory mapped logic in the EBI is stopped while in module disable mode. Do not make requests (other than to memory-mapped logic) to the EBI while it is in module disable mode—even if the clocks are not stopped. In this case, the operation is undefined. Module disable mode is entered when MDIS = 1 in the EBI_MCR. 12.1.3.4 Configurable Bus Speed Modes In configurable bus speed modes, the external CLKOUT frequency is scaled to 1/2 or 1/4 of the internal system clock frequency, which remains unchanged. The EBI drives and samples signals at the scaled CLKOUT frequency rate rather than the internal system clock. This mode is selected by writing to the external clock control register in the system integration module (SIU_ECCR). 12.1.3.5 16-Bit Data Bus Mode The EBI is limited to a 16-bit data bus, therefore, the EBI supports the 16-bit data bus mode only DATA[0:15]. MPC5533 Microcontroller Reference Manual, Rev. 0 12-4 Freescale Semiconductor To enter 16-bit data bus mode, set the data bus mode field [DBM] in the EBI Module Configuration register (EBI_MCR[DBM]) and the port size field in the EBI Base register (EBI_BRn[PS]) to one. The reset value for the DBM and PS fields is zero. External master accesses and EBI-mastered non-chip select accesses of exactly 32-bits are supported using a two (16-bit) beat transfer for both reads and writes. Data transfers that are not chip select transfers and exactly 32-bits wide are supported in standard non-burst process. See Section 12.4.2.11, “Non-Chip-Select Burst in 16-bit Data Bus Mode.” 12.1.3.6 Debug Mode When the MCU is in debug mode, the EBI remains operational. 12.2 External Signal Description Table 12-1 alphabetically lists the external signals used by the EBI. See Chapter 2, “Signals,” as not all signals are implemented in all device packages. NOTE The 208 package does not have an external bus interface. This chapter pertains only to the 324 package. Table 12-1. Signal Properties Pull1 Package and Assembly Address Bus — 324 Output Burst Data in Progress Up 324 Output Clockout — 324 CS[0] Output Chip Selects Up 324 CS[1:3] Output Chip Selects Up 324 Data Bus — 324 Output Enable Up 324 Name ADDR[12:31] BDIP CLKOUT 2 DATA[0:15] OE I/O Type I/O I/O Output Function RD_WR I/O Read/Write Up 324 TA I/O Transfer Acknowledge Up 324 TS I/O Transfer Start Up 324 Write/Byte Enables Up 324 WE/BE[0:1] Output 1 This column shows signals that require a weak pull (up or down) on the pin. The weak pullup/pulldown mechanisms are not available in the EBI module. Use the pad configuration registers in the system integration module (SIU_PCRs) to set the weak pullup or pulldown characteristic for each pin. 2 The CLKOUT signal is driven by the FMPLL module. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 12-5 12.2.1 Detailed Signal Descriptions See Chapter 2, “Signals,” as not all signals are implemented in all device packages. 12.2.1.1 Address Lines 8–31 (ADDR[8:31]) The ADDR[8:31] signals specify the physical address of the bus transaction. The 24 address lines are bits 8–31 of the EBI 32-bit internal address bus. Bits 0–7 are internally driven by the EBI for externally initiated accesses depending on the internal slave accessed. See Section 12.4.2.10.1, “Address Decoding for External Master Accesses,” for more details. ADDR[8:31] is driven by the EBI or an external master depending on which device controls the external bus. The 324 BGA packaged devices use ADDR[12:31] (24 bits available if CS[0:3] are configured to ADDR[8:11]. See Section 6.4.1.12.1, “Pad Configuration Registers 0–3 (SIU_PCR0–SIU_PCR3)”). 12.2.1.2 Burst Data in Progress (BDIP) BDIP is asserted by a master requesting the next data beat to follow the current data beat. BDIP is driven by the EBI or an external master depending on which one is in control of the external bus. This signal is driven by the EBI on all EBI-mastered external burst cycles, but is only sampled by burst mode memories that have a burst pin. See Section 12.4.2.5, “Burst Transfer.” 12.2.1.3 Clockout (CLKOUT) CLKOUT is a general-purpose clock output signal to connect to the clock input of SDR external memories and in some cases to the input clock of another MCU in multi-master configurations. 12.2.1.4 Chip Selects 0–3 (CS[0:3]) CS[n] is asserted by the master to indicate that this transaction is targeted for a particular memory bank. The chip selects are driven by the EBI or an external master depending on which module controls the external bus. The chip select is driven in the same clock as the assertion of TS and valid address, and is kept valid until the cycle is terminated. See Section 12.4.1.4, “Memory Controller with Support for Various Memory Types” for details on chip select operation. 12.2.1.5 Data Lines 0–15 (DATA[0:15]) In the 324 BGA package, DATA[0:15] transmits the data for the current transaction. DATA[0:15] is driven by the EBI when it owns the external bus and it initiates a write transaction to an external device. The EBI also drives DATA[0:15] when an external master owns the external bus and initiates a read transaction to an internal module. MPC5533 Microcontroller Reference Manual, Rev. 0 12-6 Freescale Semiconductor DATA[0:15] is driven by an external device during a read transaction from the EBI. An external master drives DATA[0:15] when it owns the bus and initiates a write transaction to an internal module or shared external memory. For 8-bit transactions, the byte lane not selected for the transfer does not supply valid data. 12.2.1.6 Output Enable (OE) OE is used to indicate when an external memory is permitted to drive back read data. External memories must have their data output buffers off when OE is negated. OE is only asserted for chip select accesses. OE is driven by the EBI or an external master depending on who owns the external bus. • Read cycles—OE is asserted one clock after TS asserts, and is held until the transfer terminates. • Write cycles—OE is negated throughout the cycle. 12.2.1.7 Read/Write (RD_WR) RD_WR indicates whether the current transaction is a read access or a write access. RD_WR is driven by the EBI or an external master depending on who owns the external bus. RD_WR is driven in the same clock as the assertion of TS and valid address, and is kept valid until the cycle is terminated. 12.2.1.8 Transfer Acknowledge (TA) TA is asserted to indicate that the slave device has received the data (and completed the access) for a write cycle, or returned data for a read cycle. If the transaction is a burst read, TA is asserted for each one of the transaction beats. For write transactions, TA is only asserted once at access completion, even if more than one write data beat is transferred. TA is driven by the EBI when the access is controlled by the chip selects or when an external master initiates the transaction to an internal module. Otherwise, TA is driven by the slave device to which the current transaction was addressed. See Section 12.4.2.9, “Termination Signals Protocol” for more details. 12.2.1.9 Transfer Start (TS) TS is asserted by the current bus owner to indicate the start of a transaction on the external bus. TS is driven by the EBI or an external master depending on who owns the external bus. TS is only asserted for the first clock cycle of the transaction, and is negated in the successive clock cycles until the end of the transaction. 12.2.1.10 Write/Byte Enables (WE/BE) Write and byte enables (WE/ BE[0:1]) are used to enable program operations to a particular memory. Write enable is used for write operations only. Byte enable is used for read and write operations to configure the MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 12-7 byte lanes. These signals are set by the WEBS bit in the SIU_PCR registers. WE/BE are only asserted for chip select accesses. WE/BE signals are driven by the EBI or an external master depending on which one controls the external bus. See Section 12.4.1.10, “Two Write/Byte Enable (WE/BE) Signals” for more details on WE/BE functionality. 12.2.2 Signal Function and Direction by Mode The EBI operating mode is configured using two fields in the EBI Master Control register (EBI_MCR): EXTM and MDIS. Their settings determine which EBI signals are valid and the I/O direction. When a signal is configured for non-EBI function in the EBI_MCR, the EBI always negates the signal if the EBI controls the corresponding pad (determined by SIU configuration). Table 12-2 lists the function and direction of the external signals in each of the EBI modes of operation. The clock signals are not included because they are output only (from the FMPLL module) and are not affected by EBI modes. See Section 12.3.1.3, “EBI Module Configuration Register (EBI_MCR)” for details on the EXTM and MDIS bits. Table 12-2. Signal Function According to EBI Mode Settings Modes Signal Name Module Disable Function Single Master Function I/O Direction EXTM = n, MDIS = 1 EXTM = 0, MDIS = 0 External Master Function I/O Direction EXTM = 1, MDIS = 0 ADDR[8:11] 1 non-EBI function Address bus (output) Address bus (I/O)2 ADDR[12:31] non-EBI function Address bus (output) Address bus (I/O)2 BDIP non-EBI function Burst data in progress (output)3 CS[0:3] 1 non-EBI function Chip selects (output)3 DATA[0:15] non-EBI function Data bus (I/O) OE non-EBI function Output enable (output) RD_WR non-EBI function Read/write (output) TA non-EBI function Transfer acknowledge (I/O) TS non-EBI function Transfer start (output) WE/BE[0:1] non-EBI function Write/byte enables (output)3 Read/write (I/O) Transfer start (I/O) 1 These signals are muxed with the chip select (CS) signals on this device. Use the pad configuration registers (PCR) in the system integration module (SIU) to configure the balls to use the address signals or chip select signals–not both. 2 All I/O signals are tri-stated by the EBI when not actively involved in a transfer. 3 Although external master accesses can drive these pins, the EBI three-states the pins and does not sample them for input. MPC5533 Microcontroller Reference Manual, Rev. 0 12-8 Freescale Semiconductor NOTE The open-drain mode of the pad configuration module is not used for any EBI signals. For a description of how signals are driven by multiple devices in external master mode, see Section 12.4.2.10, “Bus Operation in External Master Mode.” 12.3 Memory Map and Register Definition NOTE The 208 package does not have an external bus interface. This chapter pertains to the 324 package only. Table 12-3 is a memory map of the EBI registers. Table 12-3. EBI Memory Map Address Base (0xC3F8_4000) Register Name EBI_MCR Register Description EBI module configuration register 32 Base + 0x0004 — Base + 0x0008 EBI_TESR EBI transfer error status register 32 Base + 0x000C EBI_BMCR EBI bus monitor control register 32 Base + 0x0010 EBI_BR0 EBI base register bank 0 32 Base + 0x0014 EBI_OR0 EBI option register bank 0 32 Base + 0x0018 EBI_BR1 EBI base register bank 1 32 Base + 0x001C EBI_OR1 EBI option register bank 1 32 Base + 0x0020 EBI_BR2 EBI base register bank 2 32 Base + 0x0024 EBI_OR2 EBI option register bank 2 32 Base + 0x0028 EBI_BR3 EBI base register bank 3 32 Base + 0x002C EBI_OR3 EBI option register bank 3 32 12.3.1 12.3.1.1 Reserved Bits — Register Descriptions Writing EBI Registers While a Transaction is in Progress Do not write to EBI registers while: • An EBI transaction (from an internal or external master) is in progress; or • Within two CLKOUT cycles after a transaction completes to allow the internal state machines to enter the IDLE state. Exceptions for writing to the EBI registers while an EBI transaction is in progress are: • • All bits in the EBI Transfer Error Status register (EBI_TESR) The SIZE, SIZEN fields in the EBI Module Configuration register (EBI_MCR) MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 12-9 If you write to other fields in the EBI registers, or when an EBI transaction is in progress and is not one of the exception cases described, the operations are indeterminable. See Section 12.5.1, “Booting from External Memory,” for additional information. 12.3.1.2 Separate Input Clock for Registers The EBI registers are accessed with a clock signal separate from the clock used by the rest of the EBI. In module disable mode, the clock used by the non-register portion of the EBI is disabled to reduce power consumption. The clock signal dedicated to the registers, however, allows access to the registers even while the EBI is in the module disable mode. Flag bits in the EBI transfer error status register (EBI_TESR), however, are set and cleared with the clock used by the non-register portion of the EBI. Consequently, in module disable mode, the EBI_TESR does not have a clock signal and is therefore not writable. 12.3.1.3 EBI Module Configuration Register (EBI_MCR) The EBI_MCR contains bits that configure various attributes associated with EBI operation. Base (0xC3F8_4000) R Access: R/W 0 1 2 3 4 0 0 0 0 0 5 6 SIZEN 7 8 9 10 11 12 13 14 15 0 0 0 0 0 0 0 0 SIZE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 0 0 0 0 0 0 0 0 0 0 R ACGE EXTM EARB MDIS DBM W Reset 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 Figure 12-2. EBI Module Configuration Register (EBI_MCR) Table 12-4. EBI_MCR Field Descriptions Field 0–4 Description Reserved 5 SIZEN SIZE enable. The SIZEN bit enables the control of transfer size by the SIZE field for external master transactions to internal address space. See Section 12.5.5.3, “Setting the Transfer Size.” 0 Invalid value 1 Enable transfer size controlled by SIZE field Note: You must change this value to 1 to control the data transfer size. 6–7 SIZE Transfer size. The SIZE field defines the transfer size of external master transactions to internal address space when SIZEN=1. See Section 12.5.5.3, “Setting the Transfer Size.” This field is ignored when SIZEN=0. SIZE encoding: 00 Invalid value 01 Byte 10 16-bit 11 Invalid value MPC5533 Microcontroller Reference Manual, Rev. 0 12-10 Freescale Semiconductor Table 12-4. EBI_MCR Field Descriptions (Continued) Field Description 8–15 Reserved 16 ACGE Automatic CLKOUT gating enable. Enables the EBI feature of turning off CLKOUT (holding it high) during idle periods in-between external bus accesses. 0 Automatic CLKOUT gating is disabled 1 Automatic CLKOUT gating is enabled 17 EXTM External master mode. Enables the external master mode of operation when MDIS = 0. When MDIS = 1, the EXTM bit is not used, and is treated as 0. In external master mode, an external master on the external bus can access any internal memory-mapped space while the internal e200z3 core is fully operational. When EXTM = 0, only internal masters can access the internal memory space. See Section 12.5.5, “Dual-MCU Operations.“ 0 External master mode is inactive (single master mode) 1 External master mode is active Note: Only master/slave systems support the EXTM functionality. 18–24 Reserved 25 MDIS Module disable mode. Allows the clock to be stopped to the non-memory mapped logic in the EBI, effectively putting the EBI in a software controlled power-saving state. No external bus accesses can be performed when the EBI is in module disable mode (MDIS = 1). Most registers remain accessible in this mode. See Section 12.1.3.3, “Module Disable Mode,” for more information. 0 Module disable mode is inactive 1 Module disable mode is active 26–30 Reserved 31 DBM Data bus mode. Sets the EBI to 16-bit data bus mode. 0 Invalid value 1 16-bit data bus mode is used 12.3.1.4 EBI Transfer Error Status Register (EBI_TESR) The EBI_TESR contains a bit for each type of transfer error on the external bus. A bit set to logic 1 indicates what type of transfer error occurred since the last time the bits were cleared. Each bit can be cleared by reset or by writing a 1 to it. Writing a 0 has no effect. Base + 0x0008 R Access: R/W1c 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BMTF W Reset R W Reset w1c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 12-3. EBI Transfer Error Status Register (EBI_TESR) MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 12-11 Table 12-5. EBI_TESR Field Descriptions Field Description 0–30 Reserved 31 BMTF Bus monitor timeout flag. Set if the cycle was terminated by a bus monitor timeout. 0 No error 1 Bus monitor timeout occurred This bit can be cleared by writing a 1 to it. 12.3.1.5 EBI Bus Monitor Control Register (EBI_BMCR) The EBI_BMCR controls the timeout period of the bus monitor, and whether it is enabled or disabled. Base + 0x000C R Access: R/W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset R BMT [0:7] BME W Reset 1 1 1 1 1 1 1 1 1 Figure 12-4. EBI Bus Monitor Control Register (EBI_BMCR) Table 12-6. EBI_BMCR Field Descriptions Field Description 0–15 Reserved 16–23 BMT [0:7] Bus monitor timing. Defines the timeout period, in 8 external bus clock resolution, for the bus monitor. See Section 12.4.1.6, “Bus Monitor,” for more details on bus monitor operation. 2 + (8 × BMT) Timeout Period = -------------------------------------------------------------------------------External Bus Clock Frequency 24 BME 25–31 Bus monitor enable. Controls whether the bus monitor is enabled for internal to external bus cycles. Regardless of the BME value, the bus monitor is always disabled for chip select accesses, since these always use internal TA and thus have no danger of hanging the system. 0 Disable bus monitor 1 Enable bus monitor (for non-chip select accesses only) Reserved MPC5533 Microcontroller Reference Manual, Rev. 0 12-12 Freescale Semiconductor 12.3.1.6 EBI Base Registers 0–3 (EBI_BRn) The EBI_BRn are used to define the base address and other attributes for the corresponding chip select. Base + 0x0010 (EBI_BR0) Base + 0x0018 (EBI_BR1) Base + 0x0020 (EBI_BR2) Base + 0x0028 (EBI_BR3) R Access: R/W 0 1 2 0 0 1 3 4 5 6 7 8 9 10 11 12 13 14 15 BA W Reset 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 0 0 0 0 0 0 0 0 BI V 1 0 R BA PS BL WEBS TBDIP W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 12-5. EBI Base Registers 0–3 (EBI_BRn) Table 12-7. EBI_BRn Field Descriptions Field Description 0–16 BA [0:16] Base address. Compared to the corresponding unmasked address signals among ADDR[0:16] of the internal address bus to determine if a memory bank controlled by the memory controller is being accessed by an internal bus master. Note: The upper 3 bits of the base address (BA) field, EBI_BRn[0:2], are tied to a fixed value of 001. These bits reset to their fixed value. 17–19 Reserved 20 PS 21–24 25 BL Port size. Determines the data bus width of transactions to this chip select bank.1 0 Invalid value 1 16-bit port. Reserved Burst length. Determines the amount of data transferred in a burst for this chip select, measured in 32-bit words. The number of beats in a burst is automatically determined by the EBI according to the port size bit (PS) so the burst fetches the number of words chosen by BL. 0 Invalid value 1 4-word burst length Note: 1 2 Value Burst Length 1 PS # Beats in Burst 2 1 4-word 1 8 Total amount of data fetched in a burst transfer. Number of external data beats used in external burst transfer. The size of each beat is determined by PS value. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 12-13 Table 12-7. EBI_BRn Field Descriptions (Continued) Field 1 Description 26 WEBS Write enable/byte select. Controls the functionality of the WE/BE[0:1] signals. 0 The WE/BE[0:1] signals function as WE[0:1]. 1 The WE/BE[0:1] signals function as BE[0:1]. 27 TBDIP Toggle burst data in progress. Determines how long the BDIP signal is asserted for each data beat in a burst cycle. See Section 12.4.2.5.1, “TBDIP Effect on Burst Transfer,” for details. 0 Assert BDIP throughout the burst cycle, regardless of wait state configuration. 1 Only assert BDIP (BSCY + 1) external bus cycles before expecting subsequent burst data beats. 28–29 Reserved 30 BI Burst inhibit. Determines whether or not burst read accesses are allowed for this chip select bank. 0 Enable burst accesses for this bank. 1 Disable burst accesses for this bank. This is the default value out of reset. 31 V Valid bit. Indicates that the contents of this base register and option register pair are valid. The appropriate CS signal does not assert unless the corresponding V-bit is set. 0 This bank is not valid. 1 This bank is valid. The the value of PS bit in the EBI_MCR[DBM] register is not used and the value used is always 1. 12.3.1.7 EBI Option Registers 0–3 (EBI_ORn) The EBI_ORn registers are used to define the address mask and other attributes for the corresponding chip select. Base + 0x0014 (EBI_OR0) Base + 0x001C (EBI_OR1) Base + 0x0024 (EBI_OR2) Base + 0x002C (EBI_OR3) R Access: R/W 0 1 2 1 1 1 3 4 5 6 7 8 9 10 11 12 13 14 15 AM W Reset 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 0 0 0 0 0 0 R 0 AM SCY 0 BSCY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 12-6. EBI Option Registers 0–3 (EBI_ORn) MPC5533 Microcontroller Reference Manual, Rev. 0 12-14 Freescale Semiconductor Table 12-8. EBI_ORn Field Description 0–16 AM [0:16] Address mask. Allows masking of any corresponding bits in the associated base register. Masking the address independently allows external devices of different size address ranges to be used. Any clear bit masks the corresponding address bit. Any set bit causes the corresponding address bit to be used in comparison with the address pins. Address mask bits can be set or cleared in any order in the field, allowing a resource to reside in more than one area of the address map. This field can be read or written at any time. Note: The upper 3 bits of the address mask (AM) field, EBI_ORx[0:2] are tied to a fixed value of 111. These bits reset to their fixed value. 17–23 Reserved 24–27 SCY [0:3] Cycle length in clocks. Represents the number of wait states (external bus cycles) inserted after the address phase in the single cycle case, or in the first beat of a burst, when the memory controller handles the external memory access. Values range from 0 to 15. This is the main parameter for determining the length of the cycle. • The total cycle length for the first beat (including the TS cycle): (2 + SCY) external clock cycles See Section 12.5.3.1, “Example Wait State Calculation”. 28 29–30 BSCY [0:1] Reserved Burst beats length in clocks. This field determines the number of wait states (external bus cycles) inserted in all burst beats except the first, when the memory controller starts handling the external memory access and thus is using SCY[0:3] to determine the length of the first beat. • Total memory access length for each beat: (1 + BSCY) External Clock Cycles • Total cycle length (including the TS cycle): (2 + SCY) + [(Number of Beats – 1) x (BSCY + 1)] Note: The number of beats (4, 8, 16) is determined by BL and PS bits in the base register. 00 0-clock cycle wait states (1 clock per data beat) 01 1-clock cycle wait states (2 clocks per data beat) 10 2-clock cycle wait states (3 clocks per data beat) 11 3-clock cycle wait states (4 clocks per data beat) 12.4 Functional Description NOTE The 208 package does not have an external bus interface. This chapter pertains to the 324 package only. 12.4.1 12.4.1.1 External Bus Interface Features 32-Bit Address Bus The transfer size for an external transaction is indicated by the SIZE and SIZEN fields in the EBI_MCR register during the clock when the address is valid. Valid transaction sizes are 8, 16, and 32 bits. The 324 package has 20 address lines pinned out externally (24 bits available if CS[0:3] are configured as ADDR[8:11]). A full 32-bit decode is done internally to determine the target of the transaction and whether to assert a chip select. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 12-15 See Section 6.4.1.12.1, “Pad Configuration Registers 0–3 (SIU_PCR0–SIU_PCR3)” 12.4.1.2 16-Bit Data Bus A 16-bit data bus mode is available using the DBM bit in EBI_MCR. See Section 12.1.3.5, “16-Bit Data Bus Mode.” 12.4.1.3 Support for External Master Accesses to Internal Addresses The EBI allows an external master to access internal address space when the EBI is configured for external master mode in the EBI_MCR. Section 12.4.2.10, “Bus Operation in External Master Mode” describes the external master operations. 12.4.1.4 Memory Controller with Support for Various Memory Types The EBI contains a memory controller that supports a variety of memory types: • Standard SRAM • Synchronous burst mode to memory (flash or external SRAM) • Asynchronous memory (flash or external SRAM) and peripherals Each CS bank is configured with a pair of base and option registers. Each time an internal to external bus cycle access is requested, the following occurs: As shown in Figure 12-7, the internal address is compared with the base address of each valid base register (17 bits are masked). If a match occurs in one memory bank, the BR and OR bank attribute values control the memory access. If a match occurs in more than one memory bank, the matched bank with the lowest bank number handles the memory access. For example, bank 0 is selected over memory bank 1. MPC5533 Microcontroller Reference Manual, Rev. 0 12-16 Freescale Semiconductor Base Address BA [0] BA [1] BA [2] BA [3] BA [4] Address Mask ••• BA [15] BA [16] AM [0] AM [1] AM [2] AM [3] AM [4] AM [5] AM AM ••• [6] [16] A[0:16] AM[0:16] Comp Comp Comp Comp Comp • • • Comp Comp ••• Match Figure 12-7. Bank Base Address and Match Structure When a match occurs on one of the chip select banks, all its attributes (from the base and option registers) are selected for the functional operation of the external memory access: • Number of wait states for a single memory access, and for any beat in a burst access • Burst enable • Port size for the external accessed device See the following sections for a full description of all chip select attributes: Section 12.3.1.6, “EBI Base Registers 0–3 (EBI_BRn)” Section 12.3.1.7, “EBI Option Registers 0–3 (EBI_ORn)” When no match occurs on any of the chip select banks, the default transfer attributes shown in Table 12-9 are used. NOTE The port size (PS) value defaults to 32-bits. You must ensure the port size (PS) is set to 16-bits before initiating the transfer. Table 12-9. Default Attributes for Transfers Other than Chip Select Chip Select Attribute (CS[0:3]) Default Value PS 0 32-bit port size BL 0 BL = “don’t care” (burst is disabled) WEBS 0 Write enables TBDIP 0 TBDIP = “don’t care” (burst is disabled) BI 1 Burst inhibited Comment MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 12-17 Table 12-9. Default Attributes for Transfers Other than Chip Select (Continued) 12.4.1.5 Chip Select Attribute (CS[0:3]) Default Value SCY 0 SCY = “don’t care” BSCY 0 BSCY = “don’t care” Comment Burst Support (Wrapped Only) This device has no cache, therefore the core does not support burst transfers. The eDMA only can launch a burst transfer to external memory. The EBI supports burst read accesses to external burstable memory. The EBI in 16-bit data bus mode (EBI_MCR[DBM] = 1) does not support burst writes, except for 32-bit two-beat non-chip select burst writes to 32-bit. This allows 32-bit coherent accesses to another MCU. Internal requests to write more than 32-bits externally are divided into separate 16-bit external transactions according to the port size. To enable bursts to a memory region, clear the BI (Burst Inhibit) bit in the base register. External burst lengths of four and eight words are supported. Burst length is configured for each chip select by using the BL bit in the base register. See Section 12.4.2.5, “Burst Transfer” for more details. In 16-bit data bus mode, a special two-beat burst case is supported for reads and writes for 32-bit non-chip select accesses only. See Section 12.4.2.11, “Non-Chip-Select Burst in 16-bit Data Bus Mode”. Burst writes are not supported except from a 32-bit non-chip-select write in 16-bit data bus mode. Internal requests to write more than 32 bits externally are divided into separate 16-bit external transactions according to the port size. See Section 12.4.2.6, “Small Accesses (Small Port Size and Short Burst Length)” for more detail on these cases. 12.4.1.6 Bus Monitor When enabled (via the BME bit in the EBI_BMCR), the bus monitor detects when no TA assertion is received within a maximum timeout period for non-chip select accesses (accesses that use external TA). The timeout for the bus monitor is specified by the BMT field in the EBI_BMCR. Each time a timeout error occurs, the BMTF bit is set in the EBI_TESR. The timeout period is measured in external bus (CLKOUT) cycles. Thus the effective real-time period is multiplied (by two or four) when a configurable bus speed mode is used, even though the BMT field itself is unchanged. MPC5533 Microcontroller Reference Manual, Rev. 0 12-18 Freescale Semiconductor 12.4.1.7 Port Size Configuration per Chip Select The EBI supports memories with data widths of 16 bits. The port size (PS) for a chip select is configured using the PS bit in the base register. 12.4.1.8 Configurable Wait States You can program 0–15 wait states for any cycle that the memory controller generates, using the SCY bits in the option register. You can program 0–3 wait states between burst beats using the BSCY bits in the option register. 12.4.1.9 Four Chip Select (CS[0:3]) Signals The EBI contains four chip select signals, controlling four independent memory banks. See Section 12.4.1.4, “Memory Controller with Support for Various Memory Types,” for more details on chip select bank configuration. 12.4.1.10 Two Write/Byte Enable (WE/BE) Signals The functionality of the WE/BE[0:1] signals depends on the value of the WEBS bit in the corresponding base register. Setting WEBS to 1 configures these pins as BE[0:1], while clearing it configures the pins as WE[0:1]. The WE[0:1] signals are asserted only during write accesses, while BE[0:1] signals are asserted for both read and write accesses. The timing of the WE/BE[0:1] signals remains the same in both cases. The WE/BE[0] signal indicates that the upper eight bits of the data bus (DATA[0:7]) contain valid data during a write/read cycle. The WE/BE[1] signal indicates that the lower eight bits of the data bus (DATA[8:15]) contain valid data during a write/read cycle. The write/byte enable lines affected in a transaction are shown in Table 12-10. Only big endian byte ordering is supported by the EBI. Table 12-10. Write/Byte Enable Signals Function 16-Bit Port Size1 Address Transfer Size A[30] A[31] WE/BE[0] WE/BE[1] 0 0 0 1 0 1 1 0 1 0 0 1 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 8 bits 16 bits Burst 1 DBM must be 1 for 16-bit data bus mode. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 12-19 12.4.1.11 Optional Automatic CLKOUT Gating The EBI can hold the external CLKOUT pin high when the EBI internal master state machine is idle and no requests are pending. The EBI outputs a signal to the pads logic in the MCU to disable CLKOUT. This feature is disabled out of reset, and can be enabled or disabled by the ACGE bit in the EBI_MCR. 12.4.1.12 Compatible with MPC500 External Bus (with Some Limitations) The EBI is compatible with the external bus of the MPC500 parts, meaning that it supports most devices supported by the MPC500 family of parts. However, there are some differences between this EBI and that of the MPC500 parts that you must be aware of before assuming that an MPC500-compatible device works with this EBI. See Section 12.5.6, “Summary of Differences from MPC500,” for details. NOTE Due to testing and complexity concerns, master/slave operation between an MPC55xx and MPC5xx is not guaranteed. Multi-master operations are not supported on this device. 12.4.2 External Bus Operations The following sections provide a functional description of the external bus, the bus cycles provided for data transfer operations, bus arbitration, and error conditions. 12.4.2.1 External Clocking The CLKOUT signal sets the frequency of operation for the bus interface directly. Internally, the MCU uses a phase-locked loop (PLL) circuit to generate a master clock for all of the MCU circuitry (including the EBI) which is phase-locked to the CLKOUT signal. In general, all signals for the EBI are specified with respect to the rising-edge of the CLKOUT signal, and they are guaranteed to be sampled as inputs or changed as outputs with respect to that edge. 12.4.2.2 Reset Upon detection of internal reset, the EBI immediately terminates all transactions. 12.4.2.3 Basic Transfer Protocol The basic transfer protocol defines the sequence of actions that must occur on the external bus to perform a complete bus transaction. A simplified scheme of the basic transfer protocol is shown in Figure 12-8. Address transfer Data transfer Termination Figure 12-8. Basic Transfer Protocol MPC5533 Microcontroller Reference Manual, Rev. 0 12-20 Freescale Semiconductor In single-master mode, the EBI is the permanent bus owner. The address transfer phase specifies the address for the transaction and the transfer attributes that describe the transaction. The signals related to the address transfer phase are TS, ADDR, CS[0:3], RD_WR, and BDIP. The address and its related signals (with the exception of TS, BDIP) are driven on the bus with the assertion of the TS signal, and kept valid until the bus master receives TA asserted (the EBI holds them one cycle beyond TA for writes and external TA accesses). For writes with internal TA, RD_WR is not held one cycle past TA. The data transfer phase transfers data from master to slave (on write cycles), or from slave to master (on read cycles). The data phase can transfer a: • Single beat of data (1–2 bytes) for non-burst operations; or • A 2-, 4-, 8-, or 16-beat burst of data (EBI_MCR[DBM] = 1, at 2 bytes per beat) when burst is enabled. On a write cycle, the master must not drive write data until after the address transfer phase is complete. This avoids electrical contentions when switching between drivers. The master must start driving write data one cycle after the address transfer cycle. The master can stop driving the data bus as soon as it samples the TA line asserted on the rising edge of CLKOUT. For chip select accesses, use the output enable (OE) signal to indicate that the external device can drive data onto the bus during an MCU read cycle. To prevent bus contentions for chip select accesses, you must use OE to determine when the external device can drive the bus. Read Timing—On a read cycle, the master accepts the data bus contents as valid on the rising edge of CLKOUT when the TA signal asserts and is sampled. See Figure 12-10 for an example of read timing. The termination phase completes by the assertion of TA (normal termination). Write Timing—To facilitate asynchronous write support, the EBI keeps driving valid write data on the data bus until one clock after the rising edge, when RD_WR (and WE for chip select accesses) are negated. See Figure 12-19 for an example of write timing. Section 12.4.2.9, “Termination Signals Protocol.” describes in detail the termination phase. 12.4.2.4 Single-Beat Transfer The flow and timing diagrams in this section assume that the EBI is configured in single master mode. Therefore, arbitration is not needed and is not shown in these diagrams. See Section 12.4.2.10, “Bus Operation in External Master Mode,” to read how the flow and timing diagrams change for external master mode. 12.4.2.4.1 Single-Beat Read Flow The handshakes for a single-beat read cycle are illustrated in the following flow and timing diagrams. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 12-21 Master (EBI) Slave Asserts transfer start (TS) drives address and attributes Receives address Drives Data Yes CS access ? No Asserts transfer acknowledge (TA) Asserts transfer acknowledge (TA) Receives data Figure 12-9. Basic Flow Diagram of a Single-Beat Read Cycle CLKOUT ADDR[8:31] RD_WR BDIP TS DATA[0:15] TA CS[n] DATA is valid OE Figure 12-10. Single-Beat 16-bit Read Cycle, CS Access, Zero Wait States MPC5533 Microcontroller Reference Manual, Rev. 0 12-22 Freescale Semiconductor CLKOUT ADDR[8:31] RD_WR BDIP TS DATA[0:15] TA CS[n] Wait state DATA is valid OE Figure 12-11. Single-Beat 16-bit Read Cycle, CS Access, One Wait State CLKOUT ADDR[8:31] RD_WR BDIP TS DATA[0:15] TA(input) DATA is valid CS[n] OE * The EBI drives address and control signals an extra cycle because it uses a latched version of the external TA (1 cycle delayed) to terminate the cycle. Figure 12-12. Single-Beat 16-bit Read Cycle, Non-CS Access, Zero Wait States MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 12-23 12.4.2.4.2 Single-Beat Write Flow The handshakes for a single-beat write cycle are illustrated in the following flow and timing diagrams. Slave Master Asserts Transfer Start (TS) Drives Address and Attributes Receives Address Drives Data Receives Data Yes CS Access ? No Asserts Transfer Acknowledge (TA) Asserts Transfer Acknowledge (TA) Waits 1 Clock Stops Driving Data Figure 12-13. Basic Flow Diagram of a Single-beat Write Cycle MPC5533 Microcontroller Reference Manual, Rev. 0 12-24 Freescale Semiconductor CLKOUT ADDR[8:31] RD_WR BDIP TS DATA is valid DATA[0:15] TA CS[n] WE[0:1] Figure 12-14. Single-Beat 16-bit Write Cycle, CS Access, Zero Wait States CLKOUT ADDR[8:31] RD_WR BDIP TS DATA is valid DATA[0:15] TA Wait state CS[n] WE[0:1] Figure 12-15. Single-Beat 16-bit Write Cycle, CS Access, One Wait State MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 12-25 CLKOUT ADDR[8:31] * RD_WR BDIP TS DATA is valid DATA[0:15] TA (Input) DATA is valid CS[n] WE[0:1] * The EBI drives address and control signals an extra cycle because it uses a latched version of the external TA (1 cycle delayed) to terminate the cycle. Figure 12-16. Single-Beat 16-bit Write Cycle, Non-CS Access, Zero Wait States 12.4.2.4.3 Back-to-Back Accesses Due to internal bus protocol, one dead cycle is necessary between back-to-back external bus accesses that are not part of a set of small accesses. A dead cycle refers to a cycle between the TA of a previous transfer and the TS of the next transfer. See Section 12.4.2.6, “Small Accesses (Small Port Size and Short Burst Length)” for small access timing. NOTE In some cases, CS remains asserted during a dead cycle, such as the cases of back-to-back writes or read-after-write to the same chip-select. See Figure 12-20 and Figure 12-21. Besides a dead cycle, in most cases, back-to-back accesses on the external bus do not cause any change in the timing from that shown in the previous diagrams, and the two transactions are independent of each other. Back-to-back accesses where the first access ends with an externally-driven TA. In these cases, an extra cycle is required between the end of the first access and the TS assertion of the second access. See Section 12.4.2.9, “Termination Signals Protocol,” for more details. The following diagrams show a few examples of back-to-back accesses on the external bus. MPC5533 Microcontroller Reference Manual, Rev. 0 12-26 Freescale Semiconductor CLKOUT ADDR[8:31] RD_WR BDIP TS DATA[0:15] TA CS[n] DATA is valid DATA is valid OE Figure 12-17. Back-to-Back 16-bit Reads to the Same CS Bank CLKOUT ADDR[8:31] RD_WR BDIP TS DATA[0:15] TA CS[n] DATA is valid DATA is valid CS[y] OE Figure 12-18. Back-to-Back 16-bit Reads to Different CS Banks MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 12-27 CLKOUT ADDR[8:31] RD_WR BDIP TS DATA is valid DATA[0:15] TA DATA is valid CS[n] WE Figure 12-19. Write After Read to the Same CS Bank CLKOUT ADDR[8:31] RD_WR BDIP TS DATA is valid DATA is valid DATA[0:15] TA CS[n] WE Figure 12-20. Back-to-Back 16-bit Writes to the Same CS Bank MPC5533 Microcontroller Reference Manual, Rev. 0 12-28 Freescale Semiconductor CLKOUT ADDR[8:31] RD_WR BDIP TS DATA is valid DATA[0:15] TA DATA is valid CS[n] WE Figure 12-21. Read After Write to the Same CS Bank 12.4.2.5 Burst Transfer On all burst cycles, the EBI requires that addresses are aligned on a doubleword boundary. The EBI supports burst wrapping for 32-byte critical-doubleword-first transfers. Bursting is supported for internally-requested 32-byte read accesses to external devices that use: • Chip select (CS) accesses only • 32-bit non-chip select accesses using a two-beat 16-bit for each word Other than these exceptions, all accesses from an external master to devices operating without a chip select are always single beat. If an internal request to the EBI indicates a burst transfer less than 32 bytes, one or more single-beat external transfers are used—not by an external burst transfer. An 8-word wrapping burst reads eight 32-bit words by supplying a starting address that points to one of the words (doubleword aligned), and requires the memory device to sequentially drive each word on the data bus. The selected slave device must internally increment ADDR[27:30] of the supplied address for each transfer until the address of the 8-word boundary is reached, and then wraps the address to the beginning of the 8-word boundary. The address and transfer attributes supplied by the EBI do not change during the transfers, and the EBI terminates each beat transfer by asserting TA. Table 12-11 shows the burst order of beats returned for an 8-word burst to a 32-bit memory interface using two-beat 16-bit accesses. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 12-29 Table 12-11. Wrap Bursts Order Burst Starting Address ADDR[27:30] Burst Order (two-beat 16-bit access = 1 word) 00 word0 −> word1 −> word2 −> word3 −> word4 −> word5 −> word6 −> word7 01 word2 −> word3 −> word4 −> word5 −> word6 −> word7 −> word0 −> word1 10 word4 −> word5 −> word6 −> word7 −> word0 −> word1 −> word2 −> word3 11 word6 −> word7 −> word0 −> word1 −> word2 −> word3 −> word4 −> word5 Burst transfers default to external memory with a 32-bit bus and 8-word burst length. The EBI can burst from 16-bit port size memories, using twice as many external beats to fetch the data. The EBI can also burst from 16-bit or 32-bit memories that have a 4-word burst length (BL = 1 in the appropriate base register). In this case, two external 4-word burst transfers (wrapping on 4-word boundary) are performed to fulfill the internal 8-word request. This operation is considered atomic by the EBI, so the EBI does not allow other master accesses to intervene between the transfers. During burst cycles, the BDIP (burst data in progress) signal indicates the duration of the burst data. During the data phase of a burst read cycle, the EBI receives data from the addressed slave. If the EBI needs more than one data transfer, it asserts the BDIP signal. Upon receiving the word prior to the last word, the EBI negates BDIP. Therefore, the slave stops driving succeeding data on the rising edge of the clock after BDIP negates. Some slave devices internally configure burst length and timing, which does not support using the BDIP signal. In this case, BDIP is driven by the EBI normally, but the output is ignored by memory and the burst transfer mechanism is determined by the internal configuration of the EBI and slave device. When the TBDIP bit is set in the base register, the timing for BDIP is altered. See Section 12.4.2.5.1, “TBDIP Effect on Burst Transfer,” for this timing. Burst writes are not supported by the EBI except for 32-bit non-chip select accesses in 16-bit data bus mode. For all other burst writes, the EBI negates BDIP during write cycles. MPC5533 Microcontroller Reference Manual, Rev. 0 12-30 Freescale Semiconductor Master Slave Asserts transfer start (TS) Drives address and attributes Receives address Assert BDIP Drives data Asserts transfer acknowledge (TA) Receives data No Next -tolast data beat ? Yes Negate BDIP Drives last data Asserts transfer acknowledge (TA) Receives last data Figure 12-22. Basic Flow Diagram of a Burst Read Cycle MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 12-31 CLKOUT ADDR[8:31] ADDR[29:31] = ‘000’ RD_WR TS Expects more data BDIP DATA[0:15] DATA is valid TA CS[n] OE Figure 12-23. Burst 16-bit Read Cycle, Zero Wait States CLKOUT ADDR[29:31] = ‘000’ ADDR[8:31] RD_WR TS Expects more data BDIP DATA[0:15] DATA is valid TA Wait state CS[n] OE Figure 12-24. Burst 16-bit Read Cycle, One Initial Wait State 12.4.2.5.1 TBDIP Effect on Burst Transfer Some memories require different timing on the BDIP signal than the default to run burst cycles. Using the default value of TBDIP = 0 in the appropriate EBI base register results in BDIP being asserted (SCY+1) cycles after the address transfer phase, and being held asserted throughout the cycle regardless of the wait MPC5533 Microcontroller Reference Manual, Rev. 0 12-32 Freescale Semiconductor states between beats (BSCY). Figure 12-25 shows an example of the TBDIP = 0 timing for a 4-beat burst with BSCY = 1. CLKOUT ADDR[29:31] = ‘000’ ADDR[8:31] RD_WR TS Expects more data BDIP DATA[0:15] DATA is valid TA Wait state CS[n] Wait state Wait state Wait state OE Figure 12-25. Burst 32-bit Read Cycle, One Wait State between Beats, TBDIP = 0 When using TBDIP = 1, the BDIP behavior changes to toggle between every beat when BSCY is a non-zero value. Figure 12-26 shows an example of the TBDIP = 1 timing for the same four-beat burst shown in Figure 12-25. CLKOUT ADDR[29:31] = ‘000’ ADDR[8:31] RD_WR TS Expects more data BDIP DATA[0:15] DATA is valid TA Wait state CS[n] Wait state Wait state Wait state OE Figure 12-26. Burst 32-bit Read Cycle, One Wait State between Beats, TBDIP = 1 MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 12-33 12.4.2.6 Small Accesses (Small Port Size and Short Burst Length) In this context, a small access refers to an access whose burst length and port size are such that the number of bytes requested by the internal master cannot all be fetched (or written) in one external transaction. This is the case when the base register’s burst length bit (EBI_BRn[BL]) and port size bit (EBI_BRn[PS]) are set such that one of two situations occur: • Burst accesses are inhibited and the number of bytes requested by the master is greater than the port size (16) can accommodate in a single access. • Burst accesses are enabled and the number of bytes requested by the master is greater than the selected burst length (8 words). If this is the case, the EBI initiates multiple transactions until all the requested data is transferred. All the transactions initiated to complete the data transfer are considered as an atomic transaction, so the EBI does not allow other unrelated master accesses to intervene between the transfers. Table 12-12 shows all the combinations of burst length, port size, and requested byte count that cause the EBI to run multiple external transactions to fulfill the request. Table 12-12. Small Access Cases Byte Count Requested by Internal Master Burst Length Port Size # External Accesses to Fulfill Request Non-burstable Chip-Select Banks (BI = 1) or Non-Chip-Select Access 4 1 beat 16-bit 11 8 1 beat 16-bit 4 32 1 beat 16-bit 16 Burstable Chip-Select Banks (BI = 0) 32 (8 words) 1 8 beats 16-bit 2 16-bit data bus mode (DBM = 1), one 2-beat burst access is performed and this is not considered a small access case. See Section 12.4.2.11, “Non-Chip-Select Burst in 16-bit Data Bus Mode” for this special DBM = 1 case. In most cases, the timing for small accesses is the same as for normal single-beat and burst accesses, except that multiple back-to-back external transfers are executed for each internal request. These transfers have no additional dead cycles between external accesses that are not present for back-to-back stand-alone transfers except for the case of writes with an internal request size greater than 64 bits. See Section 12.4.2.6.2, “Small Access Example #2: 32-byte Write with External TA.” The following sections show a few examples of small accesses. The timing for the remaining cases in Table 12-12 can be extrapolated from these and the other timing diagrams in this document. MPC5533 Microcontroller Reference Manual, Rev. 0 12-34 Freescale Semiconductor 12.4.2.6.1 Small Access Example #1: 32-bit Write to 16-bit Port Figure 12-27 shows an example of a 32-bit write to a 16-bit port, requiring two 16-bit external transactions. CLKOUT ADDR[8:31] A A+2 RD_WR BDIP TS DATA[0:15] DATA is valid DATA is valid ABCDXXXX EFGHXXXX TA CS[n] WE Figure 12-27. Single-beat 32-bit Write Cycle, 16-bit Port Size, Basic Timing 12.4.2.6.2 Small Access Example #2: 32-byte Write with External TA Figure 12-28 shows an example of a 32-byte write to a non-chip select device, such as an external master, using external TA, requiring eight 32-bit external transactions. Due to the use of external TA, RD_WR does not toggle between the accesses unless that access is the end of a 64-bit boundary. In this case, an extra cycle is required between TA and the next TS to get the next 64-bits of write data internally and RD_WR negates during this extra cycle. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 12-35 CLKOUT A ADDR[8:31] A + 0x0004 A + 0x0008 A+0x000C RD_WR BDIP TS 1 DATA is valid 2 DATA is valid * 3 DATA is valid 4** DATA[0:15] TA CS[n] WE * This extra cycle is required after accesses 2, 4, and 6 to get the next 64-bits of internal write data. ** Four more external accesses (not shown) are required to complete the internal 32-byte request. The timing of these is the same as accesses 1–4 shown in this diagram. Figure 12-28. 32-Byte Write Cycle with External TA, Basic Timing 12.4.2.7 Size, Alignment, and Packaging on Transfers Table 12-13 shows the allowed sizes that an internal or external master can request from the EBI. The behavior of the EBI for request sizes not shown below is undefined. No error signal is asserted for these erroneous cases. Table 12-13. Transaction Sizes Supported by EBI Number of Bytes Internal Master External Master 1 1 2 2 4 4 8 32 Even though misaligned non-burst transfers from internal masters are supported, the EBI naturally aligns the accesses when it sends them out to the external bus, splitting them into multiple aligned accesses if necessary. Natural alignment for the EBI means: • Byte access can have any address. • 16-bit access, address bit 31 must be 0. MPC5533 Microcontroller Reference Manual, Rev. 0 12-36 Freescale Semiconductor • • 32-bit access, address bits 30–31 must be 0. For burst accesses of any size, address bits 29–31 must be 0. The EBI never generates a misaligned external access, so a multi-master system with two MCUs can never have a misaligned external access. In the erroneous case that an externally-initiated misaligned access does occur, the EBI errors the access and does not initiate the access on the internal bus. The EBI requires that the portion of the data bus used for a transfer to/from a particular port size be fixed. A 16-bit port must reside on bits 0–15. In the following figures and tables the following convention is adopted: • The most significant byte of a 32-bit operand is OP0, and OP3 is the least significant byte. • The two bytes of a 16-bit operand are OP0 (most significant) and OP1, or OP2 (most significant) and OP3, depending on the address of the access. • The single byte of a byte-length operand is OP0, OP1, OP2, or OP3, depending on the address of the access. The convention can be seen in Figure 12-29. 0 16-bit 15 OP0 OP1 16 31 OP2 OP3 0 Byte OP0 OP1 OP2 31 OP3 Figure 12-29. Internal Operand Representation Table 12-14 lists the bytes required on the data bus for read cycles. The bytes indicated as ‘—’ are not required during that read cycle. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 12-37 Table 12-14. Data Bus Requirements for Read Cycles Transfer Size SIZE [0:1] 8 bits 16 bits 32 bits 1 Address 16-Bit Port Size A[30] A[31] D[0:7] D[8:15] 01 0 0 OP0 — 01 0 1 — OP1 01 1 0 OP2 — 01 1 1 — OP3 10 0 0 OP0 OP1 10 1 0 OP2 OP3 00 0 0 OP0 and OP2 1 OP1 and OP3 This case consists of two 16-bit external transactions, the first fetching OP0 and OP1, the second fetching OP2 and OP3. Table 12-15 lists the patterns of the data transfer for write cycles when accesses are initiated by the MCU. The bytes indicated as ‘—’ are not driven during that write cycle. Table 12-15. Data Bus Contents for Write Cycles SIZE[0:1] 8 bits 16 bits 32 bits 1 2 12.4.2.8 16-Bit Port Size1 Address Transfer Size A[30] A[31] D[0:7] D[8:15] 01 0 0 OP0 — 01 0 1 — OP1 01 1 0 OP2 — 01 1 1 — OP3 10 0 0 OP0 OP1 10 1 0 OP2 OP3 00 0 0 OP0 and OP2 2 OP1 and OP3 DBM = 1 for 16-bit data bus mode. This case consists of two 16-bit external transactions, the first writing OP0 and OP1, the second writing OP2 and OP3. Arbitration This device does not have arbitration pins, so multi-master operation with arbitration is not supported. However, limited dual-MCU functionality is supported for the case of a Master and Slave configuration. See Section 12.5.5, “Dual-MCU Operations.” MPC5533 Microcontroller Reference Manual, Rev. 0 12-38 Freescale Semiconductor 12.4.2.9 Termination Signals Protocol The termination signals protocol was defined to avoid electrical contention on lines that can be driven by various sources. To do that, a slave must not drive signals associated with the data transfer until the address phase is completed and it recognizes the address as its own. The slave must disconnect from signals immediately after it acknowledges the cycle and not later than the termination of the next address phase cycle. For EBI-mastered non-chip select accesses, the EBI requires assertion of TA from an external device to signal that the bus cycle is complete. The EBI uses a latched version of TA (1 cycle delayed) for these accesses to help make timing at high frequencies. This results in the EBI driving the address and control signals 1 cycle longer than required, as seen in Figure 12-37. However, the DATA does not need to be held 1 cycle longer by the slave, because the EBI latches DATA every cycle during non-chip select accesses. During these accesses, the EBI does not drive the TA signal, leaving it up to an external device (or weak internal pull-up) to drive TA. For EBI-mastered chip select accesses, the EBI drives TA the entire cycle, asserting according to internal wait state counters to terminate the cycle. During idle periods on the external bus, the EBI drives TA negated as long as it is granted the bus; when it no longer owns the bus it lets go of TA. When an external master does a transaction to internal address space, the EBI only drives TA for the cycle it asserts TA to return data and for 1 cycle afterwards to ensure fast negation. Table 12-16 summarizes how the EBI recognizes the termination signals provided from an external device. Table 12-16. Termination Signals Protocol TA1 Negated X Asserted 1 Action No termination Transfer error termination Normal transfer termination Latched version (1 cycle delayed) used for externally driven TA. 12.4.2.10 Bus Operation in External Master Mode External master mode enables an external master to access the internal address space of the MCU. Figure 12-30 shows how to connect an MCU to an external master (a second MCU) and a shared SDR memory to operate in external master mode. Limited support for external master accesses (master/slave systems only) is available in this device. See Section 12.5.5, “Dual-MCU Operations.” MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 12-39 Master MCU Slave MCU Configured for internal arbitration Configured for external arbitration CLKOUT CS[0] TS WE/BE[0] ADDR[8:31]* DATA[0:15] BDIP RD_WR TA EXTAL CS[0] TS WE/BE[0] ADDR[8:31]* DATA[0:15] BDIP RD_WR TA SDR Memory CK CS ADV BAA WE A[0:21] DATA[0:15] * Only ADDR[8:29] are connected to the 32-bit SDR memory. Figure 12-30. MCU Connected to External Master and SDR Memory When the external master requires external bus accesses, it takes ownership on the external bus, and the direction of most of the bus signals is inverted, relative to its direction when the MCU owns the bus. Most of the bidirectional signals shown in Figure 12-30 are only driven by the EBI when the EBI owns the external bus. The only exception is the TA signal and the DATA bus, which are driven by the EBI for external master reads to internal address space. As long as the external master device follows the same protocol for driving signals as this EBI, there is no need to use the open drain mode of the pads configuration module for any EBI pins. See Section 12.4.2.9, “Termination Signals Protocol” for more information. The Power Architecture storage reservation protocol is not supported by the EBI. Coherency between multiple masters must be maintained via software techniques, such as event passing. MPC5533 Microcontroller Reference Manual, Rev. 0 12-40 Freescale Semiconductor The EBI does not provide memory controller services to an external master that accesses shared external memories. Each master must correctly configure its own memory controller and drive its own chip selects when sharing a memory between two masters. The EBI does not support burst accesses from an external master; only single accesses of 8-, 16-, or 32-bits can be performed.1 12.4.2.10.1 Address Decoding for External Master Accesses The EBI allows external masters to access internal address space when the EBI is configured for external master mode. The external address is compared for any external master access, to determine if EBI operation is required. Because only 24 address bits are available on the external bus, special decoding logic is required to allow an external master to access on-chip locations whose upper eight address bits are non-zero. This is done by using the upper four external address bits (ADDR[8:11]) as a code to determine whether the access is on-chip and if so, for which internal slave it is targeted. The options for the address compare sequence are explained in the following bullets: • External master access to another device — If ADDR[8] = 0, then the access is assumed to be to another device and is ignored by the EBI. • External master access to valid internal slave — If ADDR[8] = 1, then ADDR[9:11] are checked versus a list of 3-bit codes to determine which internal slave to forward the access to. The upper 8 internal address bits are set appropriately by the EBI according to this 3-bit code, and internal address bits [8:11] are set appropriately to match the internal slave selected. • External master access to invalid internal slave — If the 3-bit code does not match a valid internal slave, then the EBI responds with a bus error. 1. Except for the special case of a 32-bit non-chip select access in 16-bit data bus mode. See Section 12.4.2.11, “Non-Chip-Select Burst in 16-bit Data Bus Mode”. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 12-41 Table 12-17 shows the possible 3-bit codes that are associated with various slaves in the MCU, as well as the resulting upper 12 address bits required to appropriately match up with the memory map of each internal slave. Table 12-17. EBI Internal Slave Address Decoding External ADDR[8:11]1 Internal ADDR[0:7]2 Internal ADDR[8:11]3 (off-chip) 0b0xxx — — Internal flash 0b10xx 0b0000_0000 0b00, ADDR[10:11] Internal SRAM 0b1100 0b0100_0000 0b0000 Reserved 0b1101 0b0110_0000 0b0000 Bridge A peripherals 0b1110 0b1100_0011 0b1111 Bridge B peripherals 0b1111 0b1111_1111 0b1111 Internal Slave 1 Value on upper 4 bits of 24-bit external address bus ADDR[8:31]. ADDR[8] determines whether the access is on or off chip. 2 Value on upper 8 bits of 32-bit internal address bus. 3 Value on bits 8:11 of 32-bit internal address bus. 12.4.2.10.2 Bus Transfers Initiated by an External Master The external master gets ownership of the bus and asserts TS to initiate an external master access. The access is directed to the internal bus only if the input address matches to the internal address space. The access is terminated with TA. If the access was successfully completed, the MCU asserts TA, and the external master can proceed with another external master access, or relinquish the bus. MPC5533 Microcontroller Reference Manual, Rev. 0 12-42 Freescale Semiconductor Figure 12-31 and Figure 12-32 illustrate the basic flow of read and write external master accesses. External Master EBI (Slave) Receives address Address in internal memory map ? Yes No Other shared device Drives data Asserts transfer acknowledge (TA) Drives data Asserts transfer acknowledge (TA) Receives data Figure 12-31. Basic Flow Diagram of an External Master Read Access (EARB = 1) External Master EBI (Slave) Receives address Drives data Receives data No Other shared device asserts transfer acknowledge (TA) Address in internal memory map ? Yes Asserts transfer acknowledge (TA) Receives data Figure 12-32. Basic Flow Diagram of an External Master Write Cycle (EARB = 1) MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 12-43 Figure 12-33 and Figure 12-34 describe read and write cycles from an external master accessing internal space in the MCU. The minimal latency for an external master access is three clock cycles. The actual latency of an external to internal cycle varies depending on which internal module is being accessed and how much internal bus traffic is going on at the time of the access. CLKOUT ADDR[8:31] RD_WR BDIP TS (input) DATA[0:15] TA (output) Minimum 2 wait states DATA is valid Figure 12-33. External Master Read from MCU CLKOUT ADDR[8:31] RD_WR BDIP TS (input) DATA is valid ** DATA[0:15] TA (output) Minimum 2 wait states DATA is valid ** If the external master is another MCU with this EBI, then DATA remains valid as shown due to use of latched TA internally. These extra data valid cycles (past TA) are not required by the slave EBI. Figure 12-34. Basic Flow Diagram of an EBI Read Access in External Master Mode (EARB = 0) MPC5533 Microcontroller Reference Manual, Rev. 0 12-44 Freescale Semiconductor CLKOUT ADDR[8:31] RD_WR BDIP TS DATA[0:15] TA DATA is valid CS[n] OE Figure 12-35. Single-Beat CS Read Cycle in External Master Mode, Zero Wait States 12.4.2.11 Non-Chip-Select Burst in 16-bit Data Bus Mode The timing diagrams in this section apply only to the special case of a non-chip select 32-bit access in 16-bit data bus mode. They specify the behavior for both the EBI-master and EBI-slave, as the external master is expected to be another MCU with this EBI. For this case, a special two-beat burst protocol is used for reads and writes, so that the EBI-slave can internally generate one 32-bit read or write access (thus 32-bit coherent), as opposed to two separate 16-bit accesses. Figure 12-36 shows a 32-bit read from an external master in 16-bit data bus mode. Figure 12-37 shows a 32-bit write from an external master in 16-bit data bus mode. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 12-45 CLKOUT ADDR[8:31] RD_WR BDIP TS (Input) DATA[0:15] TA (Output) Minimum 2 wait states DATA is valid DATA is valid Figure 12-36. External Master 32-bit Read from MCU with DBM = 1 CLKOUT ADDR[8:31] RD_WR BDIP TS (Input) DATA is valid DATA is valid DATA[0:15] TA (Output) Minimum 3 wait states Figure 12-37. External Master 32-bit Write to MCU with DBM=1 MPC5533 Microcontroller Reference Manual, Rev. 0 12-46 Freescale Semiconductor 12.5 Initialization and Application Information NOTE The 208 package does not have an external bus interface. This chapter pertains to the 324 package only. 12.5.1 Booting from External Memory The EBI block does not support booting directly from external memory (fetching the first instruction after an external RESET). The MCU uses an internal boot assist module (BAM), which executes after each reset and configures the EBI block, allowing for external boot if desired. See Chapter 15, “Boot Assist Module (BAM),” for detail information about the boot modes supported by the MCU. Do not modify the EBI registers during external accesses. If external memory must write to the EBI registers, avoid modifying EBI registers: • Copy the code that writes to the EBI registers (plus the return branches) to internal SRAM • Branch to internal SRAM to run the code, ending with a branch back to external memory 12.5.2 Running with SDR (Single Data Rate) Burst Memories This includes flash and external SRAM memories with a compatible burst interface. BDIP is required only for some SDR memories. Figure 12-36 shows a block diagram of an MCU connected to a 32-bit SDR burst memory. MCU CLKOUT CAL_CS[0] *** CS[0] TS BDIP WE/BE[0] ADDR[8:29] DATA[0:15] OE SDR burstable flash or SRAM 4M x 32 CK CE ADV BAA* WE** ADDR[0:21] DATA[0:15] OE * Connection depending on the type of memory. ** Flash memories typically use one WE signal as shown, RAMs use 2 (16-bit). *** Not available on all devices, see the Signals chapter. Figure 12-38. MCU Connected to SDR Burst Memory See Figure 12-23 for an example of the timing of a typical burst read operation to an SDR burst memory. See Figure 12-24 for an example of the timing of a typical single write operation to SDR memory. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 12-47 12.5.3 Using Asynchronous Memory The EBI supports asynchronous memory, even though the EBI does not have an asynchronous mode. Asynchronous memories do not support bursting, and do not require the CLKOUT, TS, and BDIP signals. The EBI drives the output, and latches all signals at the positive edge of CLKOUT. The data timing is controlled by setting the SCY bits in the option register to a valid number of wait states for the access time to asynchronous memory. 12.5.3.1 Example Wait State Calculation This example applies to any chip select memory, synchronous or asynchronous. As an example, say we have a memory with 50 ns access time, and we are running the external bus at 66 MHz (CLKOUT period: 15.2 ns). When the input data specification for the MCU is 4 ns: Number of wait states = (access time) ÷ (CLKOUT period) + (0 or 1) (depending on setup time) 50 ÷ 15.2 = 3 with 4.4 ns remaining (minimum of three wait states, then check setup time) 15.2 - 4.4 = 10.8 ns (this is the achieved input data setup time) Because actual input setup (10.8 ns) is greater than the input setup specification (4.0 ns), three wait states is sufficient. If the input setup is less than 4.0 ns, use four wait states. 12.5.3.2 Timing and Connections for Asynchronous Memories The connections to an asynchronous memory are the same as for a synchronous memory, except that the CLKOUT, TS, and BDIP signals are not used. Figure 12-39 shows a block diagram of an MCU connected to an asynchronous memory. MCU 2 Asynchronous Memory CAL_CS[0] CS[0] WE/BE[0] WE 1 ADDR[9:30] A[0:21] DATA[0:15] D[0:15] OE 1 CE OE Flash memories typically use WE[0] signal as shown, RAMs use two (WE/BE[0:1]). available on all devices, see the Signals chapter. 2 Not Figure 12-39. MCU Connected to Asynchronous Memory Figure 12-40 shows a timing diagram of a read operation to a 16-bit asynchronous memory using three wait states. Figure 12-41 shows a timing diagram of a write operation to a 16-bit asynchronous memory using three wait states. MPC5533 Microcontroller Reference Manual, Rev. 0 12-48 Freescale Semiconductor CLKOUT CS[n] TS ADDR[8:31] OE WE[0:1] DATA[0:15] TA 3 wait states DATA is valid Figure 12-40. Read Operation to Asynchronous Memory, Three Initial Wait States CLKOUT CS[n] TS ADDR[8:31] WE[0:1] OE DATA is valid DATA[0:15] TA 3 wait states Figure 12-41. Write Operation to Asynchronous Memory, Three Initial Wait States MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 12-49 12.5.4 Connecting an MCU to Multiple Memories The MCU can be connected to more than one memory at a time. Figure 12-42 shows an example of how two memories can be connected to one MCU. SDR Memory MCU CLKOUT CS[0] TS WE/BE[0] ADDR[8:29] DATA[0:15] OE BDIP CK CE ADV WE** ADDR[0:21] DATA[0:15] OE BAA* SDR Memory CS[1] WE/BE[1] CK CE ADV A[0:21] WE** BAA* DATA[0:15] OE * The connection depends on the memory used. ** Flash memories typically use WE[0] signal as shown, RAMs use two (WE/BE[0:1]). Figure 12-42. MCU Connected to Multiple Memories 12.5.5 Dual-MCU Operations This section describes how to configure dual-MCU systems when a signal or pin is not available. More than one section can apply if the signals or pins are not present on one or both MCUs. 12.5.5.1 Connecting 16-bit MCU to 32-bit MCU (Master and Slave) Connect DATA[0:15] between both MCUs, and configure both for 16-bit data bus mode operation (DBM=1 in EBI_MCR). Does not support 32-bit external memories. MPC5533 Microcontroller Reference Manual, Rev. 0 12-50 Freescale Semiconductor 12.5.5.2 Arbiting a Master and Slave configuration A dual master system is not supported, because the two masters have no method to arbitrate access to the external bus without conflicts. However, you can configure a master/slave system for arbitration. To implement a master/slave system, you must configure the master MCU for internal arbitration (EARB=0 in EBI_MCR) and the slave MCU for external arbitration (EARB=1). The slave MCU never attempts to start an access on the external bus. The master MCU maintains control of the bus without arbitration delays. If the slave MCU executes internal code to access an external address, the access never completes and eventually times-out in the slave MCU. 12.5.5.3 Setting the Transfer Size To set the block size the Master uses to access the slave device, set the SIZEN bit in the internal SIZE field of the EBI_MCR for the slave MCU. To access the slave MCU using a different block size, the Master MCU must first write the block transfer size to the slave MCU’s SIZE field before processing subsequent transaction. 12.5.5.4 Acknowledging a Transfer You must configure the chip select and external memory to access valid chip select regions only. This ensures the EBI latches the data to the correct cycle count for the valid chip region. The EBI does not have built-in protection to prevent external accesses to invalid chip and memory regions. Without logic to identify the valid chip region, the EBI cannot latch the data to the correct cycle. 12.5.5.5 Detecting a Transfer Error If an access times out in the EBI bus monitor, the EBI (master) terminates the access early, but the MCU does not detect the access termination. Therefore, the slave device can drive the data much later, colliding with a subsequent access that is already underway. Therefore, disable the EBI bus monitor. 12.5.5.6 Detecting Burst Data in Progress If an MCU does not have a BDIP signal, burst support is available if the memory does not require BDIP to support data burst. Many external memories use a self-timed configurable burst mechanism that does not require a dynamic burst indicator. Check the applicable external memory specification to see if BDIP is required. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 12-51 12.5.6 Summary of Differences from MPC500 The following summary lists of the significant differences between this EBI used in the MPC5500 devices and that of the MPC500 devices: • SETA feature not supported: chip select devices cannot use the external TA signal, instead must use wait state configuration. • No memory controller support for external masters: no support for multi-master system to drive its own chip selects • Changes in bit fields: — Removed these variable timing attributes from the option register: CSNT, ACS, TRLX, EHTR — Removed LBDIP base register bit, now late BDIP assertion is the default — The BL field of the base register has inverted logic from the MPC56x devices (0 = 8-beat burst on the MPC5500, 1 = 8-beat burst on the MPC56x) • Removed reservation support on external bus • Removed address type (AT), write-protect (WP), and dual-mapping features because these functions can be replicated by memory management unit (MMU) in e200z3 core • Removed support for 8-bit ports • Removed boot chip select operation: on-chip boot assist module (BAM) handles boot (and configuration of EBI registers) • Added support for 32-bit coherent read and write non-chip select accesses in 16-bit data bus mode • Misaligned accesses are not supported • Removed support for 3-master systems MPC5533 Microcontroller Reference Manual, Rev. 0 12-52 Freescale Semiconductor Chapter 13 Flash Memory 13.1 Introduction This section provides information about the flash bus interface unit (FBIU) and the flash memory block. 13.1.1 Block Diagram Figure 13-1 shows a block diagram of the flash memory module. The FBIU is addressed through the system bus while the flash control and status registers are addressed through the slave (peripheral) bus. VSS VFLASH1 VDD VPP Flash Memory Block System Bus 1 V is not available on FLASH the 208 package. Flash Bus Interface Unit (FBIU) Flash Memory Interface (MI) Control/Status Registers Slave Bus Flash Core Figure 13-1. Flash System Block Diagram 13.1.2 Overview The flash module serves as electrically programmable and erasable non-volatile memory (NVM) that is ideal for program and data storage for single-chip applications allowing for field reprogramming without requiring external programming voltage sources. The module is a solid-state silicon memory device consisting of blocks of single-transistor storage elements. The device flash contains a flash bus interface unit (FBIU) and a flash memory array. The flash BIU interfaces the system bus to a dedicated flash memory array controller. The FBIU supports a 64-bit data bus width at the system bus port, and a 128-bit read data interface from the flash memory array. If enabled, the flash BIU contains a four-entry prefetch buffer, each entry containing 128 bits of data, and an associated controller that prefetches sequential lines of data from the flash array into the buffer. Prefetch MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 13-1 buffer hits support zero-wait responses. Normal flash array accesses (accesses that don’t go to the prefetch buffers) are registered in the FBIU in a single cycle, and are forwarded to the system bus on the next cycle, incurring at least two wait states (depending on the frequency). Additional wait states are indicated in FLASH_BUICR[RWSC]. See Table 13-14 for more information. The flash memory block is arranged as two functional units, the first being the flash core. The flash core is composed of arrayed non-volatile storage elements, sense amplifiers, row selects, column selects, charge pumps, ECC logic and redundancy logic. The arrayed storage elements in the flash core are subdivided into physically separate units referred to as blocks. The second functional unit of flash memory is the memory interface (MI). The MI contains the registers and logic that control the operation of the flash core. The MI is also the interface between the flash module and the FBIU. The FBIU connects the MCU system bus to the flash module, and provides all system level customization and configuration functionality. The flash array has three address spaces. Low address space (LAS) is 256-KB in size. Mid address space (MAS) is also 256-KB in size. High address space (HAS) is 256 KB in size. Total address space is 768 KB. Flash Array Blocks Low Address Space—256 KB Low Address Space Mid Address Space—256 KB Mid Address Space High Address Space— 256 KB High Address Space Figure 13-2. Flash Array Diagram MPC5533 Microcontroller Reference Manual, Rev. 0 13-2 Freescale Semiconductor 13.1.3 Features The following list summarizes the key features of the FBIU: • The FBIU system bus interface supports a 64-bit data bus. All byte, halfword, word, and doubleword reads are supported. Only aligned word and doubleword writes are supported. • The flash array interface supports a 128-bit read data bus and a 64-bit write data bus. • The FBIU provides configurable read buffering and line prefetch support. Four line read buffers (each 128 bits wide) and a prefetch controller are used to support single-cycle read responses (zero wait-states) for hits in the buffers. • The FBIU provides hardware and software configurable read and write access protections on a per-master basis. • The FBIU interface to the flash array is pipelined with a depth of 1. • The FBIU allows configurable access timing. • The FBIU provides multiple-mapping support and mapping-based block access timing allowing use for emulation of other memory types. The flash memory array has the following features: • Software programmable block program/erase restriction control for low, mid, and high address spaces. • Erase of selected blocks. • ECC with single-bit correction, double-bit detection. • Page program size of 128 bits allows programming from one to two consecutive 64-bit doublewords in a page. • Embedded hardware program and erase algorithm. • Read while write with multiple partitions. • Stop mode for low-power stand-by. • Erase suspend, program suspend, and erase-suspended program. • Automotive flash that meets automotive endurance and reliability requirements. Shadow information is stored in a non-volatile shadow block. • Independent program/erase of the shadow block. 13.1.4 13.1.4.1 Modes of Operation User Mode User mode is the default operating mode of the flash memory block. In this mode, you can read, write, program, and erase the flash. See Section 13.4.2, “Flash Memory Array: User Mode.” 13.1.4.2 Stop Mode In stop mode (FLASH_MCR[STOP] = 1), all DC current sources in the flash are disabled. See Section 13.4.3, “Flash Memory Array: Stop Mode.” MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 13-3 13.2 External Signal Description Table 13-1 shows a list of signals required for flash. Table 13-1. Signal Properties 13.2.1 Name Function Reset State VFLASH Flash read power supply — VPP Flash program/erase power supply — Voltage for Flash Only VFLASH VFLASH is a supply required for reads of the flash core. This voltage is specified as 3.3 V with a tolerance of ± 0.3 V. 208 Package: 13.2.2 The VFLASH pin is not available on the 208 package. Program and Erase Voltage for Flash Only VPP VPP is a supply required for program and erase of the flash core. This voltage is specified as 5 V with a tolerance of -0.5 V to +0.25 V during program and erase operations. VPP is required at all times, even during normal reads of flash memory. During read operations, VPP can be as high as 5.3 V and as low as 3.0 V. 13.3 Memory Map/Register Description The flash BIU occupies a 512-MB portion of the address space. The actual flash array is multiply-mapped within this space. The MCU internal flash has a feature that allows the internal flash timing to be modified to emulate an external memory, hence the name, external emulation mode. The upper five address lines are used to provide additional timing control that allows the FBIU response timing on the system bus (which must be controlled to provide for timing emulation of alternate memory types). See Figure 13-3. 0bYYYYY_0000_0000_0000_0000_0000_0000 – 0bYYYYY_1111_1111_1111_1111_1111_1111 Flash array access or flash shadow block access YYYYY – Additional primary wait-states Figure 13-3. Flash BIU Address Scheme This feature allows calibration parameters to be tested using an external memory; and then in production, the internal flash access timing is modified to match timing of the external memory. The access time of the internal flash is lengthened based on the address range being accessed. To access an area with a slower access time, the address is modified per Table 13-2. MPC5533 Microcontroller Reference Manual, Rev. 0 13-4 Freescale Semiconductor Table 13-2. Internal Flash External Emulation Mode Address Range YYYYY Wait States 0x0000_0000 0x001F_FFFF 00000 0 0x0100_0000 0x011F_FFFF 01000 8 0x0200_0000 0x021F_FFFF 10000 16 0x0300_0000 0x031F_FFFF 11000 24 0x0400_0000 0x041F_FFFF 00001 1 0x0500_0000 0x051F_FFFF 01001 9 0x0600_0000 0x061F_FFFF 10001 17 0x0700_0000 0x071F_FFFF 11001 25 0x0800_0000 0x081F_FFFF 00010 2 0x0900_0000 0x091F_FFFF 01010 10 0x0A00_0000 0x0A1F_FFFF 10010 18 0x0B00_0000 0x0B1F_FFFF 11010 26 0x0C00_0000 0x0C1F_FFFF 00011 3 0x0D00_0000 0x0D1F_FFFF 01011 11 0x0E00_0000 0x0E1F_FFFF 10011 19 0x0F00_0000 0x0F1F_FFFF 11011 27 0x1000_0000 0x101F_FFFF 00100 4 0x1100_0000 0x111F_FFFF 01100 12 0x1200_0000 0x121F_FFFF 10100 20 0x1300_0000 0x131F_FFFF 11100 28 0x1400_0000 0x141F_FFFF 00101 5 0x1500_0000 0x151F_FFFF 01101 13 0x1600_0000 0x161F_FFFF 10101 21 0x1700_0000 0x171F_FFFF 11101 29 0x1800_0000 0x181F_FFFF 00110 6 0x1900_0000 0x191F_FFFF 01110 14 0x1A00_0000 0x1A1F_FFFF 10110 22 0x1B00_0000 0x1B1F_FFFF 11110 30 0x1C00_0000 0x1C1F_FFFF 00111 7 0x1D00_0000 0x1D1F_FFFF 01111 15 0x1E00_0000 0x1E1F_FFFF 10111 23 0x1F00_0000 0x1F1F_FFFF 11111 31 MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 13-5 13.3.1 Flash Memory Map Table 13-3 shows the flash array memory map and how it is mapped using byte addressing. Base addresses for the device are the following: • Shadow base address = 0x00FF_FC00 • Array base address = 0x0000_0000 • Control registers base address = 0xC3F8_8000 Table 13-3. Module Flash Array Memory Map Byte Address Type and Amount of Space Used Access Shadow base + (0x0000_0000–0x0000_03FF) Shadow block space (1024 bytes) User Array base + (0x0000_0000–0x0003_FFFF) Low address space (256 KB) User Array base + (0x0004_0000–0x0007_FFFF) Mid address space (256 KB) User Array base + (0x0008_0000–0x000F_FFFF) High address space (256 KB) User Table 13-4 shows how the array is partitioned into three address spaces — low, mid, and high — and into partitions and blocks. Table 13-4. Flash Partitions Address (Array base + offset) Block Bytes Partition Low 0 16 KB 1 Array Base + 0x0000_4000 Low 1 48 KB Array Base + 0x0001_0000 Low 2 48 KB Array Base + 0x0001_C000 Low 3 16 KB Array Base + 0x0002_0000 Low 4 64 KB Array Base + 0x0003_0000 Low 5 64 KB Med 0 128 KB Med 1 128 KB High 0 128 KB High 1 128 KB Array Base + 0x0000_0000 Array Base + 0x0004_0000 Use Low address space Mid address space Array Base + 0x0006_0000 Array Base + 0x0008_0000 High address space Array Base + 0x000A_0000 2 3 4 Array Base + 0x00FF_FC00 Shadow block space, general use Shadow 472 All 1 Array Base + 0x00FF_FDD8 Flash shadow block, serial passcode Shadow 8 All 1 Array Base + 0x00FF_FDE0 Flash shadow block, control word Shadow 4 All 1 Array Base + 0x00FF_FDE4 General use Shadow 4 All 1 Array Base + 0x00FF_FDE8 Flash shadow block, FLASH_LMLR reset configuration Shadow 4 All 1 Array base + 0x00FF_FDEC General use Shadow 4 All 1 Array base + 0x00FF_FDF0 Flash shadow block, FLASH_HLR reset configuration Shadow 4 All 1 Array base + 0x00FF_FDF4 General use Shadow 4 All 1 MPC5533 Microcontroller Reference Manual, Rev. 0 13-6 Freescale Semiconductor Table 13-4. Flash Partitions (Continued) Address (Array base + offset) Use Block Bytes Partition Array base + 0x00FF_FDF8 Flash shadow block, FLASH_SLMLR reset configuration Shadow 4 All 1 Array base + 0x00FF_FE00 Flash shadow block, FLASH_BIUCR2 reset configuration Shadow 4 All 1 Shadow 508 All 1 Array base + 0x00FF_FE04–0x00FF_FFFF General use 1 The shadow block does not support RWW. See Section 13.4.2.5, “Flash Shadow Block.” Table 13-5 shows the register set for the flash module. Table 13-5. Module Register Memory Map Byte Address Register Name Register Description Bits Register Base + 0x0000 FLASH_MCR Module configuration register 32 Register Base + 0x0004 FLASH_LMLR Low/mid address space block locking register 32 Register Base + 0x0008 FLASH_HLR High address space block locking register 32 Register Base + 0x000C FLASH_SLMLR Secondary low/mid address space block locking register 32 Register Base + 0x0010 FLASH_LMSR Low/mid address space block select register 32 Register Base + 0x0014 FLASH_HSR High address space block select register 32 Register Base + 0x0018 FLASH_AR Address register 32 Register Base + 0x001C FLASH_BIUCR Flash bus interface unit control register 32 Register Base + 0x0020 FLASH_BIUAPR Flash bus interface unit access protection register 32 Register Base + 0x0024 FLASH_BIUCR2 Flash bus interface unit control register 2 32 Reserved — Register Base + (0x0028–0x7FFF) 13.3.2 — Register Descriptions The flash registers are detailed in the following sections. 13.3.2.1 Module Configuration Register FLASH_MCR A number of module configuration register (FLASH_MCR) bits are protected from a write while another bit or set of bits are in a specific state. These locks are discussed in relationship to each bit in this section. Simultaneously writing bits which lock each other out is discussed in Section 13.3.2.1.1, “MCR Simultaneous Register Writes.” The MCR is always available to be read except when the flash module is disabled. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 13-7 Address: Base (0xC3F8_8000) + 0x0000 R 0 1 2 3 0 0 0 0 0 0 0 0 Access: User R/W 4 5 6 7 SIZE 8 9 0 10 11 LAS 12 13 14 15 0 0 0 MAS W Reset 17 18 19 R EER 16 RWE 1 1 W w1c w1c 1 1 Reset 0 0 0 0 1 1 0 1 1 0 0 0 0 0 20 21 22 238 24 25 26 27 28 29 30 31 PEAS DONE PEG 0 1 1 0 0 PRD STOP 0 0 0 0 PGM PSUS ERS ESUS EHV 0 0 0 0 0 Figure 13-4. Module Configuration Register (FLASH_MCR) Table 13-6. FLASH_MCR Field Descriptions Field 0–3 4–7 SIZE[0:3] 8 9–11 LAS[0:2] 12–14 Description Reserved Array space size. Dependent upon the size of the flash module. SIZE is read only. 0000–0010 Invalid value 0011 Total array size is 1.0 MB 0100–1111 Invalid value Reserved Low address space. The LAS field is read only (R/O). Indicates the memory configuration of the low address space. 110 Memory configuration: two 16-KB blocks, two 48-KB blocks, and two 64-KB blocks. Reserved 15 MAS Mid address space size. MAS is read only. Corresponds to the configuration of the mid address space. MAS is read only. 0 Two 128-KB blocks are available1Invalid value 16 EER ECC event error. Provides information on previous reads; if a double-bit detection occurred, the EER bit is set to 1. This bit must then be cleared, or a reset must occur before this bit returns to a 0 state. This bit cannot be set by the application. In the event of a single bit detection and correction, this bit is not set. If EER is not set, or remains 0, this indicates that all previous reads (from the last reset, or clearing of EER) were correct. Since this bit is an error flag, it must be cleared to a 0 by writing a 1 to the register location. A write of 0 has no effect. 0 Reads are occurring normally. 1 An ECC Error occurred during a previous read. Note: This bit can be set on speculative prefetches that cause double bit error detection. Therefore, use the ECSM[FNCE] flag for detecting non-correctable ECC errors in the flash instead of using FLASH_MCR[EER]. 17 RWE Read while write event error. Provides information on previous RWW reads. If a read while write error occurs, this bit is set to 1. This bit must then be cleared, or a reset must occur before this bit returns to a 0 state. This bit cannot be set to 1 by the application. If RWE is not set, or remains 0, this indicates that all previous RWW reads (from the last reset, or clearing of RWE) were correct. Since this bit is an error flag, it must be cleared to a 0 by writing a 1 to the register location. A write of 0 has no effect. 0 Reads are occurring normally. 1 A read while write error occurred during a previous read. 18–19 Reserved MPC5533 Microcontroller Reference Manual, Rev. 0 13-8 Freescale Semiconductor Table 13-6. FLASH_MCR Field Descriptions (Continued) Field Description 20 PEAS Program/erase access space. Indicates which space is valid for program and erase operations, either main array space or shadow space. PEAS is read only. 0 Shadow address space is disabled for program/erase and main address space enabled. 1 Shadow address space is enabled for program/erase and main address space disabled. 21 DONE State machine status. Indicates if the flash module is performing a high voltage operation. DONE is set to a 1 on termination of the flash module reset and at the end of program and erase high voltage sequences. 0 Flash is executing a high voltage operation. 1 Flash is not executing a high voltage operation. 22 PEG Program/erase good. Indicates the completion status of the last flash program or erase sequence for which high voltage operations were initiated. The value of PEG is updated automatically during the program and erase high voltage operations. Aborting a program/erase high voltage operation causes PEG to be cleared, indicating the sequence failed. PEG is set to a 1 when the module is reset. PEG is read only. The value of PEG is valid only when PGM = 1 and/or ERS = 1 and after DONE has transitioned from 0 to 1 due to an abort or the completion of a program/erase operation. PEG is valid until PGM/ERS makes a 1 to 0 transition or EHV makes a 0 to 1 transition. The value in PEG is not valid after a 0 to 1 transition of DONE caused by PSUS or ESUS being set to logic 1. A diagram presenting PEG valid times is presented in Figure 13-5. If PGM and ERS are both 1 when DONE makes a qualifying 0 to 1 transition the value of PEG indicates the completion status of the PGM sequence. This happens in an erase-suspended program operation. 0 Program or erase operation failed. 1 Program or erase operation successful. 23 Reserved 24 PRD Pipelined Reads Disabled. PRD is used to allow pipelined reads to be disabled. By default PRD is 0, which enables pipelined accesses. In systems with slower clocks (<30MHz), the pipelined read feature can be disabled by writing this bit to a 1. This allows single-cycle clock accesses in systems with a slower clock. In systems with faster clocks (>30MHz), accesses are multiple cycles, and the pipelined read feature can be used to get faster throughput on successive reads (PRD = 0). 1 Pipelined Reads are disabled. 0 Pipelined Reads are enabled. Note: PRD must be set before setting the flash wait states to 0 (done in FLASH_BIUCR) 25 STOP Stop mode enabled. Puts the flash into stop mode. Changing the value in STOP from a 0 to a 1 places the flash module in stop mode. A 1 to 0 transition of STOP returns the flash module to normal operation. STOP can be written only when PGM and ERS are low. When STOP = 1, only the STOP bit in the MCR can be written. In STOP mode all address spaces, registers, and register bits are deactivated except for the FLASH_MCR[STOP] bit. 0 Flash is not in stop mode; the read state is active. 1 Flash is in stop mode. 26 27 PGM Reserved Program. Used to set up flash for a program operation. A 0 to 1 transition of PGM initiates an flash program sequence. A 1 to 0 transition of PGM ends the program sequence. PGM can be set only under one of the following conditions: • User mode read (STOP and ERS are low). • Erase suspend1 (ERS and ESUS are 1) with EHV low. PGM can be cleared by you only when EHV are low and DONE is high. PGM is cleared on reset. 0 Flash is not executing a program sequence. 1 Flash is executing a program sequence. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 13-9 Table 13-6. FLASH_MCR Field Descriptions (Continued) Field Description 28 PSUS Program suspend. Indicates the flash module is in program suspend or in the process of entering a suspend state. The flash module is in program suspend when PSUS = 1 and DONE = 1. PSUS can be set high only when PGM and EHV are high. A 0 to 1 transition of PSUS starts the sequence which sets DONE and places the flash in program suspend. PSUS can be cleared only when DONE and EHV are high. A 1 to 0 transition of PSUS with EHV = 1 starts the sequence which clears DONE and returns the flash module to program. The flash module cannot exit program suspend and clear DONE while EHV is low. PSUS is cleared on reset. 0 Program sequence is not suspended. 1 Program sequence is suspended. 29 ERS Erase. Used to set up flash for an erase operation. A 0 to 1 transition of ERS initiates an flash erase sequence. A 1 to 0 transition of ERS ends the erase sequence. ERS can be set only in a normal operating mode read (STOP and PGM are low). ERS can be cleared by you only when ESUS and EHV are low and DONE is high. ERS is cleared on reset. 0 Flash is not executing an erase sequence. 1 Flash is executing an erase sequence. 30 ESUS Erase suspend. Indicates that the flash module is in erase suspend or in the process of entering a suspend state. The flash module is in erase suspend when ESUS = 1 and DONE = 1. ESUS can be set high only when ERS and EHV are high and PGM is low. A 0 to 1 transition of ESUS starts the sequence which sets DONE and places the flash in erase suspend. ESUS can be cleared only when DONE and EHV are high and PGM is low. A 1 to 0 transition of ESUS with EHV = 1 starts the sequence which clears DONE and returns the flash module to erase mode. The flash module cannot exit erase suspend and clear DONE while EHV is low. ESUS is cleared on reset. 0 Erase sequence is not suspended. 1 Erase sequence is suspended. 31 EHV Enable high voltage. Enables the flash module for a high voltage program/erase operation. EHV is cleared on reset. EHV must be set after an interlock write to start a program/erase sequence. EHV can be set, initiating a program/erase, after an interlock write under one of the following conditions: • Erase (ERS = 1, ESUS = 0). • Program (ERS = 0, ESUS = 0, PGM = 1, PSUS = 0). • Erase-suspended program (ERS = 1, ESUS = 1, PGM = 1, PSUS = 0). If a program operation is to be initiated while an erase is suspended you must clear EHV while in erase suspend before setting PGM. In normal operation, a 1 to 0 transition of EHV with DONE high, PSUS and ESUS low terminates the current program/erase high voltage operation. When an operation is aborted2, there is a 1 to 0 transition of EHV with DONE low and the suspend bit for the current program/erase sequence low. An abort causes the value of PEG to be cleared, indicating a failed program/erase; address locations being operated on by the aborted operation contain indeterminate data after an abort. A suspended operation cannot be aborted. EHV can be written during suspend. EHV must be high for the flash to exit suspend. Do not write the EHV bit after a suspend bit is set high and before DONE has transitioned high. Do not set the EHV bit low after the current suspend bit is set low and before DONE has transitioned low. 0 Flash is not enabled to perform a high voltage operation. 1 Flash is enabled to perform a high voltage operation. 1 In an erase-suspended program, programming flash locations in blocks which were being operated on in the erase can corrupt flash core data. Avoid this due to reliability implications. 2 Aborting a high voltage operation leaves flash core addresses in an indeterminate data state. This can be recovered by executing an erase on the affected blocks. MPC5533 Microcontroller Reference Manual, Rev. 0 13-10 Freescale Semiconductor FLASH_MCR[PGM/ERS] Abort Program/Erase FLASH_MCR[EHV] FLASH_MCR[DONE] FLASH_MCR[PEG] PEG Valid PEG Valid PEG Valid Figure 13-5. PEG Valid Times 13.3.2.1.1 MCR Simultaneous Register Writes A number of MCR bits are write-protected depending on the value of another bit or set of bits. These write locks are described in Section 13.3.2.1, “Module Configuration Register FLASH_MCR.” The write locks detailed in this section do not consider the effects of trying to write two or more bits simultaneously. The effect of writing bits simultaneously places the flash module in an invalid state. The flash does not allow you to write two or more bits simultaneously, which puts the device into an invalid state. This is implemented through a priority mechanism among the bits. The bit changing priorities are detailed in Table 13-7. Table 13-7. MCR Bit Set/Clear Priority Levels Priority Level MCR Bits 1 STOP 2 ERS 3 PGM 4 EHV 5 ESUS, PSUS If you try to write two or more MCR bits simultaneously then only the bit with the highest priority level is written. Setting two bits with the same priority level is prevented by existing write locks and does not put the flash in an invalid state. For example, setting FLASH_MCR[STOP] and FLASH_MCR[PGM] simultaneously results in only FLASH_MCR[STOP] being set. Attempting to clear FLASH_MCR[EHV] while setting FLASH_MCR[PSUS] results in FLASH_MCR[EHV] being cleared, while FLASH_MCR[PSUS] remains unaffected. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 13-11 13.3.2.2 Low/Mid Address Space Block Locking Register FLASH_LMLR The low and mid address block locking register provides a means to protect blocks from being modified. These bits along with bits in the secondary LMLOCK field (FLASH_SLMLR), determine if the block is locked from program or erase. An “OR”’ of FLASH_LMLR and FLASH_SLMLR determine the final lock status. See Section 13.3.2.4, “Secondary Low/Mid Address Space Block Locking Register FLASH_SLMLR” for more information on FLASH_SLMLR. NOTE In the event that blocks are not present (due to configuration or total memory size), the LOCK bits defaults to locked, and are not writable. The reset value is always 1 (independent of the shadow block), and register writes have no effect. Address: Base (0xC3F8_8000) + 0x0004 0 1 2 3 4 5 6 7 8 Access: User R/W 9 10 R LME 0 0 0 0 0 0 0 0 0 0 W Reset 0 1 0 0 0 0 0 0 0 0 0 0 11 SLOCK 11 12 13 1 1 14 15 MLOCK 11 11 11 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 1 1 1 1 1 1 1 1 1 1 LLOCK 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 The reset value of these bits is determined by flash values in the shadow block. Erasing the array sets the reset value to 1. Figure 13-6. Low/Mid Address Space Block Locking Register (FLASH_LMLR) Table 13-8. FLASH_LMLR Field Descriptions Field Description 0 LME Low and mid address lock enable. Enables the locking register fields (SLOCK, MLOCK and LLOCK) to be set or cleared by register writes. This bit is a status bit only, and cannot be written or cleared, and the reset value is 0. The method to set this bit is to write a password, and if the password matches, the LME bit is set to reflect the status of enabled, and is enabled until a reset operation occurs. For LME, the password 0xA1A1_1111 must be written to the FLASH_LMLR. 0 Low and mid address locks are disabled, and cannot be modified. 1 Low and mid address locks are enabled and can be written. 1–10 Reserved 11 SLOCK Shadow lock. Locks the shadow block from programs and erases. The SLOCK bit is not writable when a high voltage operation is suspended. Upon reset, information from the shadow block is loaded into the SLOCK bit. The SLOCK bit can be written as a register. A reset changes the bits to their shadow block value. The default value of the SLOCK bit (when the shadow block bit is cleared) is locked. SLOCK is not writable unless LME is high. 0 Shadow block is available to receive program and erase pulses. 1 Shadow block is locked for program and erase. 12–13 Reserved MPC5533 Microcontroller Reference Manual, Rev. 0 13-12 Freescale Semiconductor Table 13-8. FLASH_LMLR Field Descriptions (Continued) Field Description 14–15 Mid address block lock. MLOCK[1:0] 1 = Locked for program and erase. 0 = Block can receive program and erase pulses. The lock register is not writable when a high voltage operation is suspended. Upon reset, information from the shadow block is loaded into the block registers. The LOCK bits can be written as a register. A reset changes the bits to their shadow block value. The default value of the LOCK bits (assuming erased fuses) is locked. When no blocks are available due to configuration or total memory size, the LOCK bits default to locked, and are not writable. The reset value is always 1 (independent of the shadow block), and register writes have no effect. MLOCK is not writable unless LME is high. 16–25 Reserved 26–31 Low address block lock. These bits have the same description and attributes as MLOCK. As an example of how LLOCK[5:0] the LLOCK bits are used, if a configuration has six 16-KB blocks in the low address space, the block residing at address array base + 0, corresponds to LLOCK0. The next 16-KB block corresponds to LLOCK1, and so on up to LLOCK5. 13.3.2.3 High Address Space Block Locking Register (FLASH_HLR) The high address space block locking register provides a means to protect blocks from being modified. Address: Base (0xC3F8_8000) + 0x0008 0 Access: User R/W 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R HBE 0 0 0 1 1 1 1 1 1 1 0 0 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 W Reset 0 1 0 1 1 HLOCK The reset value of these bits is determined by flash values in the shadow block. An erased array causes the reset value to be 1. Figure 13-7. High Address Space Block Locking Register (FLASH_HLR) Table 13-9. FLASH_HLR Field Descriptions Field Description 0 HBE High address lock enable. Enables the locking field (HLOCK) to be set or cleared by register writes. This bit is a status bit only, and cannot be written to or cleared, and the reset value is 0. The method to set this bit is to provide a password, and if the password matches, the HBE bit is set to reflect the status of enabled, and is enabled until a reset operation occurs. For HBE, the password 0xB2B2_2222 must be written to FLASH_HLR. 0 High address locks are disabled, and cannot be modified. 1 High address locks are enabled to be written. 1–27 Reserved 28–31 High address space block lock. Has the same characteristics as MLOCK. See Section 13.3.2.2, “Low/Mid HLOCK[3:0] Address Space Block Locking Register FLASH_LMLR” for more information. The block numbering for High Address space starts with HLOCK[0] and continues until all blocks are accounted. HLOCK is not writable unless HBE is set. In the event that blocks are not present (due to configuration or total memory size), the HLOCK bits default to locked, and are not writable. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 13-13 13.3.2.4 Secondary Low/Mid Address Space Block Locking Register FLASH_SLMLR The FLASH_SLMLR provides an alternative means to protect blocks from being modified. These bits along with bits in the LMLOCK field (FLASH_LMLR), determine if the block is locked from program or erase. An “OR” of FLASH_LMLR and FLASH_SLMLR determine the final lock status. See Section 13.3.2.2, “Low/Mid Address Space Block Locking Register FLASH_LMLR” for more information on FLASH_LMLR. Address: Base (0xC3F8_8000) + 0x000C 0 Access: User R/W 1 2 3 4 5 6 7 8 9 10 R SLE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 1 0 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 1 1 SM 1 1 1 1 1 1 1 1 1 1 SS LOCK LOCK 11 SLLOCK 1 1 11 11 1 1 1 1 1 1 1 1 1 1 11 11 11 11 11 11 The reset value of these bits is determined by flash values in the shadow block. An erased array sets the reset value to 1. Figure 13-8. Secondary Low/Mid Address Space Block Locking Register (FLASH_SLMLR) Table 13-10. FLASH_SLMLR Field Descriptions Field Description 0 SLE Secondary low and mid address lock enable. Enables the secondary lock fields (SSLOCK, SMLOCK, and SLLOCK) to be set or cleared by register writes. This bit is a status bit only, and cannot be written to or cleared, and the reset value is 0. The method to set this bit is to provide a password, and if the password matches, the SLE bit is set to reflect the status of enabled, and is enabled until a reset operation occurs. For SLE, the password 0xC3C3_3333 must be written to the FLASH_SLMLR. 0 Secondary low and mid address locks are disabled, and cannot be modified. 1 Secondary low and mid address locks are enabled to be written. 1–10 Reserved 11 SSLOCK 12–13 14–15 SMLOCK [1:0] 16–25 26–31 SLLOCK [5:0] Secondary shadow lock. An alternative method to lock the shadow block from programs and erases. SSLOCK has the same description as SLOCK in Section 13.3.2.2, “Low/Mid Address Space Block Locking Register FLASH_LMLR.” SSLOCK is not writable unless SLE is high. Reserved Secondary mid address block lock. Alternative method to lock the mid address space blocks from programs and erases. SMLOCK has the same description as MLOCK in section Section 13.3.2.2, “Low/Mid Address Space Block Locking Register FLASH_LMLR.” SMLOCK is not writable unless SLE is set. In the event that blocks are not present (due to configuration or total memory size), the SMLOCK bits default to locked, and are not writable. Reserved Secondary low address block lock. These bits are an alternative method to lock the low address space blocks from programs and erases. SLLOCK has the same description as LLOCK in Section 13.3.2.2, “Low/Mid Address Space Block Locking Register FLASH_LMLR. SLLOCK is not writable unless SLE is high. In the event that blocks are not present (due to configuration or total memory size), the SLLOCK bits default to locked, and are not writable. MPC5533 Microcontroller Reference Manual, Rev. 0 13-14 Freescale Semiconductor 13.3.2.5 Low/Mid Address Space Block Select Register FLASH_LMSR The FLASH_LMSR provides a means to select blocks to be operated on during erase. Address: Base (0xC3F8_8000) + 0x0010 Access: User R/W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 MSEL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSEL 0 0 0 0 0 0 Figure 13-9. Low/Mid Address Space Block Select Register (FLASH_LMSR) Table 13-11. FLASH_LMSR Field Descriptions Field Description 0–13 Reserved 14–15 MSEL[1:0] 16–25 Mid address space block select. Values in the selected register signify that a block(s) is or is not selected for erase. The reset value for the select registers is 0. The blocks must be selected (or unselected) before doing an erase interlock write as part of the erase sequence. The select register is not writable after an interlock write is completed or if a high voltage operation is suspended. In the event that blocks are not present (due to configuration or total memory size), the corresponding SELECT bits default to unselected, and are not writable. The reset value is always 0, and register writes have no effect. A description of how blocks are numbered is detailed in Section 13.3.2.2, “Low/Mid Address Space Block Locking Register FLASH_LMLR.” 0b0000 Mid address space blocks are not selected for erase 0b0001 One mid address space block is selected for erase 0b0011 Two mid address space blocks are selected for erase Reserved 26–31 LSEL[5:0] 13.3.2.6 Low address space block select. Used to select blocks in the low address space; these have the same description and attributes as the MSEL bits 0b0000 Low address space blocks are not selected for erase 0b0001 One low address space block is selected for erase 0b0011 Two low address space blocks are selected for erase 0b0111 Three low address space blocks are selected for erase 0b1111 Four low address space blocks are selected for erase 0b1_1111 Five low address space blocks are selected for erase 0b11_1111 Six low address space blocks are selected for erase High Address Space Block Select Register FLASH_HSR The FLASH_HSR allows the application to select the high address flash blocks on which to operate. Address: Base (0xC3F8_8000) + 0x0014 Access: User R/W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HBSEL W Reset 0 0 0 0 0 Figure 13-10. High Address Space Block Select Register (FLASH_HSR) MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 13-15 Table 13-12. FLASH_HSR Field Descriptions Field Description 0–27 Reserved 28–31 High address space block select. Has the same characteristics as MSEL. For more information see HBSEL[3:0] Section 13.3.2.5, “Low/Mid Address Space Block Select Register FLASH_LMSR.” 0b0000 High address space blocks are not selected for erase 0b0001 One high address space block is selected for erase 0b0011 Two high address space blocks are selected for erase 0b0111 Three high address space blocks are selected for erase 0b1111 Four high address space blocks are selected for erase 13.3.2.7 Address Register FLASH_AR The FLASH_AR provides the first failing address in the event of ECC event error (FLASH_MCR[EER] set), as well as providing the address of a failure that occurs in a state machine operation (FLASH_MCR[PEG] cleared). ECC event errors take priority over state machine errors. This is especially valuable in the event of a RWW operation, where the read senses an ECC error and the state machine fails simultaneously. This address is always a doubleword address that selects 64 bits. In normal operating mode, the FLASH_AR is not writable. Address: Base (0xC3F8_8000) + 0x0018 Access: User R/O 0 1 2 3 4 5 6 7 8 9 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 ADDR 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 13-11. Address Register (FLASH_AR) Table 13-13. FLASH_AR Field Descriptions Field 0–9 Description Reserved 10–28 Doubleword address of first failing address in the event of an ECC error, or the address of a failure occurring ADDR[3:21] during state machine operation. 29–31 Always read as 0. ADDR[0:2] 13.3.2.8 Flash Bus Interface Unit Control Register FLASH_BIUCR The FLASH_BIUCR is the control register for the set up and control of the flash interface. This register must not be written while executing from flash. Only use a 32-bit write operation to write to this register. MPC5533 Microcontroller Reference Manual, Rev. 0 13-16 Freescale Semiconductor Address: Base (0xC3F8_8000) + 0x001C Access: User R/W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 0 0 0 0 0 0 0 0 0 0 M3 PFE M2 PFE M1 PFE M0 PFE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 28 29 30 31 R W Reset R APC W Reset 1 1 WWSC 1 1 1 RWSC 1 1 1 25 26 27 0 DPF EN 0 IPF EN 0 0 0 0 PFLIM 0 0 BFEN 0 0 Figure 13-12. Flash Bus Interface Unit Control Register (FLASH_BIUCR) Table 13-14. FLASH_BIUCR Field Descriptions Bits 0–11 Description Reserved. Do not set these bits. 12–15 MnPFE Master n prefetch enable. Used to control whether prefetching can be triggered based on the master ID of a requesting master. These bits are cleared by hardware reset. 0 No prefetching can be triggered by this master 1 Prefetching can be triggered by this master These fields are identified as follows: M3PFE = EBI M2PFE = eDMA M1PFE = Nexus M0PFE = MCU core 16–18 APC 1 Address pipelining control. Used to control the number of cycles between pipelined access requests. This field must be set to a value corresponding to the operating frequency of the system clock. The required settings are documented in Table 13-15. 000 Accesses can be pipelined back-to-back 001 Access requests require one additional hold cycle 010 Access requests require two additional hold cycles ... 110 Access requests require six additional hold cycles 111 No address pipelining 19–20 WWSC 1 Write wait state control. Used to control the number of wait-states added to the best-case flash array access time for writes. This field must be set to a value corresponding to the operating frequency of the system clock. The required settings are documented in Table 13-15. 00 No additional wait states are added 01 One additional wait state is added 10 Two additional wait states are added 11 Three additional wait states are added 21–23 RWSC 1 Read wait state control. Used to control the number of wait states added to the best-case flash array access time for reads. This field must be set to a value corresponding to the operating frequency of the system clock. The required settings are documented in Table 13-16. 000 No additional wait states are added 001 One additional wait state is added ... 111 Seven additional wait states are added MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 13-17 Table 13-14. FLASH_BIUCR Field Descriptions (Continued) Bits 24 25 DPFEN 26 1 Description Reserved. Do not set this bit. Data prefetch enable. Enables or disables prefetching initiated by a data read access. This field is cleared by hardware reset. 0 No prefetching is triggered by a data read access 1 Prefetching can be triggered by any data read access Reserved. Do not set this bit. 27 IPFEN Instruction prefetch enable. Enables or disables prefetching initiated by an instruction read access. This field is cleared by hardware reset. 0 No prefetching is triggered by an instruction read access 1 Prefetching can be triggered by any instruction read access 28–30 PFLIM Prefetch limit. Controls the prefetch algorithm used by the FBIU prefetch controller. This field defines a limit on the maximum number of sequential prefetches attempted between buffer misses. This field is cleared by hardware reset. 000 No prefetching is performed 001 The referenced line is prefetched on a buffer miss (i.e. prefetch on miss) 01x The referenced line is prefetched on a buffer miss, or the next sequential line is prefetched on a buffer hit (if not already present), i.e., prefetch on miss or hit. 1xx See 01x (support for legacy code) 31 BFEN FBIU line read buffers enable. Enables or disables line read buffer hits. It is also used to invalidate the buffers. These bits are cleared by hardware reset. 0 The line read buffers are disabled from satisfying read requests, and all buffer valid bits are cleared. 1 The line read buffers are enabled to satisfy read requests on hits. Buffer valid bits can be set when the buffers are successfully filled. Note: Disable prefetching before invalidating the buffers. This includes starting a program or erase operation, or turning on and off the buffers. APC, WWSC, and RWSC values are determined by the maximum frequency of operation. See Table 13-15. MPC5533 Microcontroller Reference Manual, Rev. 0 13-18 Freescale Semiconductor MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 13-19 Table 13-15. FLASH_BIU Settings vs. Frequency of Operation1 Target Maximum Frequency (MHz) APC WWSC RWSC DPFEN 2 IPFEN 2 PFLIM 3 BFEN 2 up to and including 27 MHz 4, 5 0b000 0b01 0b000 0b0, 0b1 0b0, 0b1 0b000 to 0b010 0b0, 0b1 up to and including 52 MHz 6 0b001 0b01 0b001 0b0, 0b1 0b0, 0b1 0b000 to 0b010 0b0, 0b1 up to and including 77 MHz 7 0b010 0b01 0b010 0b0, 0b1 0b0, 0b1 0b000 to 0b010 0b0, 0b1 up to and including 82 MHz 8 0b011 0b01 0b011 0b0, 0b1 0b0, 0b1 0b000 to 0b010 0b0, 0b1 0b111 0b11 0b111 0b0 0b0 0b000 0b0 Reset values: 1 2 3 4 5 6 7 8 Invalid combinations exist. Therefore, all entries must be taken from the same row in this table. For maximum flash performance, set to 0b1. For maximum flash performance, set to 0b010. 27 MHz parts allow for 25 MHz system clock + 2% frequency modulation (FM). The APC/RWSC/WWSC combination requires setting the flash MCR register bit PRD=1. 52 MHz parts allow for 50 MHz system clock + 2% frequency modulation (FM). 77 MHz parts allow for 75 MHz system clock + 2% frequency modulation (FM). 82 MHz parts allow for 80 MHz system clock + 2% frequency modulation (FM). 13.3.2.9 Flash Bus Interface Unit Access Protection Register FLASH_BIUAPR The FLASH_BIUAPR controls access protection for the flash from masters on the crossbar switch. Use a 32-bit write operation only to this register. Address: Base (0xC3F8_8000) + 0x0020 R W Reset R W Reset Access: User R/W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 M3AP 1 1 M2AP 1 1 M1AP 1 1 M0AP 1 1 Figure 13-13. Flash Bus Interface Unit Access Protection Register (FLASH_BIUAPR) MPC5533 Microcontroller Reference Manual, Rev. 0 13-20 Freescale Semiconductor Table 13-16. FLASH_BIUAPR Field Descriptions Field Description 0–23 Reserved. Reads/Writes have no effect. 24–31 MnAP [0:1] Master n access protection. Controls whether read and write accesses to the flash are allowed based on the master ID of a requesting master. These fields are initialized by hardware reset. See Table 8-4. 00 No accesses can be performed by this master 01 Only read accesses can be performed by this master 10 Only write accesses can be performed by this master 11 Both read and write accesses can be performed by this master These fields are identified as follows: M0AP= MCU core M1AP= Nexus M2AP= eDMA M3AP= EBI 13.3.2.10 Flash Bus Interface Unit Control Register 2 FLASH_BIUCR2 The FLASH_BIUCR2 defines the operations of the four line buffers. Address: Base (0xC3F8_8000) + 0x0024 0 R W Reset R 1 LBCFG Access: User R/W 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 –1 –1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 238 24 25 26 27 28 29 30 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 1 See bit description in Table 13-17 for reset values. Figure 13-14. Flash Bus Interface Unit Control Register 2 (FLASH_BIUCR2) MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 13-21 Table 13-17. FLASH_BIUCR2 Field Descriptions Bits Description 0–1 LBCFG Line Buffer Configuration.This field controls the configuration of the four line buffers in the FBIU controller. The buffers can be organized as a “pool” of available resources, or with a fixed partition between instruction and data buffers. In all cases, when a buffer miss occurs, it is allocated to the least-recently-used buffer within the group and the just-fetched entry then marked as most-recently-used. If the flash access is for the next-sequential line, the buffer is not marked as most-recently-used until the given address produces a buffer hit. This field is initialized by hardware reset to the value contained in the address (0x0200 + the shadow base address) of the flash array. An erased or unprogrammed flash sets this field to 0b11. 00 All four buffers are available for any flash access, i.e., there is no partitioning of the buffers based on the access type. 01 Reserved 10 The buffers are partitioned into two groups with buffers 0 and 1 allocated for instruction fetches and buffers 2 and 3 for data accesses. 11 The buffers are partitioned into two groups with buffers 0,1, 2 allocated for instruction fetches and buffer 3 for data accesses. 2–31 Reserved To temporarily change the values of any of the fields in the FLASH_BIUCR2, a write to the IPS-mapped register is performed. To change the values loaded into the FLASH_BIUCR2 at reset, the word location at address (0x0200 + the shadow base address) in the flash array must be programmed using the normal sequence of operations. 13.4 13.4.1 Functional Description Flash Bus Interface Unit (FBIU) The flash BIU interfaces between the system bus and the flash memory interface unit and generates read and write enables, the flash array address, write size, and write data as inputs to the flash memory interface unit (MI). The flash BIU captures read data from the MI and drives it on the system bus. Up to four lines (1 line is a 128-bit width) of data or instructions are buffered by the flash BIU. Lines can be prefetched in advance of being requested by the system bus interface, allowing single-cycle read data responses on buffer hits. Several prefetch control algorithms are available for controlling line read buffer fills. Prefetch triggering can be restricted to instruction accesses only, data accesses only, or can be unrestricted. Prefetch triggering can also be controlled on a per-master basis. Buffers can also be selectively enabled or disabled for allocation by instruction and data prefetch (see Section 13.3.2.10, “Flash Bus Interface Unit Control Register 2 FLASH_BIUCR2”). Access protections can be applied on a per-master basis for both reads and writes to support security and privilege mechanisms. MPC5533 Microcontroller Reference Manual, Rev. 0 13-22 Freescale Semiconductor 13.4.1.1 FBIU Basic Interface Protocol The flash BIU interfaces to the flash array by driving addresses and read or write enable signals to the flash memory interface unit. The access time of the flash is determined by the settings of the wait state control bits in the FLASH_BIUCR, as well as the pipelining of addresses. The flash BIU also has the capability of extending the normal system bus access timing by inserting additional primary (initial access) wait states for reads and burst reads. This capability is provided to allow emulation of other memories which have different access time characteristics. 13.4.1.2 FBIU Access Protections The flash BIU provides hardware configurable access protections for both read and write cycles from masters. It allows restriction of read and write requests on a per-master basis. The FBIU also supports software configurable access protections. Detection of a protection violation results in an error response from the flash BIU to the system bus. 13.4.1.3 Flash Read Cycles—Buffer Miss Read data is normally stored in the least-recently updated line read buffer in parallel with the requested data being forwarded to the system bus. If the flash access was directly the result of a system bus transaction, the line buffer is marked as most-recently-used as it is being loaded. If the flash access was the result of a speculative prefetch to the next sequential line, it is first loaded into the least-recently-used buffer. The status of this buffer is not changed to most-recently-used until a subsequent buffer hit occurs. 13.4.1.4 Flash Read Cycles—Buffer Hit Single clock read responses to the system bus are possible with the flash BIU when the requested read access is buffered. 13.4.1.5 Flash Access Pipelining Accesses to the flash array can be pipelined by driving a subsequent access address and control signals while waiting for the current access to complete. Pipelined access requests are always run to completion and are not aborted by the flash BIU. Request pipelining allows for improved performance by reducing the access latency seen by the system bus master. Access pipelining can be applied to both read and write cycles by the flash array. 13.4.1.6 Flash Error Response Operation The flash array can terminate a requested access with an error. This can occur due to an ECC error that is uncorrectable, an access control violation, or because of improper access sequencing during program/erase operations. When an error response is received, the flash BIU marks a line read buffer as invalid. An error response can be signaled on read or write operations. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 13-23 13.4.1.7 FBIU Line Read Buffers and Prefetch Operation The flash BIU contains four 128-bit line read buffers which are used to hold data read from the flash array. Each buffer operates independently and is filled using a single array access. The buffers are used for both prefetch and normal demand fetches. Prefetch triggering is controllable on a per-master and access-type basis. Bus masters can be enabled or disabled from triggering prefetches, and triggering can be further restricted based on whether a read access is for instruction or data and whether or not it is a burst access. A read access to the flash BIU can trigger a prefetch to the next sequential line of array data on the cycle following the request. The access address is incremented to the next-higher 16-byte boundary, and a flash array prefetch is initiated if the data is not already resident in a line read buffer. Prefetched data is always loaded into the least-recently-used buffer. Buffers can be in one of six states, listed in prioritized order: • Invalid—the buffer contains no valid data. • Used—the buffer contains valid data which has been provided to satisfy a burst type read. • Valid—the buffer contains valid data which has been provided to satisfy a single type read. • Prefetched—the buffer contains valid data which has been prefetched to satisfy a potential future access. • Busy—the buffer is currently being used to satisfy a burst read. • Busy fill—the buffer has been allocated to receive data from the flash array, and the array access is still in progress. Selection of a buffer to be loaded on a miss is based on the following replacement algorithm: 1. First, the buffers are examined to determine if there are any invalid buffers. If there are multiple invalid buffers, the one to be used is selected using a reverse numeric priority, where buffer 0 is selected first, then buffer 1, etc. 2. If there are no invalid buffers, the least-recently-used buffer is selected for replacement. Once the candidate line buffer has been selected, the flash array is accessed and read data loaded into the buffer. If the buffer load was in response to a miss, the just-loaded buffer is immediately marked as most-recently-used. If the buffer load was in response to a speculative fetch to the next-sequential line address after a buffer hit, the recently-used status is not changed. Rather, it is marked as most-recently-used only after a subsequent buffer hit. This policy maximizes performance based on reference patterns of flash accesses and allows for prefetched data to remain valid when non-prefetch enabled bus masters are granted flash access. Several algorithms are available for prefetch control which trade off performance for power. They are described in Section 13.3.2.8, “Flash Bus Interface Unit Control Register FLASH_BIUCR.” More aggressive prefetching increases power due to the number of wasted (discarded) prefetches, but can increase performance by lowering average read latency. 13.4.1.8 Prefetch Triggering Prefetch triggering can be enabled for instruction and data reads, but never by write cycles. Prefetch triggering can be controlled for individual bus masters. MPC5533 Microcontroller Reference Manual, Rev. 0 13-24 Freescale Semiconductor 13.4.1.9 FBIU Buffer Invalidation The line read buffers can be invalidated under hardware and software control. Buffers are automatically invalidated whenever the buffers are turned on or off, or at the beginning of a program or erase operation. NOTE Disable prefetching before invalidating the buffers. This includes starting a program or erase operation, or turning on and off the buffers. 13.4.1.10 Flash Wait-state Emulation Emulation of other memory array timings are supported by the flash BIU. This functionality can be useful to maintain the access timing for blocks of memory which were used to overlay flash blocks for the purpose of system calibration or tuning during code development. The flash BIU inserts additional wait states according to the upper address lines ADDR[28:24]. When these address lines are non-zero, additional cycles are added to system bus transfers. Normal system bus termination is extended. In addition, no line read buffer prefetches are initiated, and buffer hits are ignored. 13.4.2 Flash Memory Array: User Mode In user (normal) operating mode the flash module can be read, written (register writes and interlock writes), programmed, or erased. The following subsections define all actions that can be performed in normal operating mode. The registers mentioned in these sections are detailed in Section 13.3.2, “Register Descriptions.” 13.4.2.1 Flash Read and Write The default state of the flash module is read. The main and shadow address space can be read only in the read state. The module configuration register (FLASH_MCR) is always available for read. The flash module enters the read state on reset. The flash module is in the read state under four sets of conditions: • The read state is active when FLASH_MCR[STOP] = 0 (user mode read). • The read state is active when FLASH_MCR[PGM] = 1 and/or FLASH_MCR[ERS] = 1 and high voltage operation is ongoing (read while write). NOTE Reads done to the partitions being operated on (either erased or programmed) result in errors and the FLASH_MCR[RWE] bit is set. • • The read state is active when FLASH_MCR[PGM] = 1 and FLASH_MCR[PSUS] = 1 in the MCR. (Program suspend). The read state is active when FLASH_MCR[ERS] = 1 and FLASH_MCR[ESUS] = 1 and FLASH_MCR[PGM] = 0 in the MCR. (Erase suspend). MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 13-25 NOTE Flash core reads are done through the BIU. In many cases the BIU does page buffering to allow sequential reads to be done with higher performance. This can create a data coherency issue that must be handled with software. Data coherency can be an issue after a program or erase operation, as well as shadow block operations. In flash normal operating mode, registers can be written and the flash array can be written to do interlock writes. Reads attempted to invalid locations result in indeterminate data. Invalid locations occur when addressing is done to blocks that do not exist in non 2 n array sizes. Interlock writes attempted to invalid locations (due to blocks that do not exist in non 2 n array sizes), result in an interlock occurring, but attempts to program or erase these blocks do not occur since they are forced to be locked. See the following sections for more information: Section 13.3.2.2, “Low/Mid Address Space Block Locking Register FLASH_LMLR” Section 13.3.2.3, “High Address Space Block Locking Register (FLASH_HLR)” Section 13.3.2.4, “Secondary Low/Mid Address Space Block Locking Register FLASH_SLMLR” 13.4.2.2Read While Write (RWW) The flash core is divided into partitions. Partitions are always comprised of two or more blocks. Partitions are used to determine read while write (RWW) groupings. While a write (program or erase) is being done within a given partition, a read can be simultaneously executed to any other partition. Partitions are listed in Table 13-4. Each partition in high address space comprises of two 128-KB blocks. The shadow block has unique RWW restrictions described in Section 13.4.2.5, “Flash Shadow Block.” The flash core is also divided into blocks to implement independent erase or program protection. The shadow block exists outside the normal address space and is programmed, erased and read independently of the other blocks. The shadow block is included to support systems that require NVM for security or system initialization information. A software mechanism is provided to independently lock or unlock each block in high-, mid-, and low-address space against program and erase. 13.4.2.3 Flash Programming Programming changes the value stored in an array bit from logic 1 to logic 0 only. Programming cannot change a stored logic 0 to a logic 1. Addresses in locked/disabled blocks cannot be programmed. You can program the values in any or all of four words within a page in a single program sequence. Word addresses are selected using bits 3:2 of the page-bound word. Whenever a program operation occurs, ECC bits are programmed. ECC is handled on a 64-bit boundary. Thus, if only 1 word in any given 64-bit ECC segment is programmed, do not program the adjoining word (in that segment) because the ECC calculation has already completed for that 64-bit segment. Attempts to program the adjoining word results in an operation failure. All programming operations must be from 64 bits to 128 bits, and be 64-bit aligned. The programming operation must completely fill the selected ECC segments within the page. MPC5533 Microcontroller Reference Manual, Rev. 0 13-26 Freescale Semiconductor The program operation consists of the following sequence of events: 1. Change the value in the FLASH_MCR[PGM] bit from a 0 to a 1. NOTE Ensure the block that contains the address to be programmed is unlocked. 2. Write the first address to be programmed in the flash module with the program data. This write is referred to as a program data interlock write. An interlock write can either be an aligned word or doubleword. 3. To program more than one word or doubleword, write the data to be programmed into each additional address in the page, which is called a program data write. All unwritten data words default to 0xFFFF_FFFF. 4. Write a logic 1 to the FLASH_MCR[EHV] bit to start the internal program sequence or skip to step 9 to terminate. 5. Wait until the FLASH_MCR[DONE] bit goes high. 6. Confirm FLASH_MCR[PEG] = 1. 7. Write a logic 0 to the FLASH_MCR[EHV] bit. 8. If more addresses are to be programmed, return to step 2. 9. Write a logic 0 to the FLASH_MCR[PGM] bit to terminate the program sequence. The program sequence is presented graphically in Figure 13-15. The program suspend operation detailed in Figure 13-15 is discussed in Section 13.4.2.3.2, “Flash Program Suspend/Resume.” The first write after a program is initiated determines the page address to be programmed. The program can be initiated with the 0 to 1 transition of the FLASH_MCR[PGM] bit or by clearing the FLASH_MCR[EHV] bit at the end of a previous program. This first write is referred to as an interlock write. If the program is not an erase-suspended program, the interlock write determines if the shadow or normal array space is programmed and causes FLASH_MCR[PEAS] to be set/cleared. In the case of an erase-suspended program, the value in FLASH_MCR[PEAS], is retained from the erase. An interlock write must be performed before setting FLASH_MCR[EHV]. You can terminate a program sequence by clearing FLASH_MCR[PGM] prior to setting FLASH_MCR[EHV]. If multiple writes are done to the same location the data for the last write is used in programming. While FLASH_MCR[DONE] is low, FLASH_MCR[EHV] is high and FLASH_MCR[PSUS] is low you can clear FLASH_MCR[EHV], resulting in a program abort. A program abort forces the module to step 8 of the program sequence. An aborted program results in FLASH_MCR[PEG] being set low, indicating a failed operation. The data space being operated on before the abort contains indeterminate data. You cannot abort a program sequence while in program suspend. WARNING Aborting a program operation leaves the flash core addresses being programmed in an indeterminate data state. This can be recovered by executing an erase on the affected blocks. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 13-27 User Mode Read State Erase Suspend Write MCR Step 1 PGM = 1 Step 2 Program Write Step 3 Last Write ? No Yes Step 4 Write MCR PGM = 0 EHV = 1 Step 5 Abort WRITE EHV = 0 PEG = 0 User Mode Read State or Erase Suspend WRITE PSUS = 1 High Voltage Active Access MCR DONE = 0 Step 6 Success PEG = 1 PSUS = 0 EHV = 1 DONE ? PEG Valid Period Read MCR DONE = 1 Program Suspend Write MCR Note: PSUS cannot be cleared while EHV = 0. PSUS and EHV cannot both be changed in a single write operation. DONE = 1 Read MCR PEG Value ? Failure PEG = 0 Step 7 Write MCR EHV = 0 Step 8 PGM More Words ? Yes No Step 9 Go to Step 2 Note: PEG remains valid under this condition until EHV is set high or PGM is cleared. Write MCR PGM = 0 0 User Mode Read State ESUS ? 1 Erase Suspend Figure 13-15. Program Sequence MPC5533 Microcontroller Reference Manual, Rev. 0 13-28 Freescale Semiconductor 13.4.2.3.1 Software Locking A software mechanism is provided to independently lock/unlock each high, mid, and low address space against program and erase. Software Locking is done through the FLASH_LMLR (low/mid address space block locking register), FLASH_SLMLR (secondary low/mid address space block locking register), or FLASH_HLR (high address space block locking register). These can be written through register writes, and can be read through register reads. When the program/erase operations are enabled through hardware, software locks are enforced through doing register writes. 13.4.2.3.2 Flash Program Suspend/Resume The program sequence can be suspended to allow read access to the flash core. It is not possible to erase or program during a program suspend. Do not attempt interlock writes during program suspend. A program suspend can be initiated by changing the value of the FLASH_MCR[PSUS] bit from a 0 to a 1. FLASH_MCR[PSUS] can be set high at any time when FLASH_MCR[PGM] and FLASH_MCR[EHV] are high. A 0 to 1 transition of FLASH_MCR[PSUS] causes the flash module to start the sequence to enter program suspend, which is a read state. The module is not suspended until FLASH_MCR[DONE] = 1. At this time, flash core reads can be attempted. After it is suspended, the flash core can only be read. Reads to the blocks being programmed/erased return indeterminate data. The program sequence is resumed by writing a logic 0 to FLASH_MCR[PSUS]. FLASH_MCR[EHV] must be set to a 1 before clearing FLASH_MCR[PSUS] to resume operation. When the operation resumes, the flash module continues the program sequence from one of a set of predefined points. This can extend the time required for the program operation. 13.4.2.4 Flash Erase Erase changes the value stored in all bits of the selected blocks to logic 1. Locked or disabled blocks cannot be erased. If multiple blocks are selected for erase during an erase sequence, the blocks are erased sequentially starting with the lowest numbered block and terminating with the highest. Aborting an erase operation leaves the flash core blocks being erased in an indeterminate data state. This can be recovered by executing an erase on the affected blocks. The erase sequence consists of the following sequence of events: 1. Change the value in the FLASH_MCR[ERS] bit from 0 to a 1. 2. Select the block, or blocks to be erased by writing ones to the appropriate registers in FLASH_LMSR or FLASH_HSR. If the shadow block is to be erased, this step can be skipped, and FLASH_LMSR and FLASH_HSR are ignored. For shadow block erase, see section Section 13.4.2.5, “Flash Shadow Block” for more information. NOTE Lock and Select are independent. If a block is selected and locked, no erase occurs. Write to any address in flash. This is referred to as an erase interlock write. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 13-29 3. Write a logic 1 to the FLASH_MCR[EHV] bit to start an internal erase sequence or skip to step 8 to terminate. 4. Wait until the FLASH_MCR[DONE] bit goes high. 5. Confirm FLASH_MCR[PEG] = 1. 6. Write a logic 0 to the FLASH_MCR[EHV] bit. 7. If more blocks are to be erased, return to step 2. 8. Write a logic 0 to the FLASH_MCR[ERS] bit to terminate the erase. The erase sequence is presented graphically in Figure 13-16. The erase suspend operation detailed in Figure 13-16 is discussed in section Section 13.4.2.4.1, “Flash Erase Suspend/Resume.” After setting FLASH_MCR[ERS], one write, referred to as an interlock write, must be performed before FLASH_MCR[EHV] can be set to a 1. Data words written during erase sequence interlock writes are ignored. You can terminate the erase sequence by clearing FLASH_MCR[ERS] before setting FLASH_MCR[EHV]. An erase operation can be aborted by clearing FLASH_MCR[EHV] assuming FLASH_MCR[DONE] is low, FLASH_MCR[EHV] is high and FLASH_MCR[ESUS] is low. An erase abort forces the module to step 7 of the erase sequence. An aborted erase results in FLASH_MCR[PEG] being set low, indicating a failed operation. The blocks being operated on before the abort contain indeterminate data. You cannot abort an erase sequence while in erase suspend. WARNING Aborting an erase operation leaves the flash core blocks being erased in an indeterminate data state. This can be recovered by executing an erase on the affected blocks. 13.4.2.4.1 Flash Erase Suspend/Resume The erase sequence can be suspended to allow read access to the flash core. The erase sequence can also be suspended to program (erase-suspended program) the flash core. A program started during erase suspend can in turn be suspended. Only one erase suspend and one program suspend are allowed at a time during an operation. It is not possible to erase during an erase suspend, or program during a program suspend. During suspend, all reads to flash core locations targeted for program and blocks targeted for erase return indeterminate data. Programming locations in blocks targeted for erase during erase-suspended program can result in corrupted data. An erase suspend operation is initiated by setting the FLASH_MCR[ESUS] bit. FLASH_MCR[ESUS] can be set to a 1 at any time when FLASH_MCR[ERS] and FLASH_MCR[EHV] are high and FLASH_MCR[PGM] is low. A 0 to 1 transition of FLASH_MCR[ESUS] causes the flash module to start the sequence which places it in erase suspend. You must wait until FLASH_MCR[DONE] = 1 before the module is suspended and further actions are attempted. After it is suspended, the array can be read or a program sequence can be initiated (erase-suspended program). Before initiating a program sequence you must first clear FLASH_MCR[EHV]. If a program sequence is initiated the value of the FLASH_MCR[PEAS] is not reset. These values are fixed at the time of the first interlock of the erase. Flash core reads while FLASH_MCR[ESUS] = 1 from the blocks being erased return indeterminate data. MPC5533 Microcontroller Reference Manual, Rev. 0 13-30 Freescale Semiconductor The erase operation is resumed by clearing the FLASH_MCR[ESUS] bit. The flash continues the erase sequence from one of a set of predefined points. This can extend the time required for the erase operation. WARNING In an erase-suspended program, programming flash locations in blocks which were being operated on in the erase can corrupt flash core data. User Mode Read State Write MCR Step 1 ERS = 1 Step 2 Select Blocks Step 3 Erase Interlock Write Step 4 Write MCR ERS = 0 EHV = 1 Step 5 Abort WRITE EHV = 0 PEG = 0 WRITE ESUS = 1 High Voltage Active Access MCR DONE = 0 User Mode Read State Read MCR ESUS = 0 EHV = 1 DONE ? PEG Valid Period DONE = 1 Erase Suspend Write MCR EHV = 0 Write MCR DONE = 1 PGM = 1 Step 6 Success PEG = 1 Read MCR PEG ? Program, Step 2 Failure PEG = 0 Note: ESUS cannot be cleared while EHV = 0. ESUS and EHV cannot both be changed in a single write operation. Step 7 Write MCR EHV = 0 Step 8 Erase More Blocks ? Yes No Step 9 Go to Step 2 Note: PEG remains valid under this condition until EHV is set high or ERS is cleared. Write MCR ERS = 0 User Mode Read State Figure 13-16. Erase Sequence MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 13-31 13.4.2.5 Flash Shadow Block The flash shadow block is a memory-mapped block in the flash memory map. Program and erase of the shadow block are enabled only when FLASH_MCR[PEAS] = 1. After you has begun an erase operation on the shadow block, the operation cannot be suspended to program the main address space and vice-versa. You must terminate the shadow erase operation to program or erase the main address space. NOTE If an erase of user space is requested, and a suspend is done with attempts to erase suspend program shadow space, this attempted program is directed to user space as dictated by the state of FLASH_MCR[PEAS]. Likewise an attempted erase suspended program of user space, while the shadow space is being erased, is directed to shadow space as dictated by the state of FLASH_MCR[PEAS]. The shadow block cannot utilize the RWW feature. After an operation is started in the shadow block, a read cannot be done to the shadow block, or any other block. Likewise, after an operation is started in a block in low/mid/high address space, a read cannot be done in the shadow block. The shadow block contains information on how the lock registers are reset. The first and second words can be used for reset configuration words. All other words can be used for user defined functions or other configuration words. The shadow block also contains information on how FLASH_BIUCR2 is reset. The shadow block can be locked/unlocked against program or erase by using the FLASH_LMLR or FLASH_SLMLR discussed in Section 13.3.2, “Register Descriptions.” Programming of the shadow block has similar restrictions to programming the array in terms of how ECC is calculated. See Section 13.4.2.3, “Flash Programming” for more information. Only one program is allowed per 64 bit ECC segment between erases. Erase of the shadow block is done similarly as an array erase. See section Section 13.4.2.4, “Flash Erase” for more information. 13.4.2.6 Censorship Censorship logic disables access to internal flash based on the censorship control word value and the BOOTCFG[0:1] bits in the SIU_RSR. This prevents modification of the FLASH_BIUAPR bitfields associated with all masters except the core based on the censorship control word value, the BOOTCFG[0:1] bits in the SIU_RSR, and the EXTM bit in the EBI_MCR. Also, censorship logic sets the boot default value to external-with-external-master access disabled based on the value of the censorship control word and a TCU input signal. 208 Package: BOOTCFG[0] is not available due to pin limitations and internally asserted (driven to 0). The value of the censorship control word defaults to internal flash on the 208 package. MPC5533 Microcontroller Reference Manual, Rev. 0 13-32 Freescale Semiconductor 13.4.2.6.1 Censorship Control Word The censorship control word is a 32-bit value located at the base address of the shadow block plus 0x1E0. The flash module latches the value of the control word prior to the negation of system reset. Censorship logic uses the value latched in the flash module to disable access to internal flash, disable the NDI, prevent modification of the FLASH_BIUAPR bitfields, and/or set the boot default value. 13.4.2.6.2 Flash Disable Censorship logic disables read and write access to internal flash according to the logic presented in Table 13-18. Table 13-18 shows the encoding of the BOOTCFG signals in conjunction with the value stored in the Censorship word in the shadow block of internal flash memory. The table also shows: the name of the boot mode; whether the internal flash memory is enabled or disabled; whether the Nexus port is enabled or disabled; whether the password downloaded in serial boot mode is compared with a fixed ‘public’ password or compared to a user programmable flash password. Table 13-18. Flash Access Disable Logic BOOTCFG1 [0:1] 00 Censorship Serial Boot Control Control 0x00FF_FDE0 0x00FF_FDE2 (Upper Half) (Lower Half) !0x55AA Internal Flash State Nexus State2 Serial Password Internal – Censored Enabled Disabled Flash Internal – Public Enabled Enabled Public 0x55AA Serial – Flash Password Enabled Disabled Flash !0x55AA Serial – Public Password Disabled Enabled Public External – No Arbitration – Censored Disabled Enabled Public External – No Arbitration -– Public Enabled Enabled Public External – External Arbitration – Censored Disabled Enabled Public External – External Arbitration – Public Enabled Public Don't care 0x55AA 01 10 Don't care !0x55AA Don't care 0x55AA 11 !0x55AA 0x55AA Don't care Boot Mode Name Enabled ’!’ = ’NOT’ (any value other than the value specified) 1 BOOTCFG[0:1] bits are located in the SIU_RSR. BOOTCFG[0] is not available on the 208 package and is internally asserted (driven to 0). 2 The Nexus port controller is held in reset when in censored mode. The FBIU returns a bus error if an access is attempted while flash access is disabled. Flash access is any read, write or execute access. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 13-33 13.4.2.6.3 FLASH_BIUAPR Modification Censorship logic prevents modification of the access protection register (FLASH_BIUAPR) bit fields associated with all masters except the core according to the logic presented in Table 13-19. Table 13-19. PFBAPR Modification Logic BOOTCFG1 1 2 13.4.2.6.4 Censorship Control Word EXTM2 PFBAPR Bitfields Writable [0] [1] Upper Half Lower Half 0 0 0x55AA 0xXXXX 0 Yes 0 0 !0x55AA 0xXXXX 0 Yes 1 0 0x55AA 0xXXXX 0 Yes 1 0 !0x55AA 0xXXXX 0 Yes 1 1 0x55AA 0xXXXX 0 Yes 1 1 !0x55AA 0xXXXX 0 Yes 0 1 0xXXXX 0x55AA 0 Yes 0 1 0xXXXX !0x55AA 0 Yes 0 0 0x55AA 0xXXXX 1 Yes 0 0 !0x55AA 0xXXXX 1 No 1 0 0x55AA 0xXXXX 1 Yes 1 0 !0x55AA 0xXXXX 1 No 1 1 0x55AA 0xXXXX 1 Yes 1 1 !0x55AA 0xXXXX 1 No 0 1 0xXXXX 0x55AA 1 No 0 1 0xXXXX !0x55AA 1 No BOOTCFG[0:1] bits are located in the SIU_RSR. EXTM bit is located in the EBI_MCR. External Boot Default The SIU latches the boot default value in the SIU_RSR BOOTCFG[0:1] bits if and only if RSTCFG is negated. Censorship logic sets the boot default value before the SIU latches the value to external-with-external-master access disabled (EXTM=0) if the lower half of the censorship control word equals 0xFFFF or 0x0000. Otherwise, censorship logic sets the boot default value to internal flash. 208 Package: BOOTCFG[0] and RSTCFG are not available due to pin limitations. This signal is internally asserted (driven to 0) therefore, the device defaults to internal flash on the 208 package. MPC5533 Microcontroller Reference Manual, Rev. 0 13-34 Freescale Semiconductor 13.4.3 Flash Memory Array: Stop Mode Stop mode is entered by setting the FLASH_MCR[STOP] bit. The FLASH_MCR[STOP] bit cannot be written when FLASH_MCR[PGM] = 1 or FLASH_MCR[ERS] = 1. In stop mode all DC current sources in the flash module are disabled. Stop mode is exited by clearing the FLASH_MCR[STOP] bit. Accessing the flash memory array when STOP is asserted results in an error response from the flash BIU to the system bus. Memory array accesses must not be attempted until the flash transitions out of stop mode. 13.4.4 Flash Memory Array: Reset A reset is the highest priority operation for the flash and terminates all other operations. The flash uses reset to initialize register and status bits to their default reset values. If the flash is executing a program or erase operation and a reset is issued, the operation is aborted and the flash disables the high voltage logic without damage to the high voltage circuits. Reset aborts all operations and forces the flash into normal operating mode ready to receive accesses. FLASH_MCR[DONE] is set to 1 at the exit of reset. After reset is negated, register accesses can be performed, even though registers that require updating from shadow information, or other inputs, cannot read updated values until flash exits reset. FLASH_MCR[DONE] can be polled to determine if reset has been exited. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 13-35 MPC5533 Microcontroller Reference Manual, Rev. 0 13-36 Freescale Semiconductor Chapter 14 Internal Static RAM (SRAM) 14.1 Introduction The SRAM provides 48 KB of general-purpose system SRAM. The first 32 KB of SRAM is powered by a separate power supply pin for standby operation. Figure 14-1 shows the internal SRAM block diagram. VSTBY SRAM 32 KB Standby SRAM Figure 14-1. Internal SRAM Block Diagram The SRAM controller has these features: • Read/write accesses can map to SRAM from any master • 32 KB with a separate power source for standby operation • Byte, halfword, word, and doubleword addressable • Single-bit correction and double-bit error detection 14.2 SRAM Operating Modes Table 14-1 lists and describes the SRAM operating modes. Table 14-1. SRAM Operating Modes Mode Normal (functional) Standby 14.3 Description Allows reads and writes of SRAM. Preserves the 32 KB of standby memory when the VDD (1.5 V) power drops below the level of VSTBY (0.8–1.2 V). Updates to standby SRAM are inhibited during system reset or during standby mode. External Signal Description The external signal for SRAM is the VSTBY RAM power supply. If the standby feature of the SRAM is not used, tie the VSTBY pin to VSS. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 14-1 14.4 Register Memory Map The SRAM occupies 48 KB of memory starting at the base address as shown in Table 14-2. Table 14-2. SRAM Memory Map Address Register Name Register Description Size Base (0x4000_0000) — SRAM powered by VSTBY 32 KB Base + 0x8000 — 16-KB RAM 16 KB The internal SRAM has no registers. Registers for the SRAM ECC are located in the ECSM. See Chapter 7, “Error Correction Status Module (ECSM),” for more information. 14.5 Functional Description ECC checks are performed during the read portion of an SRAM ECC read/write (R/W) operation, and ECC calculations are performed during the write portion of a read/write (R/W) operation. Because the ECC bits can contain random data after the device is powered on, you must initialize the SRAM by executing 32-bit write instructions to the entire SRAM.The platform RAM for the e200z3 is segmented on a 32-bit boundary, instead of the 64-bit organization for MPC5500 family members that are based on the e200z6. For software compatibility with other members of the MPC5500 family, use 64-bit writes to initialize the ECC bits of two 32-bit words simultaneously. For more information, see Section 14.7, “Initialization and Application Information.” 14.6 SRAM ECC Mechanism The SRAM ECC detects the following conditions and produces the following results: • Detects and corrects all 1-bit errors • Detects and flags all 2-bit errors as non-correctable errors • Detects 39-bit reads (32-bit data bus + 7-bit ECC) that return all zeros or all ones, asserts an error indicator on the bus cycle, and sets the error flag SRAM does not detect all errors greater than two bits. Internal SRAM writes are done on byte boundaries: • 1 byte (0:7 bits) • 2 bytes (0:15 bits) • 4 bytes or 1 word (0:31 bits) • 8 bytes or a doubleword (0:63 bits) If the entire 32 data bits are written to SRAM, no read operation is performed and the ECC is calculated across the 32-bit data bus. The 7-bit ECC is appended to the data segment and written to SRAM. If the write operation is less than the entire 32-bit data width (1- or 2-byte segment), the following occurs: 1. The ECC mechanism checks the entire 32-bit data bus for errors, detecting and either correcting or flagging errors. 2. The write data bytes (1- or 2-byte segment) are merged with the corrected 64 bits on the data bus. 3. The ECC is then calculated on the resulting 64 bits formed in the previous step. MPC5533 Microcontroller Reference Manual, Rev. 0 14-2 Freescale Semiconductor 4. The 7-bit ECC result is appended to the 32 bits from the data bus, and the 39-bit value is then written to SRAM. 14.6.1 Access Timing The system bus is a two-stage pipelined bus, which makes the timing of any access dependent on the access during the previous clock. Table 14-3 lists the various combinations of read and write operations to SRAM and the number of wait states used for the each operation. The table columns contain the following information: Current operation Lists the type of SRAM operation executing currently Previous operation Lists the valid types of SRAM operations that can precede the current SRAM operation (valid operation during the preceding clock) Wait states Lists the number of wait states (bus clocks) the operation requires which depends on the combination of the current and previous operation Table 14-3. Number of Wait States Required for RAM Operation Current Operation Previous Operation Number of Wait States Idle 0 Read 0 32 or 64-bit write 0 8 or 16-bit write 1 Idle 0 Read 0 32 or 64-bit write 0 8 or 16-bit write 1 Idle 0 Read 0 32 or 64-bit write 0 8 or 16-bit write 1 Read 32 or 64-bit write 8 or 16-bit write 14.6.2 Reset Effects on SRAM Accesses If a reset event asserts during a read or write operation to SRAM, the completion of that access depends on the cycle at which the reset occurs. Data read from or written to SRAM before the reset event occurred is retained, and no other address locations are accessed or changed. 14.7 Initialization and Application Information To use the SRAM, the ECC must check all bits that require initialization after power on. Use a 64-bit write to each SRAM location to initialize the SRAM array as part of the application initialization code. All writes must specify an even number of registers performed on 64-bit word-aligned boundaries. If the write MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 14-3 is not the entire 64-bits (8-, 16-, or 32-bits), a read / modify / write operation is generated that checks the ECC value upon the read. See Section 14.6, “SRAM ECC Mechanism.” NOTE You must initialize SRAM, even if the application does not use ECC reporting. 14.7.1 Example Code Because the ECC uses 64-bit based instructions, use 64-bit writes for this device, even though you must initialize the SRAM with 32-bit writes. To initialize SRAM correctly, use a store multiple word (stmw) instruction to implement 64-bit writes to all SRAM locations. The stmw instruction concatenates two 32-bit registers to implement a single 64-bit write. To ensure the writes are 64-bits, specify an even number of registers and write on 64-bit word-aligned boundaries. The following example code illustrates the use of the stmw instruction to initialize the SRAM ECC bits. init_RAM: lis r11,0x4000 ori r11,r11,0 li r12,384 mtctr r12 init_ram_loop: stmw r0,0(r11) addi r11,r11,128 bdnz init_ram_loop blr # # # # base address of the not needed for this loop counter to get 48k/4 bytes/32 GPRs SRAM, 64-bit word aligned address but could be for others all of SRAM; = 384 # # # # write all 32 GPRs to SRAM inc the ram ptr; 32 GPRs * 4 bytes = 128 loop for 48k of SRAM done MPC5533 Microcontroller Reference Manual, Rev. 0 14-4 Freescale Semiconductor Chapter 15 Boot Assist Module (BAM) 15.1 Introduction This chapter describes the boot assist module (BAM). 15.1.1 Overview The BAM contains the MCU boot program code. The BAM control block is connected to peripheral bridge B and occupies the last 16 KB of the MCU memory space. The BAM program supports the following booting modes: • Internal flash • External memory (324 package only; not available on the 208 package) • Serial boot using an eSCI interface • Serial boot using a FlexCAN interface The BAM program is executed by the e200z3 core just after the MCU reset. Depending on the boot mode, the program initializes the minimum MCU resources to start application code execution. Figure 15-1 is a block diagram of the BAM. Peripheral bridge B BAM BAM control block Figure 15-1. BAM Block Diagram MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 15-1 15.1.2 Features The BAM program provides the following features: • Initial e200z3 core MMU setup with minimum address translation for all internal MCU resources and external memory address space • Locate and detect application boot code • Automatic switch to serial boot mode if the flash is not initialized or is invalid: — Internal flash module; or — External memory (324 package only; not available on the 208 package) • Programmable 64-bit password protection for serial boot mode • Boot application code from: — Internal flash module; or — External memory without arbitration (324 package only; not available on the 208 package) • Serial boot can load the application boot code from a FlexCAN or eSCI bus into internal SRAM • Censorship protection for internal flash module • Watchdog timer enable option in the e200z3 core • Configurable memory map for use with the legacy PowerPC Book E code or Freescale VLE code 15.1.3 15.1.3.1 Modes of Operation Normal Mode In normal operation, the BAM responds to all read requests within its address space. The BAM program is executed following the negation of reset. 15.1.3.2 Debug Mode The BAM program is not executed when the MCU comes out of reset in OnCE debug mode. Use the development tool to configure and initialize the MCU before accessing the MCU resources. 15.1.3.3 Internal Boot Mode Use internal boot mode to boot from internal flash memory. Configuration information, initialization, and boot code are kept in internal flash. If the application requires, the BAM program can complete the boot process before the application enables the external bus interface. 15.1.3.4 External Boot Modes Use external boot mode for systems that have application code and configuration information in external memory connected by the EBI. Do not select external boot mode for devices without an external bus. MPC5533 Microcontroller Reference Manual, Rev. 0 15-2 Freescale Semiconductor 15.1.3.5 Serial Boot Mode This mode of operation can load a user program into internal SRAM using either the eSCI or FlexCAN serial interface, then execute the downloaded program. The program can then control the downloading of data, as well as erasing and programming the internal or external flash memory. Serial boot mode downloads: • • • 64-bit password 32-bit start address 32-bit download consisting of 1-bit VLE flag (most significant bit) followed by a 31-bit length field containing the number of bytes to receive (download length) Set the VLE flag to 1 for devices that support variable length encoding and must run in VLE mode. When the VLE flag is set, the BAM configures: • Memory Management Unit (MMU) TLB entries one, two, and three with the VLE attribute for the external bus interface (EBI) • Internal RAM • Internal flash Clear the VLE bit to 0 for devices that use the PowerPC Book E or Power Architecture instruction set mode. 15.2 Memory Map The BAM has 16 KB of memory, from 0xFFFF_C000 through 0xFFFF_FFFF, which is divided into four 4-KB segments, each containing a copy of the BAM program code. The BAM code resides in the 4-KB memory segment beginning at 0xFFFF_F000. A copy of the BAM code resides in the three preceding 4-KB segments, as shown in Table 15-1. The BAM program executes from the reset vector at address 0xFFFF_FFFC. Table 15-1 shows the addresses for the BAM code in the memory map. Table 15-1. BAM Memory Map 15.3 15.3.1 Address Description 0xFFFF_C000–0xFFFF_CFFF BAM program mirrored 0xFFFF_D000–0xFFFF_DFFF BAM program mirrored 0xFFFF_E000–0xFFFF_EFFF BAM program mirrored 0xFFFF_F000–0xFFFF_FFFF BAM program Functional Description BAM Program Resources The BAM program initializes and uses the following MCU resources: • BOOTCFG field in the reset status register (SIU_RSR) to determine the boot option MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 15-3 • • • • • • — For devices using the 208 package, the BAM determines the value of BOOTCFG[1] only, since BOOTCFG[0] is not available due to pin limitations and is internally asserted (driven to 0). Location and value of the reset configuration halfword (RCHW), which contains the address and configuration options for the boot code. See Chapter 4, “Reset,” for information about the RCHW. DISNEX bit in the SIU_CCR register to determine if the Nexus port is enabled MMU allows core access to MCU internal resources and the EBI EBI registers and external bus pads, when using external boot modes FlexCAN A, eSCI A and their pads, when using serial boot mode eDMA during serial boot mode 15.3.2 BAM Program Operation The MCU core accesses the BAM after RSTOUT negates and before the application program executes. The BAM program configures the e200z3 core MMU access for all MCU internal resources and external memory, according to Table 15-2. The memory map configuration remains the same for internal flash boot mode. Table 15-2. MMU Configuration for Internal Flash Boot TLB Entry Region Attributes Logical Base Address Physical Base Address Size 0 Peripheral bridge B and BAM • Guarded • Big endian • Global PID 0xFFF0_0000 0xFFF0_0000 1 MB 1 Internal flash • Not guarded • Big endian • Global PID 0x0000_0000 0x0000_0000 16 MB 2 EBI • Not guarded • Big endian • Global PID 0x2000_0000 0x2000_0000 16 MB 3 Internal SRAM • Not guarded • Big endian • Global PID 0x4000_0000 0x4000_0000 256 KB The MMU maps the logical addresses to the same physical addresses for all modules except for the external bus interface (EBI). The logical EBI addresses are mapped to physical addresses in internal flash memory. This allows code developed to run from external memory to run from internal flash memory. The BAM program reads the following data and determines the boot mode for the boot sequence: • BOOTCFG[0:1] located in the reset status register (SIU_RSR) • Censorship control field located at 0x00FF_FDE0 in the shadow block of internal flash • Serial boot control field located at 0x00FF_FDE2 in the shadow block of internal flash The boot mode determines the following: • Enables or disables internal flash memory MPC5533 Microcontroller Reference Manual, Rev. 0 15-4 Freescale Semiconductor • • Enables or disables the Nexus port Compares the password received in serial boot mode to a preset public password or a programmable password located in internal flash Table 15-3 summarizes the different boot modes. Table 15-3. Boot Modes BOOTCFG [0:1] Censorship Serial Boot Control Control 0x00FF_FDE0 0x00FF_FDE2 Internal Flash State Nexus State Serial Password Internal—Censored Enabled Disabled Flash Internal—Public Enabled Enabled Public 0x55AA Serial—Flash password Enabled Disabled Flash !0x55AA Serial—Public password Disabled Enabled Public External—No arbitration—Censored Disabled Enabled Public External—No arbitration—Public Enabled Enabled Public !0x55AA1 Boot Mode Name Any value 00 0x55AA 01 Any value !0x55AA 10 Any value 0x55AA 11 1 Invalid value ‘!’ = ‘NOT,’ as in !0x55AA, means all values except 0x55AA. Do not use 0x0000 or 0xFFFF for the value of the censorship control or serial boot control words. The 32-bit censorship word, which contains the censorship control and serial boot control fields, is read and interpreted during the boot process. Its value is used in conjunction with the BOOTCFG[0:1] values to enable or disable the internal flash memory and the Nexus interface. The censorship word is programmed at the factory to contain 0x55AA_55AA, which uses a password in internal flash to activate serial boot mode for an uncensored (public) device. The censorship word starts at address 0x00FF_FDE0 and contains a 16-bit censorship control field [0:15] and a 16-bit serial boot control field [16:31]. The factory default settings are shown in Figure 15-2: Address: 0x00FF_FDE0 Value: 0x55AA MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Binary value 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 Hex value 5 5 A A Censorship control field–default value configures the device as uncensored. Address: 0x00FF_FDE2 Binary value Value: 0x55AA 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 Hex value 5 5 A A Serial boot control field–default value reads a password from internal flash. Figure 15-2. Censorship Word MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 15-5 The BAM program reads the DISNEX bit to determine which of the following passwords to compare with the serial password received in serial boot mode: • Public password (64-bit fixed value of 0xFEED_FACE_CAFE_BEEF); or • Flash password (64-bit value in the shadow block of internal flash at address 0x00FF_FDD8). Serial boot flash password starts at address 0x00FF_FDD8: Address: 0x00FF_FDD8 Value: 0xFEED MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Binary value 1 1 1 1 1 1 1 0 1 1 1 0 1 1 0 1 Hex value F E E D Address: 0x00FF_FDDA Binary value Value: 0xFACE 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 1 1 1 1 1 0 1 0 1 1 0 0 1 1 1 0 Hex value F A C E Address: 0x00FF_FDDC Value: 0xCAFE MSB 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Binary value 1 1 0 0 1 0 1 0 1 1 1 1 1 1 1 0 Hex value C A F E Address: 0x00FF_FDDE Binary value Hex value Value: 0xBEEF 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 1 0 1 1 1 1 1 0 1 1 1 0 1 1 1 1 B E E F Figure 15-3. Serial Boot Flash Password 15.3.2.1 Boot Mode Features The BAM program continues to initialize in one of the following boot modes: • Internal boot mode from flash • External boot mode from: — External memory without bus arbitration (324 package only; not available on the 208 package) • Serial boot mode from one of the following interfaces: — eSCI interface — FlexCAN interface MPC5533 Microcontroller Reference Manual, Rev. 0 15-6 Freescale Semiconductor 15.3.2.2 Internal Boot Mode Flow When the BAM detects internal flash boot mode, a bus error exception handler is set up to avoid bus errors and manage corrupt data from internal flash memory. The BAM program then reads up to six locations to find a valid reset configuration halfword (RCHW). When the RCHW is: • Valid—BAM sets the e200z3 watchdog timer enable bit RCHW[WTE] • Invalid —BAM uses the serial boot mode 15.3.2.2.1 Finding the Reset Configuration Halfword The BAM searches internal flash memory for a valid reset configuration halfword (RCHW). A valid RCHW is a 16-bit value that contains a fixed 8-bit boot identifier and the reset configuration halfword (RCHW). The RCHW is the first halfword in one of the six low address flash blocks as shown in Table 15-4. Table 15-4. Low Address Space (LAS) Block Memory Addresses Block Address 0 0x0000_0000 1 0x0000_4000 2 0x0001_0000 3 0x0001_C000 4 0x0002_0000 5 0x0003_0000 Read Section 4.4.3.5.1, “Reset Configuration Half Word (RCHW) Definition” for the definition and description of the RCHW. If a valid RCHW value is located, the BAM: 1. Sets the watchdog timer enable bit (RCHW[WTE]) 2. Fetches the reset vector from BOOT_BLOCK_ADDRESS + 0x0004 3. Branches to the reset boot vector The application must have a valid instruction at the reset boot vector address. If the BAM fails to find a valid RCHW, the validity of the flash memory is unreliable and the device defaults to serial boot operating mode. MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 15-7 BOOT_BLOCK_ADDRESS + 0x0000_0004 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Figure 15-4. Reset Boot Vector If the watchdog timer is enabled for internal boot mode, the watchdog timeout is set to 2.5 × 217 system clock cycles. 15.3.2.3 External Boot Modes Flow Use external boot mode to boot application code from an external asynchronous memory device that is connected to the EBI. External boot mode is controlled by CS[0]. 15.3.2.3.1 External Boot MMU Configuration As shown in Table 15-5, the BAM program sets up two MMU regions differently than in internal flash boot mode. The internal flash logical addresses are mapped to the physical addresses of the EBI. Table 15-5. MMU Configuration for External Boot Mode TLB Entry Region Attributes Logical Base Address Physical Base Address Size 1 Internal flash memory • Not guarded • Big endian • Global PID 0x0000_0000 0x2000_0000 16 MB 2 EBI • Not guarded • Big endian • Global PID 0x2000_0000 0x2000_0000 16 MB This allows code written to run from internal flash memory to execute from external memory. 15.3.2.3.2 Single Bus Master Use External boot with no arbitration mode for single-master systems where the MCU is the only bus master, therefore no arbitration of the external bus is necessary. See Section 15.3.2.3.3, “Configure the EBI for External Boot—Single Master with no Arbitration.” The boot modes are specified by the BOOTCFG[0:1] value. 208 Package: BOOTCFG[0] is not available, and is internally asserted (driven to 0), therefore the 208 package is limited to boot from internal flash memory or a serial port. MPC5533 Microcontroller Reference Manual, Rev. 0 15-8 Freescale Semiconductor 15.3.2.3.3 Configure the EBI for External Boot—Single Master with no Arbitration The BAM program configures: • Chip select CS[0] as a 16-bit port starting at base address 0x2000_0000 with: — no burst — 15 wait states — 8 MB • EBI for no external master (clears EXTM bit) • Enables the EBI for normal operation • Configures the following EBI signals: — ADDR[8:31] — DATA[0:15] — WE[0] — OE — TS — CS[0] 15.3.2.3.4 Read the Reset Configuration Halfword The BAM program reads the first location in external memory (i.e. address 0x2000_0000) for a valid reset configuration halfword (RCHW). If the BAM program finds a valid RCHW, the following occurs: 1. The CS[0] port size and data pins are configured according to the RCHW[PS0] bit 2. The e200z3 core watchdog timeout is enabled or disabled using the RCHW[WTE] bit. The watchdog timeout interval is 2.5 × 217 system clock periods when using the RCHW. 3. MMU boots using PowerPC Book E code or Freescale VLE code according to the RCHW[VLE] setting. The BAM program then reads the reset vector from the address 0x2000_0004 and branches to that reset vector address, starting application program execution. See Figure 15-4 for more information. 15.3.2.4 Serial Boot Mode Operation Serial boot operating mode configures: • FlexCAN A and the eSCI A GPIO signals • Unused message buffers in FlexCAN A are designated as scratch pad SRAM • Memory Management Unit (MMU) TLB entries • Watchdog timer is enabled and set to 2.5 × 227 system clock cycles Serial boot mode downloads: • 64-bit password • 32-bit start address • 32-bit download consisting of a 1-bit VLE flag followed by a 31-bit length field MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 15-9 Set the VLE flag to 1 for devices that support variable length encoding and must run in VLE mode. When the VLE flag is set, the BAM configures these components: • External bus interface (EBI) signals and port size • SRAM structure • VLE attribute is set in Memory Management Unit (MMU) TLB entries one, two, and three Clear the VLE bit to 0 for devices that use the PowerPC Book E or Power Architecture instruction set mode. 15.3.2.4.1 Serial Boot Mode MMU and EBI Configuration The BAM program sets up the MMU for all peripheral and memory regions in one of two different modes and sets up the EBI in one of three different modes; depending on how serial boot mode was entered. If serial boot mode is entered directly by choosing the mode with the BOOTCFG signals, or was entered indirectly from internal boot mode because no valid RCHW was found, then the MMU is configured the same way as for internal boot mode. The EBI is disabled and all bus pins function as GPIO. If serial boot mode is entered indirectly from external boot/single-master because no valid RCHW was found, then the MMU and EBI are configured the for an external boot mode with a 16-bit data bus. See Table 15-3 and Table 15-5 for more information. 15.3.2.4.2 Serial Boot Mode FlexCAN and eSCI Configuration In serial boot mode, the BAM program configures FlexCAN A and eSCI A to receive messages. The CNRXA and RXDA signals are configured as inputs to the FlexCAN and eSCI modules. The CNTXA signal is configured as an output from the FlexCAN module. The TXDA signal of the eSCI A remains configured as GPIO input. The BAM program writes 0x0000_0000_0000_0000 to the e200z3 core timebase registers (TB), enables the e200z3 core setting the watchdog timer to use 2.5 × 227 system clock cycles before a reset occurs. See Table 15-6 for examples of time out periods. In serial boot mode the FlexCAN controller is configured to operate at a baud (bit) rate equal to the system clock frequency divided by 60 with one message buffer (MB) using the standard 11-bit identifier format detailed in the CAN 2.0A specification. See Section 20.4.5.4, “Protocol Timing,” for information on FlexCAN bit rate generation. The BAM ignores the following errors: • Bit 1 errors • Bit 0 errors • Acknowledge errors • Cyclic redundancy code errors • Form errors • Stuffing errors • Transmit error counter errors MPC5533 Microcontroller Reference Manual, Rev. 0 15-10 Freescale Semiconductor • Receive error counter errors All data received is accepted as valid and is echoed out on the CNTXA signal. NOTE The host computer must compare the ‘echoed data’ to the sent data and restart the process if an error is detected. See Figure 15-5 for details of FlexCAN bit timing. NRZ signal SYNC_SEG Time segment 1 1 time quanta 9 time quanta Time segment 2 2 time quanta 1 bit time Sample point Transmit point 1 time quanta = 5 system clock periods = 3.3 crystal clock periods (with PLL enabled) Figure 15-5. FlexCAN Bit Timing The eSCI is configured for one start bit, eight data bits, no parity and one stop bit and to operate at a baud rate equal to the system clock divided by 1250. See Table 15-6 for examples of baud rates. The BAM ignores the following eSCI errors: • Overrun errors • Noise errors • Framing errors • Parity errors All data received is accepted as valid and is echoed out on the TXD signal. The host computer is responsible for comparing the echoes with the sent data, and restarting the process if an error is detected. Table 15-6. Serial Boot Mode—Baud Rate and Watchdog Summary Crystal Frequency (MHz) System Clock Frequency (MHz) SCI Baud Rate FlexCAN Baud Rate Watchdog Timeout Period (seconds) fref_crystal fsys = 1.5 x fref_crystal fsys ÷ 1250 fsys ÷ 60 (2.5 x 227) ÷ fsys 8 12 9600 200 K 28.0 12 18 14400 300 K 18.6 MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 15-11 Table 15-6. Serial Boot Mode—Baud Rate and Watchdog Summary (Continued) Crystal Frequency (MHz) System Clock Frequency (MHz) SCI Baud Rate FlexCAN Baud Rate Watchdog Timeout Period (seconds) 16 24 19200 400 K 14.0 20 30 24000 500 K 11.2 Upon receiving a valid FlexCAN message with an ID equal to 0x0011 that contains eight data bytes, or a valid eSCI message, the BAM uses a serial boot submode: FlexCAN serial boot mode, or eSCI serial boot mode. In FlexCAN serial boot mode, the eSCI A signal RXDA reverts to GPIO input. All data is downloaded on the FlexCAN bus and eSCI messages are ignored. In eSCI serial boot mode, the FlexCAN A signals CNRXA and CNTXA revert to GPIO inputs and the TXDA signal is configured as an output. All data is downloaded on the eSCI bus and FlexCAN messages are ignored. Table 15-7. FlexCAN and eSCI Reset Configuration for FlexCAN and eSCI Boot Reset Function Initial Serial Boot Mode CNTXA GPIO CNRXA Pin Label Serial Boot Mode after Receiving a Valid FlexCAN Message eSCI Message CNTXA CNTXA GPIO GPIO CNRXA CNRXA GPIO TXDA GPIO GPIO GPIO TXDA RXDA GPIO RXDA GPIO RXDA Table 15-8. FlexCAN and eSCI Reset Pin Configuration Hysteresis Driver Configuration Slew Rate Input Buffer Enable Enabled Up — Push/pull Medium N Input Enabled Up Y — — — Input Enabled Up Y — — — Pins I/O CNTXA_TXDA Output CNRXA_RXDA GPIO 15.3.2.4.3 Weak Pullup State Download Process for FlexCAN Serial Boot Mode The download process contains the following steps: 1. Download the 64-bit password. 2. Download the start address, VLE flag, and the number of data bytes to download. 3. Download the data. 4. Execute the boot code from the start address. MPC5533 Microcontroller Reference Manual, Rev. 0 15-12 Freescale Semiconductor Each step of the process must complete before the next step starts. 1. Download the 64-bit password. The host computer must send a FlexCAN message with ID = 0x011 that contains the 64-bit serial download password. FlexCAN messages with other IDs or fewer bytes of data are ignored. When a valid message is received, the BAM transmits a FlexCAN message with ID = 0x001 that contains the data received. The host must not send a second FlexCAN message until it receives the echo of the first message. A FlexCAN message sent before the echo is received is ignored. The received 64-bit password is validated to ensure that none of the four 16-bit halfwords have a value of 0x0000 or 0xFFFF, which are invalid passwords. A valid password must have at least one 0 and one 1 in each halfword lane. The BAM program then reads the disable Nexus bit [DISNEX] in the SIU_CCR register to determine the censorship status of the MCU. If Nexus is disabled, the MCU is censored and the password is compared to a password stored in the shadow block in internal flash memory. If Nexus is enabled, the MCU is not censored or booting from external flash and the password is compared to the constant value = 0xFEED_FACE_CAFE_BEEF. If the password fails any validity tests, the MCU stops responding to all stimulus. To repeat boot operation, the MCU needs to be reset by external reset or by watchdog. If the password is valid, the BAM program refreshes the e200z3 watchdog timer and the next step in the protocol can be performed. 2. Download the start address, VLE bit, and the download size. The host computer must send a FlexCAN message with an ID = 0x012 that contains: — 32-bit start address in internal SRAM indicating where to store the succeeding data in memory; — 32-bit number containing a 1-bit variable length encoded (VLE) flag followed by a 31-bit length field that contains the number of data bytes to receive and store in memory before switching to execute the code just loaded. The start address is expected on a 32-bit word boundary, therefore the least significant 2 bits of the address are ignored. FlexCAN messages with other IDs or fewer data bytes are ignored. Set the VLE bit in the serial download data (most significant bit in the LENGTH word) if the code to download uses VLE instructions. When a valid message is received, the BAM transmits a FlexCAN message with an ID = 0x002 that contains the received data. The host computer must not send another FlexCAN message until it receives the echo from the previous message. A FlexCAN message sent before the echo is received is ignored. 3. Download the data. The host computer must send a succession of FlexCAN messages with ID = 0x013 that contains raw binary data (the data length is variable). Each data byte received is stored in MCU memory, starting at the address specified in the previous step and incrementing through memory until the number of data bytes received and stored in memory matches the number specified in the previous step. FlexCAN messages with ID values other than 0x013 are ignored. When a valid message is received, the BAM transmits a FlexCAN message with an ID = 0x003 that contains the data received. The host computer must not send another FlexCAN message until MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 15-13 it receives the echo from the previous message. A FlexCAN message sent before the echo is received is ignored. NOTE Internal SRAM is protected by 64-bit error correction (ECC) hardware. All writes to uninitialized internal SRAM must be 64-bits wide, or an ECC error occurs. The BAM buffers 8 bytes of downloaded data before executing a single 64-bit write. Only internal SRAM supports 64-bit writes. Downloading data to other RAM causes errors. If the start address of the downloaded data is not at an 8-byte boundary, the BAM writes 0x00 to the memory locations from the preceding 8-byte boundary to the start address (maximum 4 bytes). The BAM also writes 0x00 to all memory locations from the last byte of data downloaded to the following 8-byte boundary (maximum 7 bytes). 4. Execute code. The BAM waits for the last FlexCAN message transmission to complete. Then the FlexCAN controller is disabled. CNTXA and CNRXA become GPIO inputs. The BAM branches to the starting address of the downloaded code, as specified in step 2. NOTE The code that downloads and executes must: • • Periodically refresh the e200z3 watchdog timer; or Change the timeout period to a value that does not cause resets during normal operation. Table 15-9. FlexCAN Serial Boot Mode Download Process Step MCU Response Message Host Message Sent Action 1 FlexCAN ID = 0x011 + 64-bit password FlexCAN ID = 0x001 + 64-bit password Password checked for validity and compared against stored password. e200z3 watchdog timer is refreshed if the password check is successful. 2 FlexCAN ID = 0x012 + 32-bit store address + 32-bit number of bytes FlexCAN ID = 0x002 + 32-bit store address + 32-bit number of bytes The load address and the number of bytes to download are stored for future use. 3 FlexCAN ID = 0x013 + 8 to 64 bits of raw binary data FlexCAN ID = 0x003 + 8 to 64 bits of raw binary data Each data byte received is written to MCU memory, starting at the address specified in the previous step and incrementing until the number of data bytes received and stored matches the number of bytes to download and store (specified in step 2). 4 None None The BAM program returns I/O pins and the FlexCAN module to their reset state, then branches to the start address of the stored data (specified in step 2). MPC5533 Microcontroller Reference Manual, Rev. 0 15-14 Freescale Semiconductor 15.3.2.4.4 eSCI Serial Boot Mode Download Process The eSCI serial boot mode download process contains the following steps: 1. Download the 64-bit password. 2. Download the start address, VLE flag, and the number of data bytes to download. 3. Download the data. 4. Execute the code from start address. Each step in the following process must complete before the next step starts. The eSCI operates in half duplex mode where the host sends a byte of data, then waits for the echo back from the MCU before proceeding with the next byte. Bytes sent from the host before the previous echo from the MCU is received are ignored. 1. Download the 64-bit password. The first 8 bytes of eSCI data the host computer sends must contain the 64-bit serial download password. For each valid eSCI message received, the BAM transmits the same data on the eSCI A TXDA signal. The received 64-bit password is checked for validity. It is checked to ensure that none of the 4 x 16-bit halfwords are invalid passwords (0x0000 or 0xFFFF). A password must have at least one 0 and one 1 in each halfword to qualify as legal. The BAM program then checks the censorship status of the MCU by checking the DISNEX bit in the SIU_CCR. If Nexus is disabled, the MCU is considered censored and the password is compared with a password stored in the shadow block of internal flash memory. If Nexus is enabled, the MCU is not censored or is booting from external flash and the password is compared to the constant value of 0xFEED_FACE_CAFE_BEEF. If the password fails a validity test, the MCU stops responding to all stimulus. To repeat the boot operation, assert the RESET signal or wait for the watchdog timer to reset the MCU. If the password is valid, the BAM refreshes the e200z3 watchdog timer and proceeds to step 2. 2. Download the start address, VLE bit, and the download size. The host computer must send the next eight bytes of eSCI data that contains: — 32-bit start address in internal SRAM indicating where to store the succeeding data in memory; — 32-bit number containing a 1-bit variable length encoded (VLE) flag followed by a 31-bit length field that contains the number of data bytes to receive and store in memory before switching to execute the code just loaded. The start address is normally located on a word boundary (4-bytes), therefore the least significant 2 bits of the address are ignored. For each valid eSCI message received, the BAM transmits the same data on the eSCI A TXDA signal. Set the VLE bit in the serial download data (most significant bit in the LENGTH word) if the code to download uses VLE instructions. 3. Download the data. The host computer must then send a succession of eSCI messages, each containing raw binary data. Each byte of data received is stored in the MCU’s memory, starting at the address specified in the previous step and incrementing through memory until the number of data bytes received and stored MPC5533 Microcontroller Reference Manual, Rev. 0 Freescale Semiconductor 15-15 in memory matches the number specified in the previous step. For each valid eSCI message received, the BAM transmits the same data on the TXDA signal. NOTE Internal SRAM is protected by 64-bit wide error correction coding hardware (ECC). All writes to uninitialized internal SRAM must be 64 bits wide, or an ECC error occurs. The BAM buffers download data until 8-bytes are received, and then executes a single 64-bit wide write. Only internal SRAM supports 64-bit writes. Downloading data to RAM other than internal SRAM causes errors. If the start address of the downloaded data is not on an 8-byte boundary, the BAM writes 0x00 beginning at the preceding 8-byte boundary memory location to the start address (4 byte maximum). The BAM also writes 0x00 to all memory locations from the last data byte downloaded to the following 8-byte boundary (7 byte maximum). 4. Execute the code. The BAM waits for the last eSCI message transmission to complete and then disables the eSCI. TXDA and RXDA revert to general-purpose inputs. The BAM branches to the starting address where the downloaded code is stored (s