16-bit S12X Microcontroller Family with Integrated FlexRay Interface Covers ...

Freescale Semiconductor
Product Brief
MC9S12XF512PB
Rev. 1, 06-Dec-2006
16-bit S12X Microcontroller
Family with Integrated FlexRay
Interface
Covers MC9S12XF512, MC9S12XF384, MC9S12XF256 and
MC9S12XF128
Introduction
Targeted at actuators, sensors and other distributed nodes in the FlexRay network for Chassis and Body
Electronics, the MC9S12XF-Family will deliver 32-bit performance with all the advantages and
efficiencies of a 16-bit MCU. The design goal is to retain the low cost, power consumption, EMC and
code-size efficiency advantages currently enjoyed by users of Freescale Semiconductor's existing 16-bit
MC9S12 MCU families.
Based around an enhanced S12X core, the MC9S12XF-Family will run 16-bit wide accesses without wait
states for all peripherals and memories. The MC9S12XF-Family also features a new flexible interrupt
handler, which allows multilevel nested interrupts.
The MC9S12XF-Family features the performance boosting enhanced XGATE co-processor. The XGATE
is programmable in “C” language and runs at twice the bus frequency of the S12. Its instruction set is
optimized for data movement, logic and bit manipulation instructions. Any peripheral module can be
serviced by the XGATE.
© Freescale Semiconductor, Inc., 2006. All rights reserved.
PRELIMINARY
Introduction
The MC9S12XF-Family features a FlexRay module for high speed serial communication supporting
various bit rates up to 10 Mbit/s. The FlexRay clock can be derived from crystals ranging from 4MHz to
40MHz for cost and EMC optimization using an Internal PLL (IPLL). The 64-pin LQFP allows interfacing
to a single FlexRay channel. The 64-pin LQFP (10mm x 10mm) is intended for those applications
challenged by the size constraint of some satellite FlexRay modules. The 112-pin LQFP offer increase
number of I/Os as well as 16 A/D channels, in addition to that the 144-pin LQFP provides a full 16-bit wide
non-multiplexed external bus interface with the pins usable in single-chip mode as general purpose I/O.
NOTE
The 144-Pin LQFP version will not be qualified for production and is
intended to be used for emulation (development tools) only.
The MC9S12XF-Family features the MSCAN module with a FIFO receiver buffer arrangement, and input
filters optimized for Gateway applications handling numerous message identifiers.
The MCU9S12XF Family provides Flash memory sizes from 128K throughout 512K non volatile memory
together with enhanced EEPROM functionality (EE-Emulation) with built in Error Correcting Code
(ECC).The memory uses Freescale Semiconductor's industry-leading, full automotive qualified SGFlash.
The inclusion of a frequency modulated PLL circuit allows power consumption and performance to be
adjusted to suit operational requirements and allows optimization of the radiated emissions (EMC).
The ADC now offers 12 Bit resolution at a conversion rate down to 3µs per channel.
The Enhanced Programmable Interrupt Timer offers the possibility to schedule up to 3 ADC trigger events
after an initial PMF or PIT sync event. Additional trigger events can be scheduled via software.
In addition to the I/O ports available in each module, up to eleven further I/O ports are available with
interrupt capability allowing wake-up from STOP or WAIT mode.
16-bit S12X Microcontroller Family with Integrated FlexRay Interface, Rev. 1
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Freescale Semiconductor
PRELIMINARY
Features
Features
Features of the MC9S12XF-Family are listed here. Please see Table 1 for memory options and Table 2
for the peripheral features that are available on the different family members.
•
Upward compatible with MC9S12 instruction set
•
Enhanced indexed addressing
•
Additional (superset) instructions to improve 32-bit calculations and
semaphore handling
•
Access large data segments independent of PPAGE
•
Note: Five Fuzzy instructions are removed (MEM, WAV,WAVR,
REV, REVW)
•
Eight levels of nested interrupt
•
Flexible assignment of interrupt sources to each interrupt level.
•
One non-maskable high priority interrupt (XIRQ)
•
Wake-up Interrupt Inputs
– IRQ and non-maskable XIRQ
•
Programmable, high performance I/O coprocessor module – up to
100 MIPS RISC performance
•
Transfers data to or from all peripherals and RAM without CPU
intervention or CPU wait states
•
Performs logical, shifts, arithmetic, and bit operations on data
•
Can interrupt the HCS12X CPU signalling transfer completion
•
Triggers from any hardware module as well as from the CPU possible
•
NEW! Two interrupt levels to service high priority tasks
•
Enables Full CAN capability when used in conjunction with MSCAN
module
•
Full LIN master or slave capability when used in conjunction with the
integrated LIN SCI module
•
Power-on reset (POR)
•
Illegal address detection with reset
•
Low-voltage detection with interrupt or reset
•
Computer Operating Properly (COP) watchdog
– configurable as window COP for enhanced failure detection
– Can be initialized out of reset using option bits located in Flash
•
Clock monitor supervising the correct function of the oscillator
16-Bit CPU12X
Enhanced Interrupt
Module
XGATE
System Integrity
Support
16-bit S12X Microcontroller Family with Integrated FlexRay Interface, Rev. 1
Freescale Semiconductor
3
PRELIMINARY
Features
•
Crossbar architecture for efficient data flow
•
128K, 256k, 384K and 512K byte Flash
•
2K, 4K byte Emulated EEPROM
•
16K, 24K and 32K Byte RAM
•
Flash General Features
– NEW! 64 data bits plus 8 syndrome ECC (Error Correction Code)
bits allow single bit error correction and double fault detection
– Erase sector size 1024 bytes
– Automated program and erase algorithm
– Security option to prevent unauthorized access
– Sense-amp margin level setting for reads
•
NEW! Data Flash General Features
– Up to 32K bytes of D-Flash memory with 256-byte sectors for user
access.
– Dedicated commands to access D-Flash memory over EEE
operation
– Single bit fault correction and double fault detection within a word
during read operations
– Automated program and erase algorithm with verify and
generation of ECC parity bits
– Fast sector erase and word program operation
– Ability to program up to four words in a burst sequence
•
NEW! Emulated EEPROM General Features
– Automatic EEE file handling using internal Memory Controller
– Automatic transfer of valid EEE data from D-Flash memory to
buffer RAM on reset
– Ability to monitor the number of outstanding EEE related buffer
RAM words left to be programmed into D-Flash memory
– Ability to disable EEE operation and allow priority access to the
D-Flash memory
– Ability to cancel all pending EEE operations to allow priority
access to the D-Flash memory
•
Loop Control Pierce oscillator utilizing a 4MHz to 16MHz crystal
•
Good noise immunity
•
Full-swing Pierce option utilizing a 2MHz to 40MHz crystal
•
Transconductance sized for optimum start-up margin for typical
crystals
Memory Options
Oscillator (OSC_LCP)
16-bit S12X Microcontroller Family with Integrated FlexRay Interface, Rev. 1
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Freescale Semiconductor
PRELIMINARY
Features
•
Phase-locked-loop (IPLL) clock frequency multiplier
– NEW! Internally filtered. No external components required
– Configurable option to spread spectrum for reduced EMC
radiation (frequency modulation)
•
Fast wake up from STOP in self clock mode for power saving and
immediate program execution
•
16 data wide
•
Support for external WAIT input or internal wait cycles to adapt MCU
speed to peripheral speed requirements
•
Up to four chip select outputs to select 16K, 768K, 2M and 4MByte
address spaces
•
Supports glue less interface to popular asynchronous RAMs and
Flash devices
•
External address space 4MByte for Data and Program space
•
FlexRay protocol implementation according to FlexRay V2.1 Protocol
Implementation document
•
Optimized programmers model to fit small address footprint
•
NEW! Supports Data Rates of 2.5, 5, 8 and 10MBit/s on each of the
two channels
•
NEW! The FlexRay clock can be derived from crystals ranging from
4MHz to 40MHz for cost and EMC optimization using a PLL.
•
FlexRay clocking independent from the CPU and XGATE bus
frequency
•
Up to two channels for fault tolerant systems (see Table 2 Peripheral
Feature Summary of MC9S12XF-Family Members)
•
Single channel operation on channel A, configurable to run FlexRay
channel A or channel B protocol
•
32 configurable message buffers
– Message buffers can be configured as Receive, single buffered
Transmit or double buffer Transmit message buffer
– Message buffer header, status and payload data stored in
System RAM
– 2 independent message buffer segments with configurable size of
payload data section
– Size of message buffer payload data section configurable from 0
up to 254 bytes
•
2 independent receive FIFOs, 1 per channel
•
Six separate interrupt channels for Receive, receive FIFO channel A,
receive FIFO channel B, Transmit, Error and Wake-up
•
Internal signals can be routed to I/O pins to ease debugging
Clock and Reset
Generator (CRG)
Non-Multiplexed
External Bus
(144 Pin package only)
FlexRay Module (FR)
16-bit S12X Microcontroller Family with Integrated FlexRay Interface, Rev. 1
Freescale Semiconductor
5
PRELIMINARY
Features
Analog-to-Digital
Converter (ADC)
Enhanced Capture
Timer (ECT)
NEW! Enhanced
Programmable
Interrupt Timer (EPIT)
Real Time Interrupt
(RTI)
NEW! Asynchronous
Periodic Interrupt
(API)
•
NEW! 8/10/12 Bit resolution
•
Multiplexer for 16 analog input channels
•
NEW! 3µs, 12-bit single conversion time
•
Left or right justified result data
•
External and internal conversion trigger capability
•
Internal oscillator for conversion in Stop Modes
•
Wake-up from low power modes on analog comparison > or <=
match
•
8 x 16-bit channels for input capture or output compare
•
16-bit free-running counter with 8-bit precision prescaler
•
16-bit modulus down counter with 8-bit precision prescaler
•
4 x 8-bit or 2 x 16-bit pulse accumulators
•
Four channels have enhanced input capture capabilities:
– Delay counter for noise immunity
– 16-bit capture buffer
– 8-bit pulse accumulator buffer
•
Up to 8 timers with independent time-out periods
•
Time-out periods selectable between 1 and 224 bus clock cycles
•
Time-out interrupt and peripheral triggers
•
3 Sync sources (e.g. PMF) to select.
•
Eight time-out trigger output signals available to trigger peripheral
modules.
•
Start of timer channels can be aligned to each other.
•
Start of timer channels can be aligned to an external trigger event.
•
Real Time Interrupt for task scheduling purposes or cyclic wake-up
•
Can be active in Pseudo Stop mode for low power precision timing
tasks
•
Available in all modes including Full Stop mode
•
Trimmable to +-10% accuracy
•
Time-out periods range from 0.2ms to ~13s with a 0.2ms resolution
16-bit S12X Microcontroller Family with Integrated FlexRay Interface, Rev. 1
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Freescale Semiconductor
PRELIMINARY
Features
Pulse Width
Modulator with Fault
detection (PMF)
Multi-scalable
Controller
Area Networks
(MSCAN)
Serial Peripheral
Interface (SPI)
•
Six channel Pulse width Modulator with Fault protection (PMF)
optimized for electrical motor control
•
Three independent 15-bit counters with synchronous mode
•
Complementary channel operation
•
Edge and center aligned PWM signals
•
Programmable dead time insertion
•
Integral reload rates from 1 to 16
•
Up to four fault protection shut down input pins depending on the
package option
•
Up to three current sense input pins depending on the package option
(see Table 3 Port and Peripheral Availability by Package Option)
•
CAN 2.0 A, B software compatible
– Standard and extended data frames
– 0 - 8 bytes data length
– Programmable bit rate up to 1 Mbps
•
Five receive buffers with FIFO storage scheme
•
Three transmit buffers with internal prioritization
•
Flexible identifier acceptance filter programmable as:
– 2 x 32-bit
– 4 x 16-bit
– 8 x 8-bit
•
Wake-up with integrated low pass filter option
•
Loop back for self test
•
Listen-only mode to monitor CAN bus
•
Bus-off recovery by software intervention or automatically
•
16-bit time stamp of transmitted/received messages
•
Up to two SPI modules (see Table 2 Peripheral Feature Summary of
MC9S12XF-Family Members)
•
NEW! configurable 8 or 16-bit data size
•
Full-duplex or single-wire bidirectional
•
Double-buffered transmit and receive
•
Master or Slave mode
•
MSB-first or LSB-first shifting
•
Serial clock phase and polarity options
16-bit S12X Microcontroller Family with Integrated FlexRay Interface, Rev. 1
Freescale Semiconductor
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PRELIMINARY
Features
Serial Communication
Interfaces (SCI)
•
Up to two SCI modules (see Table 2 Peripheral Feature Summary of
MC9S12XF-Family Members)
•
Full-duplex or single wire operation
•
Standard mark/space non-return-to-zero (NRZ) format
•
Selectable IrDA 1.4 return-to-zero-inverted (RZI) format with
programmable pulse widths
•
13-bit baud rate selection
•
Programmable character length
•
Programmable polarity for transmitter and receiver
•
Receive wakeup on active edge
•
Break detect and transmit collision detect supporting LIN
•
Background debug controller (BDM) with single-wire interface
– Non-intrusive memory access commands
– Supports in-circuit programming of on-chip non-volatile memory
– Supports security
•
Four comparators A, B, C and D
– Each can monitor CPU or XGATE busses
– A and C compares 23-bit address bus and 16-bit data bus with
mask register
– B and D compares 23-bit address bus only
– Three modes: simple address/data match, inside address range
or outside address range
•
64 x 64-bit circular trace buffer to capture change-of-flow addresses
or address and data of every access
•
Tag-type or force-type hardware breakpoint requests
•
Two parallel, linear voltage regulators with bandgap reference
•
Low-voltage detect (LVD) with low-voltage interrupt (LVI)
•
Power-on reset (POR) circuit
•
3V to 5V range operation
•
Low-voltage reset (LVR)
•
up to 110 general-purpose input/output (I/O) pins depending on the
package option and 2 input-only pins
•
Hysteresis and configurable pull up/pull down device on all input pins
•
Configurable drive strength on all output pins
•
144-pin low-profile quad flat-pack (LQFP)
•
112-pin low-profile quad flat-pack (LQFP)
•
64-pin low-profile exposed quad flat-pack (LQFP)
Background Debug
(BDM)
Debugger (DBG)
On-Chip Voltage
Regulator (VREG)
Input/Output
Package Options
16-bit S12X Microcontroller Family with Integrated FlexRay Interface, Rev. 1
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Freescale Semiconductor
PRELIMINARY
Features
Operating Conditions
•
Ambient temperature range –40°C to 85°C
•
Temperature Options:
– –40°C to 105°C
– –40°C to 125°C
•
Supply voltage range from 3.15V to 5.5V
•
Internal Voltage Regulator providing 1.8V logic and 3.0V Flash
supply
•
MCU9S12XF-Family:
– 40MHz maximum CPU bus frequency
– 80MHz maximum XGATE bus frequency
16-bit S12X Microcontroller Family with Integrated FlexRay Interface, Rev. 1
Freescale Semiconductor
9
PRELIMINARY
Block Diagram
Voltage Regulator
CPU12X
XTAL
Amplitude Controlled
Low Power Pierce or
Full drive Pierce
Oscillator
PLL with Frequency
Modulation option
PA[7:0]
PTK
XIRQ
IRQ
RW/WE
LSTRB/LDS
ECLK
MODA/TAGLO/RE
MODB/TAGHI
XCLKS/ECLKX2
EWAIT
ADDR[22:16]
ADDR[15:8]
PC[7:0]
PTC
ADDR[7:0]
DATA[15:8]
PD[7:0]
PTD
PB[7:0]
PTA
PK[7:0]
PTB
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PTE
TEST
Reset Generation
and Test Entry
DATA[7:0]
EPIT
8ch 16-bit Timer
Enhanced Multilevel
Interrupt Module
Non-Multiplexed External Bus Interface
RESET
Clock Monitor
COP Watchdog
Periodic Interrupt
Async. Periodic Int.
X
EXTAL
XGATE
BKGD
Debug Module
Single-wire Background 4 address breakpoints
Debug Module
2 data breakpoints
512 Byte Trace Buffer
MOSI
SCK
Synchronous Serial IF
SS
RXCAN
CAN0
TXCAN
msCAN 2.0B
FAULT2
FAULT3
MISO
SPI1
MOSI
Synchronous SCK
Serial IF
SS
PMF0
PMF1
15-bit 6-channel
PMF2
Pulse Width Modulation PMF3
with Fault Protection
PMF4
PMF5
FAULT0
FAULT1
IS0
IS1
IS2
STB0
STB1
STB2
STB3
FlexRay
Channel A
RXD_A
TXD_A
TXE_A
Channel B
RXD_B
TXD_B
TXE_B
PTAD0
PT[7:0]
PTS
IOC[7:0]
16-bit 8 channel
Enhanced Capture Timer
RXD
SCI0
TXD
Asynchronous Serial IF
RXD
SCI1
TXD
Asynchronous Serial IF
SPI0
MISO
PTM
2K … 4K bytes EEPROM
VDDR
VDD1
VDDF
VDDPLL
PTP
16K … 32K bytes RAM
PAD[15:0]
PTJ
8/10/12-bit 16-channel AN[15:0]
Analog-Digital Converter
ECT
PTH
ATD
128K … 512M bytes Flash
PTT
Block Diagram
PS0
PS1
PS2
PS3
PS4
PS5
PS6
PS7
PM0
PM1
PM2
PM3
PM4
PM5
PM6
PM7
PP0
PP1
PP2
PP3
PP4
PP5
PP6
PP7
PJ0
PJ1
PJ2
PJ3
PJ4
PJ5
PJ6
PJ7
PH0
PH1
PH2
PH3
PH4
PH5
PH6
PH7
16-bit S12X Microcontroller Family with Integrated FlexRay Interface, Rev. 1
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Freescale Semiconductor
PRELIMINARY
Block Diagram
Table 1 Package and Memory Options of MC9S12X F-Family Members
Device
Package
Flash
RAM
EEPROM
512K
32K
4K
384K
24K
4K
256K
20K
2K
128K
16K
2K
144 LQFP(1)
9S12XF512
112 LQFP
64 LQFP
144 LQFP(1)
9S12XF384
112 LQFP
64 QFP
144 LQFP(1)
9S12XF256
112 LQFP
64 QFP
144 LQFP(1)
9S12XF128
112 LQFP
64 QFP
NOTES:
1. The 144-Pin LQFP version will not be qualified for production and is
intended to be used for emulation (development tools) only.
Table 2 Peripheral Feature Summary of MC9S12X F-Family Members
Package
FlexRay
ECT
EPIT
CAN
SCI
SPI
A/D
PMF
144 LQFP(1)
2-ch
8ch
8ch
1
2
2
16-ch
6-ch
4 Fault Inputs
3 Current Sense
112 LQFP
2-ch
8ch
8ch
1
2
2
16-ch
6-ch
4 Fault Inputs
3 Current Sense
64 LQFP
1-ch
8ch
8ch
1
1
1
8-ch
6-ch
0 Fault Inputs
0 Current Sense
NOTES:
1. The 144-Pin LQFP version will not be qualified for production and is intended to be used for emulation
(development tools) only.
16-bit S12X Microcontroller Family with Integrated FlexRay Interface, Rev. 1
Freescale Semiconductor
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PRELIMINARY
Pin Assignments
Pin Assignments
Table 3 Port and Peripheral Availability by Package Option
Port
144 LQFP
112 LQFP
64 LQFP
Port AD/ADC Channels
16/16
16/16
8/8
Port A pins
8
8
0
Port B pins
8
2
0
Port C pins
8
0
0
Port D pins
8
6
0
Port E pins inc. IRQ/XIRQ input only
8
8
4
Port H/FlexRay Channels
8/A+B
8/A+B
4/A
Port J/PMF Current Sense
8/3
8/3
4/0
Port K pins
8
0
0
Port M/CAN/PMF Fault Inputs/SPI
8/1/2/1
8/1/2/1
2/1/0/0
Port P/PMF channels/PMF Fault Inputs
8/6/2
8/6/2
6/6/0
Port S/SCI/SPI
8/2/1
8/2/1
6/1/1
Port T/Timer Channels
8/8
8/8
8/8
VDDX/VSSX
4/4
3/3
2/2
Table 4 Pin-Out Summary
LQFP-144(1)
LQFP-112
LQFP-64
1
1
1
PP1
PMF1
2
2
2
PP0
PMF0
3
3
PD3
DATA3
4
4
PD2
DATA2
5
5
PD1
DATA1
6
6
PD0
DATA0
7
7
PT0
IOC0
3
Pin
2nd Func.
3rd Func.
4th Func.
16-bit S12X Microcontroller Family with Integrated FlexRay Interface, Rev. 1
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Freescale Semiconductor
PRELIMINARY
Pin Assignments
Table 4 Pin-Out Summary
LQFP-144(1)
LQFP-112
LQFP-64
8
8
4
PT1
IOC1
9
9
5
PT2
IOC2
10
10
6
PT3
IOC3
11
11
PJ0
IS0
12
12
PJ1
IS1
13
13
PJ2
IS2
14
14
7
VDDF
15
15
8
VSS1
16
16
VSSX3
17
17
VDDX3
18
18
9
PT4
IOC4
STB1
19
19
10
PT5
IOC5
STB2
20
20
11
PT6
IOC6
STB3
21
21
12
PT7
IOC7
22
PC0
DATA8
23
PC1
DATA9
24
PC2
DATA10
25
PC3
DATA11
26
PC4
DATA12
27
PC5
DATA13
28
PC6
DATA14
29
PC7
DATA15
Pin
2nd Func.
30
22
13
PJ3
STB0
31
23
14
PJ4
STB1
32
24
15
PJ5
STB2
33
25
16
PJ6
STB3
34
26
PJ7
35
27
PB0
ADDR0
36
28
PB1
ADDR1
3rd Func.
4th Func.
STB0(2)
UDS
16-bit S12X Microcontroller Family with Integrated FlexRay Interface, Rev. 1
Freescale Semiconductor
13
PRELIMINARY
Pin Assignments
Table 4 Pin-Out Summary
LQFP-144(1)
LQFP-112
LQFP-64
Pin
2nd Func.
37
PB2
ADDR2
38
PB3
ADDR3
3rd Func.
4th Func.
39
29
17
BKGD
MODC
40
30
18
PE7
XCLKS
ECLKX2
41
31
PE6
MODB
TAGHI
42
32
PE5
MODA
TAGLO
RE
43
33
PE4
ECLK
44
34
PE3
LSTRB
LDS
EROMCTL
45
35
PE2
RW
WE
46
36
PH4
RXD_B
47
37
PH5
TXD_B
48
38
PH6
TXE_B
49
39
PH7
50
40
20
VDDX2
51
41
21
VSSX2
52
42
22
VSS3
53
43
23
VDDR
54
44
24
RESET
55
45
25
VDDPLL
56
46
26
NC
57
47
27
VSSPLL
58
48
28
EXTAL
59
49
29
XTAL
60
50
30
TEST
19
No internal connection. Don’t connect!
61
PB4
ADDR4
62
PB5
ADDR5
63
PB6
ADDR6
64
PB7
ADDR7
PA0
ADDR8
65
51
16-bit S12X Microcontroller Family with Integrated FlexRay Interface, Rev. 1
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Freescale Semiconductor
PRELIMINARY
Pin Assignments
Table 4 Pin-Out Summary
LQFP-144(1)
LQFP-112
66
52
PA1
ADDR9
67
53
PA2
ADDR10
68
54
PA3
ADDR11
LQFP-64
Pin
69
VDDX4
70
VSSX4
2nd Func.
71
55
31
PE1
IRQ
72
56
32
PE0
XIRQ
73
57
33
PH0
RXD_A
74
58
34
PH1
TXD_A
75
59
35
PH2
TXE_A
76
60
36
PH3
3rd Func.
77
PK0
ADDR16
IQSTAT0
78
PK1
ADDR17
IQSTAT1
79
PK2
ADDR18
IQSTAT2
80
PK3
ADDR19
IQSTAT3
81
PK4
ADDR20
ACC0
82
PK5
ADDR21
ACC1
83
PK6
ADDR22
ACC2
84
PK7
EWAIT
ROMCTL
85
61
PA4
ADDR12
86
62
PA5
ADDR13
87
63
PA6
ADDR14
88
64
PA7
ADDR15
89
65
37
VDD
90
66
38
VSS2
91
67
39
PAD00
AN0
92
68
PAD08
AN8
93
69
PAD01
AN1
94
70
PAD09
AN9
40
4th Func.
16-bit S12X Microcontroller Family with Integrated FlexRay Interface, Rev. 1
Freescale Semiconductor
15
PRELIMINARY
Pin Assignments
Table 4 Pin-Out Summary
LQFP-144(1)
LQFP-112
LQFP-64
95
71
41
96
72
97
73
98
74
99
75
100
76
101
77
102
78
103
79
104
80
105
81
106
82
107
83
47
VDDA
108
84
48
VRH
109
85
49
VRL
110
86
50
VSSA
42
43
44
45
46
Pin
2nd Func.
PAD02
AN2
PAD10
AN8
PAD03
AN3
PAD11
AN11
PAD04
AN4
PAD12
AN12
PAD05
AN5
PAD13
AN13
PAD06
AN6
PAD14
AN14
PAD07
AN7
PAD15
AN15
111
NC
112
NC
113
87
51
PS0
RXD0
114
88
52
PS1
TXD0
115
89
PS2
RXD1
116
90
PS3
TXD1
117
91
53
PS4
MISO0
118
92
54
PS5
MOSI0
119
93
55
PS6
SCK0
120
94
56
PS7
SS0
121
NC
122
NC
123
95
PM7
SS1
3rd Func.
4th Func.
CS3
16-bit S12X Microcontroller Family with Integrated FlexRay Interface, Rev. 1
16
Freescale Semiconductor
PRELIMINARY
Pin Assignments
Table 4 Pin-Out Summary
LQFP-144(1)
LQFP-112
124
96
PM6
SCK1
125
97
PM5
MOSI1
126
98
PM4
MISO1
CS2
127
99
PM3
FAULT3
CS1
128
100
PM2
FAULT2
CS0
LQFP-64
Pin
129
NC
130
NC
2nd Func.
131
101
57
PM1
TXCAN0
132
102
58
PM0
RXCAN0
133
103
59
VSSX1
134
104
60
VDDX1
135
PD7
DATA7
136
PD6
DATA6
137
105
PD5
DATA5
138
106
PD4
DATA4
139
107
PP7
FAULT1
140
108
PP6
FAULT0
141
109
61
PP5
PMF5
142
110
62
PP4
PMF4
143
111
63
PP3
PMF3
144
112
64
PP2
PMF2
3rd Func.
4th Func.
NOTES:
1. The 144-Pin LQFP version will not be qualified for production and is intended to be used for emulation
(development tools) only.
2. STB3-0 on PT3-6 are equivalent to STB3-0 on PJ3-6
16-bit S12X Microcontroller Family with Integrated FlexRay Interface, Rev. 1
Freescale Semiconductor
17
PRELIMINARY
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
NC =No internal Connection
MC9S12XF-Family
144LQFP
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
VRH
VDDA
PAD15/AN15
PAD07/AN7
PAD14/AN14
PAD06/AN6
PAD13/AN13
PAD05/AN5
PAD12/AN12
PAD04/AN4
PAD11/AN11
PAD03/AN3
PAD10/AN10
PAD02/AN2
PAD09/AN9
PAD01/AN1
PAD08/AN08
PAD00/AN0
VSS2
VDD
PA7/ADDR15
PA6/ADDR14
PA5/ADDR13
PA4/ADDR12
PK7/EWAIT/ROMCTL
PK6/ADDR22/ACC2
PK5/ADDR21/ACC1
PK4/ADDR20/ACC0
PK3/ADDR19/IQSTAT3
PK2/ADDR18/IQSTAT2
PK1/ADDR17/IQSTAT1
PK0/ADDR16/IQSTAT0
PH3
PH2/TXE_A
PH1/TXD_A
PH0/RXD_A
ADDR2/PB2
ADDR3/PB3
MODC/BKGD
ECLKX2/XCLKS/PE7
TAGHI/MODB/PE6
RE/TAGLO/MODA/PE5
ECLK/PE4
EROMCTL/LDS/LSTRB/PE3
WE/RW/PE2
RXD_B/PH4
TXD_B/PH5
TXE_B/PH6
PH7
VDDX2
VSSX2
VSS3
VDDR
RESET
VDDPLL
NC
VSSPLL
EXTAL
XTAL
TEST
ADDR4/PB4
ADDR5/PB5
ADDR6/PB6
ADDR7/PB7
ADDR8/PA0
ADDR9/PA1
ADDR10/PA2
ADDR11/PA3
VDDX4
VSSX4
IRQ/PE1
XIRQ/PE0
PMF1/PP1
PMF0/PP0
DATA3/PD3
DATA2/PD2
DATA1/PD1
DATA0/PD0
IOC0/PT0
IOC1/PT1
IOC2/PT2
STB0/IOC3/PT3
IS0/PJ0
IS1/PJ1
IS2/PJ2
VDDF
VSS1
VSSX3
VDDX3
STB1/IOC4/PT4
STB2/IOC5/PT5
STB3/IOC6/PT6
IOC7/PT7
DATA8/PC0
DATA9/PC1
DATA10/PC2
DATA11/PC3
DATA12/PC4
DATA13/PC5
DATA14/PC6
DATA15/PC7
STB0/PJ3
STB1/PJ4
STB2/PJ5
STB3/PJ6
PJ7
UDS/ADDR0/PB0
ADDR1/PB1
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
112
112
111
110
109
PP2/PMF2
PP3/PMF3
PP4/PMF4
PP5/PMF5
PP6/FAULT0
PP7/FAULT1
PD4/DATA4
PD5/DATA5
PD6/DATA6
PD7/DATA7
VDDX1
VSSX1
PM0/RXCAN0
PM1/TXCAN0
NC
NC
PM2/FAULT2/CS0
PM3/FAULT3/CS1
PM4/MISO1/CS2
PM5/MOSI1
PM6/SCK1
PM7/SS1/CS3
NC
NC
PS7/SS0
PS6/SCK0
PS5/MOSI0
PS4/MISO0
PS3/TXD1
PS2/RXD1
PS1/TXD0
PS0/RXD0
NC
NC
VSSA
VRL
Pin Assignments
Pins shown in BOLD are not available on the 64-pin package option
Pins shown in ITALICS are not available on the 112-pin and 64-pin package options
Figure 1. MC9S12XF-Family Pin Assignments 144-pin LQFP Package
16-bit S12X Microcontroller Family with Integrated FlexRay Interface, Rev. 1
18
Freescale Semiconductor
PRELIMINARY
NC =No internal Connection
MC9S12XF-Family
112LQFP
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
VRH
VDDA
PAD15/AN15
PAD07/AN7
PAD14/AN14
PAD06/AN6
PAD13/AN13
PAD05/AN5
PAD12/AN12
PAD04/AN4
PAD11/AN11
PAD03/AN3
PAD10/AN10
PAD02/AN2
PAD09/AN09
PAD01/AN1
PAD08/AN08
PAD00/AN0
VSS2
VDD
PA7
PA6
PA5
PA4
PH3
PH2/TXE_A
PH1/TXD_A
PH0/RXD_A
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
MODC/BKGD
ECLKX2/XCLKS/PE7
PE6
PE5
ECLK/PE4
PE3
PE2
RXD_B/PH4
TXD_B/PH5
TXE_B/PH6
PH7
VDDX2
VSSX2
VSS3
VDDR
RESET
VDDPLL
NC
VSSPLL
EXTAL
XTAL
TEST
PA0
PA1
PA2
PA3
IRQ/PE1
XIRQ/PE0
PMF1/PP1
PMF0/PP0
PD3
PD2
PD1
PD0
IOC0/PT0
IOC1/PT1
IOC2/PT2
STB0/IOC3/PT3
IS0/PJ0
IS1/PJ1
IS2/PJ2
VDDF
VSS1
VSSX3
VDDX3
STB1/IOC4/PT4
STB2/IOC5/PT5
STB3/IOC6/PT6
IOC7/PT7
STB0/PJ3
STB1/PJ4
STB2/PJ5
STB3/PJ6
PJ7
PB0
PB1
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
PP2/PMF2
PP3/PMF3
PP4/PMF4
PP5/PMF5
PP6/FAULT0
PP7/FAULT1
PD4
PD5
VDDX1
VSSX1
PM0/RXCAN0
PM1/TXCAN0
PM2/FAULT2/CS0
PM3/FAULT3/CS1
PM4/MISO1/CS2
PM5/MOSI1
PM6/SCK1
PM7/SS1/CS3
PS7/SS0
PS6/SCK0
PS5/MOSI0
PS4/MISO0
PS3/TXD1
PS2/RXD1
PS1/TXD0
PS0/RXD0
VSSA
VRL
Pin Assignments
Pins shown in BOLD are not available on the 64-pin package option
Figure 2. MC9S12XF-Family Pin Assignments 112-pin LQFP Package
16-bit S12X Microcontroller Family with Integrated FlexRay Interface, Rev. 1
Freescale Semiconductor
19
PRELIMINARY
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
PP2/PMF2
PP3/PMF3
PP4/PMF4
PP5/PMF5
VDDX1
VSSX1
PM0/RXCAN0
PM1/TXCAN0
PS7/SS0
PS6/SCK0
PS5/MOSI0
PS4/MISO0
PS1/TXD0
PS0/RXD0
VSSA
VRL
Pin Assignments
NC =No internal Connection
MC9S12XF-Family
64LQFP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VRH
VDDA
PAD07/AN7
PAD06/AN6
PAD05/AN5
PAD04/AN4
PAD03/AN3
PAD02/AN2
PAD01/AN1
PAD00/AN0
VSS2
VDD
PH3
PH2/TXE_A
PH1/TXD_A
PH0/RXD_A
MODC/BKGD
XCLKS/PE7
ECLK/PE4
VDDX2
VSSX2
VSS3
VDDR
RESET
VDDPLL
NC
VSSPLL
EXTAL
XTAL
TEST
IRQ/PE1
XIRQ/PE0
PMF1/PP1
PMF0/PP0
IOC0/PT0
IOC1/PT1
IOC2/PT2
STB0/IOC3/PT3
VDDF
VSS1
STB1/IOC4/PT4
STB2/IOC5/PT5
STB3/IOC6/PT6
IOC7/PT7
STB0/PJ3
STB1/PJ4
STB2/PJ5
STB3/PJ6
Figure 3. MC9S12XF-Family Pin Assignments 64-pin LQFP Package
NOTE
Pin 56 on the 114-pin LQFP, Pin 46 on the 112-pin LQFP and pin 26 on the
64-pin LQFP don’t have to be connected.
16-bit S12X Microcontroller Family with Integrated FlexRay Interface, Rev. 1
20
Freescale Semiconductor
PRELIMINARY
Memory Maps
Memory Maps
0x0000
2K Register Space
0x0800
0x0C00
Data Flash accessible * 1K pages through 0x0800 - 0x0BFF
EEPAGE * 1K pages accessible through 0x0800 - 0x0BFF
1K fixed EEPROM
0x1000
RAM
RPAGE * 4K pages accessible through 0x1000 - 0x1FFF
0x2000
RAM
8K Fixed RAM
0x4000
1K, 2K, 4K or 8K Protected Sector
16K Fixed Flash or 16K RAM (Remappable range)
External
0x8000
16K Page Window
PPAGE * 16K Flash Pages
0xC000
16K Fixed Flash
VECTORS
VECTORS
BDM
NORMAL
SINGLE CHIP
EXPANDED
SPECIAL
SINGLE CHIP
0xFF00
2K, 4K, 8K or 16K
Protected Boot Sector
0xFFFF
Figure 4. MC9S12XF-Family Memory Map
16-bit S12X Microcontroller Family with Integrated FlexRay Interface, Rev. 1
Freescale Semiconductor
21
PRELIMINARY
Memory Maps
CPU and BDM
Local Memory Map
Global Memory Map
0x00_0000
0x00_07FF
2K REGISTERS
CS3
Unimplemented
RAM
0x0000
0x0800
0x0C00
0x1000
RAMSIZE
RAM_LOW
RAM
2K REGISTERS
1K EEPROM window
EPAGE
0x0F_FFFF
1K EEPROM
DFLASH
4K RAM window
RPAGE
DF_HIGH
0x2000
EEEPROM
RESSOURCES
8K RAM
0x4000
0x13_FFFF
CS2
Unpaged
16K FLASH
0x1F_FFFF
CS1
0x8000
External
Space
PPAGE
0x3F_FFFF
0xC000
CS0
16K FLASH window
Unimplemented
FLASH
Unpaged
16K FLASH
Reset Vectors
FLASH_LOW
FLASHSIZE
0xFFFF
FLASH
0x7F_FFFF
Figure 5 MC9S12XF512 Global Memory Map
16-bit S12X Microcontroller Family with Integrated FlexRay Interface, Rev. 1
22
Freescale Semiconductor
PRELIMINARY
Memory Maps
Table 5 9S12XF512 Dependent Memory Parameters
Device
FLASH_LOW
PPAGE(1)
RAM_LOW
RPAGE(2)
DF_HIGH
EPAGE
9S12XF512
0x78_0000
32
0x0F_8000
8
0x10_7FFF
32
NOTES:
1. Number of 16K pages addressable via PPAGE register
2. Number of 4K pages addressing the RAM. RAM can also be mapped to 0x4000 - 0x7FFF
16-bit S12X Microcontroller Family with Integrated FlexRay Interface, Rev. 1
Freescale Semiconductor
23
PRELIMINARY
Memory Maps
CPU and BDM
Local Memory Map
Global Memory Map
0x00_0000
0x00_07FF
2K REGISTERS
CS3
Unimplemented
RAM
0x0000
0x0800
0x0C00
0x1000
RAMSIZE
RAM_LOW
RAM
2K REGISTERS
1K EEPROM window
EPAGE
0x0F_FFFF
RPAGE
DF_HIGH
1K EEPROM
4K RAM window
DFLASH
0x2000
EEEPROM
RESSOURCES
8K RAM
0x4000
0x13_FFFF
CS2
Unpaged
16K FLASH
0x1F_FFFF
External
Space
CS1
0x8000
PPAGE
0x3F_FFFF
0xC000
CS0
16K FLASH window
Unimplemented
FLASH
Unpaged
16K FLASH
0xFFFF
Reset Vectors
0x78_0000
FLASHSIZE
FLASH0_LOW
Unimplemented
FLASH
FLASH1_HIGH
CS0
FLASH0
FLASH1
0x7F_FFFF
Figure 6 MC9S12XF384 , MC9S12XF256 and MC9S12XF128 Global Memory Map
16-bit S12X Microcontroller Family with Integrated FlexRay Interface, Rev. 1
24
Freescale Semiconductor
PRELIMINARY
Memory Maps
Table 6 Derivative Dependent Memory Parameters
Device
FLASH0_LOW
FLASH1_HIGH
PPAGE(1)
RAM_LOW
RPAGE(2)
DF_HIGH
EPAGE
9S12XF384
0x79_FFFF
0x7C_0000
24
0x0F_A000
6
0x10_7FFF
32
9S12XF256
0x79_FFFF
0x7E_0000
16
0x0F_6000
5
0x10_7FFF
32
9S12XF128
0x78_FFFF
0x7F_0000
8
0x0F_C000
4
0x10_3FFF
16
NOTES:
1. Number of 16K pages addressable via PPAGE register
2. Number of 4K pages addressing the RAM. RAM can also be mapped to 0x4000 - 0x7FFF
16-bit S12X Microcontroller Family with Integrated FlexRay Interface, Rev. 1
Freescale Semiconductor
25
PRELIMINARY
Mechanical Package Dimensions
Mechanical Package Dimensions
0.20 T L-M N
4X
PIN 1
IDENT
0.20 T L-M N
4X 36 TIPS
144
109
1
108
4X
J1
P
J1
L
M
CL
B
V
X
G
140X
B1
VIEW Y
36
VIEW Y
V1
NOTES:
1. DIMENSIONS AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS.
3. DATUMS L, M, N TO BE DETERMINED AT THE
SEATING PLANE, DATUM T.
4. DIMENSIONS S AND V TO BE DETERMINED
AT SEATING PLANE, DATUM T.
5. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.25 PER SIDE. DIMENSIONS
A AND B DO INCLUDE MOLD MISMATCH
AND ARE DETERMINED AT DATUM PLANE H.
6. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL NOT CAUSE THE D
DIMENSION TO EXCEED 0.35.
73
37
72
N
A1
S1
A
S
VIEW AB
C
0.1 T
θ2
144X
SEATING
PLANE
θ2
T
PLATING
J
AA
F
C2
0.05
R2
θ
R1
0.08
M
0.25
BASE
METAL
D
GAGE PLANE
T L-M N
SECTION J1-J1
(ROTATED 90 ° )
144 PL
(K)
C1
E
(Y)
VIEW AB
MILLIMETERS
DIM MIN MAX
A
20.00 BSC
A1
10.00 BSC
B
20.00 BSC
B1
10.00 BSC
C
1.40
1.60
C1
0.05
0.15
C2
1.35
1.45
D
0.17
0.27
E
0.45
0.75
F
0.17
0.23
G
0.50 BSC
J
0.09
0.20
K
0.50 REF
P
0.25 BSC
R1
0.13
0.20
R2
0.13
0.20
S
22.00 BSC
S1
11.00 BSC
V
22.00 BSC
V1
11.00 BSC
Y
0.25 REF
Z
1.00 REF
AA
0.09
0.16
θ
0°
θ1
0°
7°
θ2
11°
13 °
θ1
(Z)
Figure 7 144-pin LQFP Mechanical Dimensions (case no. 918-03)
16-bit S12X Microcontroller Family with Integrated FlexRay Interface, Rev. 1
26
Freescale Semiconductor
PRELIMINARY
Mechanical Package Dimensions
0.20 T L-M N
4X
PIN 1
DENT
0.20 T L-M N
4X 28 TIPS
112
J1
85
4X
P
J1
1
CL
84
VIEW Y
108X
G
X
X=L, M OR N
VIEW Y
B
L
V
M
B1
28
AA
J
V1
57
29
F
D
56
0.13
N
M
BASE
METAL
T L-M N
SECTION J1-J1
ROTATED 90 ° COUNTERCLOCKWISE
A1
S1
A
S
C2
C
VIEW AB
θ2
0.050
0.10 T
112X
SEATING
PLANE
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS.
3. DATUMS L, M AND N TO BE DETERMINED AT
SEATING PLANE, DATUM T.
4. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE, DATUM T.
5. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.25 PER SIDE. DIMENSIONS
A AND B INCLUDE MOLD MISMATCH.
6. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL NOT CAUSE THE D
DIMENSION TO EXCEED 0.46.
θ3
T
θ
R
R2
R
0.25
R1
GAGE PLANE
(K)
C1
E
θ1
(Y)
(Z)
VIEW AB
DIM
A
A1
B
B1
C
C1
C2
D
E
F
G
J
K
P
R1
R2
S
S1
V
V1
Y
Z
AA
θ
θ1
θ2
θ3
MILLIMETERS
MIN
MAX
20.000 BSC
10.000 BSC
20.000 BSC
10.000 BSC
--1.600
0.050
0.150
1.350
1.450
0.270
0.370
0.450
0.750
0.270
0.330
0.650 BSC
0.090
0.170
0.500 REF
0.325 BSC
0.100
0.200
0.100
0.200
22.000 BSC
11.000 BSC
22.000 BSC
11.000 BSC
0.250 REF
1.000 REF
0.090
0.160
8 °
0°
7 °
3 °
13 °
11 °
11 °
13 °
Figure 8 112-pin LQFP Mechanical Dimensions (case no. 987)
16-bit S12X Microcontroller Family with Integrated FlexRay Interface, Rev. 1
Freescale Semiconductor
27
PRELIMINARY
Mechanical Package Dimensions
4X
4X 16 TIPS
0.2 H A–B D
0.2 C A–B D
A2
D
PIN 1
IDENTIFIER
0.05
S
49
64
1
(S)
48
Z1
A
0.25
B
Z
E
E1
R1
A1
3X
E1/2
VIEW Y
16
E/2
D/2
D1
D
Z2
4X
A
0.08 C
J
64X
SEATING
PLANE
C
0.08
M
b
J
Z3
4X
8. THESE DIMENSIONS APPLY TO THE FLAT SECTION
OF THE LEAD BETWEEN 0.10 mm AND 0.25 mm FROM
THE LEAD TIP.
VIEW AA
C A–B D
X
X=A, B OR D
CL
AB
e/2
AB
60X
L
(L1)
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES PER
ASME Y14.5M–1994.
3. DATUMS A, B AND D TO BE DETERMINED AT DATUM
PLANE H.
4. DIMENSIONS D AND E TO BE DETERMINED AT
SEATING PLANE C.
5. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED
THE MAXIMUM b DIMENSION BY MORE THAN 0.08
mm. DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN
PROTRUSION AND ADJACENT LEAD OR
PROTRUSION 0.07 mm.
6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 mm
PER SIDE. D1 AND E1 ARE MAXIMUM PLASTIC BODY
SIZE DIMENSIONS INCLUDING MOLD MISMATCH.
7. EXACT SHAPE OF EACH CORNER IS OPTIONAL.
32
D1/2
H
GAGE PLANE
VIEW AA
33
17
R
BASE METAL
ÇÇÇÇ
ÉÉÉÉÉ
ÉÉÉÉÉ
ÇÇÇÇ
ÇÇÇÇ
ÉÉÉÉÉ
8
b1
e
VIEW Y
8
F
PLATING
c
c1 8
8
b
SECTION AB–AB
DIM
A
A1
A2
b
b1
c
c1
D
D1
e
E
E1
L
L1
R1
R2
S
F
G
Z
Z1
Z2
Z3
MILLIMETERS
MIN
MAX
–––
1.60
0.05
0.15
1.35
1.45
0.17
0.27
0.17
0.23
0.09
0.20
0.09
0.16
12.00 BSC
10.00 BSC
0.50 BSC
12.00 BSC
10.00 BSC
0.45
0.75
1.00 REF
0.08
–––
0.08
–––
0.20
–––
6.00
7.00
6.00
7.00
0_
7_
0_
–––
11 _
13 _
11 _
13 _
ROTATED 90 _ CLOCKWISE
G
EXPOSED PAD
VIEW J–J
Figure 9 64-pin exposed LQFP Mechanical Dimensions (case no. 840K-01)
16-bit S12X Microcontroller Family with Integrated FlexRay Interface, Rev. 1
28
Freescale Semiconductor
PRELIMINARY
Revision History
Revision History
Table 7 Revision History
Revision
Number
Revision
Date
1
06-Dec-2006
Author
Description
Updated global memory map for all XF family derivatives.
16-bit S12X Microcontroller Family with Integrated FlexRay Interface, Rev. 1
Freescale Semiconductor
29
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