Freescale Semiconductor Product Brief S12XHZ512PB Rev. 4.1, 4-Jan-2007 MC9S12XHZ512 Also covers MC9S12XHZ384 and MC9S12XHZ256 16-bit S12X Microcontroller with LCD and Stepper Motor Drivers Introduction Targeted at automotive instrumentation applications, the MC9S12XHZ512 microcontroller unit (MCU) is a fully pin-compatible extension to the existing MC9S12HZ-Family of microcontrollers. It offers not only a larger memory than the existing S12-based family but also incorporates all the architectural benefits of the new S12X-based family to deliver significantly higher performance. The MC9S12XHZ512 retains the low cost, power consumption, EMC and code-size efficiency advantages currently associated with the MC9S12HZ-Family products. Based around S12X core, the MC9S12XHZ512 runs 16-bit wide accesses without wait states for all peripherals and memories. The MC9S12XHZ512 also features a new flexible interrupt handler, which allows multilevel nested interrupts. The MC9S12XHZ512 features the performance boosting XGATE co-processor. The XGATE is programmable in “C” language and runs at twice the bus frequency of the S12. Its instruction set is optimized for data movement, logic and bit manipulation instructions. Any peripheral module can be serviced by the XGATE. The MC9S12XHZ512 contains 512K bytes of Freescale Semiconductor’s industry leading, full automotive qualified Split-Gate Flash memory, with 4K bytes of additional integrated data EEPROM and 32K bytes of static RAM. © Freescale Semiconductor, Inc., 2006. All rights reserved. Features The MC9S12XHZ512 features a 32x4 liquid crystal display (LCD) controller/driver and a motor pulse width modulator (MC) consisting of up to 24 high current outputs suited to drive six stepper motors with stall detectors (SSD) to simultaneously calibrate the pointer reset position of each motor. It also features two MSCAN modules, each with a FIFO receiver buffer arrangement, and input filters optimized for Gateway applications handling numerous message identifiers. In addition, the MC9S12XHZ512 is composed of standard on-chip peripherals including two asynchronous serial communications interfaces (SCI0 and SCI1), one serial peripheral interface (SPI), two IIC-bus interface (IIC0 and IIC1), an 8-channel 16-bit enhanced capture timer (ECT), a 16-channel, 10-bit analog-to-digital converter (ADC), and one 8-channel pulse width modulator (PWM). The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirements. The new fast-exit from STOP mode feature can further improve system power consumption. In addition to the I/O ports available in each module, 8 general purpose I/O ports are available with interrupt capability allowing wake-up from STOP or WAIT mode. The MC9S12XHZ512 is available in 112-pin LQFP and 144-pin LQFP packages. The 144-pin LQFP package option provides a full 16-bit wide non-multiplexed external bus interface. Features Features of the MC9S12XHZ512 are listed here. Please see Table 1 for the features that are available on the different family members. 16-Bit CPU12X Enhanced Interrupt Module XGATE • Upward compatible with MC9S12 instruction set • Enhanced indexed addressing • Additional (superset) instructions to improve 32-bit calculations and semaphore handling • Access large data segments independent of PPAGE • Eight levels of nested interrupt • Flexible assignment of interrupt sources to each interrupt level • One non-maskable high priority interrupt (XIRQ) • Wakeup interrupt inputs (IRQ and XIRQ) • Programmable, high performance I/O co-processor - up to 80 MIPS RISC performance • Transfers data to or from all peripherals and RAM without CPU intervention or CPU wait states • Performs simple logical, shifts, arithmetic, and bit operations on data • Enables FullCAN capability when used in conjunction with MSCAN • Full LIN master or slave capability when used in conjunction with SCI. • Triggers from any hardware module as well as from the CPU MC9S12XHZ512, Rev. 4.1 2 Freescale Semiconductor Features • 512K, 384K, 256K byte FLASH – Erase sector size 1024 bytes – Automated program and erase algorithm – Fast sector erase and word program operation – 2-stage command pipeline for faster multi-word program times – Sector erase abort feature for critical interrupt response – Protection scheme to prevent accidental program or erase – Security option to prevent unauthorized access – Code integrity check using built-in data compression – Sense-amp margin level setting for reads • 4K byte EEPROM – Small erase sector 4 bytes – Automated program and erase algorithm – Fast sector erase and word program operation – 2-stage command pipeline for faster multi-word program times – Sector erase abort feature for critical interrupt response – Protection scheme to prevent accidental program or erase • 32K, 28K, 16K byte RAM • Loop Control Pierce oscillator utilizing a 0.5Mhz to 16Mhz crystal • Option for full-swing Pierce without internal feedback resistor utilizing a 0.5Mhz to 40Mhz crystal • Current gain control on amplitude output – Signal with low harmonic distortion – Low power – Good noise immunity – Eliminates need for external current limiting resistor • Transconductance sized for optimum start-up margin for typical crystals • Clock monitor • Phase-locked-loop clock frequency multiplier – Reference divider – Automatic bandwidth control mode for low-jitter operation – Automatic frequency lock detector • Fast wake up from STOP in self clock mode for power saving and immediate program execution • Computer Operating Properly (COP) watchdog with optional safety window to initialize time-out counter • Real Time Interrupt for task scheduling purposes or cyclic wake-up from low power modes • System reset generation Memory Options Oscillator (OSC_LCP) Clock and Reset Generator (CRG) MC9S12XHZ512, Rev. 4.1 Freescale Semiconductor 3 Features Liquid Crystal Display (LCD) Motor Controller (MC) Stepper Stall Detector (SSD0, SSD1, SSD2, SSD3, SSD4, SSD5) Analog-to-Digital Converter (ADC) Enhanced Capture Timer (ECT) • 32 frontplanes and 4 backplanes • 5 modes of operation allow for different display sizes to meet application requirements • Programmable frame clock generator and bias voltage level • 24 high current drivers suited for PWM motor control • Each PWM channel switchable between two drivers in an H-bridge configuration • Support for sine and cosine drive • 11-bit resolution with selectable dithering function • Left, right or center aligned outputs • Slew rate control • Flexible full step and polarity set up to return the pointer to its reset position in clockwise or counter clockwise direction. • Integrator/Sigma Delta converter circuit to measure the induced voltage by the back EMF of non-powered coil during full step (only one of the two motor coils is powered) operation. • 16-Bit Down Counter to monitor blanking and integration time to support stepper motors with different gear ratios. • 16-Bit accumulator register to read integration value, compare to a threshold at the end of integration time, and decide if the motor is stalled under this value or moving above this value. • 8-bit or 10-bit resolution • Multiplexer for 16 analog input channels • 7µs, 10-bit single conversion time • Programmable sample time • Left/right, signed/unsigned result data • Continuous conversion mode • Multiple channel scans • External and internal conversion trigger capability • Eight 16-bit channels for input capture or output compare • One 16-bit free-running counter with 8-bit precision prescaler • One 16-bit modulus down counter with 8-bit precision prescaler • Four 8-bit or two 16-bit pulse accumulators • Four channels have enhanced input capture capabilities: – Delay counter for noise immunity – 16-bit capture buffer – 8-bit pulse accumulator buffer MC9S12XHZ512, Rev. 4.1 4 Freescale Semiconductor Features • Four channel x 24-bit modulus down-count timers – Timeout interrupt – Timeout peripheral trigger • Start of timers can be aligned • Eight 8-bit or four 16-bit independent channels • Programmable period and duty cycle per channel • Center-aligned or left-aligned outputs • Programmable clock select and with a wide frequency range • CAN 2.0 A, B software compatible – Standard and extended data frames – 0 - 8 bytes data length – Programmable bit rate up to 1 Mbps • Five receive buffers with FIFO storage scheme • Three transmit buffers with internal prioritization • Flexible identifier acceptance filter programmable as: – 2 x 32-bit – 4 x 16-bit – 8 x 8-bit • Wake-up with integrated low pass filter option • Loop back for self test • Listen-only mode to monitor CAN bus • Bus-off recovery by software intervention or automatically • 16-bit time stamp of transmitted/received messages • FullCAN capability when used in conjuntion with XGATE • Full-duplex or single wire operation • Standard mark/space non-return-to-zero (NRZ) format • Selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse widths • 13-bit baud rate selection • Programmable character length • Programmable polarity for transmitter and receiver • Receive wakeup on active edge • Break detect and transmit collision detect supporting LIN Periodic Interrupt Timer (PIT) Pulse Width Modulator (PWM) Multi-scalable Controller Area Networks (MSCAN0, MSCAN1) Serial Communication Interfaces (SCI0, SCI1) MC9S12XHZ512, Rev. 4.1 Freescale Semiconductor 5 Features Serial Peripheral Interface (SPI) Inter-IC Bus (IIC0, IIC1) • Full-duplex or single-wire bidirectional • Double-buffered transmit and receive • Master or Slave mode • MSB-first or LSB-first shifting • Serial clock phase and polarity options • Compatible with I2C Bus standard • Supports 400 kbps • Multi-master operation • Software programmable for one of 256 different serial clock frequencies • Software selectable acknowledge bit • Interrupt driven byte-by-byte data transfer • Arbitration lost interrupt with automatic switch from master to slave mode • 7-bit or 10-bit calling address identication interrupt • Bus busy detection • Supports General Call address • Background debug controller (BDC) with single-wire interface – Non-intrusive memory access commands – Supports in-circuit programming of on-chip non-volatile memory – Supports security • Four comparators A, B, C and D – Each can monitor CPU or XGATE busses – A and C compares 23-bit address bus and 16-bit data bus with mask register – B and D compares 23-bit address bus only – Three modes: simple address/data match, inside address range or outside address range • 64 x 64-bit circular trace buffer to capture change-of-flow addresses or address and data of every access • Tag-type or force-type hardware breakpoint requests • Power-on reset (POR) • Illegal opcode and illegal address detection with reset • Low-voltage detection with interrupt or reset Background Debug (BDM) Debugger (XDBG) System Protection MC9S12XHZ512, Rev. 4.1 6 Freescale Semiconductor Features Input/Output Package Options • 115 general-purpose input/output (I/O) pins and 2 input-only pins • Hysteresis and configurable pull up/pull down device on all input pins • Configurable drive strength on all output pins • Eight interrupt pins with digital filtering and rising or falling edge trigger • 144-pin low-profile quad flat-pack (LQFP) • 112-pin low-profile quad flat-pack (LQFP) • Ambient temperature range –40 to 125°C • Temperature options: – –40 to 85°C – –40 to 105°C – –40 to 125°C • Supply voltage 4.5 to 5.5 V • 40 MHz maximum CPU bus frequency in single chip mode • 80 Mhz maximum XGATE bus frequency Operating Conditions Table 1 Options of MC9S12XHZ-Family Device Package Flash RAM EEPROM XGATE CAN SCI SPI IIC A/D ECT LCD PWM Motor SSD KWU EBI I/O 9S12XHZ512 9S12XHZ384 9S12XHZ256 • 144 LQFP 112 LQFP 144 LQFP 112 LQFP 144 LQFP 112 LQFP 512K 32K 4K yes 2 2 1 2 16 8 32x4 384K 28K 4K yes 2 2 1 2 16 8 32x4 256K 16K 4K yes 2 2 1 2 16 8 32x4 8 24/6 6 6 16/4 4 8 24/6 6 6 16/4 4 8 24/6 6 6 16/4 4 8 8 8 Yes 117 No Yes 117 No 85 Yes 117 No Pin out explanations: – A/D is the number of A/D channels. – PWM is the number of PWM channels. – ECT is the number of ECT channels. – LCD denotes the number of front planes times the number of back planes. – Motor denotes the number of high current drive pins / number of stepper motors which can be driven – SSD denotes whether this device features a Stepper Stall Detection Circuit – Versions with one SCI will use SCI0 – Versions with one CAN will use CAN0 – Versions with one IIC will use IIC0 – I/O is the sum of ports capable to act as digital input or output. MC9S12XHZ512, Rev. 4.1 Freescale Semiconductor 85 7 85 Block Diagram Block Diagram Pins and signals shown in BOLD are not available in the 112 QFP package 512K, 284K, 256K Bytes Flash EEPROM 4k Bytes EEPROM VDDR VDD1 VSS1,2 Enahanced Capture Timer SSD1 SSD2 FP23 LCD Driver SSD3 M2COSM M2COSP M2SINM M2SINP M3COSM M3COSP M3SINM M3SINP SSD4 M4COSM M4COSP M4SINM M4SINP SSD5 M5COSM M5COSP M5SINM M5SINP PTAD DDRAD PU0 PU1 PU2 PU3 PWM2 M0C1M M0C1P M1C0M M1C0P PWM3 M1C1M M1C1P PU6 PU7 PWM4 M2C0M M2C0P PV0 PV1 M2C1M M2C1P M3C0M M3C0P PV2 PV3 PWM1 PWM5 PWM6 M3C1M M3C1P M4C0M PWM8 M4C0P M4C1M PWM9 M4C1P M5C0M PWM10 M5C0P M5C1M PWM11 M5C1P PTU M0SINM M0SINP M1COSM M1COSP M1SINM M1SINP PV4 PV5 PW0 PW1 PW2 PW3 PW4 PW5 PW6 PW7 VSSM1,2,3 A/D Converter & Voltage Regulator 5V VDDA RXCAN1 CAN1 TXCAN1 SCI0 RXD0 TXD0 SCI1 RXD1 TXD1 SPI MISO MOSI SCK SS VSSA PLL Supply 2.5V VDDPLL VSSPLL I/O Supply 5V VDDX1,2 VSSX1,2 PW0 PW1 Pulse PW2 Width Modulator PW3 PW4 PW5 PW6 PW7 Internal 2.5V VDD1 VSS1,2 Voltage Regulator 5V VDDR Voltage Regulator IIC0 SDA0 SCL0 IIC1 SDA1 SCL1 PTM RXCAN0 CAN0 TXCAN0 DDRS PTS Motor Supplies VDDM1,2,3 DDRM VLCD PTP FP24 FP25 FP26 FP27 SDA0 SCL0 SDA1 SCL1 PU4 PU5 PV6 PV7 PWM7 VLCD FP0 FP1 FP2 FP3 FP4 FP5 FP6 FP7 FP8 FP9 FP10 FP11 FP12 FP13 FP14 FP15 PAD0 PAD1 PAD2 PAD3 PAD4 PAD5 PAD6 PAD7 M0C0M M0C0P PWM0 DDRU FP22 BP0 BP1 BP2 BP3 M0COSM M0COSP PTV SSD0 KWAD0 KWAD1 KWAD2 KWAD3 KWAD4 KWAD5 KWAD6 KWAD7 DDRV FP20 FP21 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 DDRP IOC0 IOC1 IOC2 IOC3 IOC4 IOC5 IOC6 IOC7 Non-Multiplexed External Bus Interface XIRQ IRQ RW/WE LSTRB/LDS/EROMCTL ECLK MODA/TAGLO/RE MODB/TAGHI XCLKS/ECLKX2 ADDR16/IQSTAT0 ADDR17/IQSTAT1 ADDR18/IQSTAT2 ADDR19/IQSTAT3 ADDR20/ACC0 ADDR21/ACC1 ADDR22/ACC2 EWAIT/ROMCTL DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 VDDA VSSA VRH VRL VDDA VSSA VRH VRL Analog to Digital Converter PTW Breakpoints Enhanced Multilevel Interrupt Module AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 DDRW Clock Monitor DDRL PTL PTE DDRE DDRK PTK PTD DDRD DDRC PTC PTB COP Watchdog FP16 FP17 FP18 FP19 FP28 FP29 FP30 FP31 ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 4-Channel Programmable Interrupt Timer (PIT) for internal timebases Periodic Interrupt Clock and Reset Generation Module DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 XGATE Peripheral Co-Processor Module-to-Port-Routing PT0 PT1 PT2 PT3 PT4 PT5 PT6 PT7 DDRB PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PTA PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 DDRA PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 PK0 PK1 PK2 PK3 PK4 PK5 PK6 PK7 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PLL PTT XFC VDDPLL VSSPLL EXTAL XTAL RESET PL0 PL1 PL2 PL3 PL4 PL5 PL6 PL7 32K, 28K, 16K Bytes RAM Single-Wire Background CPU12X Debug Module DDRT TEST BKGD PM1 CS1 PM2 PM3 PM4 PM5 PS0 PS1 PS2 CS3 PS3 PS4 PS5 PS6 PS7 PP0 PP1 PP2 PP3 PP4 PP5 PP6 CS0 PP7 CS2 Figure 1. MC9S12XHZ512 Block Diagram MC9S12XHZ512, Rev. 4.1 8 Freescale Semiconductor Pin Assignments 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 PT7/IOC7/SCL1 PT6/IOC6/SDA1 PT5/IOC5/SCL0 PT4/IOC4/SDA0 PT3/IOC3/FP27 PT2/IOC2/FP26 PT1/IOC1/FP25 PT0/IOC0/FP24 PC7/DAT15 PC6/DAT14 PC5/DAT13 PC4/DAT12 VSSX1 VDDX1 PK7/EWAIT/ROMCTL/FP23 PE7/ECLKX2/XCLKS/FP22 PE3/LSTRB/LDS/EROMCTL/FP21 PE2/RW/WE/FP20 PC3/DAT11 PC2/DAT10 PC1/DAT9 PC0/DAT8 PL3/AN11/FP19 PL2/AN10/FP18 PL1/AN9/FP17 PL0/AN8/FP16 PA7/ADDR15/FP15 PA6/ADDR14/FP14 PA5/ADDR13/FP13 PA4/ADDR12/FP12 PA3/ADDR11/FP11 PA2/ADDR10/FP10 PA1/ADDR9/FP9 PA0/ADDR8/FP8 PB7/ADDR7/FP7 PB6/ADDR6/FP6 Pin Assignments 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 144 LQFP Pins shown in BOLD are not available in the 112 QFP package 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 PB5/ADDR5/FP5 PB4/ADDR4/FP4 PB3/ADDR3/FP3 PB2/ADDR2/FP2 PB1/ADDR1/FP1 PB0/ADDR0/FP0 PK0/ADDR16/BP0 PK1/ADDR17/BP1 PK2/ADDR18/BP2 PK3/ADDR19/BP3 VLCD VSS1 VDD1 PD7/DATA7 PD6/DATA6 PD5/DATA5 PD4/DATA4 PD3/DATA3 PD2/DATA2 PD1/DATA1 PD0/DATA0 PAD7/KWAD7/AN7 PAD6/KWAD6/AN6 PAD5/KWAD5/AN5 PAD4/KWAD4/AN4 PAD3/KWAD3/AN3 PAD2/KWAD2/AN2 PAD1/KWAD1/AN1 PAD0/KWAD0/AN0 VDDA VRH VRL VSSA PE0/XIRQ PE4/ECLK PE6/MODB/TAGHI PWM3/PP3 RXD1/PWM2/PP2 TXD1/PWM0/PP0 PWM1/PP1 CS0/SDA1/PWM6/PP6 CS2/SCL1/PWM7/PP7 ACC0/ADDR20/PK4 ACC1/ADDR21/PK5 RXD0/PS0 TXD0/PS1 CS3/RXD1/PS2 TXD1/PS3 VSS2 VDDR VDDX2 VSSX2 MODC/BKGD RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST ACC2/ADDR22/PK6 CS1/PM1 RXCAN0/PM2 TXCAN0/PM3 RXCAN1/PM4 TXCAN1/PM5 TAGLO/RE/MODA/PE5 MISO/PS4 MOSI/PS5 SCK/PS6 SS/PS7 IRQ/PE1 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 FP28/AN12/PL4 FP29AN13//PL5 FP30/AN14//PL6 FP31/AN15/PL7 M4C0M/M4COSM/PW0 M4C0P/M4COSP/PW1 M4C1M/M4SINM/PW2 M4C1P/M4SINP/PW3 VDDM1 VSSM1 M0C0M/M0COSM/PU0 M0C0P/M0COSP/PU1 M0C1M/M0SINM/PU2 M0C1P/M0SINP/PU3 M1C0M/M1COSM/PU4 M1C0P/M1COSP/PU5 M1C1M/M1SINM/PU6 M1C1P/M1SINP/PU7 VDDM2 VSSM2 M2C0M/M2COSM/PV0 M2C0P/M2COSP/PV1 M2C1M/M2SINM/PV2 M2C1P/M2SINP/PV3 M3C0M/M3COSM/PV4 M3C0P/M3COSP/PV5 M3C1M/M3SINM/PV6 M3C1P/M3SINP/PV7 VDDM3 VSSM3 M5C0M/M5COSM/PW4 M5C0P/M5COSP/PW5 M5C1M/M5SINM/PW6 M5C1P/M5SINP/PW7 SCL0/PWM5/PP5 SDA0/PWM4/PP4 Figure 2. 144-Pin Package Signal Assignments MC9S12XHZ512, Rev. 4.1 Freescale Semiconductor 9 PT3/IOC3/FP27 PT2/IOC2/FP26 PT1/IOC1/FP25 PT0/IOC0/FP24 VSSX1 VDDX1 PK7/FP23 PE7/XCLKS/FP22 PE3/FP21 PE2/FP20 PL3/AN11/FP19 PL2/AN10/FP18 PL1/AN9/FP17 PL0/AN8/FP16 PA7/FP15 PA6/FP14 PA5/FP13 PA4/FP12 PA3/FP11 PA2/FP10 PA1/FP9 PA0/FP8 PB7/FP7 PB6/FP6 PT7/IOC7/SCL1 PT6/IOC6/SDA1 PT5/IOC5/SCL0 PT4/IOC4/SDA0 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 112 LQFP PB5/FP5 PB4/FP4 PB3/FP3 PB2/FP2 PB1/FP1 PB0/FP0 PK0/BP0 PK1/BP1 PK2/BP2 PK3/BP3 VLCD VSS1 VDD1 PAD7/KWAD7/AN7 PAD6/KWAD6/AN6 PAD5/KWAD5/AN5 PAD4/KWAD4/AN4 PAD3/KWAD3/AN3 PAD2/KWAD2/AN2 PAD1/KWAD1/AN1 PAD0/KWAD0/AN0 VDDA VRH VRL VSSA PE0/XIRQ PE4/ECLK PE6 PE5 MISO/PS4 MOSI/PS5 SCK/PS6 SS/PS7 IRQ/PE1 RXCAN1/PM4 TXCAN1/PM5 PWM3/PP3 RXD1/PWM2/PP2 TXD1/PWM0/PP0 PWM1/PP1 RXD0/PS0 TXD0/PS1 VSS2 VDDR VDDX2 VSSX2 MODC/BKGD RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST RXCAN0/PM2 TXCAN0/PM3 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 FP28/AN12/PL4 FP29AN13//PL5 FP30/AN14//PL6 FP31/AN15/PL7 VDDM1 VSSM1 M0C0M/M0COSM/PU0 M0C0P/M0COSP/PU1 M0C1M/M0SINM/PU2 M0C1P/M0SINP/PU3 M1C0M/M1COSM/PU4 M1C0P/M1COSP/PU5 M1C1M/M1SINM/PU6 M1C1P/M1SINP/PU7 VDDM2 VSSM2 M2C0M/M2COSM/PV0 M2C0P/M2COSP/PV1 M2C1M/M2SINM/PV2 M2C1P/M2SINP/PV3 M3C0M/M3COSM/PV4 M3C0P/M3COSP/PV5 M3C1M/M3SINM/PV6 M3C1P/M3SINP/PV7 VDDM3 VSSM3 SCL0/PWM5/PP5 SDA0/PWM4/PP4 Figure 3. 112-Pin Package Signal Assignments MC9S12XHZ512, Rev. 4.1 10 Freescale Semiconductor Table 2. Port and Peripheral Availability by Package Option Port 144 LQFP 112 LQFP Port AD pins 8 8 Port A pins 8 8 Port B pins 8 8 Port C pins 8 0 Port D pins 8 0 Port E pins incl. IRQ/XIRQ input only 8 8 Port K pins 5 5 Port L pins 8 8 Port M pins 8 4 Port P pins 8 6 Port S pins 8 6 Port T pins 8 8 Port U pins 8 8 Port V pins 8 8 Port W pins 8 0 Sum of Ports 117 85 PM3:2 PM5:4 PS1:0 PP0,PP2 IIC1 IIC0 SPI SCI1 SCI0 CAN1 CAN0 Table 3. Peripheral–Port Cross Reference(1) X X X X PP5:4 X PP7:6 PS3:2 X O PS7:4 X PT5:4 O PT7:6 O NOTES: 1. X denotes the reset condition and O denotes a possible rerouting under software control MC9S12XHZ512, Rev. 4.1 Freescale Semiconductor 11 Memory Maps Memory Maps Figure 4 shows the CPU & BDM local address translation to the global memory map. It indicates also the location of the internal resources in the memory map. Table 4 Device Internal Resources Device RAMSIZE / RAM_LOW EEPROMSIZE / EEPROM_LOW FLASHSIZE0 / FLASH_LOW FLASHSIZE1 / FLASH_HIGH MC9S12XHZ512 32K / 0x0F_8000 4K / 0x13_F000 256K / 0x7B_FFFF 256K / 0x7C_0000 MC9S12XHZ384 28K / 0x0F_9000 4K / 0x13_F000 128K / 0x79_FFFF 256K / 0x7C_0000 MC9S12XHZ256 16K / 0x0F_C000 4K / 0x13_F000 128K / 0x79_FFFF 128K / 0x7E_0000 Figure 5 shows XGATE local address translation to the global memory map. It indicates also the location of used internal resources in the memory map. Table 5 XGATE Resources Device XGRAMSIZE / XGRAM_LOW XGFLASHSIZE / XGFLASH_HIGH MC9S12XHZ512 32K / 0x0F_8000 30K / 0x78_7FFF MC9S12XHZ384 28K / 0x0F_9000 MC9S12XHZ256 16K / 0x0F_C000 MC9S12XHZ512, Rev. 4.1 12 Freescale Semiconductor Memory Maps CPU and BDM Local Memory Map Global Memory Map 0x00_0000 0x00_07FF 2K REGISTERS CS3 Unimplemented RAM 0x0800 0x0C00 0x1000 RAM 2K REGISTERS 1K EEPROM window EPAGE 0x0F_FFFF 1K EEPROM 4K RAM window Unimplemented EEPROM RPAGE CS2 0x0000 RAMSIZE RAM_LOW 8K RAM EEPROM_LOW EEPROM 0x4000 0x13_FFFF CS2 Unpaged 16K FLASH 0x1F_FFFF FLASH0_LOW Unimplemented FLASH FLASH1_HIGH FLASH1 0x7F_FFFF FLASHSIZE FLASH0 FLASHSIZE1 0x78_0000 FLASHSIZE0 Unimplemented FLASH Unpaged 16K FLASH Reset Vectors CS0 0x3F_FFFF CS0 PPAGE 0xC000 0xFFFF External Space CS1 0x8000 16K FLASH window EEPROMSIZE 0x2000 Figure 4. S12X CPU & BDM Global Address Mapping MC9S12XHZ512, Rev. 4.1 Freescale Semiconductor 13 Memory Maps XGATE Local Memory Map Global Memory Map 0x00_0000 Registers 0x00_07FF XGRAM_LOW 0x0800 RAM 0x0F_FFFF RAMSIZE Registers XGRAMSIZE 0x0000 FLASH RAM 0x78_0800 0xFFFF FLASHSIZE FLASH XGFLASH_HIGH 0x7F_FFFF Figure 5. XGATE Global Address Mapping MC9S12XHZ512, Rev. 4.1 14 Freescale Semiconductor Mechanical Package Dimensions Mechanical Package Dimensions 0.20 T L-M N 4X PIN 1 IDENT 0.20 T L-M N 4X 36 TIPS 144 109 1 108 4X J1 L J1 M C L B V X 140X B1 VIEW Y 36 V1 NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DATUMS L, M, N TO BE DETERMINED AT THE SEATING PLANE, DATUM T. 4. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE, DATUM T. 5. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE H. 6. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE 72 N A1 S1 A S VIEW AB C 0.1 T θ2 144X SEATING PLANE θ2 T PLATING J F AA C2 0.05 R2 θ R1 D 0.08 M 0.25 BASE METAL GAGE PLANE T L-M N SECTION J1-J1 (ROTATED 90 ° ) 144 PL (K) C1 (Y) VIEW AB G VIEW Y 73 37 P E MILLIMETERS DIM MIN MAX A 20.00 BSC A1 10.00 BSC B 20.00 BSC B1 10.00 BSC C 1.40 1.60 C1 0.05 0.15 C2 1.35 1.45 D 0.17 0.27 E 0.45 0.75 F 0.17 0.23 G 0.50 BSC J 0.09 0.20 K 0.50 REF P 0.25 BSC R1 0.13 0.20 R2 0.13 0.20 S 22.00 BSC S1 11.00 BSC V 22.00 BSC V1 11.00 BSC Y 0.25 REF Z 1.00 REF AA 0.09 0.16 θ 0° θ1 0° 7° θ2 11° 13 ° θ1 (Z) Figure 6. 144-pin LQFP Mechanical Dimensions (case no. 918-03) MC9S12XHZ512, Rev. 4.1 Freescale Semiconductor 15 Mechanical Package Dimensions 0.20 T L-M N 4X PIN 1 IDENT 0.20 T L-M N 4X 28 TIPS 112 J1 85 4X P J1 1 C L 84 VIEW Y 108X G X X=L, M OR N VIEW Y V B L M 28 B1 AA J V1 57 29 F D 56 0.13 N M BASE METAL T L-M N SECTION J1-J1 ROTATED 90 ° COUNTERCLOCKWISE A1 S1 A S C2 C VIEW AB θ2 0.050 0.10 T 112X SEATING PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DATUMS L, M AND N TO BE DETERMINED AT SEATING PLANE, DATUM T. 4. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE, DATUM T. 5. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE θ3 T θ R R2 R 0.25 R1 GAGE PLANE (K) C1 E θ1 (Y) VIEW AB (Z) DIM A A1 B B1 C C1 C2 D E F G J K P R1 R2 S S1 V V1 Y Z AA θ θ1 θ2 θ3 MILLIMETERS MIN MAX 20.000 BSC 10.000 BSC 20.000 BSC 10.000 BSC --- 1.600 0.050 0.150 1.350 1.450 0.270 0.370 0.450 0.750 0.270 0.330 0.650 BSC 0.090 0.170 0.500 REF 0.325 BSC 0.100 0.200 0.100 0.200 22.000 BSC 11.000 BSC 22.000 BSC 11.000 BSC 0.250 REF 1.000 REF 0.090 0.160 8 ° 0° 7 ° 3 ° 13 ° 11 ° 11 ° 13 ° Figure 7. 112-pin LQFP Mechanical Dimensions (case no. 987) MC9S12XHZ512, Rev. 4.1 16 Freescale Semiconductor Mechanical Package Dimensions MC9S12XHZ512, Rev. 4.1 Freescale Semiconductor 17 How to Reach Us: Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted USA/Europe/Locations not listed: Freescale Semiconductor Literature Distribution P.O. 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Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006. S12XHZ512PB Rev. 4.1, 4-Jan-2007