D D R R A A A A A FT FT FT FT FT D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D Preliminary user manual D Rev. 1.0 — 7 November 2012 R R R LPC800 User manual D D D UM10601 D FT FT A A R R D D D R A FT D R A Document information Info Content Keywords ARM Cortex M0+, LPC800, USART, I2C, LPC810M021FN8, LPC811M001FDH16, LPC812M101FDH16, LPC812M101FD20, LPC812M101FDH20 Abstract LPC800 Preliminary user manual D D D D D R R R R R D R R FT R F FT FT A A A D FT FT A A R R D Preliminary LPC800 user manual D R R 20121107 R A D D 1 D R FT FT A A R R D D D Description FT FT FT FT Date A A A A R R D D D Rev FT FT FT FT FT UM10601 LPC800 User manual Revision history A A A A A NXP Semiconductors D D R A FT D R A Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 2 of 313 D D R R R R R A A A A A FT FT FT FT FT D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D Chapter 1: LPC800 Introductory information R A F FT FT A A R R D D Preliminary user manual D Rev. 1.0 — 7 November 2012 D D D UM10601 D FT FT A A R R D D D 1.1 Introduction R A – ARM Cortex-M0+ processor, running at frequencies of up to 30 MHz. – ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC). – Micro Trace Buffer – System tick timer • Memory: – 16 kB on-chip flash programming memory. – 4 kB SRAM. – In-System Programming (ISP) and In-Application Programming (IAP) via on-chip boot loader software. • Boot ROM API support: – UART drivers – I2C drivers – Power profiles – IAP/ISP • Digital peripherals: – High-speed GPIO interface connected to the ARM Cortex-M0+ I/O port with up to 18 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors. – Pin interrupt generation capability with boolean pattern-matching feature onup to eightselectable GPIO inputs. – Switch matrix for flexible configuration of each I/O pin function. – State Configurable Timer (SCT) with input and output functions (including capture and match) assigned to pins through the switch matrix. – Multiple-channel multi-rate timer for repetitive interrupt generation at up to four programmable, fixed rates. – Wake-up timer for self-timed wake-up from reduced power modes. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 3 of 313 A • System: R 1.2 Features D The peripheral complement of the UM10601 includes a CRC engine, one I2C-bus interface, up to three USARTs, up to two SPI interfaces, one multi-rate timer, self wake-up timer, and state-configurable timer, one comparator, function-configurable I/O ports through a switch matrix, an input pattern match engine, and up to 18 general-purpose I/O pins. FT The LPC800 are an ARM Cortex-M0+ based, low-cost 32-bit MCU family operating at CPU frequencies of up to 30 MHz. The UM10601 support up to 16 kB of flash memory and 4 kB of SRAM. D D D D D R R R R R D R R FT FT FT FT D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D • Analog peripherals: A A A A R R D D D – Windowed Watchdog timer FT FT FT FT FT UM10601 Chapter 1: LPC800 Introductory information – CRC engine. A A A A A NXP Semiconductors D D – Comparator with external voltage reference with pin functions assigned through the switch matrix. R A D R A • Serial interfaces: – Three UART interfaces with pin functions assigned through the switch matrix. – Two SPI controllers with pin functions assigned through the switch matrix. – One I2C-bus interface with open-drain full I2C spec fast Modeplus. • Clock generation: – 12 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as a system clock. – Crystal oscillator with an operating range of 1 MHz to 25 MHz. – Programmable watchdog oscillator with a frequency range of 9.4 kHz to 2.3 MHz. – PLL allows CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. May be run from the external clock input (CLKIN), the system oscillator, or the internal RC oscillator. • Power control: – Integrated PMU (Power Management Unit) to minimize power consumption. – Reduced power modes (Sleep, deep-sleep, power-down, deep power-down). – Power-On Reset (POR). – Brownout detect. • Unique device serial number for identification. • Single power supply. • Available in a SO20 package, TSSOP20 package, TSSOP16, and DIP8 package. UM10601 Preliminary user manual FT – Internal reference voltage. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 4 of 313 D D D D D R R R R R D R R D A FT R R FT FT A A R D D R TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 LPC812M101FD20 SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 LPC812M101FDH20 TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 Ordering options Type number Flash/kB SRAM/kB USART I2C SPI Comparator GPIO Package LPC810M021FN8 4 1 2 1 1 1 6 DIP8 LPC811M001FDH16 8 2 2 1 1 1 14 TSSOP16 LPC812M101FDH16 16 4 3 1 2 1 14 TSSOP16 LPC812M101FD20 16 4 2 1 1 1 18 SO20 LPC812M101FDH20 16 4 3 1 2 1 18 TSSOP20 All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 5 of 313 A LPC812M101FDH16 R SOT403-1 D SOT097-2 FT plastic dual in-line package; 8 leads (300 mil) plastic thin shrink small outline package; 16 leads; body width 4.4 mm A DIP8 TSSOP16 Preliminary user manual F D D Version LPC811M001FDH16 UM10601 A FT FT A A R R D D D Description LPC810M021FN8 Table 2. R R FT FT A A R R D D D Package Name FT FT FT FT Ordering information Type number A A A A R R D D D 1.3 Ordering information FT FT FT FT FT UM10601 Chapter 1: LPC800 Introductory information Table 1. A A A A A NXP Semiconductors D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D Chapter 1: LPC800 Introductory information D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D 1.4 Block diagram FT FT FT UM10601 FT FT NXP Semiconductors D FT FT A A R R D D D R /3& A FT D 6:&/.6:' 7(67'(%8* ,17(5)$&( A +,*+63((' *3,2 R [ 3,2 $50 &257(;0 3,1,17(558376 3$77(510$7&+ )/$6+ N% VODYH 520 N% 65$0 N% VODYH VODYH &7287B>@ $+%/,7(%86 6&7 &7,1B>@ VODYH VODYH &5& $+%72$3% %5,'*( 7;'576 ::'7 5;'&76 6&/. 86$57 ,2&21 7;'576 [ 6:,7&+ 0$75,; 5;'&76 6&/. 86$57 08/7,5$7(7,0(5 7;'576 5;'&76 6&/. 86$57 6&.66(/ 0,62026, 308 63, 6&.66(/ 0,62026, 6&/ ,&%86 6'$ ;7$/287 ;7$/,1 6(/) :$.(837,0(5 63, ;7$/ 5(6(7&/.,1 6<6&21 &/.287 $&03B, 9''&03 &203$5$725 $&03B2 $/:$<62132:(5'20$,1 ,5& :'2VF %2' &/2&. *(1(5$7,21 32:(5&21752/ 6<67(0 )81&7,216 325 FORFNVDQG FRQWUROV DDD Fig 1. LPC800 block diagram UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 6 of 313 D D D D D R R R R R D R R FT FT FT FT A A A A R R D D D D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D 1.5.1 ARM Cortex-M0+ core configuration FT FT FT FT FT UM10601 Chapter 1: LPC800 Introductory information 1.5 General description A A A A A NXP Semiconductors D D The ARM Cortex-M0+ core runs at an operating frequency of up to 30 MHz. Integrated in the core are the NVIC and Serial Wire Debug with four breakpoints and two watchpoints. The ARM Cortex-M0+ core supports a single-cycle I/O enabled port (IOP) for fast GPIO access at address 0xA000 0000. R A Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 7 of 313 A All information provided in this document is subject to legal disclaimers. R Preliminary user manual D UM10601 FT The core includes a single-cycle multiplier and a system tick timer (SysTick). D D R R A A A A A FT FT FT FT FT D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D Preliminary user manual D Rev. 1.0 — 7 November 2012 R R R Chapter 2: LPC800 Memory mapping D D D UM10601 D FT FT A A R R D D D 2.1 How to read this chapter R A The registers incorporated into the ARM Cortex-M0+ core, such as NVIC, SysTick, and sleep mode control, are located on the private peripheral bus. The GPIO port and pin interrupt/pattern match registers are accessed by the ARM Cortex-M0+ single-cycle I/O enabled port (IOP). UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 8 of 313 A The APB peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals. Each peripheral is allocated 16 kB of space simplifying the address decoding. R The LPC800 incorporates several distinct memory regions. Figure 2 shows the overall map of the entire address space from the user program viewpoint following reset. D 2.2 General description FT The memory mapping is identical for all LPC800 parts. Different LPC800 parts support different flash memory sizes. D D D D D R R R R R D R R FT FT FT FT A A A A R R D D D D R R A FT FT FT A A R R D D D R F D FT FT A A R R D [ A FT FT A A R R D D D $3%SHULSKHUDOV FT FT FT FT FT UM10601 Chapter 2: LPC800 Memory mapping 2.2.1 Memory mapping A A A A A NXP Semiconductors D D R D R [ 86$57 *3,2 UHVHUYHG 63, 63, UHVHUYHG ,& UHVHUYHG 6<6&21 ,2&21 IODVKFRQWUROOHU UHVHUYHG UHVHUYHG [))) UHVHUYHG UHVHUYHG [))) UHVHUYHG DQDORJFRPSDUDWRU 308 [ UHVHUYHG UHVHUYHG [& [ UHVHUYHG [ [ &5& [ UHVHUYHG [ $3%SHULSKHUDOV [ UHVHUYHG [ UHVHUYHG N%ERRW520 UHVHUYHG [ N%07% [ UHVHUYHG N%65$0/3& N%65$0/3& [ N%65$0/3& [ UHVHUYHG N%RQFKLSIODVK/3& N%RQFKLSIODVK/3& N%RQFKLSIODVK/3& [ [$ [ 6&7 [& 86$57 [$ UHVHUYHG 86$57 [$ SLQLQWHUUXSWVSDWWHUQPDWFK [ UHVHUYHG UHVHUYHG [ [ [& [ [ [ [& [ [ [ [& [ [ [ [& [ [ [ [ [ VZLWFKPDWUL[ [& VHOIZDNHXSWLPHU [ 057 [ ::'7 [ [ [ A [( UHVHUYHG *% FT [( SULYDWHSHULSKHUDOEXV *% UHVHUYHG [)))))))) UHVHUYHG *% A /3& *% DFWLYHLQWHUUXSWYHFWRUV [ [& [ DDD The private peripheral bus includes the ARM Cortex-M0+ peripherals such as the NVIC, SysTick, and the core control registers. Fig 2. LPC800 Memory mapping 2.2.2 Micro Trace Buffer (MTB) The LPC800 supports the ARM Cortex-M0+ Micro Trace Buffer. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 9 of 313 R R R R R A A A A A FT FT FT FT FT D R R A A FT FT FT FT A A R R D D D R R A FT FT FT A A R R D D D D Chapter 3: LPC800 Nested Vectored Interrupt Controller (NVIC) R R R D D D F FT FT A A Preliminary user manual A Rev. 1.0 — 7 November 2012 D D D D D UM10601 D FT FT A A R R D D D R A 3.1 How to read this chapter FT D R A The NVIC is identical on all LPC800 parts. The SPI1 and USART2 interrupts are implemented on parts LPC812M101FDH20 and LPC812M101FDH16 only. 3.2 Features • • • • • • • • Nested Vectored Interrupt Controller that is an integral part of the ARM Cortex-M0+. Tightly coupled interrupt controller provides low interrupt latency. Controls system exceptions and peripheral interrupts. The NVIC supports 32 vectored interrupts. Four programmable interrupt priority levels with hardware priority level masking. Software interrupt generation using the ARM exceptions SVCall and PendSV. Support for NMI. ARM Cortex M0+ Vector table offset register VTOR implemented. 3.3 General description The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M0+. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts. 3.3.1 Interrupt sources Table 3 lists the interrupt sources for each peripheral function. Each peripheral device may have one or more interrupt lines to the Vectored Interrupt Controller. Each line may represent more than one interrupt source. The interrupt number does not imply any interrupt priority. See Ref. 1 for a detailed description of the NVIC and the NVIC register description. Table 3. Connection of interrupt sources to the NVIC Interrupt number Name Description Flags 0 SPI0_IRQ SPI0 interrupt See Table 192 “SPI Interrupt Enable read and Set register (INTENSET, addresses 0x4005 800C (SPI0) , 0x4005 C00C (SPI1)) bit description”. 1 SPI1_IRQ SPI1 interrupt Same as SPI0_IRQ 2 - Reserved - UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 10 of 313 D D D D D R R R R R D R R FT FT FT FT A A A A R R D D D D R R A FT FT FT A A R R D D D R Name Description Flags 3 UART0_IRQ USART0 interrupt See Table 161 “USART Interrupt Enable read and set register (INTENSET, address 0x4006 400C(USART0), 0x4006 800C (USART1), 0x4006 C00C(USART2)) bit description” 4 UART1_IRQ USART1 interrupt Same as UART0_IRQ 5 UART2_IRQ USART2 interrupt Same as UART0_IRQ 6 - Reserved - 7 - Reserved - 8 I2C0_IRQ I2C0 interrupt See Table 175 “Interrupt Enable Clear register (INTENCLR, address 0x4005 000C) bit description”. 9 SCT_IRQ State configurable timer interrupt EVFLAG SCT event 10 MRT_IRQ Multi-rate timer interrupt Global MRT interrupt. F FT FT Interrupt number A A A R R D D D Connection of interrupt sources to the NVIC FT FT FT FT FT UM10601 Chapter 3: LPC800 Nested Vectored Interrupt Controller (NVIC) Table 3. A A A A A NXP Semiconductors D FT FT A A R R D D D R A D R A GFLAG1 GFLAG2 GFLAG3 11 CMP_IRQ Analog comparator interrupt COMPEDGE - rising, falling, or both edges can set the bit 12 WDT_IRQ Windowed watchdog timer interrupt WARNINT - watchdog warning interrupt 13 BOD_IRQ BOD interrupts BODINTVAL - BOD interrupt level 14 FLASH_IRQ Flash interrupt <tbd> 15 WKT_IRQ Self wake-up timer interrupt ALARMFLAG 23:16 - Reserved - 24 PININT0_IRQ Pin interrupt 0 or pattern match engine slice 0 interrupt PSTAT - pin interrupt status 25 PININT1_IRQ Pin interrupt 1 or pattern match engine slice 1 interrupt PSTAT - pin interrupt status 26 PININT2_IRQ Pin interrupt 2 or pattern match engine slice 2 interrupt PSTAT - pin interrupt status 27 PININT3_IRQ Pin interrupt 3 or pattern match engine slice 3 interrupt PSTAT - pin interrupt status 28 PININT4_IRQ Pin interrupt 4 or pattern match engine slice 4 interrupt PSTAT - pin interrupt status UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 FT GFLAG0 © NXP B.V. 2012. All rights reserved. 11 of 313 D D D D D R R R R R D R R R FT FT A D D R A FT D R A Preliminary user manual A R UM10601 F PSTAT - pin interrupt status A Pin interrupt 7 or pattern match engine slice 7 interrupt R PININT7_IRQ R 31 D PSTAT - pin interrupt status D Pin interrupt 6 or pattern match engine slice 6 interrupt FT PININT6_IRQ A 30 D PSTAT - pin interrupt status FT Pin interrupt 5 or pattern match engine slice 5 interrupt A PININT5_IRQ FT R R 29 A D D Flags D R FT FT A A R R D D D Description FT FT FT FT Name A A A A R R D D D Connection of interrupt sources to the NVIC Interrupt number FT FT FT FT FT UM10601 Chapter 3: LPC800 Nested Vectored Interrupt Controller (NVIC) Table 3. A A A A A NXP Semiconductors All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 12 of 313 R R R R R A A A A A FT FT FT FT FT D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D Chapter 4: LPC800 System configuration (SYSCON) R A F FT FT A A R R D D Preliminary user manual D Rev. 1.0 — 7 November 2012 D D D D D UM10601 D FT FT A A R R D D D 4.1 How to read this chapter R A Clock control Reset control Pin interrupt set-up Configuration of reduced power modes Wake-up control BOD configuration 4.3 Basic configuration Configure the SYSCON block as follows: • The SYSCON uses the CKIN, CLKOUT, RESET, and XTALIN/OUT pins. Configure the pin functions through the switch matrix. See Section 4.4. • No clock configuration is needed. The clock to the SYSCON block is always enabled. By default, the SYSCON block is clocked by the IRC. 4.3.1 Set up the PLL The PLL creates a stable output clock at a higher frequency than the input clock. If you need a main clock with a frequency higher than the 12 MHz IRC clock, use the PLL to boost the input frequency. 1. Power up the system PLL in the PDRUNCFG register. Section 4.6.32 “Power configuration register” 2. Select the PLL input in the SYSPLLCLKSEL register. You have the following input options: – IRC: 12 MHz internal oscillator. – System oscillator: External crystal oscillator using the XTALIN/XTALOUT pins. – External clock input CLKIN. Select this pin through the switch matrix. Section 4.6.8 “System PLL clock source select register” 3. Update the PLL clock source<tbd> in the SYSPLLCKUEN register. Section 4.6.9 “System PLL clock source update register” 4. Configure the PLL M and N dividers. Section 4.6.3 “System PLL control register” UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 13 of 313 A • • • • • • R 4.2 Features D clocks, reset, and wake-up control bits are reserved for all other parts. FT The system configuration block is identical for all LPC800 parts. USART2 and SPI1 are only available on parts LPC812M101FDH20 and LPC812M101FDH16 and the corresponding D D D D D R R R R R D R R FT FT FT FT A A A A R R D D D D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D Section 4.6.4 “System PLL status register” FT FT FT FT FT UM10601 Chapter 4: LPC800 System configuration (SYSCON) 5. Wait for the PLL to lock by monitoring the PLL lock status. A A A A A NXP Semiconductors D FT FT A A R R D D D 4.3.2 Configure the main clock and system clock R A The clock source for the registers and memories is derived from main clock. The main clock can be sourced from the IRC at a fixed clock frequency of 12 MHz or from the PLL. FT D R A The divided main clock is called the system clock and clocks the core, the memories, and the peripherals (register interfaces and peripheral clocks). 1. Select the main clock . You have the following options: – IRC: 12 MHz internal oscillator (default). – PLL output: You must configure the PLL to use the PLL output. Section 4.6.10 “Main clock source select register” 2. Update the main clock source. Section 4.6.11 “Main clock source update enable register” 3. Select the divider value for the system clock. A divider value of 0 disables the system clock. Section 4.6.12 “System clock divider register” 4. Select the memories and peripherals that are operating in your application and therefore must have an active clock. The core is always clocked. Section 4.6.13 “System clock control register” 4.3.3 Set up the system oscillator using XTALIN and XTALOUT If you want to use the system oscillator with the LPC800, you need to assign the XTALIN and XTALOUT pins, which connect to the external crystal, through the fixed-pin function in the switch matrix. XTALIN and XTALOUT can only be assigned to pins PIO0_8 and PIO0_9. 1. In the IOCON block, remove the pull-up and pull-down resistors in the IOCON registers for pins PIO0_8 and PIO0_9. 2. In the switch matrix block, enable the 1-bit functions for XTALIN and XTALOUT. 3. In the SYSOSCCTRL register, disable the BYPASS bit and select the oscillator frequency range according to the desired oscillator output clock. Related registers: Table 62 “PIO0_8 register (PIO0_8, address 0x4004 4038) bit description” Table 61 “PIO0_9 register (PIO0_9, address 0x4004 4034) bit description” Table 105 “Pin enable register 0 (PINENABLE0, address 0x4000 C1C0) bit description” Table 10 “System oscillator control register (SYSOSCCTRL, address 0x4004 8020) bit description” UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 14 of 313 D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D Chapter 4: LPC800 System configuration (SYSCON) D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D 4.4 Pin description FT FT FT UM10601 FT FT NXP Semiconductors D FT FT A A R R D The SYSCON inputs and outputs are assigned to external pins through the switch matrix. D D See Section 9.3.1 “Connect an internal signal to a package pin” to assign the CLKOUT function to a pin on the LPC800 package. R A Direction Pin Description SWM register Reference CLKOUT O any CLKOUT clock output. PINASSIGN8 Table 104 CLKIN I PIO0_1/ACMP_I2/CLKIN External clock input to the system PLL. Disable the ACMP_I2 function in the PINENABLE register. PINENABLE0 Table 105 XTALIN I PIO0_8/XTALIN PINENABLE0 Table 105 Input to the system oscillator. XTALOUT O PIO0_9/XTALOUT Output from the system oscillator. PINENABLE0 Table 105 RESET RESET/PIO0_5 External reset input PINENABLE0 Table 105 I 4.5 General description 4.5.1 Clock generation The system control block facilitates the clock generation. Except for the USART clock and the clock to configure the glitch filters of the digital I/O pins, the clocks to the core and peripherals run at the same frequency. The maximum clock frequency for LPC800 is 30 MHz. See Figure 3. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 15 of 313 A Function R SYSCON pin description D Table 4. FT See Section 9.3.2 to enable the clock input, the oscillator pins, and the external reset input. D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R R FT FT A A R D R &/2&.',9,'(5 ,2&21&/.',9 ,2&21 JOLWFKILOWHU ZDWFKGRJRVFLOODWRU 0$,1&/.6(/ PDLQFORFNVHOHFW ,5&RVFLOODWRU ;7$/,1 ;7$/287 6<67(0 26&,//$725 6<67(03// &/.,1 6<63//&/.6(/ V\VWHP3//FORFNVHOHFW 308 ,5&RVFLOODWRU V\VWHPRVFLOODWRU ZDWFKGRJRVFLOODWRU &/2&.',9,'(5 &/.287',9 &/.287SLQ &/.2876(/ &/.287FORFNVHOHFW ZDWFKGRJRVFLOODWRU ::'7 ,5&RVFLOODWRU :.7 ORZSRZHURVFLOODWRU :.7 DDD Fig 3. LPC800 clock generation 4.5.2 Power control of analog components The system control block controls the power to the analog components such as the oscillators and PLL, the BOD, and the analog comparator. For details, see the following registers: Section 4.6.30 “Deep-sleep mode configuration register” Section 4.6.3 “System PLL control register” Section 4.6.6 “Watchdog oscillator control register” Section 4.6.5 “System oscillator control register” UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 16 of 313 A 86$57 R 86$57 D 86$57 FT PHPRULHV DQGSHULSKHUDOV SHULSKHUDOFORFNV A )5$&7,21$/5$7( *(1(5$725 D 6<6$+%&/.&75/>@ V\VWHPFORFNHQDEOH F D D ,5&RVFLOODWRU A FT FT A A R R D D D $+%FORFN FRUHV\VWHP DOZD\VRQ V\VWHPFORFN &/2&.',9,'(5 8$57&/.',9 FT FT FT FT &/2&.',9,'(5 6<6$+%&/.',9 A A A A R R D D D PDLQFORFN FT FT FT FT FT UM10601 Chapter 4: LPC800 System configuration (SYSCON) 6<6&21 A A A A A NXP Semiconductors D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D Chapter 4: LPC800 System configuration (SYSCON) D R R A FT FT FT A A R R D D D R A FT FT A A R R D D The system control block configures analog blocks that can remain running in the reduced power modes (the BOD and the watchdog oscillator for safe operation) and enables various interrupts to wake up the chip when the internal clocks are shut down in Deep-sleep and Power-down modes. For details, see the following registers: F FT FT A A R R D D D 4.5.3 Configuration of reduced power-modes FT FT FT UM10601 FT FT NXP Semiconductors D D R A FT D Section 4.6.32 “Power configuration register” R A Section 4.6.29 “Start logic 1 interrupt wake-up enable register” 4.5.4 Reset and interrupt control The peripheral reset control register in the system control register allows to assert and release individual peripheral resets. See Table 7. Up to eight external pin interrupts can be assigned to any digital pin in the system control block (see Section 4.6.27 “Pin interrupt select registers”). 4.6 Register description All system control block registers reside on word address boundaries. Details of the registers appear in the description of each function. Reset values describe the content of the registers after the boot loader has executed. All address offsets not shown in Table 5 are reserved and should not be written. Table 5. Register overview: System configuration (base address 0x4004 8000) Name Access Offset Description Reset value Reference SYSMEMREMAP R/W 0x000 System memory remap 0x2 Table 6 PRESETCTRL R/W 0x004 Peripheral reset control 0x0000 1FFF Table 7 SYSPLLCTRL R/W 0x008 System PLL control 0 Table 8 SYSPLLSTAT R 0x00C System PLL status 0 Table 9 - - 0x010 Reserved - - - - 0x014 Reserved - - SYSOSCCTRL R/W 0x020 System oscillator control 0x000 Table 10 WDTOSCCTRL R/W 0x024 Watchdog oscillator control 0x0A0 Table 11 - - 0x028 Reserved - - - - 0x02C Reserved - - SYSRSTSTAT R/W 0x030 System reset status register 0 Table 12 SYSPLLCLKSEL R/W 0x040 System PLL clock source select 0 Table 13 SYSPLLCLKUEN R/W 0x044 System PLL clock source update enable 0 Table 14 MAINCLKSEL R/W 0x070 Main clock source select 0 Table 15 MAINCLKUEN R/W 0x074 Main clock source update enable 0 Table 16 SYSAHBCLKDIV R/W 0x078 System clock divider 1 Table 17 SYSAHBCLKCTRL R/W 0x080 System clock control 0x1F Table 18 UARTCLKDIV R/W 0x094 USART clock divider 0 Table 19 - - 0x098 Reserved - - UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 17 of 313 D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R Description Reset value Reference - - 0x09C Reserved - - - - 0x0A0 0x0BC Reserved - - - - 0x0CC Reserved - - CLKOUTSEL R/W 0x0E0 CLKOUT clock source select 0 Table 20 CLKOUTUEN R/W 0x0E4 CLKOUT clock source update enable 0 Table 21 CLKOUTDIV R/W 0x0E8 CLKOUT clock divider 0 Table 22 UARTFRGDIV R/W 0x0F0 USART fractional generator divider value 0 Table 23 UARTFRGMULT R/W 0x0F4 USART fractional generator multiplier value 0 Table 24 EXTTRACECMD R/W 0x0FC External trace buffer command register 0 Table 25 PIOPORCAP0 R 0x100 POR captured PIO status 0 user dependent Table 26 - - 0x104 Reserved - - IOCONCLKDIV6 R/W 0x134 Peripheral clock 6 to the IOCON block for programmable glitch filter 0x0000 0000 Table 27 IOCONCLKDIV5 R/W 0x138 Peripheral clock 5 to the IOCON block for programmable glitch filter 0x0000 0000 Table 27 IOCONCLKDIV4 R/W 0x13C Peripheral clock 4 to the IOCON block for programmable glitch filter 0x0000 0000 Table 27 IOCONCLKDIV3 R/W 0x140 Peripheral clock 3 to the IOCON block for programmable glitch filter 0x0000 0000 Table 27 IOCONCLKDIV2 R/W 0x144 Peripheral clock 2 to the IOCON block for programmable glitch filter 0x0000 0000 Table 27 IOCONCLKDIV1 R/W 0x148 Peripheral clock 1 to the IOCON block for programmable glitch filter 0x0000 0000 Table 27 IOCONCLKDIV0 R/W 0x14C Peripheral clock 0 to the IOCON block for programmable glitch filter 0x0000 0000 Table 27 BODCTRL R/W 0x150 Brown-Out Detect 0 Table 28 SYSTCKCAL R/W 0x154 System tick counter calibration 0x0 Table 29 - R/W 0x168 Reserved - - IRQLATENCY R/W 0x170 IQR delay. Allows trade-off between interrupt 0x0000 0010 latency and determinism. Table 30 NMISRC R/W 0x174 NMI Source Control 0 Table 31 PINTSEL0 R/W 0x178 GPIO Pin Interrupt Select register 0 0 Table 32 PINTSEL1 R/W 0x17C GPIO Pin Interrupt Select register 1 0 Table 32 PINTSEL2 R/W 0x180 GPIO Pin Interrupt Select register 2 0 Table 32 PINTSEL3 R/W 0x184 GPIO Pin Interrupt Select register 3 0 Table 32 PINTSEL4 R/W 0x188 GPIO Pin Interrupt Select register 4 0 Table 32 PINTSEL5 R/W 0x18C GPIO Pin Interrupt Select register 5 0 Table 32 PINTSEL6 R/W 0x190 GPIO Pin Interrupt Select register 6 0 Table 32 PINTSEL7 R/W 0x194 GPIO Pin Interrupt Select register 7 0 Table 32 STARTERP0 R/W 0x204 Start logic 0 pin wake-up enable register 0 Table 33 STARTERP1 R/W 0x214 Start logic 1 interrupt wake-up enable register 0 Table 34 F FT FT Offset A A A R R D D D Access D FT FT A A R R D D D R A 18 of 313 A © NXP B.V. 2012. All rights reserved. R Rev. 1.0 — 7 November 2012 D All information provided in this document is subject to legal disclaimers. FT Preliminary user manual FT FT FT FT Name UM10601 A A A A R R D D D Register overview: System configuration (base address 0x4004 8000) …continued FT FT FT FT FT UM10601 Chapter 4: LPC800 System configuration (SYSCON) Table 5. A A A A A NXP Semiconductors D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R Description Reset value Reference PDSLEEPCFG R/W 0x230 Power-down states in deep-sleep mode 0xFFFF Table 35 PDAWAKECFG R/W 0x234 Power-down states for wake-up from deep-sleep 0xEDF0 Table 36 PDRUNCFG R/W 0x238 Power configuration register 0xEDF0 Table 37 DEVICE_ID R 0x3F4 Device ID part dependent Table 38 D FT FT A A R R D D D R A MAP 31:2 - Description Reset value System memory remap. Value 0x3 is reserved. 0x2 0x0 Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM. 0x1 User RAM Mode. Interrupt vectors are re-mapped to Static RAM. 0x2 User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash. - Reserved - 4.6.2 Peripheral reset control register The PRESETCTRL register allows software to reset specific peripherals. A zero in any assigned bit in this register resets the specified peripheral. A 1 clears the reset and allows the peripheral to operate. Table 7. Bit Symbol 0 SPI0_RST_N 1 2 UM10601 Preliminary user manual Peripheral reset control register (PRESETCTRL, address 0x4004 8004) bit description Value Description Reset value SPI0 reset control 1 0 Assert the SPI0 reset. 1 Clear the SPI0 reset. SPI1_RST_N SPI1 reset control 0 Assert the SPI1 reset. 1 Clear the SPI1 reset. UARTFRG_RST_N 1 USART fractional baud rate generator (UARTFRG) reset control 0 Assert the UARTFRG reset. 1 Clear the UARTFRG reset. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 1 © NXP B.V. 2012. All rights reserved. 19 of 313 A 1:0 Value R System memory remap register (SYSMEMREMAP, address 0x4004 8000) bit description D The system memory remap register selects whether the exception vectors are read from boot ROM, flash, or SRAM. By default, the flash memory is mapped to address 0x0000 0000. When the MAP bits in the SYSMEMREMAP register are set to 0x0 or 0x1, the boot ROM or RAM respectively are mapped to the bottom 512 bytes of the memory map (addresses 0x0000 0000 to 0x0000 0200). FT 4.6.1 System memory remap register Symbol F FT FT Offset A A A R R D D D Access Bit FT FT FT FT Name Table 6. A A A A R R D D D Register overview: System configuration (base address 0x4004 8000) …continued FT FT FT FT FT UM10601 Chapter 4: LPC800 System configuration (SYSCON) Table 5. A A A A A NXP Semiconductors D D D D D R R R R R D R R FT D A D 9 Clear the USART1 reset. UART2_RST_N I2C_RST_N 12 31:12 Assert the USART2 reset. Clear the USART2 reset. 0 Assert the I2C reset. 1 Clear the I2C reset. 0 Assert the MRT reset. 1 Clear the MRT reset. MRT_RST_N 1 Multi-rate timer (MRT) reset control SCT_RST_N 1 SCT reset control 0 Assert the SCT reset. 1 Clear the SCT reset. WKT_RST_N 1 Self wake-up timer (WKT) reset control GPIO_RST_N Clear the WKT reset. 0 Assert the GPIO reset. 1 Clear the GPIO reset. Flash controller reset control 0 Assert the flash controller reset. 1 Clear the flash controller reset. ACMP_RST_N 1 Assert the WKT reset. GPIO and GPIO pin interrupt reset control FLASH_RST_N - 1 I2C reset control 1 11 1 USART2 reset control 0 10 A 8 R Assert the USART reset. 1 1 7 D 0 D USART1 reset control 0 6 FT UART1_RST_N A Clear the USART0 reset. R 1 1 D 5 Assert the USART0 reset. FT 4 USART0 reset control 0 FT A A R R D Reset value F FT FT A A R R R USART0_RST_N R A D D 3 Description D R FT FT A A R R D D D Value FT FT FT FT Symbol A A A A R R D D D Peripheral reset control register (PRESETCTRL, address 0x4004 8004) bit description Bit FT FT FT FT FT UM10601 Chapter 4: LPC800 System configuration (SYSCON) Table 7. A A A A A NXP Semiconductors 1 1 Analog comparator reset control 1 0 Assert the analog comparator reset. 1 Clear the analog comparator controller reset. - Reserved - 4.6.3 System PLL control register This register connects and enables the system PLL and configures the PLL multiplier and divider values. The PLL accepts an input frequency from 10 MHz to 25 MHz from various clock sources. The input frequency is multiplied to a higher frequency and then divided down to provide the actual clock used by the CPU, peripherals, and memories. The PLL can produce a clock up to the maximum allowed for the CPU. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 20 of 313 D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D 6:5 PSEL Post divider ratio P. The division ratio is 2 P. 0 D R A Reserved. Do not write ones to reserved bits. D - FT P=8 FT 0x3 A P=4 R P=2 0x2 D 0x1 FT P=1 A - 0x0 A R R 0 D Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 11111: Division ratio M = 32 D Reset value - 4.6.4 System PLL status register This register is a Read-only register and supplies the PLL lock status (see <tbd>). Table 9. System PLL status register (SYSPLLSTAT, address 0x4004 800C) bit description Bit Symbol 0 LOCK Value - Description Reset value PLL lock status 0 0 PLL not locked 1 PLL locked - Reserved - 4.6.5 System oscillator control register This register configures the frequency range for the system oscillator. Table 10. UM10601 Preliminary user manual System oscillator control register (SYSOSCCTRL, address 0x4004 8020) bit description Bit Symbol Value 0 BYPASS Reset value Bypass system oscillator 0x0 Disabled. Oscillator is not bypassed. 1 Enabled. PLL input (sys_osc_clk) is fed directly from the XTALIN pin bypassing the oscillator. Use this mode when using an external clock source instead of the crystal oscillator. FREQRANGE - Description 0 Determines frequency range for Low-power oscillator. 0 1 - 20 MHz frequency range. 1 15 - 25 MHz frequency range - Reserved All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 F FT FT Description A A A Value R R R MSEL 31:2 D D D 4:0 1 FT FT FT FT Symbol 31:1 A A A A R R D D D System PLL control register (SYSPLLCTRL, address 0x4004 8008) bit description Bit 31:7 FT FT FT FT FT UM10601 Chapter 4: LPC800 System configuration (SYSCON) Table 8. A A A A A NXP Semiconductors 0x0 0x00 © NXP B.V. 2012. All rights reserved. 21 of 313 D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D Chapter 4: LPC800 System configuration (SYSCON) D R R A FT FT FT A A R R D D D R A FT FT A A R R D D This register configures the watchdog oscillator. The oscillator consists of an analog and a digital part. The analog part contains the oscillator function and generates an analog clock (Fclkana). With the digital part, the analog output clock (Fclkana) can be divided to the required output clock frequency wdt_osc_clk. The analog output frequency (Fclkana) can be adjusted with the FREQSEL bits between 600 kHz and 4.6 MHz. With the digital part Fclkana will be divided (divider ratios = 2, 4,...,64) to wdt_osc_clk using the DIVSEL bits. F FT FT A A R R D D D 4.6.6 Watchdog oscillator control register FT FT FT UM10601 FT FT NXP Semiconductors D D R A Bit Symbol 4:0 8:5 31:9 UM10601 Preliminary user manual Watchdog oscillator control register (WDTOSCCTRL, address 0x4004 8024) bit description Description Reset value DIVSEL Select divider for Fclkana. wdt_osc_clk = Fclkana/ (2 (1 + DIVSEL)) 00000: 2 (1 + DIVSEL) = 2 00001: 2 (1 + DIVSEL) = 4 to 11111: 2 (1 + DIVSEL) = 64 0 FREQSEL Select watchdog oscillator analog output frequency (Fclkana). 0x00 - Value 0x1 0.6 MHz 0x2 1.05 MHz 0x3 1.4 MHz 0x4 1.75 MHz 0x5 2.1 MHz 0x6 2.4 MHz 0x7 2.7 MHz 0x8 3.0 MHz 0x9 3.25 MHz 0xA 3.5 MHz 0xB 3.75 MHz 0xC 4.0 MHz 0xD 4.2 MHz 0xE 4.4 MHz 0xF 4.6 MHz - Reserved All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 0x00 © NXP B.V. 2012. All rights reserved. 22 of 313 A Table 11. R Remark: The frequency of the watchdog oscillator is undefined after reset. The watchdog oscillator frequency must be programmed by writing to the WDTOSCCTRL register before using the watchdog oscillator. D Remark: Any setting of the FREQSEL bits will yield a Fclkana value within 40% of the listed frequency value. The watchdog oscillator is the clock source with the lowest power consumption. If accurate timing is required, use the IRC or system oscillator. FT The output clock frequency of the watchdog oscillator can be calculated as wdt_osc_clk = Fclkana/(2 (1 + DIVSEL)) = 9.3 kHz to 2.3 MHz (nominal values). D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D Chapter 4: LPC800 System configuration (SYSCON) D R R A FT FT FT A A R R D D D R A D FT FT A A R R D The SYSRSTSTAT register shows the source of the latest reset event. The bits are cleared by writing a one to any of the bits. The POR event clears all other bits in this register. If another reset signal - for example the external RESET pin - remains asserted after the POR signal is negated, then its bit is set to detected. Write a one to clear the reset. F FT FT A A R R D D D 4.6.7 System reset status register FT FT FT UM10601 FT FT NXP Semiconductors D D R A FT D R Table 12. System reset status register (SYSRSTSTAT, address 0x4004 8030) bit description Bit Symbol 0 POR 1 2 3 4 31:5 A The reset value given in Table 12 applies to the POR reset. Value Description Reset value POR reset status 0 0 No POR detected 1 POR detected. Writing a one clears this reset. Status of the external RESET pin. External reset status. EXTRST 0 No reset event detected. 1 Reset detected. Writing a one clears this reset. WDT Status of the Watchdog reset 0 0 No WDT reset detected 1 WDT reset detected. Writing a one clears this reset. 0 No BOD reset detected 1 BOD reset detected. Writing a one clears this reset. BOD Status of the Brown-out detect reset SYSRST 0 Status of the software system reset - 0 0 0 No System reset detected 1 System reset detected. Writing a one clears this reset. - Reserved - 4.6.8 System PLL clock source select register This register selects the clock source for the system PLL. The SYSPLLCLKUEN register (see Section 4.6.9) must be toggled from LOW to HIGH for the update to take effect. Table 13. Bit Symbol 1:0 SEL 31:2 UM10601 Preliminary user manual System PLL clock source select register (SYSPLLCLKSEL, address 0x4004 8040) bit description - Value Description Reset value System PLL clock source 0 0x0 IRC 0x1 Crystal Oscillator (SYSOSC) 0x2 Reserved. 0x3 CLKIN. External clock input. - Reserved All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 - © NXP B.V. 2012. All rights reserved. 23 of 313 D D D D D R R R R R FT FT FT FT FT UM10601 D R R FT FT FT FT A A A A R R D D D Chapter 4: LPC800 System configuration (SYSCON) D R R A FT FT FT A A R R D D D R A FT FT A A R R D D This register updates the clock source of the system PLL with the new input clock after the SYSPLLCLKSEL register has been written to. In order for the update to take effect, first write a zero to the SYSPLLUEN register and then write a one to SYSPLLUEN. F FT FT A A R R D D D 4.6.9 System PLL clock source update register A A A A A NXP Semiconductors D D R - Description Reset value Enable system PLL clock source update 0 0 No change 1 Update clock source - Reserved - 4.6.10 Main clock source select register This register selects the main system clock, which can be the system PLL (sys_pllclkout), or the watchdog oscillator, or the IRC oscillator. The main system clock clocks the core, the peripherals, and the memories. Bit 0 of the MAINCLKUEN register (see Section 4.6.11) must be toggled from 0 to 1 for the update to take effect. Table 15. Main clock source select register (MAINCLKSEL, address 0x4004 8070) bit description Bit Symbol 1:0 SEL 31:2 - Value Description Reset value Clock source for main clock 0 0x0 IRC Oscillator 0x1 PLL input 0x2 Watchdog oscillator 0x3 PLL output - Reserved - 4.6.11 Main clock source update enable register This register updates the clock source of the main clock with the new input clock after the MAINCLKSEL register has been written to. In order for the update to take effect, first write a zero to bit 0 of this register, then write a one. Table 16. Bit Symbol 0 ENA 31:1 UM10601 Preliminary user manual Main clock source update enable register (MAINCLKUEN, address 0x4004 8074) bit description - Value Description Reset value Enable main clock source update 0 0 No change 1 Update clock source - Reserved All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 - © NXP B.V. 2012. All rights reserved. 24 of 313 A 31:1 Value R Symbol ENA D Bit 0 FT System PLL clock source update enable register (SYSPLLCLKUEN, address 0x4004 8044) bit description A Table 14. D D D D D R R R R R FT FT FT FT FT UM10601 D R R FT FT FT FT A A A A R R D D D Chapter 4: LPC800 System configuration (SYSCON) D R R A FT FT FT A A R R D D D R A D FT FT A A R R D This register controls how the main clock is divided to provide the system clock to the core, memories, and the peripherals. The system clock can be shut down completely by setting the DIV field to zero. F FT FT A A R R D D D 4.6.12 System clock divider register A A A A A NXP Semiconductors D D R A System clock divider register (SYSAHBCLKDIV, address 0x4004 8078) bit description FT Table 17. D R Symbol Description Reset value 7:0 DIV System AHB clock divider values 0: System clock disabled. 1: Divide by 1. to 255: Divide by 255. 0x01 31:8 - Reserved - 4.6.13 System clock control register The SYSAHBCLKCTRL register enables the clocks to individual system and peripheral blocks. The system clock (bit 0) provides the clock for the AHB, the APB bridge, the ARM Cortex-M0+, the SYSCON block, and the PMU. This clock cannot be disabled. Table 18. Bit Symbol 0 SYS 1 2 3 4 5 UM10601 Preliminary user manual System clock control register (SYSAHBCLKCTRL, address 0x4004 8080) bit description Value Description Reset value Enables the clock for the AHB, the APB bridge, the Cortex-M0+ core clocks, SYSCON, and the PMU. This bit is read only and always reads as 1. 1 0 Reserved 1 Enable ROM Enables clock for ROM. 0 Disable 1 Enable RAM Enables clock for SRAM. 0 Disable 1 Enable FLASHREG Enables clock for flash register interface. 0 Disable 1 Enable 0 Disable 1 Enable FLASH Enables clock for flash. I2C Enables clock for I2C. 0 Disable 1 Enable All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 1 1 1 1 0 © NXP B.V. 2012. All rights reserved. 25 of 313 A Bit D D D D D R R R R R D R R R A FT A D SCT Enables clock for state configurable timer. 0 Disable 1 Enable WKT Enables clock for self wake-up timer. 0 1 10 11 12 13 14 15 16 17 MRT Preliminary user manual 0 0 Disable Enable 0 Disable 1 Enable SPI0 Enables clock for SPI0. 0 Disable 1 Enable SPI1 0 Enables clock for SPI1. 0 Disable 1 Enable CRC Enables clock for CRC. 0 Disable 1 Enable UART0 Enables clock for USART0. 0 Disable 1 Enable UART1 Enables clock for USART1. 0 Disable 1 Enable UART2 Enables clock for USART2. 0 Disable 1 Enable WWDT Enables clock for WWDT. 1 UM10601 0 Enables clock for multi-rate timer. 0 18 A Enable R 1 Enables clock for switch matrix. D Disable D 0 SWM FT Enable A 1 R 9 Disable D 8 0 0 FT 7 Enables clock for GPIO port registers and GPIO pin interrupt registers. FT A A R R D Reset value F FT FT A A R R R Description D D D GPIO D R FT FT A A R R D D D 6 Value FT FT FT FT Symbol A A A A R R D D D System clock control register (SYSAHBCLKCTRL, address 0x4004 8080) bit description …continued Bit FT FT FT FT FT UM10601 Chapter 4: LPC800 System configuration (SYSCON) Table 18. A A A A A NXP Semiconductors IOCON 0 0 0 0 0 Disable Enable Enables clock for IOCON block. 0 Disable 1 Enable All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 0 © NXP B.V. 2012. All rights reserved. 26 of 313 D D D D D R R R R R D R R R A FT R A D D D R A Reserved FT - A Enable R 1 0 D - Disable FT 31:20 Enables clock to analog comparator. 0 FT A A R R D Reset value F FT FT A A R R D D D ACMP Description D R FT FT A A R R D D D 19 Value FT FT FT FT Symbol A A A A R R D D D System clock control register (SYSAHBCLKCTRL, address 0x4004 8080) bit description …continued Bit FT FT FT FT FT UM10601 Chapter 4: LPC800 System configuration (SYSCON) Table 18. A A A A A NXP Semiconductors - 4.6.14 USART clock divider register This register configures the clock for the fractional baud rate generator and all USARTs. The UART clock can be disabled by setting the DIV field to zero (this is the default setting). Table 19. USART clock divider register (UARTCLKDIV, address 0x4004 8094) bit description Bit Symbol Description Reset value 7:0 DIV USART clock divider values. 0: Clock disabled. 1: Divide by 1. to 255: Divide by 255. 0 31:8 - Reserved - 4.6.15 CLKOUT clock source select register This register selects the signal visible on the CLKOUT pin. Any oscillator or the main clock can be selected. Bit 0 of the CLKOUTUEN register (see Section 4.6.16) must be toggled from 0 to 1 for the update to take effect. Table 20. CLKOUT clock source select register (CLKOUTSEL, address 0x4004 80E0) bit description Bit Symbol 1:0 SEL 31:2 - Value Description Reset value CLKOUT clock source 0 0x0 IRC oscillator 0x1 Crystal oscillator (SYSOSC) 0x2 Watchdog oscillator 0x3 Main clock - Reserved 0 4.6.16 CLKOUT clock source update enable register This register updates the clock source of the CLKOUT pin with the new clock after the CLKOUTSEL register has been written to. In order for the update to take effect at the input of the CLKOUT pin, first write a zero to bit 0 of this register, then write a one. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 27 of 313 D D D D D R R R R R D R R FT D R A FT FT A D D R A FT D R - A Reserved R - D D Update clock source 4.6.17 CLKOUT clock divider register This register determines the divider value for the signal on the CLKOUT pin. Table 22. CLKOUT clock divider registers (CLKOUTDIV, address 0x4004 80E8) bit description Bit Symbol Description Reset value 7:0 DIV CLKOUT clock divider values 0: Disable CLKOUT clock divider. 1: Divide by 1. to 255: Divide by 255. 0 31:8 - Reserved - 4.6.18 USART fractional generator divider value register All USART peripherals share a common clock U_PCLK, which can be adjusted by a fractional divider: U_PCLK = UARTCLKDIV/(1 + MULT/DIV). UARTCLKDIV is the USART clock configured in the UARTCLKDIV register. The fractional portion (1 + MULT/DIV) is determined by the two USART fractional divider registers in the SYSCON block: 1. The DIV value programmed in this register is the denominator of the divider used by the fractional rate generator to create the fractional component of U_PCLK. 2. The MULT value of the fractional divider is programmed in the UARTFRGMULT register. See Table 24. Remark: To use of the fractional baud rate generator, you must write 0xFF to this register to yield a denominator value of 256. All other values are not supported. See also: Section 15.3.1 “Configure the USART clock and baud rate” Section 15.7.1 “Clocking and Baud rates” UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 F FT FT 1 A A A Reset value 0 No change R R R - Description Enable CLKOUT clock source update 0 R A D D 31:1 Value D R FT FT A A R R D D D Symbol ENA FT FT FT FT Bit A A A A R R D D D CLKOUT clock source update enable register (CLKOUTUEN, address 0x4004 80E4) bit description 0 FT FT FT FT FT UM10601 Chapter 4: LPC800 System configuration (SYSCON) Table 21. A A A A A NXP Semiconductors © NXP B.V. 2012. All rights reserved. 28 of 313 D D D D D R R R R R FT FT FT FT FT UM10601 D R R FT FT FT FT A A A A R R D D D Chapter 4: LPC800 System configuration (SYSCON) D R R A FT FT FT A A R R D D D D D D A Reset value 31:8 - Reserved A FT FT A D D R A 4.6.19 USART fractional generator multiplier value register All USART peripherals share a common clock U_PCLK, which can be adjusted by a fractional divider: U_PCLK = UARTCLKDIV/(1 + MULT/DIV). UARTCLKDIV is the USART clock configured in the UARTCLKDIV register. The fractional portion (1 + MULT/DIV) is determined by the two USART fractional divider registers in the SYSCON block: 1. The DIV denominator of the fractional divider value is programmed in the UARTFRGDIV register. See Table 23. 2. The MULT value programmed in this register is the numerator of the fractional divider value used by the fractional rate generator to create the fractional component to the baud rate. See also: Section 15.3.1 “Configure the USART clock and baud rate” Section 15.7.1 “Clocking and Baud rates” Table 24. USART fractional generator multiplier value register (UARTFRGMULT, address 0x4004 80F4) bit description Bit Symbol Description Reset value 7:0 MULT Numerator of the fractional divider. MULT is equal to the programmed 0 value. 31:8 - Reserved - 4.6.20 External trace buffer command register <tbd> Table 25. UM10601 Preliminary user manual External trace buffer command register (EXTTRACECMD, address 0x4004 80FC) bit description Bit Symbol Description 0 START Trace start command <tbd> 0 1 STOP Trace stop command <tbd> 0 31:2 - Reserved 0 All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 Reset value © NXP B.V. 2012. All rights reserved. 29 of 313 FT - A Denominator of the fractional divider. DIV is equal to the programmed 0 value +1. Always set to 0xFF to use with the fractional baud rate generator. R DIV D 7:0 R Description R Symbol D D Bit F FT FT A A R R USART fractional generator divider value register (UARTFRGDIV, address 0x4004 80F0) bit description R Table 23. A A A A A NXP Semiconductors D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D Chapter 4: LPC800 System configuration (SYSCON) D R R A FT FT FT A A R R D D D R A FT FT A A R R D D The PIOPORCAP0 register captures the state of GPIO port 0 at power-on-reset. Each bit represents the reset state of one GPIO pin. This register is a read-only status register. F FT FT A A R R D D D 4.6.21 POR captured PIO status register 0 FT FT FT UM10601 FT FT NXP Semiconductors State of PIO0_17 through PIO0_0 at power-on reset Implementation dependent 31:18 - Reserved. - 4.6.22 IOCON glitch filter clock divider registers 6 to 0 These registers individually configure the seven peripheral input clocks (IOCONFILTR_PCLK) to the IOCON programmable glitch filter. The clocks can be shut down by setting the DIV bits to 0x0. Table 27. IOCON glitch filter clock divider registers 6 to 0 (IOCONCLKDIV[6:0], address 0x4004 8134 (IOCONCLKDIV6) to 0x004 814C (IOCONFILTCLKDIV0)) bit description Bit Symbol Description Reset value 7:0 DIV IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255. 0 31:8 - Reserved 0x00 4.6.23 BOD control register The BOD control register selects four separate threshold values for sending a BOD interrupt to the NVIC and for forced reset. Reset and interrupt threshold values listed in Table 28 are typical values. Both the BOD interrupt and the BOD reset, depending on the value of bit BODRSTENA in this register, can wake-up the chip from Sleep, Deep-sleep, and Power-down modes. See <tbd>. Table 28. UM10601 Preliminary user manual BOD control register (BODCTRL, address 0x4004 8150) bit description Bit Symbol Value Description 1:0 BODRSTLEV Reset value BOD reset level 0 0x0 Level 0: The reset assertion threshold voltage is <tbd>; the reset de-assertion threshold voltage is <tbd>. 0x1 Level 1: The reset assertion threshold voltage is <tbd>; the reset de-assertion threshold voltage is <tbd>. 0x2 Level 2: The reset assertion threshold voltage is <tbd>; the reset de-assertion threshold voltage is <tbd>. 0x3 Level 3: The reset assertion threshold voltage is <tbd>; the reset de-assertion threshold voltage is<tbd>. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 30 of 313 A PIOSTAT R 17:0 D Reset value D Description FT Symbol A Bit R POR captured PIO status register 0 (PIOPORCAP0, address 0x4004 8100) bit description D Table 26. D D D D D R R R R R D R R R FT D R 1 Enable reset function. - Reserved A Disable reset function. R BOD reset enable D Level 3: The interrupt assertion threshold voltage is <tbd>; the interrupt de-assertion threshold voltage is <tbd>. D 0x3 FT Level 2: The interrupt assertion threshold voltage is <tbd>; the interrupt de-assertion threshold voltage is <tbd>. A 0x2 R Level 1: The interrupt assertion threshold voltage is <tbd>; the interrupt de-assertion threshold voltage is <tbd>. D 0x1 FT Level 0: The interrupt assertion threshold voltage is <tbd>; the interrupt de-assertion threshold voltage is <tbd> FT A 31:5 - 0 0x0 0 A R BOD interrupt level BODRSTENA 0 0x00 4.6.24 System tick counter calibration register This register determines the value of the SYST_CALIB register. Table 29. System tick timer calibration register (SYSTCKCAL, address 0x4004 8154) bit description Bit Symbol Description Reset value 25:0 CAL System tick timer calibration value 0 Reserved - 31:26 - 4.6.25 IRQ latency register The IRQLATENCY register is an eight-bit register which specifies the minimum number of cycles (0-255) permitted for the system to respond to an interrupt request. The intent of this register is to allow the user to select a trade-off between interrupt response time and determinism. Setting this parameter to a very low value (e.g. zero) will guarantee the best possible interrupt performance but will also introduce a significant degree of uncertainty and jitter. Requiring the system to always take a larger number of cycles (whether it needs it or not) will reduce the amount of uncertainty but may not necessarily eliminate it. Theoretically, the ARM Cortex-M0 core should always be able to service an interrupt request within 15 cycles. System factors external to the cpu, however, bus latencies, peripheral response times, etc. can increase the time required to complete a previous instruction before an interrupt can be serviced. Therefore, accurately specifying a minimum number of cycles that will ensure determinism will depend on the application. The default setting for this register is 0x010. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 F D D 4 A FT Reset value FT A A R R R BODINTVAL A D D 3:2 D R FT FT A A R R D D D Value Description FT FT FT FT Symbol A A A A R R D D D BOD control register (BODCTRL, address 0x4004 8150) bit description Bit FT FT FT FT FT UM10601 Chapter 4: LPC800 System configuration (SYSCON) Table 28. A A A A A NXP Semiconductors © NXP B.V. 2012. All rights reserved. 31 of 313 D D D D D R R R R R FT FT FT FT FT UM10601 D R R FT FT FT FT A A A A R R D D D Chapter 4: LPC800 System configuration (SYSCON) D R R A FT FT FT A A R R D D D R A Description Reset value 7:0 LATENCY 8-bit latency value 0x010 31:8 - Reserved - D Symbol FT FT A A R R D Bit F FT FT A A R R IRQ latency register (IRQLATENCY, address 0x4004 8170) bit description D D D Table 30. A A A A A NXP Semiconductors D D R A FT D R A 4.6.26 NMI source selection register The NMI source selection register selects a peripheral interrupts as source for the NMI interrupt of the ARM Cortex-M0+ core. For a list of all peripheral interrupts and their IRQ numbers see <tbd>. For a description of the NMI functionality, see <tbd>. Table 31. NMI source selection register (NMISRC, address 0x4004 8174) bit description Bit Symbol Description Reset value 4:0 IRQNO The IRQ number of the interrupt that acts as the Non-Maskable Interrupt 0 (NMI) if bit 31 is 1. See Table 3 for the list of interrupt sources and their IRQ numbers. 30:5 - Reserved - 31 NMIEN Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by bits 4:0. 0 Note: If the NMISRC register is used to select an interrupt as the source of Non-Maskable interrupts, and the selected interrupt is enabled, one interrupt request can result in both a Non-Maskable and a normal interrupt. This can be avoided by disabling the normal interrupt in the NVIC, as described in <tbd>. 4.6.27 Pin interrupt select registers Each of these 8 registers selects one pin from all digital pins as the source of a pin interrupt or as the input to the pattern match engine. To select a pin for any of the eight pin interrupts or pattern match engine inputs, write the GPIO port pin number as 0 to 17 for pins PIO0_0 to PIO0_17 to the INTPIN bits. For example, setting INTPIN to 0x5 in PINTSEL0 selects pin PIO0_5 for pin interrupt 0. To determine the GPIO port pin number on a given LPC800 package, see the pin description table in the data sheet. Remark: The GPIO port pin number serves to identify the pin to the PINTSEL register. Any digital function, including GPIO, can be assigned to this pin through the switch matrix. Each of the 8 pin interrupts must be enabled in the NVIC using interrupt slots # 24 to 31 (see Table 3). To use the selected pins for pin interrupts or the pattern match engine, see Section 8.5.2 “Pattern match engine”. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 32 of 313 D D D D D R R R R R FT FT FT FT FT UM10601 D R R FT FT FT FT A A A A R R D D D Chapter 4: LPC800 System configuration (SYSCON) D R R A FT FT FT A A R R D D D D D D A Reset value 5:0 INTPIN Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_17 correspond to numbers 0 to 17). 0 31:6 - Reserved - R Description FT FT A A R Symbol D D Bit F FT FT A A R R Pin interrupt select registers (PINTSEL[0:7], address 0x4004 8178 (PINTSEL0) to 0x4004 8194 (PINTSEL7)) bit description R Table 32. A A A A A NXP Semiconductors D D R A FT D R A 4.6.28 Start logic 0 pin wake-up enable register The STARTERP0 register enables the selected pin interrupts for wake-up from deep-sleep mode and power-down modes. Remark: Also enable the corresponding interrupts in the NVIC. See Table 3 “Connection of interrupt sources to the NVIC”. Table 33. Bit Symbol 0 PINT0 1 2 3 4 5 6 7 31:8 UM10601 Preliminary user manual Start logic 0 pin wake-up enable register 0 (STARTERP0, address 0x4004 8204) bit description Value Reset value GPIO pin interrupt 0 wake-up 0 0 Disabled 1 Enabled 0 Disabled 1 Enabled PINT1 GPIO pin interrupt 1 wake-up PINT2 GPIO pin interrupt 2 wake-up 0 Disabled 1 Enabled PINT3 GPIO pin interrupt 3 wake-up 0 Disabled 1 Enabled PINT4 GPIO pin interrupt 4 wake-up 0 Disabled 1 Enabled 0 Disabled 1 Enabled PINT5 GPIO pin interrupt 5 wake-up PINT6 GPIO pin interrupt 6 wake-up 0 Disabled 1 Enabled PINT7 - Description GPIO pin interrupt 7 wake-up 0 Disabled 1 Enabled Reserved All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 0 0 0 0 0 0 0 - © NXP B.V. 2012. All rights reserved. 33 of 313 D D D D D R R R R R FT FT FT FT FT UM10601 D R R FT FT FT FT A A A A R R D D D Chapter 4: LPC800 System configuration (SYSCON) D R R A FT FT FT A A R R D D D R A FT FT A A R R D D This register selects which interrupts wake the LPC800 from deep-sleep and power-down modes. F FT FT A A R R D D D 4.6.29 Start logic 1 interrupt wake-up enable register A A A A A NXP Semiconductors D D Remark: Also enable the corresponding interrupts in the NVIC. See Table 3 “Connection of interrupt sources to the NVIC”. R A FT D Symbol 0 SPI0 Description Reset value SPI0 interrupt wake-up 0 0 Disabled 1 Enabled 0 Disabled 1 Enabled SPI1 SPI1 interrupt wake-up 0 2 - Reserved 3 USART0 USART0 interrupt wake-up. Configure USART 0 in synchronous slave mode. 4 5 0 Disabled 1 Enabled USART1 - USART1 interrupt wake-up. Configure USART 0 in synchronous slave mode. 0 Disabled 1 Enabled USART2 USART2 interrupt wake-up. Configure USART 0 in synchronous slave mode. 0 Disabled 1 Enabled 7:6 - Reserved - 8 I2C I2C interrupt wake-up. 0 0 Disabled 1 Enabled 11:9 - Reserved - 12 WWDT WWDT interrupt wake-up 0 13 14 Preliminary user manual Value 0 Disabled 1 Enabled BOD - BOD interrupt wake-up 0 Disabled 1 Enabled Reserved All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 0 - © NXP B.V. 2012. All rights reserved. 34 of 313 A Bit 1 UM10601 Start logic 1 interrupt wake-up enable register (STARTERP1, address 0x4004 8214) bit description R Table 34. D D D D D R R R R R D R R R A FT R 0 Disabled 1 Enabled F Self wake-up timer interrupt wake-up 0 D Reset value FT D D R A FT D R A 31:16 FT A A R R D Description A FT Value FT A A R R D D D WKT D R FT FT A A R R D D D 15 FT FT FT FT Symbol A A A A R R D D D Start logic 1 interrupt wake-up enable register (STARTERP1, address 0x4004 8214) bit description …continued Bit FT FT FT FT FT UM10601 Chapter 4: LPC800 System configuration (SYSCON) Table 34. A A A A A NXP Semiconductors Reserved. - 4.6.30 Deep-sleep mode configuration register The bits in this register (BOD_PD and WDTOSC_OD) can be programmed to control aspects of Deep-sleep and Power-down modes. The bits are loaded into corresponding bits of the PDRUNCFG register when Deep-sleep mode or Power-down mode is entered. Remark: Hardware forces the analog blocks to be powered down in Deep-sleep and Power-down modes. An exception are the exception of BOD and watchdog oscillator, which can be configured to remain running through this register. The WDTOSC_PD value written to the PDSLEEPCFG register is overwritten if the LOCK bit in the WWDT MOD register (see Table 142) is set. See Section 12.5.3 for details. Table 35. Bit Deep-sleep configuration register (PDSLEEPCFG, address 0x4004 8230) bit description Symbol Value Description 2:0 3 BOD_PD 6 - 31:7 - BOD power-down control for Deep-sleep and Power-down mode 1 Powered 1 Powered down WDTOSC_PD 15:7 0b111 0 5:4 Reserved. 11 Watchdog oscillator power-down control for Deep-sleep and Power-down mode. Changing this bit to powered-down has no effect when the LOCK bit in the WWDT MOD register is set. In this case, the watchdog oscillator is always running. 1 0 Powered 1 Powered down - Reset value Reserved. Reserved 0b111111111 Reserved 0 4.6.31 Wake-up configuration register This register controls the power configuration of the device when waking up from Deep-sleep or Power-down mode. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 35 of 313 D D D D D R R R R R D R R FT D 0 BOD wake-up configuration 0 Powered 1 Powered down 0 0 4 - Reserved. 1 5 SYSOSC_PD Crystal oscillator wake-up configuration 1 6 7 11:8 0 Powered 1 Powered down WDTOSC_PD Watchdog oscillator wake-up configuration. Changing this bit to powered-down has no effect when the LOCK bit in the WWDT MOD register is set. In this case, the watchdog oscillator is always running. 0 Powered 1 Powered down 0 Powered 1 Powered down SYSPLL_PD System PLL wake-up configuration - Reserved. Always write these bits as 0b1101 A BOD_PD R Powered down 1 1 0b1101 14:12 - Reserved. Always write these bits as 0b110 0b110 15 Analog comparator wake-up configuration 1 ACMP 31:16 - 0 Powered 1 Powered down - Reserved D FT Powered 1 0 4.6.32 Power configuration register The PDRUNCFG register controls the power to the various analog blocks. This register can be written to at any time while the chip is running, and a write will take effect immediately with the exception of the power-down signal to the IRC. To avoid glitches when powering down the IRC, the IRC clock is automatically switched off at a clean point. Therefore, for the IRC a delay is possible before the power-down state takes effect. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 F A Flash wake-up configuration 0 FT R FLASH_PD A D Powered down FT 1 A Powered R R 0 IRC oscillator power-down wake-up configuration 0 D D IRC_PD A FT FT Powered down R A A 3 1 D R R 2 Reset value IRC oscillator output wake-up configuration Powered R A D D 1 Value Description 0 D R FT FT A A R R D D D Symbol IRCOUT_PD FT FT FT FT Bit A A A A R R D D D Wake-up configuration register (PDAWAKECFG, address 0x4004 8234) bit description 0 FT FT FT FT FT UM10601 Chapter 4: LPC800 System configuration (SYSCON) Table 36. A A A A A NXP Semiconductors © NXP B.V. 2012. All rights reserved. 36 of 313 D D D D D R R R R R D R R FT A 0 - Reserved. 1 SYSOSC_PD Crystal oscillator power down 1 0 Powered 1 Powered down WDTOSC_PD Watchdog oscillator power down. Changing this bit to powered-down has no effect when the LOCK bit in the WWDT MOD register is set. In this case, the watchdog oscillator is always running. 0 Powered 1 Powered down SYSPLL_PD System PLL power down 0 Powered 1 Powered down R Powered down D 1 1 1 11:8 - Reserved. Always write these bits as 0b1101 0b1101 14:12 - Reserved. Always write these bits as 0b110 0b110 15 ACMP Analog comparator power down 1 - 0 Powered 1 Powered down - Reserved D Powered 0 4.6.33 Device ID register This device ID register is a read-only register and contains the part ID for each LPC800 part. This register is also read by the ISP/IAP commands (see Table 229). UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 F 0 BOD power down 0 FT Powered down A A 1 BOD_PD FT R Powered A D 0 Flash power down 0 R FT Powered down A Powered 1 R IRC oscillator power down 0 D Powered down D 0 1 FLASH_PD FT IRC oscillator output power Powered IRC_PD FT Reset value 0 R A A Description 5 31:16 D R R Value 4 7 R A D D IRCOUT_PD 6 D R FT FT A A R R D D D 0 3 FT FT FT FT Symbol 2 A A A A R R D D D Power configuration register (PDRUNCFG, address 0x4004 8238) bit description Bit 1 FT FT FT FT FT UM10601 Chapter 4: LPC800 System configuration (SYSCON) Table 37. A A A A A NXP Semiconductors © NXP B.V. 2012. All rights reserved. 37 of 313 D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R 0x0000 8100 = LPC810M021FN8 part-dependent FT FT A A R D D R A FT D 0x0000 8121 = LPC812M101FD20 R A 0x0000 8122 = LPC812M101FDH20 4.7 Functional description 4.7.1 System PLL functional description The LPC800 uses the system PLL to create the clocks for the core and peripherals. LUFBRVFBFON SG )&&2 36(/! 3)' /2&. '(7(&7 SG /2&. FG 3 )&/.287 DQDORJVHFWLRQ SG FG 0 06(/! Fig 4. System PLL block diagram The block diagram of this PLL is shown in Figure 4. The input frequency range is 10 MHz to 25 MHz. The input clock is fed directly to the Phase-Frequency Detector (PFD). This block compares the phase and frequency of its inputs, and generates a control signal when phase and/ or frequency do not match. The loop filter filters these control signals and drives the current controlled oscillator (CCO), which generates the main clock and optionally two additional phases. The CCO frequency range is 156 MHz to 320 MHz. These clocks are either divided by 2P by the programmable post divider to create the output clocks, or are sent directly to the outputs. The main output clock is then divided by M by the programmable feedback divider to generate the feedback clock. The output signal of the phase-frequency detector is also monitored by the lock detector, to signal when the PLL has locked on to the input clock. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 F DEVICEID R 31:0 D Reset value D Description 0x0000 8120 = LPC812M101FDH16 6<63//&/.6(/ A FT FT A A R R D D D Symbol )&/.,1 FT FT FT FT Bit 0x0000 8110 = LPC811M001FDH16 V\VBRVFBFON A A A A R R D D D Device ID register (DEVICE_ID, address 0x4004 83F4) bit description &/.,1 FT FT FT FT FT UM10601 Chapter 4: LPC800 System configuration (SYSCON) Table 38. A A A A A NXP Semiconductors © NXP B.V. 2012. All rights reserved. 38 of 313 D D D D D R R R R R FT FT FT FT FT UM10601 D R R FT FT FT FT A A A A R R D D D Chapter 4: LPC800 System configuration (SYSCON) D R R A FT FT FT A A R R D D D R A FT The lock detector measures the phase difference between the rising edges of the input and feedback clocks. Only when this difference is smaller than the so called “lock criterion” for more than eight consecutive input clock periods, the lock output switches from low to high. A single too large phase difference immediately resets the counter and causes the lock signal to drop (if it was high). Requiring eight phase measurements in a row to be below a certain figure ensures that the lock detector will not indicate lock until both the phase and frequency of the input and feedback clocks are very well aligned. This effectively prevents false lock indications, and thus ensures a glitch free lock signal. F FT A A R R D D D 4.7.1.1 Lock detector A A A A A NXP Semiconductors D FT FT A A R R D D D R A Post divider The division ratio of the post divider is controlled by the PSEL bits. The division ratio is two times the value of P selected by PSEL bits as shown in Table 8. This guarantees an output clock with a 50% duty cycle. 4.7.1.3.2 Feedback divider The feedback divider’s division ratio is controlled by the MSEL bits. The division ratio between the PLL’s output clock and the input clock is the decimal value on MSEL bits plus one, as specified in Table 8 . 4.7.1.3.3 Changing the divider values Changing the divider ratio while the PLL is running is not recommended. As there is no way to synchronize the change of the MSEL and PSEL values with the dividers, the risk exists that the counter will read in an undefined value, which could lead to unwanted spikes or drops in the frequency of the output clock. The recommended way of changing between divider settings is to power down the PLL, adjust the divider settings and then let the PLL start up again. 4.7.1.4 Frequency selection The PLL frequency equations use the following parameters (also see Figure 4): Table 39. UM10601 Preliminary user manual PLL frequency parameters Parameter System PLL FCLKIN Frequency of sys_pllclkin (input clock to the system PLL) from the SYSPLLCLKSEL multiplexer (see Section 4.6.8). FCCO Frequency of the Current Controlled Oscillator (CCO); 156 to 320 MHz. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 39 of 313 A 4.7.1.3.1 R 4.7.1.3 Divider ratio programming D To reduce the power consumption when the PLL clock is not needed, a Power-down mode has been incorporated. This mode is enabled by setting the SYSPLL_PD bit to one in the Power-down configuration register (Table 37). In this mode, the internal current reference will be turned off, the oscillator and the phase-frequency detector will be stopped and the dividers will enter a reset state. While in Power-down mode, the lock output will be low to indicate that the PLL is not in lock. When the Power-down mode is terminated by setting the SYSPLL_PD bit to zero, the PLL will resume its normal operation and will make the lock signal high once it has regained lock on the input clock. FT 4.7.1.2 Power-down control D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R Frequency of sys_pllclkout P System PLL post divider ratio; PSEL bits in SYSPLLCTRL (see Section 4.6.3). M System PLL feedback divider register; MSEL bits in SYSPLLCTRL (see Section 4.6.3). D FT FT A A R R D D D R A FT D R A Normal mode (1) Fclkout = M Fclkin = FCCO 2 P To select the appropriate values for M and P, it is recommended to follow these steps: 1. Specify the input clock frequency Fclkin. 2. Calculate M to obtain the desired output frequency Fclkout with M = Fclkout / Fclkin. 3. Find a value so that FCCO = 2 P Fclkout. 4. Verify that all frequencies and divider values conform to the limits specified in Table 8. Table 40 shows how to configure the PLL for a 12 MHz crystal oscillator using the SYSPLLCTRL register (Table 8). The main clock is equivalent to the system clock if the system clock divider SYSAHBCLKDIV is set to one (see Table 17). PLL configuration examples PLL input clock sys_pllclkin (Fclkin) Main clock (Fclkout) MSEL bits Table 8 M divider PSEL bits value Table 8 P divider value FCCO frequency 12 MHz 48 MHz 00011(binary) 4 01 (binary) 2 192 MHz 12 MHz 36 MHz 00010(binary) 3 10 (binary) 4 288 MHz 12 MHz 24 MHz 00001(binary) 2 10 (binary) 4 192 MHz Power-down mode In this mode, the internal current reference will be turned off, the oscillator and the phase-frequency detector will be stopped and the dividers will enter a reset state. While in Power-down mode, the lock output will be low, to indicate that the PLL is not in lock. When the Power-down mode is terminated by SYSPLL_PD bit to zero in the Power-down configuration register (Table 37), the PLL will resume its normal operation and will make the lock signal high once it has regained lock on the input clock. UM10601 Preliminary user manual F FT FT FCLKOUT A A A R R D D D System PLL In this mode the post divider is enabled, giving a 50% duty cycle clock with the following frequency relations: 4.7.1.4.2 FT FT FT FT Parameter Table 40. A A A A R R D D D 4.7.1.4.1 PLL frequency parameters FT FT FT FT FT UM10601 Chapter 4: LPC800 System configuration (SYSCON) Table 39. A A A A A NXP Semiconductors All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 40 of 313 R R R R R A A A A A FT FT FT FT FT D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D D R R R D D Chapter 5: LPC800 Reduced power modes and Power Management Unit (PMU) F FT FT A A Preliminary user manual A Rev. 1.0 — 7 November 2012 D D D D D UM10601 D FT FT A A R R D D D R A 5.1 How to read this chapter FT D 5.2 Features • Reduced power modes control • Low-power oscillator control • Four general purpose backup registers to retain data in Deep power-down mode 5.3 Basic configuration The PMU is always on as long as VDD is present. 5.4 Pin description The LPC800 has no configurable pins. In Deep power-down only the WAKEUP pin (pin PIO0_4) is functional. The WAKEUP function can be disabled in the DPDCTRL register to lower the power consumption even more. In this case enable the self wake-up timer to provide an internal wake-up signal. See Section 5.6.3 “Deep power-down control register”. Remark: When entering Deep power-down mode, an external pull-up resistor is required on the WAKEUP pin to hold it HIGH. Pull the RESET pin HIGH to prevent it from floating while in Deep power-down mode. 5.5 General description Power on the LPC800 is controlled by the PMU, by the SYSCON block, and the ARM Cortex-M0+ core. The following reduced power modes are supported in order from highest to lowest power consumption: 1. Sleep mode: The sleep mode affects the ARM Cortex-M0 core only. Peripherals and memories are active. 2. Deep-sleep and power-down modes: The Deep-sleep and power-down modes affect the core and the entire system with memories and peripherals. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 41 of 313 A Read this chapter to configure the reduced power modes Deep-sleep mode, Power-down mode, and Deep power-down mode. R The LPC800 provides an on-chip API in the boot ROM to optimize power consumption in active and sleep modes. See Table 247 “Power profile API calls”. D D D D D R R R R R A A A A A FT FT FT UM10601 FT FT D R R FT FT FT FT Chapter 5: LPC800 Reduced power modes and Power Management A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D a. In Deep-sleep mode, the peripherals receive no internal clocks. Memories are in stand-by mode. All registers maintain their internal states. The WWDT, WKT, and BOD can remain active to wake up the system on an interrupt. D FT FT A A R R D b. In Power-down mode, the peripherals receive no internal clocks. All registers maintain their internal states. The flash memory is powered down. The WWDT, WKT, and BOD can remain active to wake up the system on an interrupt. D D R A D R A For maximal power savings, the entire system is shut down except for the general purpose registers in the PMU and the self wake-up timer. All registers maintain their internal states. The part can wake up on a pulse on the WAKEUP pin or when the self wake-up timer times out. On wake-up, the part reboots. Remark: The LPC800 is in active mode when it is fully powered and operational after booting. 5.5.1 Wake-up process If the part receives a wake-up signal in any of the reduced power modes, it wakes up to the active mode. See these links for related registers and wake-up instructions: • To configure the system after wake-up: Table 36 “Wake-up configuration register (PDAWAKECFG, address 0x4004 8234) bit description”. • To use external interrupts for wake-up: Table 33 “Start logic 0 pin wake-up enable register 0 (STARTERP0, address 0x4004 8204) bit description” and Table 32 “Pin interrupt select registers (PINTSEL[0:7], address 0x4004 8178 (PINTSEL0) to 0x4004 8194 (PINTSEL7)) bit description” • To enable external or internal signals to wake up the part from Deep-sleep or Power-down modes: Table 34 “Start logic 1 interrupt wake-up enable register (STARTERP1, address 0x4004 8214) bit description” • To configure the USART to wake up the part: Section 15.3.2 “Configure the USART for wake-up” • For configuring the self wake-up timer: Section 14.5 • For a list of all wake-up sources: Table 41 “Wake-up sources for reduced power modes” UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 FT 3. Deep power-down mode: © NXP B.V. 2012. All rights reserved. 42 of 313 D D D D D R R R R R D R R FT FT D A FT Enable interrupt in BODCTRL register. D R BOD powered in PDSLEEPCFG register. A UM10601 Preliminary user manual Enable reset in BODCTRL register. BOD powered in PDSLEEPCFG register. Enable interrupt in NVIC and STARTERP1 registers. WWDT running. Enable WWDT in WWDT MOD register and feed. Enable interrupt in WWDT MOD register. WDOsc powered in PDSLEEPCFG register. WWDT running. Enable reset in WWDT MOD register. WDOsc powered in PDSLEEPCFG register. Enable interrupt in NVIC and STARTERP1 registers. Enable low-power oscillator in the GPREG4 register in the PCON block. Select low-power clock for WKT clock in the WKT CTRL register. Start the WKT by writing a time-out value to the WKT COUNT register. Enable interrupt in NVIC and STARTERP1 registers. Enable USART/I2C/SPI interrupts. Provide an external clock signal to the peripheral. Configure the USART in synchronous slave mode and I2C and SPI in slave mode. Enable the WAKEUP function in the GPREG4 register in the PMU. • • Enable the low-power oscillator in the GPREG4 register in the PMU. • • Select low-power clock for WKT clock in the WKT CTRL register. Enable the low-power oscillator to keep running in Deep power-down mode in the GPREG4 register in the PMU. Start WKT by writing a time-out value to the WKT COUNT register. Register overview: PMU (base address 0x4002 0000) Name Access Address offset Description Reset value Reference PCON R/W 0x000 Power control register 0x0 Table 43 GPREG0 R/W 0x004 General purpose register 0 0x0 Table 44 GPREG1 R/W 0x008 General purpose register 1 0x0 Table 44 GPREG2 R/W 0x00C General purpose register 2 0x0 Table 44 GPREG3 R/W 0x010 General purpose register 3 0x0 Table 44 DPDCTRL R/W 0x014 Deep power-down control register 0x0 Table 45 All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 F A R Enable interrupt in NVIC and STARTERP1 registers. 5.6 Register description Table 42. A R WKT time-out D Deep power-down WAKEUP pin PIO0_4 D Interrupt from USART/SPI/I2C peripheral FT Self Wake-up Timer (WKT) time-out A WWDT reset R WWDT interrupt D BOD reset • • • • • • • • • • • • • • • • • • • • FT FT Enable pin interrupts in NVIC and STARTERP0 registers. R A A Enable interrupt in NVIC. Pin interrupts BOD interrupt Conditions D R R Any interrupt Deep-sleep and Power-down R A D D Sleep D R FT FT A A R R D D D Wake-up source FT FT FT FT Power mode A A A A R R D D D Wake-up sources for reduced power modes FT FT FT FT FT UM10601 Chapter 5: LPC800 Reduced power modes and Power Management Table 41. A A A A A NXP Semiconductors © NXP B.V. 2012. All rights reserved. 43 of 313 D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D Chapter 5: LPC800 Reduced power modes and Power Management D R R A FT FT FT A A R R D D D R A FT FT A A R R D D The power control register selects whether one of the ARM Cortex-M0 controlled power-down modes (Sleep mode or Deep-sleep/Power-down mode) or the Deep power-down mode is entered and provides the flags for Sleep or Deep-sleep/Power-down modes and Deep power-down modes respectively. See <tbd> for details on how to enter the power-down modes. F FT FT A A R R D D D 5.6.1 Power control register FT FT FT UM10601 FT FT NXP Semiconductors D D R A FT D R Power control register (PCON, address 0x4002 0000) bit description Bit Symbol 2:0 PM Value 3 NODPD 7:4 - 8 SLEEPFLAG Description Reset value Power mode 000 0x0 Default. The part is in active or sleep mode. 0x1 ARM WFI will enter Deep-sleep mode. 0x2 ARM WFI will enter Power-down mode. 0x3 ARM WFI will enter Deep-power down mode (ARM Cortex-M0 core powered-down). A 1 in this bit prevents entry to Deep power-down mode 0 when 0x3 is written to the PM field above, the SLEEPDEEP bit is set, and a WFI is executed. This bit is cleared only by power-on reset, so writing a one to this bit locks the part in a mode in which Deep power-down mode is blocked. - 10:9 - 11 DPDFLAG 31:12 A Table 43. 0 0 0 Read: No power-down mode entered. LPC11Uxx is in Active mode. Write: No effect. 1 Read: Sleep/Deep-sleep or Deep power-down mode entered. Write: Writing a 1 clears the SLEEPFLAG bit to 0. - - Reserved. Do not write ones to this bit. Sleep mode flag Reserved. Do not write ones to this bit. 0 Deep power-down flag 0 0 Read: Deep power-down mode not entered. Write: No effect. 0 1 Read: Deep power-down mode entered. Write: Clear the Deep power-down flag. - Reserved. Do not write ones to this bit. 0 5.6.2 General purpose registers 0 to 3 The general purpose registers retain data through the Deep power-down mode when power is still applied to the VDD pin but the chip has entered Deep power-down mode. Only a cold boot - when all power has been completely removed from the chip - will reset the general purpose registers. Table 44. UM10601 Preliminary user manual General purpose registers 0 to 3 (GPREG[0:3], address 0x4002 0004 (GPREG0) to 0x4002 0010 (GPREG3)) bit description Bit Symbol Description Reset value 31:0 GPDATA Data retained during Deep power-down mode. 0x0 All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 44 of 313 D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D Chapter 5: LPC800 Reduced power modes and Power Management D R R A FT FT FT A A R R D D D R A FT FT A A R R D D The Deep power-down control register controls the low-power oscillator that can be used by the self wake-up timer to wake up from Deep power-down mode. In addition, this register configures the functionality of the WAKEUP pin (pin PIO0_4). F FT FT A A R R D D D 5.6.3 Deep power-down control register FT FT FT UM10601 FT FT NXP Semiconductors D D R A Deep power down control register (DPDCTRL, address 0x4002 0014) bit description Bit Symbol 0 WAKEUPHYS 1 Value Description Reset value WAKEUP pin hysteresis enable 0 0 Disabled. Hysteresis for WAKEUP pin disabled. 1 Enabled. Hysteresis for WAKEUP pin enabled. WAKEPAD_ DISABLE WAKEUP pin disable. Setting this bit disables the wake-up pin, so it can be used for other purposes. 0 Remark: Never set this bit if you intend to use a pin to wake up the part from Deep power-down mode. You can only disable the wake-up pin if the self wake-up timer is enabled and configured. Remark: Setting this bit is not necessary if Deep power-down mode is not used. 0 1 2 LPOSCEN Enabled. The wake-up function is enabled on pin PIO0_4. Disabled. Setting this bit disables the wake-up function on pin PIO0_4. Enable the low-power oscillator for use with the 10 kHz self wake-up timer 0 clock. You must set this bit if the CLKSEL bit in the self wake-up timer CTRL bit is set. Do not enable the low-power oscillator if the self wake-up timer is clocked by the divided IRC. UM10601 Preliminary user manual 0 Disabled. 1 Enabled. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 45 of 313 A Table 45. R Remark: Enabling the low-power oscillator in Deep power-down mode increases the power consumption. Only enable this oscillator if you need the self wake-up timer to wake up the part from Deep power-down mode. You may need the self wake-up timer to wake up from Deep power-down mode if the wake-up pin is used for other purposes and the wake-up function is not available. D Remark: If there is a possibility that the external voltage applied on pin VDD drops below 2.2 V during Deep power-down, the hysteresis of the WAKEUP input pin has to be disabled in this register before entering Deep power-down mode in order for the chip to wake up. FT The bits in the register not used for deep power-down control (bits 31:4) can be used for storing additional data which are retained in Deep power-down mode in the same way as registers GPREG0 to GPREG3. D D D D D R R R R R D R R R A FT R R FT FT A A R 0 D D R A FT D You must set this bit for the self wake-up timer to be able to wake up the part from Deep power-down mode. R A Remark: Do not set this bit unless you must use the self wake-up timer to wake up from Deep power-down mode. 31:4 0 Disabled. 1 Enabled. - Data retained during Deep power-down mode. 0x0 5.7 Functional description 5.7.1 Power management The LPC800 support a variety of power control features. In Active mode, when the chip is running, power and clocks to selected peripherals can be optimized for power consumption. In addition, there are four special modes of processor power reduction with different peripherals running: Sleep mode, Deep-sleep mode, Power-down mode, and Deep power-down mode. Table 46. Peripheral configuration in reduced power modes Peripheral Sleep mode Deep-sleep mode Power-down mode Deep power-down mode IRC software configurable on off off IRC output software configurable off off off Flash software configurable on off off BOD software configurable software configurable software configurable off PLL software configurable off off off SysOsc software configurable off off off WDosc/WWDT software configurable software configurable software configurable off Digital peripherals software configurable off off off WKT/low-power oscillator software configurable software configurable software configurable software configurable Remark: The Debug mode is not supported in Sleep, Deep-sleep, Power-down, or Deep power-down modes. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 F D D Enable the low-power oscillator in Deep power-down mode. Setting this bit causes the low-power oscillator to remain running during Deep power-down mode provided that bit 12 in this register is set as well. A FT Reset value FT A A R R D D D LPOSCDPDEN Description D R FT FT A A R R D D D 3 Value FT FT FT FT Symbol A A A A R R D D D Deep power down control register (DPDCTRL, address 0x4002 0014) bit description …continued Bit FT FT FT FT FT UM10601 Chapter 5: LPC800 Reduced power modes and Power Management Table 45. A A A A A NXP Semiconductors © NXP B.V. 2012. All rights reserved. 46 of 313 D D D D D R R R R R FT FT FT FT FT UM10601 D R R FT FT FT FT A A A A R R D D D Chapter 5: LPC800 Reduced power modes and Power Management D R R A FT FT FT A A R R D D D R A FT FT A A R R D D The WWDT clock select lock feature influences the power consumption in any of the power modes because locking the WWDT clock source forces the selected WWDT clock source to be on independently of the Deep-sleep and Power-down mode software configuration through the PDSLEEPCFG register. For details see Section 12.5.3 “Using the WWDT lock features”. F FT FT A A R R D D D 5.7.2 Reduced power modes and WWDT lock features A A A A A NXP Semiconductors D D R A FT D 5.7.3 Active mode In Active mode, the ARM Cortex-M0 core and memories are clocked by the system clock, and peripherals are clocked by the system clock or a dedicated peripheral clock. The chip is in Active mode after reset and the default power configuration is determined by the reset values of the PDRUNCFG and SYSAHBCLKCTRL registers. The power configuration can be changed during run time. 5.7.3.1 Power configuration in Active mode Power consumption in Active mode is determined by the following configuration choices: • The SYSAHBCLKCTRL register controls which memories and peripherals are running (Table 18). • The power to various analog blocks (PLL, oscillators, the ADC, the BOD circuit, and the flash block) can be controlled at any time individually through the PDRUNCFG register (Table 37 “Power configuration register (PDRUNCFG, address 0x4004 8238) bit description”). • The clock source for the system clock can be selected from the IRC (default), the system oscillator, or the watchdog oscillator (see Figure 3 and related registers). • The system clock frequency can be selected by the SYSPLLCTRL (Table 8) and the SYSAHBCLKDIV register (Table 17). • The USART and CLKOUT use individual peripheral clocks with their own clock dividers. The peripheral clocks can be shut down through the corresponding clock divider registers. 5.7.4 Sleep mode In Sleep mode, the system clock to the ARM Cortex-M0+ core is stopped and execution of instructions is suspended until either a reset or an interrupt occurs. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 47 of 313 A If the part uses Power-down mode with the WWDT running, the watchdog oscillator must be selected as the clock source. If the clock source is not locked, the watchdog oscillator must be powered by using the PDSLEEPCFG register. Do not lock the clock source with the IRC selected. R If the part uses Deep-sleep mode with the WWDT running, the watchdog oscillator is the preferred clock source as it minimizes power consumption. If the clock source is not locked, the watchdog oscillator must be powered by using the PDSLEEPCFG register. Alternatively, the IRC may be selected and locked in WWDT MOD register, which forces the IRC on during Deep-sleep mode. D D D D D R R R R R A A A A A FT FT FT UM10601 FT FT D R R FT FT FT FT Chapter 5: LPC800 Reduced power modes and Power Management A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D Peripheral functions, if selected to be clocked in the SYSAHBCLKCTRL register, continue operation during Sleep mode and may generate interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses. The processor state and registers, peripheral registers, and internal SRAM values are maintained, and the logic levels of the pins remain static. D FT FT A A R R D D D R A FT D R A 5.7.4.1 Power configuration in Sleep mode Power consumption in Sleep mode is configured by the same settings as in Active mode: • The clock remains running. • The system clock frequency remains the same as in Active mode, but the processor is not clocked. • Analog and digital peripherals are selected as in Active mode. 5.7.4.2 Programming Sleep mode The following steps must be performed to enter Sleep mode: 1. The PD bits in the PCON register must be set to the default value 0x0. 2. The SLEEPDEEP bit in the ARM Cortex-M0+ SCR register must be set to zero. 3. Use the ARM Cortex-M0+ Wait-For-Interrupt (WFI) instruction. 5.7.4.3 Wake-up from Sleep mode Sleep mode is exited automatically when an interrupt enabled by the NVIC arrives at the processor or a reset occurs. After wake-up due to an interrupt, the microcontroller returns to its original power configuration defined by the contents of the PDRUNCFG and the SYSAHBCLKDIV registers. If a reset occurs, the microcontroller enters the default configuration in Active mode. 5.7.5 Deep-sleep mode In Deep-sleep mode, the system clock to the processor is disabled as in Sleep mode. All analog blocks are powered down, except for the BOD circuit and the watchdog oscillator, which must be selected or deselected during Deep-sleep mode in the PDSLEEPCFG register. The main clock, and therefore all peripheral clocks, are disabled except for the clock to the watchdog timer if the watchdog oscillator is selected. The IRC is running, but its output is disabled. The flash is in stand-by mode. Deep-sleep mode eliminates all power used by analog peripherals and all dynamic power used by the processor itself, memory systems and related controllers, and internal buses. The processor state and registers, peripheral registers, and internal SRAM values are maintained, and the logic levels of the pins remain static. 5.7.5.1 Power configuration in Deep-sleep mode Power consumption in Deep-sleep mode is determined by the Deep-sleep power configuration setting in the PDSLEEPCFG (Table 35) register: • The watchdog oscillator can be left running in Deep-sleep mode if required for the WWDT. • The BOD circuit can be left running in Deep-sleep mode if required by the application. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 48 of 313 D D D D D R R R R R A A A A A D R R FT FT FT FT D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D The following steps must be performed to enter Deep-sleep mode: A A A A R R D D D Chapter 5: LPC800 Reduced power modes and Power Management 5.7.5.2 Programming Deep-sleep mode FT FT FT UM10601 FT FT NXP Semiconductors D FT FT A A R R D 1. The PD bits in the PCON register must be set to 0x1 (Table 43). D D R 2. Select the power configuration in Deep-sleep mode in the PDSLEEPCFG (Table 35) register. A 5.7.5.3 Wake-up from Deep-sleep mode The microcontroller can wake up from Deep-sleep mode in the following ways: • Signal on one of the eight pin interrupts selected in Table 32. Each pin interrupt must also be enabled in the STARTERP0 register (Table 33) and in the NVIC. • BOD signal, if the BOD is enabled in the PDSLEEPCFG register: – BOD interrupt using the deep-sleep interrupt wake-up register 1 (Table 34). The BOD interrupt must be enabled in the NVIC. The BOD interrupt must be selected in the BODCTRL register. – Reset from the BOD circuit. In this case, the BOD circuit must be enabled in the PDSLEEPCFG register, and the BOD reset must be enabled in the BODCTRL register (Table 28). • WWDT signal, if the watchdog oscillator is enabled in the PDSLEEPCFG register: – WWDT interrupt using the interrupt wake-up register 1 (Table 34). The WWDT interrupt must be enabled in the NVIC. The WWDT interrupt must be set in the WWDT MOD register. – Reset from the watchdog timer. The WWDT reset must be set in the WWDT MOD register. In this case, the watchdog oscillator must be running in Deep-sleep mode (see PDSLEEPCFG register), and the WDT must be enabled in the SYSAHBCLKCTRL register. • Via any of the USART blocks. See Section 15.3.2 “Configure the USART for wake-up”. • Via the I2C. See <tbd>. • Via any of the SPI blocks. See <tbd>. Remark: If the watchdog oscillator is running in Deep-sleep mode, its frequency determines the wake-up time. 5.7.6 Power-down mode In Power-down mode, the system clock to the processor is disabled as in Sleep mode. All analog blocks are powered down, except for the BOD circuit and the watchdog oscillator, which must be selected or deselected during Power-down mode in the PDSLEEPCFG UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 49 of 313 A 6. Use the ARM WFI instruction. R 5. Write one to the SLEEPDEEP bit in the ARM Cortex-M0 SCR register. D 4. If any of the available wake-up interrupts are needed for wake-up, enable the interrupts in the interrupt wake-up registers (Table 33, Table 34) and in the NVIC. FT 3. Select the power configuration after wake-up in the PDAWAKECFG (Table 36) register. D D D D D R R R R R A A A A A FT FT FT UM10601 FT FT D R R FT FT FT FT Chapter 5: LPC800 Reduced power modes and Power Management A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D register. The main clock and therefore all peripheral clocks are disabled except for the clock to the watchdog timer if the watchdog oscillator is selected. The IRC itself and the flash are powered down, decreasing power consumption compared to Deep-sleep mode. D FT FT A A R R D D D Power-down mode eliminates all power used by analog peripherals and all dynamic power used by the processor itself, memory systems and related controllers, and internal buses. The processor state and registers, peripheral registers, and internal SRAM values are maintained, and the logic levels of the pins remain static. Wake-up times are longer compared to the Deep-sleep mode. R A • The BOD circuit can be left running in Power-down mode if required by the application. 5.7.6.2 Programming Power-down mode The following steps must be performed to enter Power-down mode: 1. The PD bits in the PCON register must be set to 0x2 (Table 43). 2. Select the power configuration in Power-down mode in the PDSLEEPCFG (Table 35) register. 3. Select the power configuration after wake-up in the PDAWAKECFG (Table 36) register. 4. If any of the available wake-up interrupts are used for wake-up, enable the interrupts in the interrupt wake-up registers (Table 33, Table 34) and in the NVIC. 5. Write one to the SLEEPDEEP bit in the ARM Cortex-M0 SCR register. 6. Use the ARM WFI instruction. 5.7.6.3 Wake-up from Power-down mode The microcontroller can wake up from Power-down mode in the same way as from Deep-sleep mode: • Signal on one of the eight pin interrupts selected in Table 32. Each pin interrupt must also be enabled in the STARTERP0 register (Table 33) and in the NVIC. • BOD signal, if the BOD is enabled in the PDSLEEPCFG register: – BOD interrupt using the interrupt wake-up register 1 (Table 34). The BOD interrupt must be enabled in the NVIC. The BOD interrupt must be selected in the BODCTRL register. – Reset from the BOD circuit. In this case, the BOD reset must be enabled in the BODCTRL register (Table 28). • WWDT signal, if the watchdog oscillator is enabled in the PDSLEEPCFG register: UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 50 of 313 A WWDT. R • The watchdog oscillator can be left running in Power-down mode if required for the D Power consumption in Power-down mode can be configured by the power configuration setting in the PDSLEEPCFG (Table 35) register in the same way as for Deep-sleep mode (see Section 5.7.5.1): FT 5.7.6.1 Power configuration in Power-down mode D D D D D R R R R R A A A A A FT FT FT UM10601 FT FT D R R FT FT FT FT Chapter 5: LPC800 Reduced power modes and Power Management A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D – WWDT interrupt using the interrupt wake-up register 1 (Table 34). The WWDT interrupt must be enabled in the NVIC. The WWDT interrupt must be set in the WWDT MOD register. D FT FT A A R R D – Reset from the watchdog timer. The WWDT reset must be set in the WWDT MOD register. D D R A In Deep power-down mode, power and clocks are shut off to the entire chip with the exception of the WAKEUP pin and the self wake-up timer. During Deep power-down mode, the contents of the SRAM and registers are not retained except for a small amount of data which can be stored in the general purpose registers of the PMU block. All functional pins are tri-stated in Deep power-down mode except for the WAKEUP pin. Remark: Setting bit 3 in the PCON register (Table 43) prevents the part from entering Deep-power down mode. 5.7.7.1 Power configuration in Deep power-down mode Deep power-down mode has no configuration options. All clocks, the core, and all peripherals are powered down. Only the WAKEUP pin and the self wake-up timer are powered. 5.7.7.2 Programming Deep power-down mode The following steps must be performed to enter Deep power-down mode: 1. Pull the WAKEUP pin externally HIGH. 2. Ensure that bit 3 in the PCON register (Table 43) is cleared. 3. Write 0x3 to the PD bits in the PCON register (see Table 43). 4. Store data to be retained in the general purpose registers (Section 5.6.2). 5. Write one to the SLEEPDEEP bit in the ARM Cortex-M0 SCR register. 6. Use the ARM WFI instruction. 5.7.7.3 Wake-up from Deep power-down mode Pulling the WAKEUP pin LOW wakes up the LPC800 from Deep power-down, and the part goes through the entire reset process. 1. On the WAKEUP pin, transition from HIGH to LOW. – The PMU will turn on the on-chip voltage regulator. When the core voltage reaches the power-on-reset (POR) trip point, a system reset will be triggered and the chip re-boots. – All registers except the GPREG0 to GPREG3 and PCON will be in their reset state. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 51 of 313 A 5.7.7 Deep power-down mode R – Via any of the SPI blocks. See <tbd>. D – Via the I2C. See <tbd>. FT – Via any of the USART blocks. See Section 15.3.2 “Configure the USART for wake-up”. D D D D D R R R R R A A A A A FT FT FT UM10601 FT FT D R R FT FT FT FT Chapter 5: LPC800 Reduced power modes and Power Management A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D 2. Once the chip has booted, read the deep power-down flag in the PCON register (Table 43) to verify that the reset was caused by a wake-up event from Deep power-down and was not a cold reset. D FT FT A A R R D 3. Clear the deep power-down flag in the PCON register (Table 43). D D R A 4. (Optional) Read the stored data in the general purpose registers (Section 5.6.2). FT D 5. Set up the PMU for the next Deep power-down cycle. R A Remark: The RESET pin has no functionality in Deep power-down mode. For using the self wake-up timer for waking up from Deep power-down mode, see Section 14.5. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 52 of 313 A A A A A FT FT FT FT FT D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D Preliminary user manual D Rev. 1.0 — 7 November 2012 R R R R R Chapter 6: LPC800 I/O configuration (IOCON) D D D D D UM10601 D FT FT A A R R D D D 6.1 How to read this chapter R A Pins/configuration registers available TSSOP16 PIO0_0 to PIO0_13 TSSOP20 PIO0_0 to PIO0_17 SOP20 PIO0_0 to PIO0_17 DIP8 PIO0_0 to PIO0_5 6.2 Features The following electrical properties are configurable for each pin: • • • • • Pull-up/pull-down resistor Open-drain mode Hysteresis Digital glitch filter with programmable time constant Analog mode (for a subset of pins, see the LPC81xM data sheet) The true open-drain pins PIO0_10 and PIO0_11 can be configured for different I2C-bus speeds. 6.3 Basic configuration Enable the clock to the IOCON in the SYSAHBCLKCTRL register (Table 18, bit 18). Once the pins are configured, you can disable the IOCON clock to conserve power. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 53 of 313 A Package R Pinout summary D Table 47. FT The IOCON block is identical for all LPC800 parts. Registers for pins that are not available on a specific package are reserved. D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D Chapter 6: LPC800 I/O configuration (IOCON) D R R A FT FT FT A A R R D D D R F D FT FT A A R R D 6.4.1 Pin configuration A FT FT A A R R D D D 6.4 General description FT FT FT UM10601 FT FT NXP Semiconductors D D R A 9'' D R VWURQJ SXOOXS RXWSXWHQDEOH A SLQFRQILJXUHG DVGLJLWDORXWSXW GULYHU FT 9'' RSHQGUDLQHQDEOH (6' GDWDRXWSXW 3,1 VWURQJ SXOOGRZQ (6' 966 9'' ZHDN SXOOXS SXOOXSHQDEOH UHSHDWHUPRGH HQDEOH SLQFRQILJXUHG DVGLJLWDOLQSXW GDWDLQSXW VHOHFWGDWD LQYHUWHU VHOHFWJOLWFK ILOWHU SLQFRQILJXUHG DVDQDORJLQSXW Fig 5. ZHDN SXOOGRZQ SXOOGRZQHQDEOH 352*5$00$%/( */,7&+),/7(5 VHOHFWDQDORJLQSXW DQDORJLQSXW Pin configuration 6.4.2 Pin function The pin function is determined entirely through the switch matrix. By default one of the GPIO functions is assigned to each pin. The switch matrix can assign all functions from the movable function table to any pin in the IOCON block or enable a special function like an analog input on a specific pin. Related links: Table 94 “Movable functions (assign to pins PIO0_0 to PIO_17 through switch matrix)” 6.4.3 Pin mode The MODE bit in the IOCON register allows enabling or disabling an on-chip pull-up resistor for each pin. By default all pull-up resistors are enabled except for the I2C-bus pins PIO0_10 and PIO0_11, which do not have a programmable pull-up resistor. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 54 of 313 D D D D D R R R R R A A A A A FT FT FT UM10601 FT FT D R R FT FT FT FT Chapter 6: LPC800 I/O configuration (IOCON) A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D The repeater mode enables the pull-up resistor if the pin is high and enables the pull-down resistor if the pin is low. This causes the pin to retain its last known state if it is configured as an input and is not driven externally. Repeater mode may typically be used to prevent a pin from floating (and potentially using significant power if it floats to an indeterminate state) if it is temporarily not driven. D FT FT A A R R D D D R A FT D 6.4.4 Open-drain mode R A An open-drain mode can be enabled for all digital I/O pins. Except for pins PIO0_10 and PIO0_11, this mode is not a true open-drain mode. The input cannot be pulled up above VDD. 6.4.5 Analog mode The switch matrix automatically configures the pin in analog mode whenever an analog input or output is selected as the pin’s function. 6.4.6 I2C-bus mode The I2C-bus pins PIO0_10 and PIO0_11 can be programmed to support a true open-drain mode independently of whether the I2C function is selected or another digital function. If the I2C function is selected, all three I2C modes, Standard mode, Fast-mode, and Fast-mode plus, are supported. A digital glitch filter can be configured for all functions. Pins PIO0_10 and PIO0_11 operate as high-current sink drivers (20 mA) independently of the programmed function. 6.4.7 Programmable glitch filter All GPIO pins are equipped with a programmable, digital glitch filter. The filter rejects input pulses with a selectable duration of shorter than one, two, or three cycles of a filter clock (S_MODE = 1, 2, or 3). For each individual pin, the filter clock can be selected from one of seven peripheral clocks PCLK0 to 6, which are derived from the main clock using the IOCONCLKDIV0 to 6 registers. The filter can also be bypassed entirely. Any input pulses of duration Tpulse of either polarity will be rejected if: Tpulse TPCLKn S_MODE Input pulses of one filter clock cycle longer may also be rejected: Tpulse TPCLKn (S_MODE + 1) Remark: The filtering effect is accomplished by requiring that the input signal be stable for (S_MODE +1) successive edges of the filter clock before being passed on to the chip. Enabling the filter results in delaying the signal to the internal logic and should be done only if specifically required by an application. For high-speed or time critical functions ensure that the filter is bypassed. If the delay of the input signal must be minimized, select a faster PCLK and a higher sample mode (S_MODE) to minimize the effect of the potential extra clock cycle. If the sensitivity to noise spikes must be minimized, select a slower PCLK and lower sample mode. Related registers and links: UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 55 of 313 D D D D D R R R R R A A A A A FT FT FT UM10601 FT FT D R R FT FT FT FT Chapter 6: LPC800 I/O configuration (IOCON) A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D Table 27 “IOCON glitch filter clock divider registers 6 to 0 (IOCONCLKDIV[6:0], address 0x4004 8134 (IOCONCLKDIV6) to 0x004 814C (IOCONFILTCLKDIV0)) bit description” D FT FT A A R R D D D R A FT D R A UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 56 of 313 D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D Chapter 6: LPC800 I/O configuration (IOCON) D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D 6.5 Register description FT FT FT UM10601 FT FT NXP Semiconductors D FT FT A A R R D Each port pin PIOn_m has one IOCON register assigned to control the pin’s function and electrical characteristics. D D R A Register overview: I/O configuration (base address 0x4004 4000) FT Table 48. Description Reset value Reference PIO0_17 R/W 0x000 I/O configuration for pin PIO0_17 0x0000 0090 Table 49 PIO0_13 R/W 0x004 I/O configuration for pin PIO0_13 0x0000 0090 Table 50 PIO0_12 R/W 0x008 I/O configuration for pin PIO0_12 0x0000 0090 Table 51 PIO0_5 R/W 0x00C I/O configuration for pin PIO0_5/RESET 0x0000 0090 Table 52 PIO0_4 R/W 0x010 I/O configuration for pin PIO0_4 0x0000 0090 Table 53 PIO0_3 R/W 0x014 I/O configuration for pin PIO0_3/SWCLK 0x0000 0090 Table 54 PIO0_2 R/W 0x018 I/O configuration for pin PIO0_2/SWDIO 0x0000 0090 Table 55 PIO0_11 R/W 0x01C I/O configuration for pin PIO0_11. This is the pin configuration for the true open-drain pin. 0x0000 0080 Table 56 PIO0_10 R/W 0x020 I/O configuration for pin PIO0_10. This is the pin configuration for the true open-drain pin. 0x0000 0080 Table 57 PIO0_16 R/W 0x024 I/O configuration for pin PIO0_16 0x0000 0090 Table 58 PIO0_15 R/W 0x028 I/O configuration for pin PIO0_15 0x0000 0090 Table 59 PIO0_1 R/W 0x02C I/O configuration for pin PIO0_1/ACMP_I1/CLKIN 0x0000 0090 Table 60 - - 0x030 Reserved - - PIO0_9 R/W 0x034 I/O configuration for pin PIO0_9/XTALOUT 0x0000 0090 Table 61 PIO0_8 R/W 0x038 I/O configuration for pin PIO0_8/XTALIN 0x0000 0090 Table 62 PIO0_7 R/W 0x03C I/O configuration for pin PIO0_7 0x0000 0090 Table 63 PIO0_6 R/W 0x040 I/O configuration for pin PIO0_6/VDDCMP 0x0000 0090 Table 64 PIO0_0 R/W 0x044 I/O configuration for pin PIO0_0/ACMP_I0 0x0000 0090 Table 65 PIO0_14 R/W 0x048 I/O configuration for pin PIO0_14 0x0000 0090 Table 66 A Address offset 6.5.1 PIO0_17 register Table 49. UM10601 Preliminary user manual PIO0_17 register (PIO0_17, address 0x4004 4000) bit description Bit Symbol 2:0 - R Access D Name Value Description Reset value Reserved. 0 All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 57 of 313 D D D D D R R R R R D R R R FT D R R A OD D 10 D - Repeater mode. Hysteresis. 0 Disable. 1 Enable. INV 9:7 FT 6 HYS FT 0x3 5 A Pull-up resistor enabled. R 0x2 D Pull-down resistor enabled. 0b10 FT 0x1 A Inactive (no pull-down/pull-up resistor enabled). A R 0x0 0 Invert input 0 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). - Reserved. 0b001 Open-drain mode. 0 0 Disable. 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. 12:11 15:13 31:16 UM10601 Preliminary user manual S_MODE Digital filter sample mode. - 0 0x0 Bypass input filter. 0x1 1 clock cycle. Input pulses shorter than one filter clock are rejected. 0x2 2 clock cycles. Input pulses shorter than two filter clocks are rejected. 0x3 3 clock cycles. Input pulses shorter than three filter clocks are rejected. CLK_DIV Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 0x0 IOCONCLKDIV0. 0x1 IOCONCLKDIV1. 0x2 IOCONCLKDIV2. 0x3 IOCONCLKDIV3. 0x4 IOCONCLKDIV4. 0x5 IOCONCLKDIV5. 0x6 IOCONCLKDIV6. - Reserved. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 F D D Selects function mode (on-chip pull-up/pull-down resistor control). A FT Reset value FT A A R R R Description D A D D MODE R FT FT A A R R D D D 4:3 Value FT FT FT FT Symbol A A A A R R D D D PIO0_17 register (PIO0_17, address 0x4004 4000) bit description Bit FT FT FT FT FT UM10601 Chapter 6: LPC800 I/O configuration (IOCON) Table 49. A A A A A NXP Semiconductors 0 0 © NXP B.V. 2012. All rights reserved. 58 of 313 D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R F D Reset value FT Description FT A A R R D Value A FT FT A A R R D D D PIO0_13 register (PIO0_13, address 0x4004 4004) bit description Symbol FT FT FT FT Bit A A A A R R D D D 6.5.2 PIO0_13 register FT FT FT FT FT UM10601 Chapter 6: LPC800 I/O configuration (IOCON) Table 50. A A A A A NXP Semiconductors D D 5 6 Pull-down resistor enabled. 0x2 Pull-up resistor enabled. 0x3 Repeater mode. Hysteresis. 0 Disable. 1 Enable. INV 9:7 - 10 OD Inactive (no pull-down/pull-up resistor enabled). 0x1 HYS A 0x0 0 Invert input 0 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). - Reserved. 0b001 Open-drain mode. 0 0 Disable. 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. 12:11 15:13 31:16 UM10601 Preliminary user manual S_MODE Digital filter sample mode. Bypass input filter. 0x1 1 clock cycle. Input pulses shorter than one filter clock are rejected. 0x2 2 clock cycles. Input pulses shorter than two filter clocks are rejected. 0x3 3 clock cycles. Input pulses shorter than three filter clocks are rejected. CLK_DIV - 0 0x0 Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 0x0 IOCONCLKDIV0. 0x1 IOCONCLKDIV1. 0x2 IOCONCLKDIV2. 0x3 IOCONCLKDIV3. 0x4 IOCONCLKDIV4. 0x5 IOCONCLKDIV5. 0x6 IOCONCLKDIV6. - Reserved. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 R 0b10 D 0 Selects function mode (on-chip pull-up/pull-down resistor control). FT Reserved. MODE A - 4:3 R 2:0 0 0 © NXP B.V. 2012. All rights reserved. 59 of 313 D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R F D Reset value FT Description FT A A R R D Value A FT FT A A R R D D D PIO0_12 register (PIO0_12, address 0x4004 4008) bit description Symbol FT FT FT FT Bit A A A A R R D D D 6.5.3 PIO0_12 register FT FT FT FT FT UM10601 Chapter 6: LPC800 I/O configuration (IOCON) Table 51. A A A A A NXP Semiconductors D D 5 6 Pull-down resistor enabled. 0x2 Pull-up resistor enabled. 0x3 Repeater mode. Hysteresis. 0 Disable. 1 Enable. INV 9:7 - 10 OD Inactive (no pull-down/pull-up resistor enabled). 0x1 HYS A 0x0 0 Invert input 0 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). - Reserved. 0b001 Open-drain mode. 0 0 Disable. 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. 12:11 15:13 31:16 UM10601 Preliminary user manual S_MODE Digital filter sample mode. Bypass input filter. 0x1 1 clock cycle. Input pulses shorter than one filter clock are rejected. 0x2 2 clock cycles. Input pulses shorter than two filter clocks are rejected. 0x3 3 clock cycles. Input pulses shorter than three filter clocks are rejected. CLK_DIV - 0 0x0 Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 0x0 IOCONCLKDIV0. 0x1 IOCONCLKDIV1. 0x2 IOCONCLKDIV2. 0x3 IOCONCLKDIV3. 0x4 IOCONCLKDIV4. 0x5 IOCONCLKDIV5. 0x6 IOCONCLKDIV6. - Reserved. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 R 0b10 D 0 Selects function mode (on-chip pull-up/pull-down resistor control). FT Reserved. MODE A - 4:3 R 2:0 0 0 © NXP B.V. 2012. All rights reserved. 60 of 313 D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R F D Reset value FT Description FT A A R R D Value A FT FT A A R R D D D PIO0_5 register (PIO0_5, address 0x4004 400C) bit description Symbol FT FT FT FT Bit A A A A R R D D D 6.5.4 PIO0_5 register FT FT FT FT FT UM10601 Chapter 6: LPC800 I/O configuration (IOCON) Table 52. A A A A A NXP Semiconductors D D 5 6 Pull-down resistor enabled. 0x2 Pull-up resistor enabled. 0x3 Repeater mode. Hysteresis. 0 Disable. 1 Enable. INV 9:7 - 10 OD Inactive (no pull-down/pull-up resistor enabled). 0x1 HYS A 0x0 0 Invert input 0 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). - Reserved. 0b001 Open-drain mode. 0 0 Disable. 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. 12:11 15:13 31:16 UM10601 Preliminary user manual S_MODE Digital filter sample mode. Bypass input filter. 0x1 1 clock cycle. Input pulses shorter than one filter clock are rejected. 0x2 2 clock cycles. Input pulses shorter than two filter clocks are rejected. 0x3 3 clock cycles. Input pulses shorter than three filter clocks are rejected. CLK_DIV - 0 0x0 Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 0x0 IOCONCLKDIV0. 0x1 IOCONCLKDIV1. 0x2 IOCONCLKDIV2. 0x3 IOCONCLKDIV3. 0x4 IOCONCLKDIV4. 0x5 IOCONCLKDIV5. 0x6 IOCONCLKDIV6. - Reserved. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 R 0b10 D 0 Selects function mode (on-chip pull-up/pull-down resistor control). FT Reserved. MODE A - 4:3 R 2:0 0 0 © NXP B.V. 2012. All rights reserved. 61 of 313 D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R R Reset value - Reserved. 0 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 0b10 FT Description FT A A R D D 4:3 F D D 2:0 Value A FT FT A A R R D D D Symbol FT FT FT FT PIO0_4 register (PIO0_4, address 0x4004 4010) bit description Bit A A A A R R D D D 6.5.5 PIO0_4 register FT FT FT FT FT UM10601 Chapter 6: LPC800 I/O configuration (IOCON) Table 53. A A A A A NXP Semiconductors Repeater mode. HYS Hysteresis. 0 Disable. 1 Enable. INV 9:7 - 10 OD A 0x3 0 Invert input 0 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). - Reserved. 0b001 Open-drain mode. 0 0 Disable. 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. 12:11 15:13 31:16 UM10601 Preliminary user manual S_MODE Digital filter sample mode. Bypass input filter. 0x1 1 clock cycle. Input pulses shorter than one filter clock are rejected. 0x2 2 clock cycles. Input pulses shorter than two filter clocks are rejected. 0x3 3 clock cycles. Input pulses shorter than three filter clocks are rejected. CLK_DIV - 0 0x0 Select peripheral clock divider for input filter sampling clock. 0 Value 0x7 is reserved. 0x0 IOCONCLKDIV0. 0x1 IOCONCLKDIV1. 0x2 IOCONCLKDIV2. 0x3 IOCONCLKDIV3. 0x4 IOCONCLKDIV4. 0x5 IOCONCLKDIV5. 0x6 IOCONCLKDIV6. - Reserved. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 R Pull-up resistor enabled. D Pull-down resistor enabled. 0x2 FT 0x1 A 6 Inactive (no pull-down/pull-up resistor enabled). R 5 0x0 0 © NXP B.V. 2012. All rights reserved. 62 of 313 D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R F D A A R R D Reset value FT Description FT Value A FT FT A A R R D D D PIO0_3 register (PIO0_3, address 0x4004 4014) bit description Symbol FT FT FT FT Bit A A A A R R D D D 6.5.6 PIO0_3 register FT FT FT FT FT UM10601 Chapter 6: LPC800 I/O configuration (IOCON) Table 54. A A A A A NXP Semiconductors D D 5 6 Pull-down resistor enabled. 0x2 Pull-up resistor enabled. 0x3 Repeater mode. Hysteresis. 0 Disable. 1 Enable. INV 9:7 - 10 OD Inactive (no pull-down/pull-up resistor enabled). 0x1 HYS A 0x0 0 Invert input. 0 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). - Reserved. 0b001 Open-drain mode. 0 0 Disable. 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. 12:11 15:13 31:16 UM10601 Preliminary user manual S_MODE Digital filter sample mode. Bypass input filter. 0x1 1 clock cycle. Input pulses shorter than one filter clock are rejected. 0x2 2 clock cycles. Input pulses shorter than two filter clocks are rejected. 0x3 3 clock cycles. Input pulses shorter than three filter clocks are rejected. CLK_DIV - 0 0x0 Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 0x0 IOCONCLKDIV0. 0x1 IOCONCLKDIV1. 0x2 IOCONCLKDIV2. 0x3 IOCONCLKDIV3. 0x4 IOCONCLKDIV4. 0x5 IOCONCLKDIV5. 0x6 IOCONCLKDIV6. - Reserved. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 R 0b10 D 0 Selects function mode (on-chip pull-up/pull-down resistor control). FT Reserved. MODE A - 4:3 R 2:0 0 0 © NXP B.V. 2012. All rights reserved. 63 of 313 D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R F D Reset value FT Description FT A A R R D Value A FT FT A A R R D D D PIO0_2 register (PIO0_2, address 0x4004 4018) bit description Symbol FT FT FT FT Bit A A A A R R D D D 6.5.7 PIO0_2 register FT FT FT FT FT UM10601 Chapter 6: LPC800 I/O configuration (IOCON) Table 55. A A A A A NXP Semiconductors D D 5 6 Pull-down resistor enabled. 0x2 Pull-up resistor enabled. 0x3 Repeater mode. Hysteresis. 0 Disable. 1 Enable. INV 9:7 - 10 OD Inactive (no pull-down/pull-up resistor enabled). 0x1 HYS A 0x0 0 Invert input. 0 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). - Reserved. 0b001 Open-drain mode. 0 0 Disable. 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. 12:11 15:13 31:16 UM10601 Preliminary user manual S_MODE Digital filter sample mode. Bypass input filter. 0x1 1 clock cycle. Input pulses shorter than one filter clock are rejected. 0x2 2 clock cycles. Input pulses shorter than two filter clocks are rejected. 0x3 3 clock cycles. Input pulses shorter than three filter clocks are rejected. CLK_DIV - 0 0x0 Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 0x0 IOCONCLKDIV0. 0x1 IOCONCLKDIV1. 0x2 IOCONCLKDIV2. 0x3 IOCONCLKDIV3. 0x4 IOCONCLKDIV4. 0x5 IOCONCLKDIV5. 0x6 IOCONCLKDIV6. - Reserved. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 R 0b10 D 0 Selects function mode (on-chip pull-up/pull-down resistor control). FT Reserved. MODE A - 4:3 R 2:0 0 0 © NXP B.V. 2012. All rights reserved. 64 of 313 D D D D D R R R R R D R R FT FT FT FT D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D A A R R D PIO0_11 register (PIO0_11, address 0x4004 401C) bit description Symbol Description Reset value 5:0 - Reserved. 0 6 INV Invert input 0 FT Bit FT Value A A A A R R D D D 6.5.8 PIO0_11 register FT FT FT FT FT UM10601 Chapter 6: LPC800 I/O configuration (IOCON) Table 56. A A A A A NXP Semiconductors D D A 1 Selects I2C mode. 00 Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000). 10 - 12:11 S_MODE 15:13 31:16 UM10601 Preliminary user manual Standard mode/ Fast-mode I2C. 0x1 Standard I/O functionality 0x2 Fast-mode Plus I2C 0x3 Reserved. - 0 Bypass input filter. 0x1 1 clock cycle. Input pulses shorter than one filter clock are rejected. 0x2 2 clock cycles. Input pulses shorter than two filter clocks are rejected. 0x3 3 clock cycles. Input pulses shorter than three filter clocks are rejected. CLK_DIV - Reserved. Digital filter sample mode. 0x0 Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 0x0 IOCONCLKDIV0. 0x1 IOCONCLKDIV1. 0x2 IOCONCLKDIV2. 0x3 IOCONCLKDIV3. 0x4 IOCONCLKDIV4. 0x5 IOCONCLKDIV5. 0x6 IOCONCLKDIV6. - Reserved. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 R Reserved. 0x0 D I2CMODE Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). FT 9:8 1 A - Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). R 7 0 0 - © NXP B.V. 2012. All rights reserved. 65 of 313 D D D D D R R R R R D R R FT FT FT FT D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D A A R R D PIO0_10 register (PIO0_10, address 0x4004 4020) bit description Symbol Description Reset value 5:0 - Reserved. 0 6 INV Invert input 0 FT Bit FT Value A A A A R R D D D 6.5.9 PIO0_10 register FT FT FT FT FT UM10601 Chapter 6: LPC800 I/O configuration (IOCON) Table 57. A A A A A NXP Semiconductors D D A 1 Selects I2C mode. 00 Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000). 10 - 12:11 S_MODE 15:13 31:16 UM10601 Preliminary user manual Standard mode/ Fast-mode I2C. 0x1 Standard I/O functionality 0x2 Fast-mode Plus I2C 0x3 Reserved. - 0 Bypass input filter. 0x1 1 clock cycle. Input pulses shorter than one filter clock are rejected. 0x2 2 clock cycles. Input pulses shorter than two filter clocks are rejected. 0x3 3 clock cycles. Input pulses shorter than three filter clocks are rejected. CLK_DIV - Reserved. Digital filter sample mode. 0x0 Select peripheral clock divider for input filter sampling clock. 0 Value 0x7 is reserved. 0x0 IOCONCLKDIV0. 0x1 IOCONCLKDIV1. 0x2 IOCONCLKDIV2. 0x3 IOCONCLKDIV3. 0x4 IOCONCLKDIV4. 0x5 IOCONCLKDIV5. 0x6 IOCONCLKDIV6. - Reserved. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 R Reserved. 0x0 D I2CMODE Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). FT 9:8 1 A - Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). R 7 0 - © NXP B.V. 2012. All rights reserved. 66 of 313 D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R F D Reset value FT Description FT A A R R D Value A FT FT A A R R D D D PIO0_16 register (PIO0_16, address 0x4004 4024) bit description Symbol FT FT FT FT Bit A A A A R R D D D 6.5.10 PIO0_16 register FT FT FT FT FT UM10601 Chapter 6: LPC800 I/O configuration (IOCON) Table 58. A A A A A NXP Semiconductors D D 5 6 Pull-down resistor enabled. 0x2 Pull-up resistor enabled. 0x3 Repeater mode. Hysteresis. 0 Disable. 1 Enable. INV 9:7 - 10 OD Inactive (no pull-down/pull-up resistor enabled). 0x1 HYS A 0x0 0 Invert input 0 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). - Reserved. 0b001 Open-drain mode. 0 0 Disable. 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. 12:11 15:13 31:16 UM10601 Preliminary user manual S_MODE Digital filter sample mode. Bypass input filter. 0x1 1 clock cycle. Input pulses shorter than one filter clock are rejected. 0x2 2 clock cycles. Input pulses shorter than two filter clocks are rejected. 0x3 3 clock cycles. Input pulses shorter than three filter clocks are rejected. CLK_DIV - 0 0x0 Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 0x0 IOCONCLKDIV0. 0x1 IOCONCLKDIV1. 0x2 IOCONCLKDIV2. 0x3 IOCONCLKDIV3. 0x4 IOCONCLKDIV4. 0x5 IOCONCLKDIV5. 0x6 IOCONCLKDIV6. - Reserved. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 R 0b10 D 0 Selects function mode (on-chip pull-up/pull-down resistor control). FT Reserved. MODE A - 4:3 R 2:0 0 0 © NXP B.V. 2012. All rights reserved. 67 of 313 D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R F D A A R R D Reset value FT Description FT Value A FT FT A A R R D D D PIO0_15 register (PIO0_15, address 0x4004 4028) bit description Symbol FT FT FT FT Bit A A A A R R D D D 6.5.11 PIO0_15 register FT FT FT FT FT UM10601 Chapter 6: LPC800 I/O configuration (IOCON) Table 59. A A A A A NXP Semiconductors D D 5 6 Pull-down resistor enabled. 0x2 Pull-up resistor enabled. 0x3 Repeater mode. Hysteresis. 0 Disable. 1 Enable. INV 9:7 - 10 OD Inactive (no pull-down/pull-up resistor enabled). 0x1 HYS A 0x0 0 Invert input 0 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). - Reserved. 0b001 Open-drain mode. 0 0 Disable. 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. 12:11 S_MODE Digital filter sample mode. Bypass input filter. 0x1 1 clock cycle. Input pulses shorter than one filter clock are rejected. 0x2 2 clock cycles. Input pulses shorter than two filter clocks are rejected. 0x3 3 clock cycles. Input pulses shorter than three filter clocks are rejected. 15:13 CLK_DIV 31:16 - UM10601 Preliminary user manual 0 0x0 Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 0x0 IOCONCLKDIV0. 0x1 IOCONCLKDIV1. 0x2 IOCONCLKDIV2. 0x3 IOCONCLKDIV3. 0x4 IOCONCLKDIV4. 0x5 IOCONCLKDIV5. 0x6 IOCONCLKDIV6. - Reserved. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 R 0b10 D 0 Selects function mode (on-chip pull-up/pull-down resistor control). FT Reserved. MODE A - 4:3 R 2:0 0 0 © NXP B.V. 2012. All rights reserved. 68 of 313 D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R F D Reset value FT Description FT A A R R D Value A FT FT A A R R D D D PIO0_1 register (PIO0_1, address 0x4004 402C) bit description Symbol FT FT FT FT Bit A A A A R R D D D 6.5.12 PIO0_1 register FT FT FT FT FT UM10601 Chapter 6: LPC800 I/O configuration (IOCON) Table 60. A A A A A NXP Semiconductors D D 5 6 Pull-down resistor enabled. 0x2 Pull-up resistor enabled. 0x3 Repeater mode. Hysteresis. 0 Disable. 1 Enable. INV 9:7 - 10 OD Inactive (no pull-down/pull-up resistor enabled). 0x1 HYS A 0x0 0 Invert input 0 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). - Reserved. 0b001 Open-drain mode. 0 0 Disable. 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. 12:11 15:13 31:16 UM10601 Preliminary user manual S_MODE Digital filter sample mode. Bypass input filter. 0x1 1 clock cycle. Input pulses shorter than one filter clock are rejected. 0x2 2 clock cycles. Input pulses shorter than two filter clocks are rejected. 0x3 3 clock cycles. Input pulses shorter than three filter clocks are rejected. CLK_DIV - 0 0x0 Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 0x0 IOCONCLKDIV0. 0x1 IOCONCLKDIV1. 0x2 IOCONCLKDIV2. 0x3 IOCONCLKDIV3. 0x4 IOCONCLKDIV4. 0x5 IOCONCLKDIV5. 0x6 IOCONCLKDIV6. - Reserved. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 R 0b10 D 0 Selects function mode (on-chip pull-up/pull-down resistor control). FT Reserved. MODE A - 4:3 R 2:0 0 0 © NXP B.V. 2012. All rights reserved. 69 of 313 D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R F D Reset value FT Description FT A A R R D Value A FT FT A A R R D D D PIO0_9 register (PIO0_9, address 0x4004 4034) bit description Symbol FT FT FT FT Bit A A A A R R D D D 6.5.13 PIO0_9 register FT FT FT FT FT UM10601 Chapter 6: LPC800 I/O configuration (IOCON) Table 61. A A A A A NXP Semiconductors D D 5 6 Pull-down resistor enabled. 0x2 Pull-up resistor enabled. 0x3 Repeater mode. Hysteresis. 0 Disable. 1 Enable. INV 9:7 - 10 OD Inactive (no pull-down/pull-up resistor enabled). 0x1 HYS A 0x0 0 Invert input 0 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). - Reserved. 001 Open-drain mode. 0 0 Disable. 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. 12:11 15:13 31:16 UM10601 Preliminary user manual S_MODE Digital filter sample mode. Bypass input filter. 0x1 1 clock cycle. Input pulses shorter than one filter clock are rejected. 0x2 2 clock cycles. Input pulses shorter than two filter clocks are rejected. 0x3 3 clock cycles. Input pulses shorter than three filter clocks are rejected. CLK_DIV - 0 0x0 Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 0x0 IOCONCLKDIV0. 0x1 IOCONCLKDIV1. 0x2 IOCONCLKDIV2. 0x3 IOCONCLKDIV3. 0x4 IOCONCLKDIV4. 0x5 IOCONCLKDIV5. 0x6 IOCONCLKDIV6. - Reserved. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 R 10 D 0 Selects function mode (on-chip pull-up/pull-down resistor control). FT Reserved. MODE A - 4:3 R 2:0 0 0 © NXP B.V. 2012. All rights reserved. 70 of 313 D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R F D Reset value FT Description FT A A R R D Value A FT FT A A R R D D D PIO0_8 register (PIO0_8, address 0x4004 4038) bit description Symbol FT FT FT FT Bit A A A A R R D D D 6.5.14 PIO0_8 register FT FT FT FT FT UM10601 Chapter 6: LPC800 I/O configuration (IOCON) Table 62. A A A A A NXP Semiconductors D D 5 6 Pull-down resistor enabled. 0x2 Pull-up resistor enabled. 0x3 Repeater mode. Hysteresis. 0 Disable. 1 Enable. INV 9:7 - 10 OD Inactive (no pull-down/pull-up resistor enabled). 0x1 HYS A 0x0 0 Invert input 0 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). - Reserved. 0b001 Open-drain mode. 0 0 Disable. 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. 12:11 15:13 31:16 UM10601 Preliminary user manual S_MODE Digital filter sample mode. Bypass input filter. 0x1 1 clock cycle. Input pulses shorter than one filter clock are rejected. 0x2 2 clock cycles. Input pulses shorter than two filter clocks are rejected. 0x3 3 clock cycles. Input pulses shorter than three filter clocks are rejected. CLK_DIV - 0 0x0 Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 0x0 IOCONCLKDIV0. 0x1 IOCONCLKDIV1. 0x2 IOCONCLKDIV2. 0x3 IOCONCLKDIV3. 0x4 IOCONCLKDIV4. 0x5 IOCONCLKDIV5. 0x6 IOCONCLKDIV6. - Reserved. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 R 0b10 D 0 Selects function mode (on-chip pull-up/pull-down resistor control). FT Reserved. MODE A - 4:3 R 2:0 0 0 © NXP B.V. 2012. All rights reserved. 71 of 313 D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R F D Reset value FT Description FT A A R R D Value A FT FT A A R R D D D PIO0_7 register (PIO0_7, address 0x4004 403C) bit description Symbol FT FT FT FT Bit A A A A R R D D D 6.5.15 PIO0_7 register FT FT FT FT FT UM10601 Chapter 6: LPC800 I/O configuration (IOCON) Table 63. A A A A A NXP Semiconductors D D 5 6 Pull-down resistor enabled. 0x2 Pull-up resistor enabled. 0x3 Repeater mode. Hysteresis. 0 Disable. 1 Enable. INV 9:7 - 10 OD Inactive (no pull-down/pull-up resistor enabled). 0x1 HYS A 0x0 0 Invert input 0 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). - Reserved. 0b001 Open-drain mode. 0 0 Disable. 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. 12:11 15:13 31:16 UM10601 Preliminary user manual S_MODE Digital filter sample mode. Bypass input filter. 0x1 1 clock cycle. Input pulses shorter than one filter clock are rejected. 0x2 2 clock cycles. Input pulses shorter than two filter clocks are rejected. 0x3 3 clock cycles. Input pulses shorter than three filter clocks are rejected. CLK_DIV - 0 0x0 Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 0x0 IOCONCLKDIV0. 0x1 IOCONCLKDIV1. 0x2 IOCONCLKDIV2. 0x3 IOCONCLKDIV3. 0x4 IOCONCLKDIV4. 0x5 IOCONCLKDIV5. 0x6 IOCONCLKDIV6. - Reserved. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 R 0b10 D 0 Selects function mode (on-chip pull-up/pull-down resistor control). FT Reserved. MODE A - 4:3 R 2:0 0 0 © NXP B.V. 2012. All rights reserved. 72 of 313 D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R F D Reset value FT Description FT A A R R D Value A FT FT A A R R D D D PIO0_6 register (PIO0_6, address 0x4004 4040) bit description Symbol FT FT FT FT Bit A A A A R R D D D 6.5.16 PIO0_6 register FT FT FT FT FT UM10601 Chapter 6: LPC800 I/O configuration (IOCON) Table 64. A A A A A NXP Semiconductors D D 5 6 Pull-down resistor enabled. 0x2 Pull-up resistor enabled. 0x3 Repeater mode. Hysteresis. 0 Disable. 1 Enable. INV 9:7 - 10 OD Inactive (no pull-down/pull-up resistor enabled). 0x1 HYS A 0x0 0 Invert input 0 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). - Reserved. 001 Open-drain mode. 0 0 Disable. 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. 12:11 15:13 31:16 UM10601 Preliminary user manual S_MODE Digital filter sample mode. Bypass input filter. 0x1 1 clock cycle. Input pulses shorter than one filter clock are rejected. 0x2 2 clock cycles. Input pulses shorter than two filter clocks are rejected. 0x3 3 clock cycles. Input pulses shorter than three filter clocks are rejected. CLK_DIV - 0 0x0 Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 0x0 IOCONCLKDIV0. 0x1 IOCONCLKDIV1. 0x2 IOCONCLKDIV2. 0x3 IOCONCLKDIV3. 0x4 IOCONCLKDIV4. 0x5 IOCONCLKDIV5. 0x6 IOCONCLKDIV6. - Reserved. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 R 10 D 0 Selects function mode (on-chip pull-up/pull-down resistor control). FT Reserved. MODE A - 4:3 R 2:0 0 0 © NXP B.V. 2012. All rights reserved. 73 of 313 D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R F D Reset value FT Description FT A A R R D Value A FT FT A A R R D D D PIO0_0 register (PIO0_0, address 0x4004 4044) bit description Symbol FT FT FT FT Bit A A A A R R D D D 6.5.17 PIO0_0 register FT FT FT FT FT UM10601 Chapter 6: LPC800 I/O configuration (IOCON) Table 65. A A A A A NXP Semiconductors D D 5 6 Pull-down resistor enabled. 0x2 Pull-up resistor enabled. 0x3 Repeater mode. Hysteresis. 0 Disable. 1 Enable. INV 9:7 - 10 OD Inactive (no pull-down/pull-up resistor enabled). 0x1 HYS A 0x0 0 Invert input 0 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). - Reserved. 0b001 Open-drain mode. 0 0 Disable. 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. 12:11 15:13 31:16 UM10601 Preliminary user manual S_MODE Digital filter sample mode. Bypass input filter. 0x1 1 clock cycle. Input pulses shorter than one filter clock are rejected. 0x2 2 clock cycles. Input pulses shorter than two filter clocks are rejected. 0x3 3 clock cycles. Input pulses shorter than three filter clocks are rejected. CLK_DIV - 0 0x0 Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 0x0 IOCONCLKDIV0. 0x1 IOCONCLKDIV1. 0x2 IOCONCLKDIV2. 0x3 IOCONCLKDIV3. 0x4 IOCONCLKDIV4. 0x5 IOCONCLKDIV5. 0x6 IOCONCLKDIV6. - Reserved. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 R 0b10 D 0 Selects function mode (on-chip pull-up/pull-down resistor control). FT Reserved. MODE A - 4:3 R 2:0 0 0 © NXP B.V. 2012. All rights reserved. 74 of 313 D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R F D Reset value FT Description FT A A R R D Value A FT FT A A R R D D D PIO0_14 register (PIO0_14, address 0x4004 4048) bit description Symbol FT FT FT FT Bit A A A A R R D D D 6.5.18 PIO0_14 register FT FT FT FT FT UM10601 Chapter 6: LPC800 I/O configuration (IOCON) Table 66. A A A A A NXP Semiconductors D D 5 6 Pull-down resistor enabled. 0x2 Pull-up resistor enabled. 0x3 Repeater mode. Hysteresis. 0 Disable. 1 Enable. INV 9:7 - 10 OD Inactive (no pull-down/pull-up resistor enabled). 0x1 HYS A 0x0 0 Invert input 0 0 Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). 1 Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). - Reserved. 0b001 Open-drain mode. 0 0 Disable. 1 Open-drain mode enabled. Remark: This is not a true open-drain mode. 12:11 15:13 31:16 UM10601 Preliminary user manual S_MODE Digital filter sample mode. Bypass input filter. 0x1 1 clock cycle. Input pulses shorter than one filter clock are rejected. 0x2 2 clock cycles. Input pulses shorter than two filter clocks are rejected. 0x3 3 clock cycles. Input pulses shorter than three filter clocks are rejected. CLK_DIV - 0 0x0 Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 0x0 IOCONCLKDIV0. 0x1 IOCONCLKDIV1. 0x2 IOCONCLKDIV2. 0x3 IOCONCLKDIV3. 0x4 IOCONCLKDIV4. 0x5 IOCONCLKDIV5. 0x6 IOCONCLKDIV6. - Reserved. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 R 0b10 D 0 Selects function mode (on-chip pull-up/pull-down resistor control). FT Reserved. MODE A - 4:3 R 2:0 0 0 © NXP B.V. 2012. All rights reserved. 75 of 313 A A A A A FT FT FT FT FT D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D Preliminary user manual D Rev. 1.0 — 7 November 2012 R R R R R Chapter 7: LPC800 GPIO port D D D D D UM10601 D FT FT A A R R D D D 7.1 How to read this chapter R A GPIO Port 0 TSSOP16 PIO0_0 to PIO0_13 TSSOP20 PIO0_0 to PIO0_17 SOP20 PIO0_0 to PIO0_17 DIP8 PIO0_0 to PIO0_5 7.2 Features • GPIO port registers are located on the ARM Cortex M0+ I/O port for fast access. • The ARM Cortex M0+ I/O port supports single-cycle access. • GPIO ports – GPIO pins can be configured as input or output by software. – All GPIO pins default to inputs with interrupt disabled at reset. – Pin interrupt registers allow pins to be sensed and set individually. 7.3 Basic configuration For the GPIO port registers, enable the clock to the GPIO port registers in the SYSAHBCLKCTRL register (Table 18, bit 6). 7.4 Pin description All GPIO functions are fixed-pin functions. The switch matrix assigns every GPIO port pin to one and only one pin on the LPC800 package. By default, the switch matrix connects all package pins except supply and ground pins to their GPIO port pins. The pin description table (see the LPC81xM data sheet) shows how the GPIO port pins are assigned to LPC800 package pins. 7.5 General description The GPIO port registers can be used to configure each GPIO pin as input or output and read the state of each pin if the pin is configured as input or set the state of each pin if the pin is configured as output. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 76 of 313 A Package R GPIO pins available D Table 67. FT All GPIO registers refer to 32 pins per port. Depending on the package type, not all pins are available, and the corresponding bits in the GPIO registers are reserved (see Table 67). D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D Chapter 7: LPC800 GPIO port D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D 7.6 Register description FT FT FT UM10601 FT FT NXP Semiconductors D FT FT A A R R D The GPIO port registers and the GPIO pin interrupt registers are located on the ARM M0+ I/O port. The I/O port supports single-cycle access. D D R A Remark: In all GPIO registers, bits that are not shown are reserved. FT D R GPIO port addresses can be read and written as bytes, halfwords, or words. A “ext” indicates that the data read after reset depends on the state of the pin, which in turn may depend on an external source. Table 68. Register overview: GPIO port (base address 0xA000 0000) Name Access Address offset Description Reset value Width Reference B0 to B17 R/W 0x0000 to 0x0012 Byte pin registers port 0; pins PIO0_0 to PIO0_17 ext byte (8 bit) Table 69 W0 to W17 R/W 0x1000 to 0x1048 Word pin registers port 0 ext word (32 bit) Table 70 DIR0 R/W 0x2000 Direction registers port 0 0 word (32 bit) Table 71 MASK0 R/W 0x2080 Mask register port 0 0 word (32 bit) Table 72 PIN0 R/W 0x2100 Port pin register port 0 ext word (32 bit) Table 73 MPIN0 R/W 0x2180 Masked port register port 0 ext word (32 bit) Table 74 SET0 R/W 0x2200 Write: Set register for port 0 Read: output bits for port 0 0 word (32 bit) Table 75 CLR0 WO 0x2280 Clear port 0 NA word (32 bit) Table 76 NOT0 WO 0x2300 Toggle port 0 NA word (32 bit) Table 77 7.6.1 GPIO port byte pin registers Each GPIO pin has a byte register in this address range. Software typically reads and writes bytes to access individual pins, but can read or write halfwords to sense or set the state of two pins, and read or write words to sense or set the state of four pins. Table 69. GPIO port 0 byte pin registers (B[0:17], addresses 0xA000 0000 (B0) to 0xA000 0012 (B17)) bit description Bit Symbol Description 0 PBYTE 7:1 Reset Access value Read: state of the pin PIO0_n, regardless of direction, ext masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin’s output bit. R/W Reserved (0 on read, ignored on write) - 0 7.6.2 GPIO port word pin registers Each GPIO pin has a word register in this address range. Any byte, halfword, or word read in this range will be all zeros if the pin is low or all ones if the pin is high, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as zeros. Any write will clear the pin’s output bit if the value written is all zeros, else it will set the pin’s output bit. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 77 of 313 D D D D D R R R R R FT FT FT FT FT UM10601 D R R FT FT FT FT A A A A R R D D D Chapter 7: LPC800 GPIO port D R R A FT FT FT A A R R D D D D D D A Reset Access value 31:0 PWORD Read 0: pin is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. ext R Description FT FT A A R Symbol D D Bit F FT FT A A R R GPIO port 0 word pin registers (W[0:17], addresses 0xA000 1000 (W0) to 0x5000 1048 (W17)) bit description R Table 70. A A A A A NXP Semiconductors D D R R/W A FT D R A Remark: Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. 7.6.3 GPIO port direction registers Each GPIO port has one direction register for configuring the port pins as inputs or outputs. Table 71. GPIO direction port 0 register (DIR0, address 0xA000 2000) bit description Bit Symbol Description Reset Access value 17:0 DIRP0 Selects pin direction for pin PIO0_n (bit 0 = PIO0_0, bit 1 = PIO0_1, ..., bit 17 = PIO0_17). 0 = input. 1 = output. 0 R/W Reserved. 0 - 31:18 - 7.6.4 GPIO port mask registers These registers affect writing and reading the MPORT registers. Zeroes in these registers enable reading and writing; ones disable writing and result in zeros in corresponding positions when reading. Table 72. GPIO mask port 0 register (MASK0, address 0xA000 2080) bit description Bit Symbol Description 17:0 MASKP0 Controls which bits corresponding to PIO0_n are active in the 0 P0MPORT register (bit 0 = PIO0_0, bit 1 = PIO0_1, ..., bit 17 = PIO0_17). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. R/W 31:18 - - Reserved. Reset Access value 0 7.6.5 GPIO port pin registers Reading these registers returns the current state of the pins read, regardless of direction, masking, or alternate functions, except that pins configured as analog I/O always read as 0s. Writing these registers loads the output bits of the pins written to, regardless of the Mask register. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 78 of 313 D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R R/W 31:18 - Reserved. 0 - FT FT A A R D D R A FT D R A GPIO masked port 0 pin register (MPIN0, address 0xA000 2180) bit description Bit Symbol Description 17:0 MPORTP0 Masked port register (bit 0 = PIO0_0, bit 1 = PIO0_1, ..., bit ext 17 = PIO0_17). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. R/W 31:18 - Reserved. - Reset Access value 0 7.6.7 GPIO port set registers Output bits can be set by writing ones to these registers, regardless of MASK registers. Reading from these register returns the port’s output bits, regardless of pin directions. GPIO set port 0 register (SET0, address 0xA000 2200) bit description Bit Symbol Description Reset value Access 17:0 SETP0 Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. 0 R/W 31:18 - Reserved. 0 - 7.6.8 GPIO port clear registers Output bits can be cleared by writing ones to these write-only registers, regardless of MASK registers. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 F ext R Reads pin states or loads output bits (bit 0 = PIO0_0, bit 1 = PIO0_1, ..., bit 17 = PIO0_17). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. D PORT0 D 17:0 These registers are similar to the PIN registers, except that the value read is masked by ANDing with the inverted contents of the corresponding MASK register, and writing to one of these registers only affects output register bits that are enabled by zeros in the corresponding MASK register Preliminary user manual A FT FT A A R R D D D Reset Access value 7.6.6 GPIO masked port pin registers UM10601 FT FT FT FT Symbol Description Table 75. A A A A R R D D D GPIO port 0 pin register (PIN0, address 0xA000 2100) bit description Bit Table 74. FT FT FT FT FT UM10601 Chapter 7: LPC800 GPIO port Table 73. A A A A A NXP Semiconductors © NXP B.V. 2012. All rights reserved. 79 of 313 D D D D D R R R R R FT FT FT FT FT UM10601 D R R FT FT FT FT A A A A R R D D D Chapter 7: LPC800 GPIO port D R R A FT FT FT A A R R D D D R A Reset Access value 17:0 CLRP0 Clear output bits: 0 = No operation. 1 = Clear output bit. NA WO 31:18 - Reserved. 0 - FT FT A A R R Description D Symbol D Bit F FT FT A A R R GPIO clear port 0 register (CLR0, address 0xA000 2280) bit description D D D Table 76. A A A A A NXP Semiconductors D D R A FT D R A 7.6.9 GPIO port toggle registers Output bits can be toggled/inverted/complemented by writing ones to these write-only registers, regardless of MASK registers. Table 77. GPIO toggle port 0 register (NOT0, address 0xA000 2300) bit description Bit Symbol Description Reset Access value 17:0 NOTP0 Toggle output bits: 0 = no operation. 1 = Toggle output bit. NA WO 31:18 - Reserved. 0 - 7.7 Functional description 7.7.1 Reading pin state Software can read the state of all GPIO pins except those selected for analog input or output in the “I/O Configuration” logic. A pin does not have to be selected for GPIO in “I/O Configuration” in order to read its state. There are several ways to read the pin state: • The state of a single pin can be read with 7 high-order zeros from a Byte Pin register. • The state of a single pin can be read in all bits of a byte, halfword, or word from a Word Pin register. • The state of multiple pins in a port can be read as a byte, halfword, or word from a PORT register. • The state of a selected subset of the pins in a port can be read from a Masked Port (MPORT) register. Pins having a 1 in the port’s Mask register will read as 0 from its MPORT register. 7.7.2 GPIO output Each GPIO pin has an output bit in the GPIO block. These output bits are the targets of write operations “to the pins”. Two conditions must be met in order for a pin’s output bit to be driven onto the pin: 1. The pin must be selected for GPIO operation in the switch matrix. 2. The pin must be selected for output by a 1 in its port’s DIR register. If either or both of these conditions is (are) not met, writing to the pin has no effect. There are multiple ways to change GPIO output bits: UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 80 of 313 D D D D D R R R R R A A A A A FT FT FT UM10601 FT FT D R R FT FT FT FT Chapter 7: LPC800 GPIO port A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R A D FT FT A A R R D (This feature follows the definition of “truth” of a multi-bit value in programming languages.) F FT FT A A R R D D • Writing to a Byte Pin register loads the output bit from the least significant bit. • Writing to a Word Pin register loads the output bit with the OR of all of the bits written. D D R • Writing to a port’s PORT register loads the output bits of all the pins written to. • Writing to a port’s MPORT register loads the output bits of pins identified by zeros in A A 7.7.3 Masked I/O A port’s MASK register defines which of its pins should be accessible in its MPORT register. Zeroes in MASK enable the corresponding pins to be read from and written to MPORT. Ones in MASK force a pin to read as 0 and its output bit to be unaffected by writes to MPORT. When a port’s MASK register contains all zeros, its PORT and MPORT registers operate identically for reading and writing. Applications in which interrupts can result in Masked GPIO operation, or in task switching among tasks that do Masked GPIO operation, must treat code that uses the Mask register as a protected/restricted region. This can be done by interrupt disabling or by using a semaphore. The simpler way to protect a block of code that uses a MASK register is to disable interrupts before setting the MASK register, and re-enable them after the last operation that uses the MPORT or MASK register. More efficiently, software can dedicate a semaphore to the MASK registers, and set/capture the semaphore controlling exclusive use of the MASK registers before setting the MASK registers, and release the semaphore after the last operation that uses the MPORT or MASK registers. 7.7.4 Recommended practices The following lists some recommended uses for using the GPIO port registers: For initial setup after Reset or re-initialization, write the PORT registers. To change the state of one pin, write a Byte Pin or Word Pin register. To change the state of multiple pins at a time, write the SET and/or CLR registers. To change the state of multiple pins in a tightly controlled environment like a software state machine, consider using the NOT register. This can require less write operations than SET and CLR. • To read the state of one pin, read a Byte Pin or Word Pin register. • To make a decision based on multiple pins, read and mask a PORT register. Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 R The state of a port’s output bits can be read from its SET register. Reading any of the registers described in Section 7.7.1 returns the state of pins, regardless of their direction or alternate functions. UM10601 D • Writing ones to a port’s SET register sets output bits. • Writing ones to a port’s CLR register clears output bits. • Writing ones to a port’s NOT register toggles/complements/inverts output bits. • • • • FT corresponding positions of the port’s MASK register. © NXP B.V. 2012. All rights reserved. 81 of 313 D D D D D R R R R R FT FT FT FT FT D R R A A FT FT FT FT A A R R D D D R R A FT FT FT A A R R D D D D Chapter 8: LPC800 Pin interrupts/pattern match engine R A F FT FT A A R R D D Preliminary user manual D Rev. 1.0 — 7 November 2012 A A A A A UM10601 D FT FT A A R R D D D 8.1 How to read this chapter R A – Edge-sensitive interrupt pins can interrupt on rising or falling edges or both. – Level-sensitive interrupt pins can be HIGH- or LOW-active. • Pattern match engine – Up to 8 pins can be selected from all GPIO pins to contribute to a boolean expression. The boolean expression consists of specified levels and/or transitions on various combinations of these pins. – Each bit slice minterm (product term) comprising the specified boolean expression can generate its own, dedicated interrupt request. – Any occurrence of a pattern match can be programmed to also generate an RXEV notification to the ARM CPU. The RXEV signal can be connected to a pin. – Feature can be used, in conjunction with software, to create complex state machines based on pin inputs. 8.3 Basic configuration • Pin interrupts: – Select up to eight external interrupt pins from all GPIO port pins in the SYSCON block (Table 32). The pin selection process is the same for pin interrupts and the pattern match engine. The two features are mutually exclusive. – Enable the clock to the pin interrupt register block in the SYSAHBCLKCTRL register (Table 18, bit 6). – If you want to use the pin interrupts to wake up the part from deep-sleep mode or power-down mode, enable the pin interrupt wake-up feature in the STARTERP0 register (Table 33). – Each selected pin interrupt is assigned to one interrupt in the NVIC (interrupts #24 to #31 for pin interrupts 0 to 7). • Pattern match engine: – Select up to eight external pins from all GPIO port pins in the SYSCON block (Table 32). The pin selection process is the same for pin interrupts and the pattern match engine. The two features are mutually exclusive. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 82 of 313 A – Up to eight pins can be selected from all GPIO pins as edge- or level-sensitive interrupt requests. Each request creates a separate interrupt in the NVIC. R • Pin interrupts D 8.2 Features FT The pin interrupt generator and the pattern match engine are available on all LPC800 parts. D D D D D R R R R R A A A A A FT FT FT UM10601 FT FT D R R FT FT FT FT Chapter 8: LPC800 Pin interrupts/pattern match engine A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R A D FT FT A A R R D – Each bit slice of the pattern match engine is assigned to one interrupt in the NVIC (interrupts #24 to #31 for slices 0 to 7). F FT FT A A R R D D – Enable the clock to the pin interrupt register block in the SYSAHBCLKCTRL register (Table 18, bit 6). D D R – The combined interrupt from all slices or slice combinations can be connected to the ARM RXEV request and to pin function GPIO_INT_BMAT through the switch matrix movable function register (PINASSIGN8, Table 104). A Remark: The port pin number serves to identify the pin to the PINTSEL register. Any function, including GPIO, can be assigned to this pin through the switch matrix. 3. Enable each pin interrupt in the NVIC. Once the pin interrupts or pattern match inputs are configured, you can set up the pin interrupt detection levels or the pattern match boolean expression. See Section 4.6.27 “Pin interrupt select registers” in the SYSCON block for the PINTSEL registers. 8.4 Pin description The inputs to the pin interrupt and pattern match engine are determined by the pin interrupt select registers in the SYSCON block. See Section 8.3.1. The pattern match engine output is assigned to an external pin through the switch matrix. See Section 9.3.1 “Connect an internal signal to a package pin” for the steps that you need to follow to assign the GPIO pattern match function to a pin on the LPC800 package. Table 78. SCT pin description Function Direction Pin Description SWM register Reference GPIO_INT_BMAT O GPIO pattern match output PINASSIGN8 Table 104 any 8.5 General description Pins with configurable functions can serve as external interrupts or inputs to the pattern match engine. You can configure up to eight pins total using the PINTSEL registers in the SYSCON block for these features. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 83 of 313 A 2. For each pin interrupt, program the GPIO port pin number into one of the eight PINTSEL registers in the SYSCON block. R 1. Determine the pins that serve as pin interrupts on the LPC800 package. See the data sheet for determining the GPIO port pin number associated with the package pin. D Follow these steps to configure pins as pin interrupts: FT 8.3.1 Configure pins as pin interrupts or as inputs to the pattern match engine D D D D D R R R R R FT FT FT FT FT UM10601 D R R FT FT FT FT A A A A R R D D D Chapter 8: LPC800 Pin interrupts/pattern match engine D R R A FT FT FT A A R R D D D R A FT FT A A R R D D From all available GPIO pins, up to eight pins can be selected in the system control block to serve as external interrupt pins (see Table 32). The external interrupt pins are connected to eight individual interrupts in the NVIC and are created based on rising or falling edges or on the input level on the pin. F FT FT A A R R D D D 8.5.1 Pin interrupts A A A A A NXP Semiconductors D D R A FT D R A 8.5.2 Pattern match engine The pattern match feature allows complex boolean expressions to be constructed from the same set of eight GPIO pins that were selected for the GPIO pin interrupts. The pattern match logic continuously monitors these eight inputs and generates interrupts when any one or more minterms (product terms) of the specified boolean expression is matched. A separate interrupt request is generated for each individual minterm. In addition, the pattern match module can be enabled to generate a Receive Event (RXEV) output to the ARM core when the entire boolean expression is true (i.e. when any minterm is matched). The RXEV output is also be routed to GPIO_INT_BMAT pin. This allows the GPIO module to provide a rudimentary programmable logic capability employing up to eight inputs and one output. The pattern match function utilizes the same eight interrupt request lines as the pin interrupts so these two features are mutually exclusive as far as interrupt generation is concerned. A control bit is provided to select whether interrupt requests are generated in response to the standard pin interrupts or to pattern matches. Note that, if the pin interrupts are selected, the RXEV request to the CPU can still be enabled for pattern matches. Remark: Pattern matching cannot be used to wake the part up from power-down modes. Pin interrupts must be selected in order to use the GPIO for wake-up. The pattern match module is constructed of eight bit-slice elements. Each bit slice is programmed to represent one component of one minterm (product term) within the boolean expression. The interrupt request associated with the last bit slice for a particular minterm will be asserted whenever that minterm is matched. (See bit slice drawing Figure 6). The pattern match capability can be used to create complex software state machines. Each minterm (and its corresponding individual interrupt) represents a different transition event to a new state. Software can then establish the new set of conditions (i.e new boolean expression) that will cause a transition out of the current state. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 84 of 313 D D D D D R R R R R D R R FT FT FT FT A A A A R R D D D D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT D R 30&)* 3URGB(QGSWVL A 3DWWHUQB0DWFKL ,QWUB5HTL D FT 3065& 65&L A )DOO 'HWHFW )URP 3UHYLRXV 6OLFH R VWLFN\ ZLWK V\QFK FOHDU D 5LVH 'HWHFW FT A A R R D 08; VWLFN\ ZLWK V\QFK FOHDU 08; 5LVH 'HWHFW QRQVWLFN\ )DOO 'HWHFW QRQVWLFN\ 7R 1H[W 6OLFH 30&)* &)*L Fig 6. FT FT FT FT FT UM10601 Chapter 8: LPC800 Pin interrupts/pattern match engine ,1 ,1 ,1 ,1 ,1 ,1 ,1 ,1 A A A A A NXP Semiconductors Pattern match bit slice 8.5.2.1 Example Assume the expression: (IN0)~(IN1)(IN3)^ + (IN1)(IN2) + (IN0)~(IN3)~(IN4) is specified through the registers PMSRC (Table 91) and PMCFG (Table 92). Each term in the boolean expression, (IN0), ~(IN1), (IN3)^, etc., represents one bit slice of the pattern match engine. • In the first term (IN0)~(IN1)(IN3)^, bit slice 0 monitors for a high-level on input (IN0), bit slice 1 monitors for a low level on input (IN1) and bit slice 2 monitors for a rising-edge on input (IN3). If this combination is detected, that is if all three terms are true, the interrupt associated with bit slice 2 will be asserted. • In the second term (IN1)(IN2), bit slice 3 monitors input (IN1) for a high level, bit slice 4 monitors input (IN2) for a high level. If this combination is detected, the interrupt associated with bit slice 4 will be asserted. • In the third term (IN0)~(IN3)~(IN4), bit slice 5 monitors input (IN0) for a high level, bit slice 6 monitors input (IN3) for a low level, and bit slice 7 monitors input (IN4) for a low level. If this combination is detected, the interrupt associated with bit slice 7 will be asserted. • The ORed result of all three terms asserts the RXEV request to the CPU and the GPIO_INT_BMAT output. That is, if any of the three terms are true, the output is asserted. Related links: Section 8.7.2 UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 85 of 313 D D D D D R R R R R D R R FT FT FT FT A A A A R R D D D D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D 8.6 Register description FT FT FT FT FT UM10601 Chapter 8: LPC800 Pin interrupts/pattern match engine D D R Register overview: Pin interrupts/pattern match engine (base address: 0xA000 4000) FT FT A A R Table 79. A A A A A NXP Semiconductors D D Access Address Description offset Reset Reference value ISEL R/W 0x000 Pin Interrupt Mode register 0 Table 80 IENR R/W 0x004 Pin interrupt level or rising edge interrupt enable register 0 Table 81 SIENR WO 0x008 Pin interrupt level or rising edge interrupt set register NA Table 82 CIENR WO 0x00C Pin interrupt level (rising edge interrupt) clear register NA Table 83 IENF R/W 0x010 Pin interrupt active level or falling edge interrupt enable register 0 Table 84 SIENF WO 0x014 Pin interrupt active level or falling edge interrupt set register NA Table 85 CIENF WO 0x018 Pin interrupt active level or falling edge interrupt clear register NA Table 86 RISE R/W 0x01C Pin interrupt rising edge register 0 Table 87 FALL R/W 0x020 Pin interrupt falling edge register 0 Table 88 IST R/W 0x024 Pin interrupt status register 0 Table 89 PMCTRL R/W 0x028 Pattern match interrupt control register 0 Table 90 PMSRC R/W 0x02C Pattern match interrupt bit-slice source register 0 Table 91 PMCFG R/W 0x030 Pattern match interrupt bit slice configuration register 0 Table 92 R Name A Symbol Description Reset Access value 7:0 PMODE Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive 0 R/W 31:8 - - - Reserved. 8.6.2 Pin interrupt level or rising edge interrupt enable register For each of the 8 pin interrupts selected in the PINTSELn registers (see Section 4.6.27), one bit in the IENR register enables the interrupt depending on the pin interrupt mode configured in the ISEL register: • If the pin interrupt mode is edge sensitive (PMODE = 0), the rising edge interrupt is enabled. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 86 of 313 A Pin interrupt mode register (ISEL, address 0xA000 4000) bit description Bit R Table 80. D For each of the 8 pin interrupts selected in the PINTSELn registers (see Section 4.6.27), one bit in the ISEL register determines whether the interrupt is edge or level sensitive. FT 8.6.1 Pin interrupt mode register D D D D D R R R R R A A A A A FT FT FT UM10601 FT FT D R R FT FT FT FT Chapter 8: LPC800 Pin interrupts/pattern match engine A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D R A F FT FT A A The IENF register configures the active level (HIGH or LOW) for this interrupt. D FT FT A A R Pin interrupt level or rising edge interrupt enable register (IENR, address 0xA000 4004) bit description R D Table 81. D R R D D • If the pin interrupt mode is level sensitive (PMODE = 1), the level interrupt is enabled. D D Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt. 0 R/W 31:8 - Reserved. - - 8.6.3 Pin interrupt level or rising edge interrupt set register For each of the 8 pin interrupts selected in the PINTSELn registers (see Section 4.6.27), one bit in the SIENR register sets the corresponding bit in the IENR register depending on the pin interrupt mode configured in the ISEL register: • If the pin interrupt mode is edge sensitive (PMODE = 0), the rising edge interrupt is set. • If the pin interrupt mode is level sensitive (PMODE = 1), the level interrupt is set. Table 82. Pin interrupt level or rising edge interrupt set register (SIENR, address 0xA000 4008) bit description Bit Symbol Description Reset Access value 7:0 SETENRL Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt. NA WO 31:8 - Reserved. - - 8.6.4 Pin interrupt level or rising edge interrupt clear register For each of the 8 pin interrupts selected in the PINTSELn registers (see Section 4.6.27), one bit in the CIENR register clears the corresponding bit in the IENR register depending on the pin interrupt mode configured in the ISEL register: • If the pin interrupt mode is edge sensitive (PMODE = 0), the rising edge interrupt is cleared. • If the pin interrupt mode is level sensitive (PMODE = 1), the level interrupt is cleared. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 87 of 313 A ENRL R 7:0 D Reset Access value FT Description A Symbol R Bit D D D D D R R R R R FT FT FT FT FT UM10601 D R R FT FT FT FT A A A A R R D D D Chapter 8: LPC800 Pin interrupts/pattern match engine D R R A FT FT FT A A R R D D D D D D A D Description Reset Access value 7:0 CENRL Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt. NA WO 31:8 - Reserved. - - FT FT A A R Symbol R D Bit F FT FT A A R R Pin interrupt level or rising edge interrupt clear register (CIENR, address 0xA000 400C) bit description R Table 83. A A A A A NXP Semiconductors D D R A FT D R A 8.6.5 Pin interrupt active level or falling edge interrupt enable register For each of the 8 pin interrupts selected in the PINTSELn registers (see Section 4.6.27), one bit in the IENF register enables the falling edge interrupt or the configures the level sensitivity depending on the pin interrupt mode configured in the ISEL register: • If the pin interrupt mode is edge sensitive (PMODE = 0), the falling edge interrupt is enabled. • If the pin interrupt mode is level sensitive (PMODE = 1), the active level of the level interrupt (HIGH or LOW) is configured. Table 84. Pin interrupt active level or falling edge interrupt enable register (IENF, address 0xA000 4010) bit description Bit Symbol Description Reset Access value 7:0 ENAF Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH. 0 R/W Reserved. - - 31:8 - 8.6.6 Pin interrupt active level or falling edge interrupt set register For each of the 8 pin interrupts selected in the PINTSELn registers (see Section 4.6.27), one bit in the SIENF register sets the corresponding bit in the IENF register depending on the pin interrupt mode configured in the ISEL register: • If the pin interrupt mode is edge sensitive (PMODE = 0), the falling edge interrupt is set. • If the pin interrupt mode is level sensitive (PMODE = 1), the HIGH-active interrupt is selected. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 88 of 313 D D D D D R R R R R D R R FT FT FT FT A A A A R R D D D D R R A FT FT FT A A R R D D D R 7:0 SETENAF Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt. NA WO 31:8 - - - R Reset Access value FT FT A A R Symbol F D D Bit A FT FT A A R R D D D Pin interrupt active level or falling edge interrupt set register (SIENF, address 0xA000 4014) bit description Description FT FT FT FT FT UM10601 Chapter 8: LPC800 Pin interrupts/pattern match engine Table 85. A A A A A NXP Semiconductors D D R A FT D R A Reserved. 8.6.7 Pin interrupt active level or falling edge interrupt clear register For each of the 8 pin interrupts selected in the PINTSELn registers (see Section 4.6.27), one bit in the CIENF register sets the corresponding bit in the IENF register depending on the pin interrupt mode configured in the ISEL register: • If the pin interrupt mode is edge sensitive (PMODE = 0), the falling edge interrupt is cleared. • If the pin interrupt mode is level sensitive (PMODE = 1), the LOW-active interrupt is selected. Table 86. Pin interrupt active level or falling edge interrupt clear register (CIENF, address 0xA000 4018) bit description Bit Symbol Description Reset Access value 7:0 CENAF Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled. NA WO 31:8 - Reserved. - - 8.6.8 Pin interrupt rising edge register This register contains ones for pin interrupts selected in the PINTSELn registers (see Section 4.6.27) on which a rising edge has been detected. Writing ones to this register clears rising edge detection. Ones in this register assert an interrupt request for pins that are enabled for rising-edge interrupts. All edges are detected for all pins selected by the PINTSELn registers, regardless of whether they are interrupt-enabled. Table 87. Bit Symbol Description Reset Access value 7:0 RDET Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin. 0 R/W Reserved. - - 31:8 UM10601 Preliminary user manual Pin interrupt rising edge register (RISE, address 0xA000 401C) bit description All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 89 of 313 D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D Chapter 8: LPC800 Pin interrupts/pattern match engine D R R A FT FT FT A A R R D D D R A FT FT A A R R D D This register contains ones for pin interrupts selected in the PINTSELn registers (see Section 4.6.27) on which a falling edge has been detected. Writing ones to this register clears falling edge detection. Ones in this register assert an interrupt request for pins that are enabled for falling-edge interrupts. All edges are detected for all pins selected by the PINTSELn registers, regardless of whether they are interrupt-enabled. F FT FT A A R R D D D 8.6.9 Pin interrupt falling edge register FT FT FT UM10601 FT FT NXP Semiconductors D D R A FT D R Pin interrupt falling edge register (FALL, address 0xA000 4020) bit description Bit Symbol Description Reset Access value 7:0 FDET Falling edge detect. Bit n detects the falling edge of the pin 0 selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin. R/W 31:8 - Reserved. - - 8.6.10 Pin interrupt status register Reading this register returns ones for pin interrupts that are currently requesting an interrupt. For pins identified as edge-sensitive in the Interrupt Select register, writing ones to this register clears both rising- and falling-edge detection for the pin. For level-sensitive pins, writing ones inverts the corresponding bit in the Active level register, thus switching the active level on the pin. Table 89. Pin interrupt status register (IST, address 0xA000 4024) bit description Bit Symbol Description Reset Access value 7:0 PSTAT Pin interrupt status. Bit n returns the status, clears the edge 0 interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the IENF register). R/W 31:8 - Reserved. - - 8.6.11 Pattern Match Interrupt Control Register The pattern match control register contains one bit to select pattern-match interrupt generation (as opposed to pin interrupts which share the same interrupt request lines), and another to enable the RXEV output to the cpu. This register also allows the current state of any pattern matches to be read. If the pattern match feature is not used (either for interrupt generation or for RXEV assertion) the two LSB’s of this register should be left at 0b00 to conserve power. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 90 of 313 A Table 88. D D D D D R R R R R A A A A A FT FT FT UM10601 FT FT D R R FT FT FT FT Chapter 8: LPC800 Pin interrupts/pattern match engine A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D Remark: Set up the pattern-match configuration in the PMSRC and PMCFG registers before writing to this register to enable (or re-enable) the pattern-match functionality. This eliminates the possibility of spurious interrupts as the feature is being enabled. D 1 Pattern match. Interrupts are driven in response to pattern matches. 31:24 PMAT Enables the RXEV output to the ARM cpu and/or to a GPIO output when the specified boolean expression evaluates to true. 0 Disabled. RXEV output to the cpu is disabled. 1 Enabled. RXEV output to the cpu is enabled. Reserved. Do not write 1s to unused bits. - 0 0 This field displays the current state of pattern matches. 0x0 A 1 in any bit of this field indicates that the corresponding product term is matched by the current state of the appropriate inputs. 8.6.12 Pattern Match Interrupt Bit-Slice Source register The bit-slice source register specifies the input source for each of the eight pattern match bit slices. Each of the possible eight inputs is selected in the pin interrupt select registers in the SYSCON block. See Section 4.6.27. Input 0 corresponds to the pin selected in the PINTSEL0 register, input 1 corresponds to the pin selected in the PINTSEL1 register, and so forth. Remark: Writing any value to either the PMCFG register or the PMSRC register, or disabling the pattern-match feature (by clearing both the SEL_PMATCH and ENA_RXEV bits in the PMCTRL register to zeros) will erase all edge-detect history. Table 91. Pattern match bit-slice source register (PMSRC, address 0x4004 C02C) bit description Bit Symbol 7:0 Reserved UM10601 Preliminary user manual Value Description Reset value Software should not write 1s to unused bits. 0x0 All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 91 of 313 A Pin interrupt. Interrupts are driven in response to the standard pin interrupt function R 0 D - D Specifies whether the 8 pin interrupts are controlled by 0 the pin interrupt function or by the pattern match function. ENA_RXEV 23:2 Reset value FT SEL_PMATCH A 0 Description R Value D Symbol 1 FT Pattern match interrupt control register (PMCTRL, address 0x4004 C028) bit description Bit FT A A R R D Table 90. D D D D D R R R R R D R R D R R 0x1 Input 1. Selects pin interrupt input 1 as the source to bit slice 1. 0x2 Input 2. Selects pin interrupt input 2 as the source to bit slice 1. 0x3 Input 3. Selects pin interrupt input 3 as the source to bit slice 1. 0x4 Input 4. Selects pin interrupt input 4 as the source to bit slice 1. 0x5 Input 5. Selects pin interrupt input 5 as the source to bit slice 1. 0x6 Input 6. Selects pin interrupt input 6 as the source to bit slice 1. A Input 0. Selects pin interrupt input 0 as the source to bit slice 1. R Selects the input source for bit slice 1 0x0 D Input 7. Selects pin interrupt input 7 as the source to bit slice 0. D 0x7 FT Input 6. Selects pin interrupt input 6 as the source to bit slice 0. FT 0x6 A Input 5. Selects pin interrupt input 5 as the source to bit slice 0. R Input 4. Selects pin interrupt input 4 as the source to bit slice 0. 0x5 D 0x4 FT Input 3. Selects pin interrupt input 3 as the source to bit slice 0. A 0x3 A R Input 2. Selects pin interrupt input 2 as the source to bit slice 0. 000 Input 7. Selects pin interrupt input 7 as the source to bit slice 1. Selects the input source for bit slice 2 0x0 Input 0. Selects pin interrupt input 0 as the source to bit slice 2. 0x1 Input 1. Selects pin interrupt input 1 as the source to bit slice 2. 0x2 Input 2. Selects pin interrupt input 2 as the source to bit slice 2. 0x3 Input 3. Selects pin interrupt input 3 as the source to bit slice 2. 0x4 Input 4. Selects pin interrupt input 4 as the source to bit slice 2. 0x5 Input 5. Selects pin interrupt input 5 as the source to bit slice 2. 0x6 Input 6. Selects pin interrupt input 6 as the source to bit slice 2. 0x7 Input 7. Selects pin interrupt input 7 as the source to bit slice 2. Selects the input source for bit slice 3 0x0 Input 0. Selects pin interrupt input 0 as the source to bit slice 3. 0x1 Input 1. Selects pin interrupt input 1 as the source to bit slice 3. 0x2 Input 2. Selects pin interrupt input 2 as the source to bit slice 3. 0x3 Input 3. Selects pin interrupt input 3 as the source to bit slice 3. 0x4 Input 4. Selects pin interrupt input 4 as the source to bit slice 3. 0x5 Input 5. Selects pin interrupt input 5 as the source to bit slice 3. 0x6 Input 6. Selects pin interrupt input 6 as the source to bit slice 3. 0x7 Input 7. Selects pin interrupt input 7 as the source to bit slice 3. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 F D D 0x2 A FT FT A A R R D D R Preliminary user manual 000 Input 1. Selects pin interrupt input 1 as the source to bit slice 0. SRC3 UM10601 Selects the input source for bit slice 0 Input 0. Selects pin interrupt input 0 as the source to bit slice 0. SRC2 D 19:17 Reset value 0x1 0x7 16:14 Description 0x0 SRC1 FT FT FT 13:11 A A A SRC0 R R R 10:8 Value D D D Symbol FT FT FT FT Bit A A A A R R D D D Pattern match bit-slice source register (PMSRC, address 0x4004 C02C) bit description FT FT FT FT FT UM10601 Chapter 8: LPC800 Pin interrupts/pattern match engine Table 91. A A A A A NXP Semiconductors 000 000 © NXP B.V. 2012. All rights reserved. 92 of 313 D D D D D R R R R R D R R D R R 0x1 Input 1. Selects pin interrupt input 1 as the source to bit slice 5. 0x2 Input 2. Selects pin interrupt input 2 as the source to bit slice 5. 0x3 Input 3. Selects pin interrupt input 3 as the source to bit slice 5. 0x4 Input 4. Selects pin interrupt input 4 as the source to bit slice 5. 0x5 Input 5. Selects pin interrupt input 5 as the source to bit slice 5. 0x6 Input 6. Selects pin interrupt input 6 as the source to bit slice 5. A Input 0. Selects pin interrupt input 0 as the source to bit slice 5. R Selects the input source for bit slice 5 0x0 D Input 7. Selects pin interrupt input 7 as the source to bit slice 4. D 0x7 FT Input 6. Selects pin interrupt input 6 as the source to bit slice 4. FT 0x6 A Input 5. Selects pin interrupt input 5 as the source to bit slice 4. R Input 4. Selects pin interrupt input 4 as the source to bit slice 4. 0x5 D 0x4 FT Input 3. Selects pin interrupt input 3 as the source to bit slice 4. A 0x3 A R Input 2. Selects pin interrupt input 2 as the source to bit slice 4. 000 Input 7. Selects pin interrupt input 7 as the source to bit slice 5. Selects the input source for bit slice 6 0x0 Input 0. Selects pin interrupt input 0 as the source to bit slice 6. 0x1 Input 1. Selects pin interrupt input 1 as the source to bit slice 6. 0x2 Input 2. Selects pin interrupt input 2 as the source to bit slice 6. 0x3 Input 3. Selects pin interrupt input 3 as the source to bit slice 6. 0x4 Input 4. Selects pin interrupt input 4 as the source to bit slice 6. 0x5 Input 5. Selects pin interrupt input 5 as the source to bit slice 6. 0x6 Input 6. Selects pin interrupt input 6 as the source to bit slice 6. 0x7 Input 7. Selects pin interrupt input 7 as the source to bit slice 6. Selects the input source for bit slice 7 0x0 Input 0. Selects pin interrupt input 0 as the source to bit slice 7. 0x1 Input 1. Selects pin interrupt input 1 as the source to bit slice 7. 0x2 Input 2. Selects pin interrupt input 2 as the source to bit slice 7. 0x3 Input 3. Selects pin interrupt input 3 as the source to bit slice 7. 0x4 Input 4. Selects pin interrupt input 4 as the source to bit slice 7. 0x5 Input 5. Selects pin interrupt input 5 as the source to bit slice 7. 0x6 Input 6. Selects pin interrupt input 6 as the source to bit slice 7. 0x7 Input 7. Selects pin interrupt input 7 as the source to bit slice 7. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 F D D 0x2 A FT FT A A R R D D R Preliminary user manual 000 Input 1. Selects pin interrupt input 1 as the source to bit slice 4. SRC7 UM10601 Selects the input source for bit slice 4 Input 0. Selects pin interrupt input 0 as the source to bit slice 4. SRC6 D 31:29 Reset value 0x1 0x7 28:26 Description 0x0 SRC5 FT FT FT 25:23 A A A SRC4 R R R 22:20 Value D D D Symbol FT FT FT FT Bit A A A A R R D D D Pattern match bit-slice source register (PMSRC, address 0x4004 C02C) bit description FT FT FT FT FT UM10601 Chapter 8: LPC800 Pin interrupts/pattern match engine Table 91. A A A A A NXP Semiconductors 000 000 © NXP B.V. 2012. All rights reserved. 93 of 313 D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D Chapter 8: LPC800 Pin interrupts/pattern match engine D R R A FT FT FT A A R R D D D R A D FT FT A A R R D The bit-slice configuration register contains bits to select from among eight alternative conditions for each bit slice that will cause that bit slice to contribute to a pattern match. The seven LSB’s of this register specify which bit-slices are the end-points of product terms in the boolean expression (i.e. where OR terms are to be inserted in the expression). F FT FT A A R R D D D 8.6.13 Pattern Match Interrupt Bit-Slice Configuration register FT FT FT UM10601 FT FT NXP Semiconductors D D R A FT D R A This bit is only cleared when the PMCFG or the PMSRC registers are written to. Remark: Writing any value to either the PMCFG register or the PMSRC register, or disabling the pattern-match feature (by clearing both the SEL_PMATCH and ENA_RXEV bits in the PMCTRL register to zeros) will erase all edge-detect history. Table 92. Pattern match bit slice configuration register (PMCFG, address 0x4004 C030) bit description Bit Symbol 6:0 PROD_ ENDPTS Value Description Reset value A 1 in any bit of this field causes the corresponding bit slice to be the final component 0x0 of a product term in the boolean expression. This has two effects: 1. The interrupt request associated with this bit-slice will be asserted whenever a match to that product term is detected. 2. The next bit slice will start a new, independent product term in the boolean expression (i.e. an OR will be inserted in the boolean expression following the element controlled by this bit slice). 7 Reserved (Bit slice 7 is automatically considered a product end point) 0 10:8 CFG0 Specifies the match-contribution condition for bit slice 0. 0b000 0x0 Constant 1. This bit slice always contributes to a product term match. 0x1 Rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x2 Falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x3 Rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x4 High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 0x5 Low level. Match occurs when there is a low level on the specified input. 0x6 Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices) 0x7 Event. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 94 of 313 D D D D D R R R R R D R R FT FT FT FT A A A A R R D D D D R R A FT FT FT A A R R D D D D D A A R R D FT 0b000 FT Specifies the match-contribution condition for bit slice 1. D D Constant 1. This bit slice always contributes to a product term match. 0x1 Rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only R 0x0 A FT D R A cleared when the PMCFG or the PMSRC registers are written to. 0x2 Falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x3 Rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x4 High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 0x5 Low level. Match occurs when there is a low level on the specified input. 0x6 Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices) 0x7 Event. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) CFG2 Specifies the match-contribution condition for bit slice 2. 0b000 0x0 Constant 1. This bit slice always contributes to a product term match. 0x1 Rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x2 Falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x3 Rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x4 High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 0x5 Low level. Match occurs when there is a low level on the specified input. 0x6 Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices) 0x7 Event. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 F FT Reset value A A R R Description FT Value A CFG1 R 13:11 D Symbol D Pattern match bit slice configuration register (PMCFG, address 0x4004 C030) bit description …continued Bit 16:14 FT FT FT FT FT UM10601 Chapter 8: LPC800 Pin interrupts/pattern match engine Table 92. A A A A A NXP Semiconductors © NXP B.V. 2012. All rights reserved. 95 of 313 D D D D D R R R R R D R R FT FT FT FT A A A A R R D D D D R R A FT FT FT A A R R D D D D D A A R R D FT 0b000 FT Specifies the match-contribution condition for bit slice 3. D D Constant 1. This bit slice always contributes to a product term match. 0x1 Rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only R 0x0 A FT D R A cleared when the PMCFG or the PMSRC registers are written to. 0x2 Falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x3 Rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x4 High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 0x5 Low level. Match occurs when there is a low level on the specified input. 0x6 Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices) 0x7 Event. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) CFG4 Specifies the match-contribution condition for bit slice 4. 0b000 0x0 Constant 1. This bit slice always contributes to a product term match. 0x1 Rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x2 Falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x3 Rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x4 High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 0x5 Low level. Match occurs when there is a low level on the specified input. 0x6 Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices) 0x7 Event. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 F FT Reset value A A R R Description FT Value A CFG3 R 19:17 D Symbol D Pattern match bit slice configuration register (PMCFG, address 0x4004 C030) bit description …continued Bit 22:20 FT FT FT FT FT UM10601 Chapter 8: LPC800 Pin interrupts/pattern match engine Table 92. A A A A A NXP Semiconductors © NXP B.V. 2012. All rights reserved. 96 of 313 D D D D D R R R R R D R R FT FT FT FT A A A A R R D D D D R R A FT FT FT A A R R D D D D D A A R R D FT 0b000 FT Specifies the match-contribution condition for bit slice 5. D D Constant 1. This bit slice always contributes to a product term match. 0x1 Rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only R 0x0 A FT D R A cleared when the PMCFG or the PMSRC registers are written to. 0x2 Falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x3 Rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x4 High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 0x5 Low level. Match occurs when there is a low level on the specified input. 0x6 Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices) 0x7 Event. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) CFG6 Specifies the match-contribution condition for bit slice 6. 0b000 0x0 Constant 1. This bit slice always contributes to a product term match. 0x1 Rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x2 Falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x3 Rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x4 High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 0x5 Low level. Match occurs when there is a low level on the specified input. 0x6 Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices) 0x7 Event. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 F FT Reset value A A R R Description FT Value A CFG5 R 25:23 D Symbol D Pattern match bit slice configuration register (PMCFG, address 0x4004 C030) bit description …continued Bit 28:26 FT FT FT FT FT UM10601 Chapter 8: LPC800 Pin interrupts/pattern match engine Table 92. A A A A A NXP Semiconductors © NXP B.V. 2012. All rights reserved. 97 of 313 D D D D D R R R R R FT FT FT FT FT UM10601 D R R FT FT FT FT A A A A R R D D D Chapter 8: LPC800 Pin interrupts/pattern match engine D R R A FT FT FT A A R R D D D D R A A FT FT 0b000 D D Constant 1. This bit slice always contributes to a product term match. 0x1 Rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only R 0x0 A FT D R A cleared when the PMCFG or the PMSRC registers are written to. Falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x3 Rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. 0x4 High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 0x5 Low level. Match occurs when there is a low level on the specified input. 0x6 Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices) 0x7 Event. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of option 3) 8.7 Functional description 8.7.1 Pin interrupts In this interrupt facility, up to 8 pins are identified as interrupt sources by the Pin Interrupt Select registers (PINTSEL0-7). All registers in the pin interrupt block contain 8 bits, corresponding to the pins called out by the PINTSEL0-7 registers. The ISEL register defines whether each interrupt pin is edge- or level-sensitive. The RISE and FALL registers detect edges on each interrupt pin, and can be written to clear (and set) edge detection. The IST register indicates whether each interrupt pin is currently requesting an interrupt, and this register can also be written to clear interrupts. The other pin interrupt registers play different roles for edge-sensitive and level-sensitive pins, as described in Table 93. UM10601 Preliminary user manual Table 93. Pin interrupt registers for edge- and level-sensitive pins Name Edge-sensitive function Level-sensitive function IENR Enables rising-edge interrupts. Enables level interrupts. SIENR Write to enable rising-edge interrupts. Write to enable level interrupts. CIENR Write to disable rising-edge interrupts. Write to disable level interrupts. IENF Enables falling-edge interrupts. Selects active level. SIENF Write to enable falling-edge interrupts. Write to select high-active. CIENF Write to disable falling-edge interrupts. Write to select low-active. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 F FT R Specifies the match-contribution condition for bit slice 7. 0x2 A A Reset value D CFG7 Description FT 31:29 Value A Symbol R R R Bit D D Pattern match bit slice configuration register (PMCFG, address 0x4004 C030) bit description …continued D Table 92. A A A A A NXP Semiconductors © NXP B.V. 2012. All rights reserved. 98 of 313 D D D D D R R R R R D R R FT FT FT FT A A A A R R D D D D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D Suppose the desired boolean pattern to be matched is: (IN1) + (IN1 * IN2) + (~IN2 * ~IN3 * IN6fe) + (IN5 * IN7ev) FT FT FT FT FT UM10601 Chapter 8: LPC800 Pin interrupts/pattern match engine 8.7.2 Pattern Match engine example A A A A A NXP Semiconductors D D with: R A FT D IN6fe = (sticky) falling-edge on input 6 R A IN7ev = (non-sticky) event (rising or falling edge) on input 7 Each individual term in the expression shown above is controlled by one bit-slice. To specify this expression, program the pattern match bit slice source and configuration register fields as follows: • PMSRC register (Table 91): – CLR_EDGEDET: A 1 may be written to bit 5 to clear any pre-existing edge detects on bit-slice 5, if that is what is desired. – SRC0: 001 - select input 1 for bit slice 0 – SRC1: 001 - select input 1 for bit slice 1 – SRC2: 010 - select input 2 for bit slice 2 – SRC3: 010 - select input 2 for bit slice 3 – SRC4: 011 - select input 3 for bit slice 4 – SRC5: 110 - select input 6 for bit slice 5 – SRC6: 101 - select input 5 for bit slice 6 – SRC7: 111 - select input 7 for bit slice 7 • PMCTRL register (Table 90): – Bit[0]: Setting this bit will select pattern matches to generate the pin interrupts in place of the normal pin interrupt mechanism. For this example, pin interrupt 0 will be asserted when a match is detected on the first product term (which, in this case, is just a high level on input 1). Pin interrupt 2 will be asserted in response to a match on the second product term. Pin interrupt 5 will be asserted when there is a match on the third product term. Pin interrupt 7 will be asserted on a match on the last term. – Bit[1]: Setting this bit will cause the RxEv signal to the ARM CPU to be asserted whenever a match occurs on ANY of the product terms in the expression. Otherwise, the RXEV line will not be used. – Bit[31:24]: At any given time, bits 0, 2, 5 and/or 7 may be high if the corresponding product terms are currently matching. – The remaining bits will always be low. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 99 of 313 D D R R R R R A A A A A FT FT FT FT FT D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D Chapter 9: LPC800 Switch matrix R A F FT FT A A R R D D Preliminary user manual D Rev. 1.0 — 7 November 2012 D D D UM10601 D FT FT A A R R D D D 9.1 How to read this chapter R A 9.3 Basic configuration Once configured, no clocks are needed for the switch matrix to function. The system clock is needed only to write to or read from the pin assignment registers. After the switch matrix is configured, disable the clock to the switch matrix block in the SYSAHBCLKCTRL register. Before activating a peripheral or enabling its interrupt, use the switch matrix to connect the peripheral to external pins. The boot loader assigns the SWD functions to pins PIO0_2 and PIO0_3. If the user code disables the SWD functions through the switch matrix to use the pins for other functions, the SWD port is disabled. Remark: For the purpose of programming the pin functions through the switch matrix, every pin except the power and ground pins is identified in a package-independent way by its GPIO port pin number. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 100 of 313 A • Flexible assignment of digital peripheral functions to pins • Enable/disable of analog functions R 9.2 Features D switch matrix select bits are reserved for all other parts. FT The switch matrix is identical for all LPC800 parts. The USART2 and SPI1 functions are only available on parts LPC812M101FDH20 and LPC812M101FDH16 and the corresponding D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R R 3,2B;7$/,1 3,2B 3,2B;7$/287 3,2B 3,2B$&03B&/.,17', DVVLJQ)81& 8B5;' 3,1$66,*1ELWV [ A 3,2B R 3,2B 966 9'' D 3,2B! SLQQXPEHU D 3,2B 3,2B! SLQQXPEHU DVVLJQ)81& 8B7;' 3,1$66,*1ELWV [ IXQFWLRQ8B7;' DVVLJQHGWR62SDFNDJH SLQ IXQFWLRQ8B5;' DVVLJQHGWR62SDFNDJH SLQ A pin is identified for the purpose of programming the switch matrix by its default GPIO port pin. Fig 7. Example: Connect function U0_RXD and U0_TXD to pins 8 and 14 on the SO20 package The switch matrix connects all internal signals listed in the table of movable functions through the pin assignment registers to external pins on the package. External pins are identified by their default GPIO pin number PIO0_n. Follow these steps to connect an internal signal FUNC to an external pin. An example of a movable function is the UART transmit signal TXD: 1. Find the function FUNC in the list of movable function in Table 94 or in the data sheet. 2. Use the LPC800 data sheet to decide which pin x on the LPC800 package to connect FUNC to. 3. Use the pin description table to find the default GPIO function PIO0_n assigned to package pin x. m is the pin number. 4. Locate the pin assignment register for the function FUNC in the switch matrix register description. 5. Disable any special functions on pin PIO0_n in the PINENABLE0 register. 6. Program the pin number n into the bits assigned to FUNC. FUNC is now connected to pin x on the package. 9.3.2 Enable an analog input or other special function The switch matrix enables functions that can only be assigned to one pin. Examples are analog inputs, all GPIO pins, and the debug SWD pins. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 FT 6:',23,2B706 FT A 6:&/.3,2B7&. /3& 62 GLVDEOH;7$/,1 3,1(1$%/(ELW R D FT 5(6(73,2B 3,2B:$.(837567 A 3,2B9''&03 A R F D D 3,2B$&03B,7'2 3,2B A FT FT A A R R D D D 3,2B FT FT FT FT 3,2B A A A A R R D D D 9.3.1 Connect an internal signal to a package pin FT FT FT FT FT UM10601 Chapter 9: LPC800 Switch matrix 3,2B A A A A A NXP Semiconductors © NXP B.V. 2012. All rights reserved. 101 of 313 D D D D D R R R R R A A A A A FT FT FT UM10601 FT FT D R R FT FT FT FT Chapter 9: LPC800 Switch matrix A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R A F FT FT A A A R R D D function available on this pin in the PINENABLE0 register and do not assign any movable function to it. A R R D D • If you want to assign a GPIO pin to a pin on any LPC800 package, disable any special FT FT By default, all pins except pins PIO0_2, PIO0_3, and PIO0_5 are assigned to GPIO. D D R • For all other functions that are not in the table of movable functions, do the following: A On the LPC800, most functions can be assigned through the switch matrix to any external pin that is not a power or ground pin. These functions are called movable functions. A few functions like the crystal oscillator pins (XTALIN/XTALOUT) or the analog comparator inputs can only be assigned to one particular external pin with the appropriate electrical characteristics. These functions are called fixed-pin functions. If a fixed-pin function is not used, it can be replaced by any other movable function. GPIOs are fixed-pin functions. Each GPIO is assigned to one and only one external pin. By default, all external pins have the GPIO function assigned. External pins are therefore identified by their fixed-pin GPIO function. 9.4.1 Movable functions Table 94. Movable functions (assign to pins PIO0_0 to PIO_17 through switch matrix) Function name Type Description SWM Pin assign register Reference U0_TXD O Transmitter output for USART0. PINASSIGN0 Table 96 U0_RXD I Receiver input for USART0. PINASSIGN0 Table 96 U0_RTS O Request To Send output for USART0. PINASSIGN0 Table 96 U0_CTS I Clear To Send input for USART0. PINASSIGN0 Table 96 U0_SCLK I/O Serial clock input/output for USART0 in synchronous mode. PINASSIGN1 Table 97 U1_TXD O Transmitter output for USART1. PINASSIGN1 Table 97 U1_RXD I Receiver input for USART1. PINASSIGN1 Table 97 U1_RTS O Request To Send output for USART1. PINASSIGN1 Table 97 U1_CTS I Clear To Send input for USART1. PINASSIGN2 Table 98 U1_SCLK I/O Serial clock input/output for USART1 in synchronous mode. PINASSIGN2 Table 98 U2_TXD O Transmitter output for USART2. PINASSIGN2 Table 98 UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 102 of 313 A The switch matrix connects internal signals (functions) to external pins. Functions are signals coming from or going to a single pin on the package and coming from or going to an on-chip peripheral block. Examples of functions are the GPIOs, the UART transmit output (TXD), or the clock output CLKOUT. Many peripherals have several functions that must be connected to external pins. R 9.4 General description D b. Enable the function in the PINENABLE0 register. All other possible functions on this pins are now disabled. FT a. Locate the function in the pin description table in the data sheet. This shows the package pin for this function. D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R SWM Pin assign register U2_RXD I Receiver input for USART2. PINASSIGN2 Table 98 U2_RTS O Request To Send output for USART1. PINASSIGN3 Table 99 U2_CTS I Clear To Send input for USART1. PINASSIGN3 Table 99 U2_SCLK I/O Serial clock input/output for USART1 in synchronous mode. PINASSIGN3 Table 99 D FT FT A A R R D PINASSIGN4 Table 100 SPI0_SSEL I/O Slave select for SPI0. PINASSIGN4 Table 100 SPI1_SCK I/O Serial clock for SPI1. PINASSIGN4 Table 100 SPI1_MOSI I/O Master Out Slave In for SPI1. PINASSIGN5 Table 101 SPI1_MISO I/O Master In Slave Out for SPI1. PINASSIGN5 Table 101 SPI1_SSEL I/O Slave select for SPI1. PINASSIGN5 Table 101 CTIN_0 I SCT input 0. PINASSIGN5 Table 101 CTIN_1 I SCT input 1. PINASSIGN6 Table 102 CTIN_2 I SCT input 2. PINASSIGN6 Table 102 CTIN_3 I SCT input 3. PINASSIGN6 Table 102 CTOUT_0 O SCT output 0. PINASSIGN6 Table 102 CTOUT_1 O SCT output 1. PINASSIGN7 Table 103 CTOUT_2 O SCT output 2. PINASSIGN7 Table 103 CTOUT_3 O SCT output 3. PINASSIGN7 Table 103 I2C0_SDA I/O I2C-bus data input/output (open-drain if assigned to pin PIO0_11). High-current sink only if assigned to pin PIO0_11 and if I2C Fast-mode Plus is selected in the I/O configuration register. PINASSIGN7 Table 103 I2C0_SCL I/O I2C-bus clock input/output (open-drain if assigned to pin PIO0_10). High-current sink only if assigned to PIO0_10 and if I2C Fast-mode Plus is selected in the I/O configuration register. PINASSIGN8 Table 104 ACMP_O O Analog comparator output. PINASSIGN8 Table 104 CLKOUT O Clock output. PINASSIGN8 Table 104 Output of the pattern match engine. PINASSIGN8 Table 104 9.4.2 Switch matrix register interface The switch matrix consists of two blocks of pin-assignment registers PINASSIGN and PINENABLE. Every function has an assigned field (1-bit or 8-bit wide) within this bank of registers where you can program the external pin - identified by its GPIO function - you want the function to connect to. GPIOs range from PIO0_0 to PIO0_17 and, for assignment through the pin-assignment registers, are numbered 0 to 17. There are two types of functions which must be assigned to port pins in different ways: Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 103 of 313 A Master In Slave Out for SPI0. R I/O D SPI0_MISO D Table 100 FT Table 99 PINASSIGN4 A PINASSIGN3 Master Out Slave In for SPI0. R Serial clock for SPI0. I/O D I/O SPI0_MOSI All information provided in this document is subject to legal disclaimers. F FT FT Reference SPI0_SCK Preliminary user manual A Description A A R R D D D Type UM10601 FT FT FT FT Function name GPIO_INT_BMAT O A A A A R R D D D Movable functions (assign to pins PIO0_0 to PIO_17 through switch matrix) FT FT FT FT FT UM10601 Chapter 9: LPC800 Switch matrix Table 94. A A A A A NXP Semiconductors D D D D D R R R R R FT FT FT FT FT UM10601 D R R FT FT FT FT A A A A R R D D D Chapter 9: LPC800 Switch matrix D R R A FT FT FT A A R R D D D R F FT FT All movable functions are digital functions. Assign movable functions to pin numbers through the 8 bits of the PINASSIGN register associated with this function. Once the function is assigned a pin PIO0_n, it is connected through this pin to a physical pin on the package. A A A R R D D D 1. Movable functions (PINASSIGN0 to 8): A A A A A NXP Semiconductors D FT FT A A R R D D D R A Each fixed-pin function is associated with one bit in the PINENABLE0 register which selects or deselects the function. – If a fixed-pin function is deselected, any movable function can be assigned to its port and pin. – If a fixed-pin function is deselected and no movable function is assigned to this pin, the pin is GPIO. – On reset, all fixed-pin functions are deselected. – If a fixed-pin function is selected, its assigned pin can not be used for any other function. 9.5 Register description Table 95. Register overview: Switch matrix (base address 0x4000 C000) Name Access Offset Description Reset value Reference PINASSIGN0 R/W 0x000 Pin assign register 0. Assign movable functions U0_TXD, U0_RXD, U0_RTS, U0_CTS 0xFFFF FFFF Table 96 PINASSIGN1 R/W 0x004 Pin assign register 1. Assign movable functions U0_SCLC, U1_TXD, U1_RXD 0xFFFF FFFF Table 97 PINASSIGN2 R/W 0x008 Pin assign register 2. Assign movable functions U2_TXD, U2_RXD 0xFFFF FFFF Table 98 PINASSIGN3 R/W 0x00C Pin assignregister 3. Assign movable function SPI0_SCK 0xFFFF FFFF Table 99 PINASSIGN4 R/W 0x010 Pin assign register 4. Assign movable functions SPI0_MOSI, SPI0_MISO, SPI0_SSEL, SPI1_SCK 0xFFFF FFFF Table 100 PINASSIGN5 R/W 0x014 Pin assign register 5. Assign movable functions SPI1_MOSI, SPI1_MISO, SPI1_SSEL, CTIN_0 0xFFFF FFFF Table 101 PINASSIGN6 R/W 0x018 Pin assign register 6. Assign movable functions CTIN_1, CTIN_2, CTIN_3, CTOUT_0 0xFFFF FFFF Table 102 UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 104 of 313 A Some functions require pins with special characteristics and cannot be moved to other physical pins. Hence these functions are mapped to a fixed port pin. Examples of fixed-pin functions are the oscillator pins or comparator inputs. R 2. Fixed-pin functions (PINENABLE0): D Remark: You can assign more than one digital input function to one external pin. FT Remark: You can assign only one digital output function to an external pin at any given time. D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R Description Reset value Reference PINASSIGN7 R/W 0x01C Pin assign egister 7. Assign movable functions CTOUT_1, CTOUT_2, CTOUT_3, I2C_SDA 0xFFFF FFFF Table 103 PINASSIGN8 R/W 0x020 Pin assign register 8. Assign movable functions I2C_SCL, ACMP_O, CLKOUT, GPIO_INT_BMAT 0xFFFF FFFF Table 104 - - D FT FT A A R R D D D R A D R A - 0x024 Reserved PINENABLE0 R/W 0x1C0 0x1B3 Pin enable register 0. Enables fixed-pin functions ACMP_I0, ACMP_I1, SWCLK, SWDIO, XTALIN, XTALOUT, RESET, CLKIN, VDDCMP Table 105 9.5.1 Pin assign register 0 Pin assign register 0 (PINASSIGN0, address 0x4000 C000) bit description Bit Symbol Description Reset value 7:0 U0_TXD_O U0_TXD function assignment. The value is the pin number to be 0xFF assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). 15:8 U0_RXD_I U0_RXD function assignment. The value is the pin number to be 0xFF assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). 23:16 U0_RTS_O U0_RTS function assignment. The value is the pin number to be 0xFF assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). 31:24 U0_CTS_I U0_CTS function assignment. The value is the pin number to be 0xFF assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). 9.5.2 Pin assign register 1 Preliminary user manual Pin assign register 1 (PINASSIGN1, address 0x4000 C004) bit description Bit Symbol Description 7:0 U0_SCLK_IO U0_SCLK function assignment. The value is the pin number to be 0xFF assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). 15:8 U1_TXD_O U1_TXD function assignment. The value is the pin number to be 0xFF assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). Reset value 23:16 U1_RXD_I U1_RXD function assignment. The value is the pin number to be 0xFF assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). 31:24 U1_RTS_O U1_RTS function assignment. The value is the pin number to be 0xFF assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 FT - UM10601 F FT FT Offset A A A R R D D D Access Table 97. FT FT FT FT Name Table 96. A A A A R R D D D Register overview: Switch matrix (base address 0x4000 C000) …continued FT FT FT FT FT UM10601 Chapter 9: LPC800 Switch matrix Table 95. A A A A A NXP Semiconductors © NXP B.V. 2012. All rights reserved. 105 of 313 D D D D D R R R R R D R R FT FT FT FT A A A A R R D D D D R R A FT FT FT A A R R D D D R A A A R R D D Pin assign register 2 (PINASSIGN2, address 0x4000 C008) bit description F FT FT A A R R D D D Table 98. FT FT FT FT FT UM10601 Chapter 9: LPC800 Switch matrix 9.5.3 Pin assign register 2 A A A A A NXP Semiconductors Reset value 7:0 U1_CTS_I U1_CTS function assignment. The value is the pin number to be 0xFF assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). 15:8 U1_SCLK_IO U1_SCLK function assignment. The value is the pin number to be 0xFF assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). D D Table 99. Pin assign register 3 (PINASSIGN3, address 0x4000 C00C) bit description Bit Symbol Description 7:0 U2_RTS_O U2_RTS function assignment. The value is the pin number to be 0xFF assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). 15:8 U2_CTS_I U2_CTS function assignment. The value is the pin number to be 0xFF assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). 23:16 U2_SCLK_IO Reset value U2_SCLK function assignment. The value is the pin number to be 0xFF assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). 31:24 SPI0_SCK_IO SPI0_SCK function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). 0xFF 9.5.5 Pin assign register 4 Table 100. Pin assign register 4 (PINASSIGN4, address 0x4000 C010) bit description UM10601 Preliminary user manual Bit Symbol Description 7:0 SPI0_MOSI_IO SPI0_MOSI function assignment. The value is the pin number to 0xFF be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 Reset value © NXP B.V. 2012. All rights reserved. 106 of 313 R 9.5.4 Pin assign register 3 D U2_RXD function assignment. The value is the pin number to be 0xFF assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). FT 31:24 U2_RXD_I A U2_TXD function assignment. The value is the pin number to be 0xFF assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). R 23:16 U2_TXD_O A Description FT Symbol FT Bit D D D D D R R R R R FT FT FT FT FT UM10601 D R R FT FT FT FT A A A A R R D D D Chapter 9: LPC800 Switch matrix D R R A FT FT FT A A R R D D D D R Reset value 15:8 SPI0_MISO_IO SPI0_MISIO function assignment. The value is the pin number 0xFF to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). F FT Symbol FT Bit A A A R R D D Table 100. Pin assign register 4 (PINASSIGN4, address 0x4000 C010) bit description Description A A A A A NXP Semiconductors D FT FT A A R R D D D R A Table 101. Pin assign register 5 (PINASSIGN5, address 0x4000 C014) bit description Bit Symbol Description Reset value 7:0 SPI1_MOSI_IO SPI1_MOSI function assignment. The value is the pin number to 0xFF be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). 15:8 SPI1_MISO_IO SPI1_MISIO function assignment. The value is the pin number 0xFF to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). 23:16 SPI1_SSEL_IO SPI1_SSEL function assignment. The value is the pin number to 0xFF be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). 31:24 CTIN_0_I CTIN_0 function assignment. The value is the pin number to be 0xFF assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). 9.5.7 Pin assign register 6 Table 102. Pin assign register 6 (PINASSIGN6, address 0x4000 C018) bit description UM10601 Preliminary user manual Bit Symbol Description Reset value 7:0 CTIN_1_I CTIN_1 function assignment. The value is the pin number to be 0xFF assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). 15:8 CTIN_2_I CTIN_2function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). 0xFF 23:16 CTIN_3_I CTIN_3 function assignment. The value is the pin number to be 0xFF assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). 31:24 CTOUT_0_O CTOUT_0 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 0xFF © NXP B.V. 2012. All rights reserved. 107 of 313 A 9.5.6 Pin assign register 5 R SPI1_SCK function assignment. The value is the pin number to 0xFF be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). D 31:24 SPI1_SCK_IO FT 23:16 SPI0_SSEL_IO SPI0_SSEL function assignment. The value is the pin number to 0xFF be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). D D D D D R R R R R FT FT FT FT FT UM10601 D R R FT FT FT FT A A A A R R D D D Chapter 9: LPC800 Switch matrix D R R A FT FT FT A A R R D D D R A Symbol Description Reset value 7:0 CTOUT_1_O CTOUT_1 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). 0xFF 15:8 CTOUT_2_O CTOUT_2 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). 0xFF 23:16 CTOUT_3_O CTOUT_3 function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). 0xFF 31:24 I2C_SDA_IO I2C_SDA function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). 0xFF FT Bit FT A A R R D D Table 103. Pin assign register 7 (PINASSIGN7, address 0x4000 C01C) bit description F FT FT A A R R D D D 9.5.8 Pin assign register 7 A A A A A NXP Semiconductors D D R A D R A Table 104. Pin assign register 8 (PINASSIGN8, address 0x4000 C020) bit description Bit Symbol Description Reset value 7:0 I2C_SCL_IO I2C_SCL function assignment. The value is the pin 0xFF number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). 15:8 ACMP_O_O ACMP_O_O function assignment. The value is the pin 0xFF number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). 23:16 CLKOUT_O CLKOUT function assignment. The value is the pin 0xFF number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). 31:24 GPIO_INT_BMAT_O GPIO_INT_BMAT function assignment. The value is the pin number to be assigned to this function. The following pins are available: PIO0_0 (= 0) to PIO0_17 (= 0x11). 0xFF 9.5.10 Pin enable register 0 Table 105. Pin enable register 0 (PINENABLE0, address 0x4000 C1C0) bit description Bit Symbol 0 ACMP_I1_EN UM10601 Preliminary user manual Value Description Reset value Enables fixed-pin function. Writing a 1 deselects the function and any movable 1 function can be assigned to this pin. By default the fixed--pin function is deselected and GPIO is assigned to this pin. 0 Enable ACMP_I1. This function is enabled on pin PIO0_0. 1 Disable ACMP_I1. GPIO function PIO0_0 (default) or any other movable function can be assigned to pin PIO0_0. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 FT 9.5.9 Pin assign register 8 © NXP B.V. 2012. All rights reserved. 108 of 313 D D D D D R R R R R D R R D R FT R D Disable SWCLK. GPIO function PIO0_3 is selected on this pin. Any other movable function can be assigned to pin PIO0_3. SWDIO_EN Enables fixed-pin function. Writing a 1 deselects the function and any movable function can be assigned to this pin. This function is selected by default. 0 Enable SWDIO. This function is enabled on pin PIO0_2. 1 Disable SWDIO. GPIO function PIO0_2 is selected on this pin. Any other movable function can be assigned to pin PIO0_2. XTALIN_EN Enables fixed-pin function. Writing a 1 deselects the function and any movable 1 function can be assigned to this pin. By default the fixed--pin function is deselected and GPIO is assigned to this pin. 0 Enable XTALIN. This function is enabled on pin PIO0_8. 1 Disable XTALIN. GPIO function PIO0_8 (default) or any other movable function can be assigned to pin PIO0_8. XTALOUT_EN Enables fixed-pin function. Writing a 1 deselects the function and any movable 1 function can be assigned to this pin. By default the fixed--pin function is deselected and GPIO is assigned to this pin. 0 Enable XTALOUT. This function is enabled on pin PIO0_9. 1 Disable XTALOUT. GPIO function PIO0_9 (default) or any other movable function can be assigned to pin PIO0_9. RESET_EN Enables fixed-pin function. Writing a 1 deselects the function and any movable function can be assigned to this pin. This function is selected by default. 0 Enable RESET. This function is enabled on pin PIO0_5. 1 Disable RESET. GPIO function PIO0_5 is selected on this pin. Any other movable function can be assigned to pin PIO0_5. CLKIN UM10601 Preliminary user manual 0 0 Enables fixed-pin function. Writing a 1 deselects the function and any movable 1 function can be assigned to this pin. By default the fixed-pin function is deselected and GPIO is assigned to this pin. Functions CLKIN and ACMP_I2 are connected to the same pin PIO0_1. To use CLKIN, disable ACMP_I2 in bit 1 of this register and enable CLKIN. 0 Enable CLKIN. This function is enabled on pin PIO0_1. 1 Disable CLKIN. GPIO function PIO0_1 (default) or any other movable function can be assigned to pin CLKIN. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 109 of 313 A 1 R Enable SWCLK. This function is enabled on pin PIO0_3. 0 D 0 D Enables fixed-pin function. Writing a 1 deselects the function and any movable function can be assigned to this pin. This function is selected by default. FT SWCLK_EN FT Disable ACMP_I2. GPIO function PIO0_1 (default) or any other movable function can be assigned to pin PIO0_1. A Enable ACMP_I2. This function is enabled on pin PIO0_1. 1 R 7 0 D 6 Enables fixed-pin function. Writing a 1 deselects the function and any movable 1 function can be assigned to this pin. By default the fixed-pin function is deselected and GPIO is assigned to this pin. Functions CLKIN and ACMP_I2 are connected to the same pin PIO0_1. To use ACMP_I2, disable the CLKIN function in bit 7 of this register and enable ACMP_I2. FT 5 A 4 A R R D 3 F FT 2 A Reset value FT A A R R D D D Description A FT FT A A R R R ACMP_I2_EN D D D 1 Value FT FT FT FT Symbol A A A A R R D D D Bit FT FT FT FT FT UM10601 Chapter 9: LPC800 Switch matrix Table 105. Pin enable register 0 (PINENABLE0, address 0x4000 C1C0) bit description A A A A A NXP Semiconductors D D D D D R R R R R D R R D R FT R D D D R A Reserved. <tbd> All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 FT Disable VDDCMP. GPIO function PIO0_6 (default) or any other movable function can be assigned to pin PIO0_6. A 1 R Enable VDDCMP. This function is enabled on pin PIO0_6. D 0 FT Enables fixed-pin function. Writing a 1 deselects the function and any movable 1 function can be assigned to this pin. By default the fixed--pin function is deselected and GPIO is assigned to this pin. FT A Preliminary user manual A R R D UM10601 F FT 31:9 - A Reset value FT A A R R D D D Description A FT FT A A R R R VDDCMP D D D 8 Value FT FT FT FT Symbol A A A A R R D D D Bit FT FT FT FT FT UM10601 Chapter 9: LPC800 Switch matrix Table 105. Pin enable register 0 (PINENABLE0, address 0x4000 C1C0) bit description A A A A A NXP Semiconductors © NXP B.V. 2012. All rights reserved. 110 of 313 R R R R R A A A A A FT FT FT FT FT D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D Chapter 10: LPC800 State Configurable Timer (SCT) R A F FT FT A A R R D D Preliminary user manual D Rev. 1.0 — 7 November 2012 D D D D D UM10601 D FT FT A A R R D D D 10.1 How to read this chapter R A FT D The SCT is available on all LPC800 parts. R A 10.2 Features • • • • • Two 16-bit counters or one 32-bit counter. Counters clocked by bus clock or selected input. Up counters or up-down counters. State variable allows sequencing across multiple counter cycles. The following conditions define an event: a counter match condition, an input (or output) condition, a combination of a match and/or and input/output condition in a specified state, and the count direction. • Events control outputs, interrupts, and the SCT states. – Match register 0 can be used as an automatic limit. – In bi-directional mode, events can be enabled based on the count direction. – Match events can be held until another qualifying event occurs. • Selected events can limit, halt, start, or stop a counter. • Supports: – 4 inputs – 4 outputs – 5 match/capture registers – 6 events – 2 states 10.3 Basic configuration Configure the SCT as follows: • Use the SYSAHBCLKCTRL register (Table 18) to enable the clock to the SCT register interface and peripheral clock. The LPC800 system clock is the input clock to the SCT clock processing and is the source of the SCT clock. • Clear the SCT peripheral reset using the PRESETCTRL register (Table 7). • The SCT combined interrupt is connected to slot #8 in the NVIC. • Use the switch matrix to connect the SCT inputs and outputs to pins (see Section 10.4). 10.3.1 Use the SCT as a simple timer To configure the SCT as a simple timer with match or capture functionality, follow these steps: UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 111 of 313 D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R F FT FT A A A R R D D D D FT FT A A R R D 3. If you want to create a match event when the timer reaches a match value: D D a. Configure the register map for match registers. See Table 117. R A FT b. Configure one or more match registers with a match value. See Table 125. D R c. For each match value, create a match event. See Table 130. A d. If you want to create an interrupt on a match event, enable the event for interrupt. See Table 122. e. If you want to create a match output on a pin, connect the CTOUTn function to a pin (see Section 10.4) and select an output for the match event in the EVn_CTRL register. See Table 130. The EVn_CTRL registers also control what type of output signal is created. 4. If you want to capture a timer value on a capture signal: a. Configure the register map for capture registers. See Table 117. b. Create one or more capture events. See Table 130. c. Connect the CTIN functions to pins (see Section 10.4) and configure the signal to create an event. See Table 130. 5. Start the timer by writing to the CRTL register. See Table 109. 6. Read the capture registers to read the timer value at the time of the capture events. 10.4 Pin description The SCT inputs and outputs are movable functions and are assigned to external pins through the switch matrix. See Section 9.3.1 “Connect an internal signal to a package pin” to assign the SCT functions to pins on the LPC800 package. Table 106. SCT pin description Function Direction Pin Description SWM register Reference CTIN_0 I any SCT input 0 PINASSIGN5 Table 101 CTIN_1 I any SCT input 1 PINASSIGN6 Table 102 CTIN_2 I any SCT input 2 PINASSIGN6 Table 102 CTIN_3 I any SCT input 3 PINASSIGN6 Table 102 CTOUT_0 O any SCT output 0 PINASSIGN6 Table 102 CTOUT_1 O any SCT output 1 PINASSIGN7 Table 103 CTOUT_2 O any SCT output 2 PINASSIGN7 Table 103 CTOUT_3 O any SCT output 3 PINASSIGN7 Table 103 10.5 General description The State Configurable Timer (SCT) allows a wide variety of timing, counting, output modulation, and input capture operations. Rev. 1.0 — 7 November 2012 FT FT FT FT 2. Preload the 32-bit timer or the 16-bit timers with a count value. See Table 114. All information provided in this document is subject to legal disclaimers. A A A A R R D D D 1. Set up the SCT as one 32-bit timer or one or two 16-bit timers. See Table 108. Preliminary user manual FT FT FT FT FT UM10601 Chapter 10: LPC800 State Configurable Timer (SCT) UM10601 A A A A A NXP Semiconductors © NXP B.V. 2012. All rights reserved. 112 of 313 D D D D D R R R R R A A A A A FT FT FT UM10601 FT FT D R R FT FT FT FT Chapter 10: LPC800 State Configurable Timer (SCT) A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D The most basic user-programmable option is whether a SCT operates as two 16-bit counters or a unified 32-bit counter. In the two-counter case, in addition to the counter value the following operational elements are independent for each half: D FT FT A A R R D D D • State variable • Limit, halt, stop, and start conditions • Values of Match/Capture registers, plus reload or capture control values R A FT D R A In the two-counter case, the following operational elements are global to the SCT: • • • • • Clock selection Inputs Events Outputs Interrupts Events, outputs, and interrupts can use match conditions from either counter. Remark: In this chapter, the term bus error indicates an SCT response that makes the processor take an exception. V\VWHPFORFN 6&7FORFN SUHVFDOHUV Fig 8. UM10601 Preliminary user manual SCT block diagram All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 113 of 313 D D D D D R R R R R D R R FT FT FT FT A A A A R R D D D D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D 6&7FORFN FT FT FT FT FT UM10601 Chapter 10: LPC800 State Configurable Timer (SCT) D FT FT A A R R D V\VWHPFORFN A A A A A NXP Semiconductors D D R A FT D R A SUHVFDOHU +FRXQWHU 8QLILHG FRXQWHU SUHVFDOHU /FRXQWHU Fig 9. SCT counter and select logic 10.6 Register description The register addresses of the State Configurable Timer are shown in Table 107. For most of the SCT registers, the register function depends on the setting of certain other register bits: 1. The UNIFY bit in the CONFIG register determines whether the SCT is used as one 32-bit register (for operation as one 32-bit counter/timer) or as two 16-bit counter/timers named L and H. The setting of the UNIFY bit is reflected in the register map: – UNIFY = 1: Only one register is used (for operation as one 32-bit counter/timer). – UNIFY = 0: Access the L and H registers by a 32-bit read or write operation or can be read or written to individually (for operation as two 16-bit counter/timers). Typically, the UNIFY bit is configured by writing to the CONFIG register before any other registers are accessed. 2. The REGMODEn bits in the REGMODE register determine whether each set of Match/Capture registers uses the match or capture functionality: – REGMODEn = 1: Registers operate as match and reload registers. – REGMODEn = 0: Registers operate as capture and capture control registers. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 114 of 313 D D D D D R R R R R D R R R A FT R A 0x000 SCT configuration register 0x0000 7E00 Table 108 CTRL R/W 0x004 SCT control register 0x0004 0004 Table 109 CTRL_L R/W 0x004 SCT control register low counter 16-bit - Table 109 Table 109 FT FT A A R R D D R/W F FT FT A A R R D D D CONFIG 0x008 SCT limit register low counter 16-bit - Table 110 LIMIT_H R/W 0x00A SCT limit register high counter 16-bit - Table 110 HALT R/W 0x00C SCT halt condition register 0x0000 0000 Table 111 HALT_L R/W 0x00C SCT halt condition register low counter 16-bit - Table 111 HALT_H R/W 0x00E SCT halt condition register high counter 16-bit - Table 111 STOP R/W 0x010 SCT stop condition register 0x0000 0000 Table 112 STOP_L R/W 0x010 SCT stop condition register low counter 16-bit - Table 112 STOP_H R/W 0x012 SCT stop condition register high counter 16-bit - Table 112 START R/W 0x014 SCT start condition register 0x0000 0000 Table 113 START_L R/W 0x014 SCT start condition register low counter 16-bit - Table 113 - Table 113 START_H R/W 0x016 SCT start condition register high counter 16-bit - - 0x018 0x03C Reserved COUNT R/W 0x040 SCT counter register 0x0000 0000 Table 114 COUNT_L R/W 0x040 SCT counter register low counter 16-bit - Table 114 COUNT_H R/W 0x042 SCT counter register high counter 16-bit - Table 114 STATE R/W 0x044 SCT state register 0x0000 0000 Table 115 STATE_L R/W 0x044 SCT state register low counter 16-bit - Table 115 Table 115 - STATE_H R/W 0x046 SCT state register high counter 16-bit - INPUT RO 0x048 SCT input register 0x0000 0000 Table 116 REGMODE R/W 0x04C SCT match/capture registers mode register 0x0000 0000 Table 117 REGMODE_L R/W 0x04C SCT match/capture registers mode register low counter 16-bit - Table 117 REGMODE_H R/W 0x04E SCT match/capture registers mode register high counter 16-bit - Table 117 OUTPUT R/W 0x050 SCT output register 0x0000 0000 Table 118 OUTPUTDIRCTRL R/W 0x054 SCT output counter direction control register 0x0000 0000 Table 119 RES R/W 0x058 SCT conflict resolution register 0x0000 0000 Table 120 - - 0x05C - - - - - 0x060 - - - - - 0x064 0x0EC Reserved - - EVEN R/W 0x0F0 SCT event enable register 0x0000 0000 Table 121 EVFLAG R/W 0x0F4 SCT event flag register 0x0000 0000 Table 122 CONEN R/W 0x0F8 SCT conflict enable register 0x0000 0000 Table 123 CONFLAG R/W 0x0FC SCT conflict flag register 0x0000 0000 Table 124 © NXP B.V. 2012. All rights reserved. 115 of 313 A R/W R LIMIT_L D 0x0000 0000 Table 110 D - SCT limit register FT SCT control register high counter 16-bit 0x008 A 0x006 R/W R R/W LIMIT D CTRL_H Rev. 1.0 — 7 November 2012 D R FT FT A A R R D D D Reset value Reference All information provided in this document is subject to legal disclaimers. FT FT FT FT Access Address Description offset Preliminary user manual A A A A R R D D D Name UM10601 FT FT FT FT FT UM10601 Chapter 10: LPC800 State Configurable Timer (SCT) Table 107. Register overview: State Configurable Timer (base address 0x5000 4000) A A A A A NXP Semiconductors D D D D D R R R R R D R R FT R A A A F FT FT D 0x100 to SCT match value register of match channels 0 to 0x110 4; low counter 16-bit; REGMOD0_L to REGMODE4_L = 0 - Table 124 MATCH_H0 to MATCH_H4 R/W 0x102 to SCT match value register of match channels 0 to 0x112 4; high counter 16-bit; REGMOD0_H to REGMODE4_H = 0 - Table 124 CAP0 to CAP4 0x100 to SCT capture register of capture channel 0 to 4; 0x110 REGMOD0 to REGMODE4 = 1 0x0000 0000 Table 126 CAP_L0 to CAP_L4 0x100 to SCT capture register of capture channel 0 to 4; 0x110 low counter 16-bit; REGMOD0_L to REGMODE4_L = 1 - Table 126 CAP_H0 to CAP_H4 0x102 to SCT capture register of capture channel 0 to 4; 0x13E high counter 16-bit; REGMOD0_H to REGMODE4_H = 1 - Table 126 FT R/W FT A A R R D MATCH_L0 to MATCH_L4 D D R A FT D R A MATCHREL0 to MATCHREL4 R/W 0x200 to SCT match reload value register 0 to 4 0x210 REGMOD0 = 0 to REGMODE4 = 0 0x0000 0000 Table 127 MATCHREL_L0 to MATCHREL_L4 R/W 0x200 to SCT match reload value register 0 to 4; low 0x210 counter 16-bit; REGMOD0_L = 0 to REGMODE4_L = 0 - Table 127 MATCHREL_H0 to MATCHREL_H4 R/W 0x202 to SCT match reload value register 0 to 4; high 0x212 counter 16-bit; REGMOD0_H = 0 to REGMODE4_H = 0 - Table 127 CAPCTRL0 to CAPCTRL4 0x200 to SCT capture control register 0 to 4; REGMOD0 = 0x0000 0000 Table 128 0x210 1 to REGMODE4 = 1 CAPCTRL_L0 to CAPCTRL_L4 0x200 to SCT capture control register 0 to 4; low counter 0x210 16-bit; REGMOD0_L = 1 to REGMODE4_L = 1 - Table 128 CAPCTRL_H0 to CAPCTRL_H4 0x202 to SCT capture control register 0 to 4; high counter 0x212 16-bit; REGMOD0 = 1 to REGMODE4 = 1 - Table 128 EV0_STATE R/W 0x300 SCT event 0 state register 0x0000 0000 Table 129 EV0_CTRL R/W 0x304 SCT event 0 control register 0x0000 0000 Table 130 EV1_STATE R/W 0x308 SCT event 1 state register 0x0000 0000 Table 129 EV1_CTRL R/W 0x30C SCT event 1 control register 0x0000 0000 Table 130 EV2_STATE R/W 0x310 SCT event 2 state register 0x0000 0000 Table 129 EV2_CTRL R/W 0x314 SCT event 2 control register 0x0000 0000 Table 130 EV3_STATE R/W 0x318 SCT event 3 state register 0x0000 0000 Table 129 EV3_CTRL R/W 0x31C SCT event 3 control register 0x0000 0000 Table 130 EV4_STATE R/W 0x320 SCT event 4 state register 0x0000 0000 Table 129 EV4_CTRL R/W 0x324 SCT event 4 control register 0x0000 0000 Table 130 EV5_STATE R/W 0x328 SCT event 5 state register 0x0000 0000 Table 129 EV5_CTRL R/W 0x32C SCT event 5 control register 0x0000 0000 Table 130 OUT0_SET R/W 0x500 SCT output 0 set register 0x0000 0000 Table 131 OUT0_CLR R/W 0x504 SCT output 0 clear register 0x0000 0000 Table 132 OUT1_SET R/W 0x508 SCT output 1 set register 0x0000 0000 Table 131 Rev. 1.0 — 7 November 2012 D R R 0x0000 0000 Table 124 All information provided in this document is subject to legal disclaimers. R A D D 0x100 to SCT match value register of match channels 0 to 0x110 4; REGMOD0 to REGMODE4 = 0 Preliminary user manual D R FT FT A A R R D D D Reset value Reference MATCH0 to MATCH4 R/W UM10601 FT FT FT FT Access Address Description offset A A A A R R D D D Name FT FT FT FT FT UM10601 Chapter 10: LPC800 State Configurable Timer (SCT) Table 107. Register overview: State Configurable Timer (base address 0x5000 4000) …continued A A A A A NXP Semiconductors © NXP B.V. 2012. All rights reserved. 116 of 313 D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R R/W 0x50C SCT output 1 clear register 0x0000 0000 Table 132 OUT2_SET R/W 0x510 SCT output 2 set register 0x0000 0000 Table 131 OUT2_CLR R/W 0x514 SCT output 2 clear register 0x0000 0000 Table 132 OUT3_SET R/W 0x518 SCT output 3 set register 0x0000 0000 Table 131 OUT3_CLR R/W 0x51C SCT output 3 clear register 0x0000 0000 Table 132 D FT FT A A R R D D D R A 2:1 6:3 Reset value SCT operation 0 0 The SCT operates as two 16-bit counters named L and H. 1 The SCT operates as a unified 32-bit counter. CLKMODE SCT clock mode 0 0x0 The bus clock clocks the SCT and prescalers. 0x1 The SCT clock is the bus clock, but the prescalers are enabled to count only when sampling of the input selected by the CKSEL field finds the selected edge. The minimum pulse width on the clock input is 1 bus clock period. This mode is the high-performance sampled-clock mode. 0x2 The input selected by CKSEL clocks the SCT and prescalers. The input is synchronized to the bus clock and possibly inverted. The minimum pulse width on the clock input is 1 bus clock period. This mode is the low-power sampled-clock mode. 0x3 Reserved. CKSEL SCT clock select. All other values are reserved. 0x0 Rising edges on input 0. 0x1 Falling edges on input 0. 0x2 Rising edges on input 1. 0x3 Falling edges on input 1. 0x4 Rising edges on input 2. 0x5 Falling edges on input 2. 0x6 Rising edges on input 3. 0 0x7 Falling edges on input 3. 7 NORELAOD_L - A 1 in this bit prevents the lower match registers from being reloaded from their 0 respective reload registers. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set. 8 NORELOAD_H - A 1 in this bit prevents the higher match registers from being reloaded from their 0 respective reload registers. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 117 of 313 A UNIFY Description R Table 108. SCT configuration register (CONFIG, address 0x5000 4000) bit description D This register configures the overall operation of the SCT. Write to this register before any other registers. FT 10.6.1 SCT configuration register 0 F FT FT OUT1_CLR A A A R R D D D Reset value Reference Value FT FT FT FT Access Address Description offset Symbol A A A A R R D D D Name Bit FT FT FT FT FT UM10601 Chapter 10: LPC800 State Configurable Timer (SCT) Table 107. Register overview: State Configurable Timer (base address 0x5000 4000) …continued A A A A A NXP Semiconductors D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R Reset value 16:9 INSYNC - Synchronization for input N (bit 9 = input 0, bit 10 = input 1,..., bit 16 = input 7). 1 A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock, before it is used to create an event. If an input is synchronous to the SCT clock, keep its bit 0 for faster response. D FT FT A A R R D D D R A R A Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set. - A one in this bit will cause a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in uni-directional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set. 31:19 - Reserved - 10.6.2 SCT control register If UNIFY = 1 in the CONFIG register, only the _L bits are used. If UNIFY = 0 in the CONFIG register, this register can be written to as two registers CTRL_L and CTRL_H. Both the L and H registers can be read or written individually or in a single 32-bit read or write operation. All bits in this register can be written to when the counter is stopped or halted. When the counter is running, the only bits that can be written are STOP or HALT. (Other bits can be written in a subsequent write after HALT is set to 1.) Table 109. SCT control register (CTRL, address 0x5000 4004) bit description Bit Symbol Value Description 0 DOWN_L - This bit is 1 when the L or unified counter is counting down. Hardware sets this bit 0 when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0. 1 STOP_L - When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events 0 related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes. 2 HALT_L - When this bit is 1, the L or unified counter does not run and no events can occur. A reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register. Reset value 1 Remark: Once set, only software can clear this bit to restore counter operation. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 D A one in this bit causes a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in uni-directional mode or to change the direction of count in bi-directional mode. AUTOLIMIT_H FT When the CKMODE field is 1x, the bit in this field, corresponding to the input selected by the CKSEL field, is not used. 18 F FT Description FT Value A A A R R D D D Symbol - FT FT FT FT Bit AUTOLIMIT_L A A A A R R D D D Table 108. SCT configuration register (CONFIG, address 0x5000 4000) bit description …continued FT FT FT FT FT UM10601 Chapter 10: LPC800 State Configurable Timer (SCT) 17 A A A A A NXP Semiconductors © NXP B.V. 2012. All rights reserved. 118 of 313 D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R CLRCTR_L - Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0. 0 4 BIDIR_L L or unified counter direction select 0 D FT FT A A R R D D D R A FT The counter counts up to its limit condition, then is cleared to zero. 1 The counter counts up to its limit, then counts down to a limit condition or to 0. - Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. D 0 R A 0 Remark: Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. 15:13 - 16 DOWN_H - This bit is 1 when the H counter is counting down. Hardware sets this bit when the 0 counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0. 17 STOP_H - When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related 0 to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes. 18 HALT_H - When this bit is 1, the H counter does not run and no events can occur. A reset sets 1 this bit. When the HALT_H bit is one, the STOP_H bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register. Reserved Remark: Once set, this bit can only be cleared by software to restore counter operation. 19 CLRCTR_H - Writing a 1 to this bit clears the H counter. This bit always reads as 0. 0 20 BIDIR_H Direction select 0 28:21 PRE_H 0 The H counter counts up to its limit condition, then is cleared to zero. 1 The H counter counts up to its limit, then counts down to a limit condition or to 0. - Specifies the factor by which the SCT clock is prescaled to produce the H counter 0 clock. The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Remark: Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. 31:29 - Reserved 10.6.3 SCT limit register If UNIFY = 1 in the CONFIG register, only the _L bits are used. If UNIFY = 0 in the CONFIG register, this register can be written to as two registers LIMIT_L and LIMIT_H. Both the L and H registers can be read or written individually or in a single 32-bit read or write operation. The bits in this register set which events act as counter limits. When a limit event occurs, the counter is cleared to zero in unidirectional mode or changes the direction of count in bidirectional mode. When the counter reaches all ones, this state is always treated as a limit event, and the counter is cleared in unidirectional mode or, in bidirectional mode, begins counting down on the next clock edge - even if no limit event as defined by the SCT limit register has occurred. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 F FT 3 FT Reset value A A A R R D D D Symbol PRE_L FT FT FT FT Bit 12:5 A A A A R R D D D Value Description FT FT FT FT FT UM10601 Chapter 10: LPC800 State Configurable Timer (SCT) Table 109. SCT control register (CTRL, address 0x5000 4004) bit description A A A A A NXP Semiconductors © NXP B.V. 2012. All rights reserved. 119 of 313 D D D D D R R R R R A A A A A FT FT FT UM10601 FT FT D R R FT FT FT FT Chapter 10: LPC800 State Configurable Timer (SCT) A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D Note that in addition to using this register to specify events that serve as limits, it is also possible to automatically cause a limit condition whenever a match register 0 match occurs. This eliminates the need to define an event for the sole purpose of creating a limit. The AUTOLIMITL and AUTOLIMITH bits in the configuration register enable/disable this feature (see Table 108). D FT FT A A R R D D D R A FT D Table 110. SCT limit register (LIMIT, address 0x5000 4008) bit description Description Reset value 5:0 LIMMSK_L If bit n is one, event n is used as a counter limit for the L or 0 unified counter (event 0 = bit 0, event 1 = bit 1, event 5 = bit 5). 15:6 - Reserved. 20:16 LIMMSK_H If bit n is one, event n is used as a counter limit for the H 0 counter (event 0 = bit 16, event 1 = bit 17, event 5 = bit 20). 31:21 - Reserved. - - 10.6.4 SCT halt condition register If UNIFY = 1 in the CONFIG register, only the _L bits are used. If UNIFY = 0 in the CONFIG register, this register can be written to as two registers HALT_L and HALT_H. Both the L and H registers can be read or written individually or in a single 32-bit read or write operation. Remark: Any event halting the counter disables its operation until software clears the HALT bit (or bits) in the CTRL register (Table 109). Table 111. SCT halt condition register (HALT, address 0x5004 400C) bit description Bit Symbol Description Reset value 5:0 HALTMSK_L If bit n is one, event n sets the HALT_L bit in the CTRL register 0 (event 0 = bit 0, event 1 = bit 1, event 5 = bit 5). 15:6 - Reserved. - 20:16 HALTMSK_H If bit n is one, event n sets the HALT_H bit in the CTRL register 0 (event 0 = bit 16, event 1 = bit 17, event 5 = bit 20). 31:21 - Reserved. - 10.6.5 SCT stop condition register If UNIFY = 1 in the CONFIG register, only the _L bits are used. If UNIFY = 0 in the CONFIG register, this register can be written to as two registers STOPT_L and STOP_H. Both the L and H registers can be read or written individually or in a single 32-bit read or write operation. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 120 of 313 A Symbol R Bit D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R A STOPMSK_L If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 5 = bit 5). 0 15:6 - Reserved. - FT FT A A R R 5:0 D Reset value D Description F FT FT A A R R D D D Symbol D D R 10.6.6 SCT start condition register If UNIFY = 1 in the CONFIG register, only the _L bits are used. If UNIFY = 0 in the CONFIG register, this register can be written to as two registers START_L and START_H. Both the L and H registers can be read or written individually or in a single 32-bit read or write operation. The bits in this register select which events, if any, clear the STOP bit in the Control register. (Since no events can occur when HALT is 1, only software can clear the HALT bit by writing the Control register.) Table 113. SCT start condition register (START, address 0x5000 4014) bit description Bit Symbol Description Reset value 5:0 STARTMSK_L If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 5 = bit 5). 0 15:6 - Reserved. - 20:16 STARTMSK_H If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 5 = bit 20). 0 31:21 - Reserved. - 10.6.7 SCT counter register If UNIFY = 1 in the CONFIG register, the counter is a unified 32-bit register and both the _L and _H bits are used. If UNIFY = 0 in the CONFIG register, this register can be written to as two registers COUNT_L and COUNT_H. Both the L and H registers can be read or written individually or in a single 32-bit read or write operation. In this case, the L and H registers count independently under the control of the other registers. Attempting to write a counter while it is running does not affect the counter but produces a bus error. Software can read the counter registers at any time. © NXP B.V. 2012. All rights reserved. 121 of 313 A - R Reserved. D 31:21 - FT If bit n is one, event n sets the STOP_H bit in the CTRL register 0 (event 0 = bit 16, event 1 = bit 17, event 5 = bit 20). A 20:16 STOPMSK_H Rev. 1.0 — 7 November 2012 FT FT FT FT Bit All information provided in this document is subject to legal disclaimers. A A A A R R D D D Table 112. SCT stop condition register (STOP, address 0x5000 4010) bit description Preliminary user manual FT FT FT FT FT UM10601 Chapter 10: LPC800 State Configurable Timer (SCT) UM10601 A A A A A NXP Semiconductors D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R CTR_L When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write the lower 16 bits of the 32-bit unified counter. 0 31:16 CTR_H When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write the upper 16 bits of the 32-bit unified counter. 0 F 15:0 D Reset value FT FT A A R R D Description D D R A FT D R A If UNIFY = 1 in the CONFIG register, only the _L bits are used. If UNIFY = 0 in the CONFIG register, this register can be written to as two registers STATE_L and STATE_H. Both the L and H registers can be read or written individually or in a single 32-bit read or write operation. Software can read the state associated with a counter at any time. Writing the state is only allowed when the counter HALT bit is 1; when HALT is 0, a write attempt does not change the state and results in a bus error. The state variable is the main feature that distinguishes the SCT from other counter/timer/ PWM blocks. Events can be made to occur only in certain states. Events, in turn, can perform the following actions: set and clear outputs limit, stop, and start the counter cause interrupts modify the state variable The value of a state variable is completely under the control of the application. If an application does not use states, the value of the state variable remains zero, which is the default value. A state variable can be used to track and control multiple cycles of the associated counter in any desired operational sequence. The state variable is logically associated with a state machine diagram which represents the SCT configuration. See Section 10.6.22 and 10.6.23 for more about the relationship between states and events. The STATELD/STADEV fields in the event control registers of all defined events set all possible values for the state variable. The change of the state variable during multiple counter cycles reflects how the associated state machine moves from one state to the next. Table 115. SCT state register (STATE, address 0x5000 4044) bit description Bit Symbol Description Reset value 4:0 STATE_L State variable. 0 15:5 - Reserved. - 20:16 STATE_H State variable. 0 31:21 - Reserved. Rev. 1.0 — 7 November 2012 A FT FT A A R R D D D Symbol All information provided in this document is subject to legal disclaimers. FT FT FT FT Bit 10.6.8 SCT state register Preliminary user manual A A A A R R D D D Table 114. SCT counter register (COUNT, address 0x5000 4040) bit description UM10601 FT FT FT FT FT UM10601 Chapter 10: LPC800 State Configurable Timer (SCT) • • • • A A A A A NXP Semiconductors © NXP B.V. 2012. All rights reserved. 122 of 313 D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D Chapter 10: LPC800 State Configurable Timer (SCT) D R R A FT FT FT A A R R D D D R A FT FT A A R R D D Software can read the state of the SCT inputs in this read-only register in two slightly different forms. The only situation in which these values are different is if CLKMODE = 2 in the CONFIG register. F FT FT A A R R D D D 10.6.9 SCT input register FT FT FT UM10601 FT FT NXP Semiconductors D D R A FT Table 116. SCT input register (INPUT, address 0x5000 4048) bit description Reset value 0 AIN0 Real-time status of input 0. pin 1 AIN1 Real-time status of input 1. pin 2 AIN2 Real-time status of input 2. pin 3 AIN3 Real-time status of input 3. pin 15:4 - Reserved. - 16 SIN0 Input 0 state synchronized to the SCT clock. - 17 SIN1 Input 1 state synchronized to the SCT clock. - 18 SIN2 Input 2 state synchronized to the SCT clock. - 19 SIN3 Input 3 state synchronized to the SCT clock. - 31:20 - Reserved - 10.6.10 SCT match/capture registers mode register If UNIFY = 1 in the CONFIG register, only the _L bits of this register are used. The L bits control whether each set of match/capture registers operates as unified 32-bit capture/match registers. If UNIFY = 0 in the CONFIG register, this register can be written to as two registers REGMODE_L and REGMODE_H. Both the L and H registers can be read or written individually or in a single 32-bit read or write operation.The _L bits/registers control the L match/capture registers, and the _H bits/registers control the H match/capture registers. The SCT contains 5 Match/Capture register pairs. The Register Mode register selects whether each register pair acts as a Match register (see Section 10.6.18) or as a Capture register (see Section 10.6.19). Each Match/Capture register has an accompanying register which serves as a Reload register when the register is used as a Match register (Section 10.6.20) or as a Capture-Control register when the register is used as a capture register (Section 10.6.21). REGMODE_H is used only when the UNIFY bit is 0. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 123 of 313 A Description R Symbol D Bit D D D D D R R R R R A A A A A FT FT FT UM10601 FT FT D R R FT FT FT FT Chapter 10: LPC800 State Configurable Timer (SCT) A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D D D R REGMOD_L Each bit controls one pair of match/capture registers (register 0 = bit 0, register 1 = bit 1,..., register 4 = bit 4). F 4:0 Reset value R Description FT FT A A R Symbol D D Bit A FT FT A A R R Table 117. SCT match/capture registers mode register (REGMODE, address 0x5000 404C) bit description D D R 0 A FT D 0 = registers operate as match registers. R A 1 = registers operate as capture registers. 15:5 - 19:16 REGMOD_H Reserved. - Each bit controls one pair of match/capture registers (register 0 = bit 16, register 1 = bit 17,..., register 4 = bit 19). 0 0 = registers operate as match registers. 1 = registers operate as capture registers. 31:20 - Reserved. - 10.6.11 SCT output register The SCT supports 4 outputs, each of which has a corresponding bit in this register. Software can write to any of the output registers when both counters are halted to control the outputs directly. Writing to this register when either counter is stopped or running does not affect the outputs and results in an bus error. Software can read this register at any time to sense the state of the outputs. Table 118. SCT output register (OUTPUT, address 0x5000 4050) bit description Bit Symbol Description Reset value 3:0 OUT Writing a 1 to bit n makes the corresponding output HIGH. 0 makes 0 the corresponding output LOW (output 0 = bit 0, output 1 = bit 1,..., output 3 = bit 3). 31:4 - Reserved 10.6.12 SCT bidirectional output control register This register specifies (for each output) the impact of the counting direction on the meaning of set and clear operations on the output (see Section 10.6.24 and Section 10.6.25). Table 119. SCT bidirectional output control register (OUTPUTDIRCTRL, address 0x5000 4054) bit description Bit Symbol 1:0 SETCLR0 3:2 Value Description Reset value Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value. 0 0x0 Set and clear do not depend on any counter. 0x1 Set and clear are reversed when counter L or the unified counter is counting down. 0x2 Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. SETCLR1 Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value. 0x0 Set and clear do not depend on any counter. 0x1 Set and clear are reversed when counter L or the unified counter is counting down. 0x2 Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 0 © NXP B.V. 2012. All rights reserved. 124 of 313 D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R R FT 0 FT A D D Set and clear are reversed when counter L or the unified counter is counting down. 0x2 Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. R Set and clear do not depend on any counter. 0x1 A 0x2 Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. Reserved A Set and clear are reversed when counter L or the unified counter is counting down. R Set and clear do not depend on any counter. 0x1 D 0x0 FT Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value. 31:8 - A R 0x0 SETCLR3 0 - 10.6.13 SCT conflict resolution register The registers OUTn_SETn (Section 10.6.24) and OUTnCLRn (Section 10.6.25) allow both setting and clearing to be indicated for an output in the same clock cycle, even for the same event. This SCT conflict resolution register resolves this conflict. To enable an event to toggle an output, set the OnRES value to 0x3 in this register, and set the event bits in both the Set and Clear registers. Table 120. SCT conflict resolution register (RES, address 0x5000 4058) bit description Bit Symbol 1:0 O0RES 3:2 5:4 7:6 31:8 UM10601 Preliminary user manual Value Description 0 0x0 No change. 0x1 Set output (or clear based on the SETCLR0 field). 0x2 Clear output (or set based on the SETCLR0 field). 0x3 Toggle output. Effect of simultaneous set and clear on output 1. 0 0x0 No change. 0x1 Set output (or clear based on the SETCLR1 field). 0x2 Clear output (or set based on the SETCLR1 field). 0x3 Toggle output. O2RES Effect of simultaneous set and clear on output 2. 0 0x0 No change. 0x1 Set output (or clear based on the SETCLR2 field). 0x2 Clear output n (or set based on the SETCLR2 field). 0x3 Toggle output. O3RES - Reset value Effect of simultaneous set and clear on output 0. O1RES Effect of simultaneous set and clear on output 3. 0 0x0 No change. 0x1 Set output (or clear based on the SETCLR3 field). 0x2 Clear output (or set based on the SETCLR3 field). 0x3 Toggle output. - Reserved All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 F D D 7:6 Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value. A FT Reset value FT A A R R D D D SETCLR2 Description FT FT FT FT 5:4 Value A A A A R R D D D Table 119. SCT bidirectional output control register (OUTPUTDIRCTRL, address 0x5000 4054) bit description Symbol FT FT FT FT FT UM10601 Chapter 10: LPC800 State Configurable Timer (SCT) Bit A A A A A NXP Semiconductors © NXP B.V. 2012. All rights reserved. 125 of 313 D D D D D R R R R R FT FT FT FT FT UM10601 D R R FT FT FT FT A A A A R R D D D Chapter 10: LPC800 State Configurable Timer (SCT) D R R A FT FT FT A A R R D D D R A FT FT A A R R D D This register enables flags to request an interrupt if the FLAGn bit in the SCT event flag register (Section 10.6.15) is also set. F FT FT A A R R D D D 10.6.14 SCT flag enable register A A A A A NXP Semiconductors D D R Table 121. SCT flag enable register (EVEN, address 0x5000 40F0) bit description IEN The SCT requests an interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5). 0 31:6 - Reserved 10.6.15 SCT event flag register This register records events. Writing ones to this register clears the corresponding flags and negates the SCT interrupt request if all enabled Flag bits are zero. Table 122. SCT event flag register (EVFLAG, address 0x5000 40F4) bit description Bit Symbol Description Reset value 5:0 FLAG Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5). 0 31:6 - Reserved - 10.6.16 SCT conflict enable register This register enables the “no change conflict” events specified in the SCT conflict resolution register to request an IRQ. Table 123. SCT conflict enable register (CONEN, address 0x5000 40F8) bit description Bit Symbol Description Reset value 3:0 NCEN The SCT requests interrupt when bit n of this register and the SCT 0 conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 3 = bit 3). 31:4 - Reserved 10.6.17 SCT conflict flag register This register records interrupt-enabled no-change conflict events and provides details of a bus error. Writing ones to the NCFLAG bits clears the corresponding read bits and negates the SCT interrupt request if all enabled Flag bits are zero. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 126 of 313 A 5:0 R Reset value D Description FT Symbol A Bit D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R A 3:0 NCFLAG Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 3 = bit 3). 0 D Reset value FT FT A A R R D Description F FT FT A A R R D D D Symbol D D R A FT - The most recent bus error from this SCT involved writing CTR L/Unified, STATE L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write to certain L and H registers can be half successful and half unsuccessful. 0 31 BUSERRH The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or the Output register when the H counter was not halted. 0 10.6.18 SCT match registers 0 to 4 (REGMODEn bit = 0) Match registers are compared to the counters to help create events. When the UNIFY bit is 0, the L and H registers are independently compared to the L and H counters. When UNIFY is 1, the L and H registers hold a 32-bit value that is compared to the unified counter. A Match can only occur in a clock in which the counter is running (STOP and HALT are both 0). Match registers can be read at any time. Writing to a Match register while the associated counter is running does not affect the Match register and results in a bus error. Match events occur in the SCT clock in which the counter is (or would be) incremented to the next value. When a Match event limits its counter as described in Section 10.6.3, the value in the Match register is the last value of the counter before it is cleared to zero (or decremented if BIDIR is 1). There is no “write-through” from Reload registers to Match registers. Before starting a counter, software can write one value to the Match register used in the first cycle of the counter and a different value to the corresponding Match Reload register used in the second cycle. Table 125. SCT match registers 0 to 4 (MATCH[0:4], address 0x5000 4100 (MATCH0) to 0x5000 4110 (MATCH4)) bit description (REGMODEn bit = 0) Bit Symbol Description Reset value 15:0 VALMATCH_L When UNIFY = 0, read or write the 16-bit value to be compared 0 to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter. 31:16 VALMATCH_H When UNIFY = 0, read or write the 16-bit value to be compared 0 to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter. 10.6.19 SCT capture registers 0 to 4 (REGMODEn bit = 1) These registers allow software to read the counter values at which the event selected by the corresponding Capture Control registers occurred. © NXP B.V. 2012. All rights reserved. 127 of 313 A Reserved. BUSERRL R - 30 D 29:4 Rev. 1.0 — 7 November 2012 FT FT FT FT Bit All information provided in this document is subject to legal disclaimers. A A A A R R D D D Table 124. SCT conflict flag register (CONFLAG, address 0x5000 40FC) bit description Preliminary user manual FT FT FT FT FT UM10601 Chapter 10: LPC800 State Configurable Timer (SCT) UM10601 A A A A A NXP Semiconductors D D D D D R R R R R A A A A A FT FT FT UM10601 FT FT D R R FT FT FT FT Chapter 10: LPC800 State Configurable Timer (SCT) A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D D D R A Reset value 31:16 VALCAP_H When UNIFY = 0, read the 16-bit counter value at which this 0 register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured. A FT FT A D D R A A Match register (L, H, or unified 32-bit) is loaded from the corresponding Reload register when BIDIR is 0 and the counter reaches its limit condition, or when BIDIR is 1 and the counter reaches 0. Table 127. SCT match reload registers 0 to 4 (MATCHREL[0:4], address 0x5000 4200 (MATCHREL0) to 0x5000 4210 (MATCHREL4) bit description (REGMODEn bit = 0) Bit Symbol Description Reset value 15:0 RELOAD_L When UNIFY = 0, read or write the 16-bit value to be loaded into the SCTMATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register. 0 When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register. 0 31:16 RELOAD_H 10.6.21 SCT capture control registers 0 to 4 (REGMODEn bit = 1) If UNIFY = 1 in the CONFIG register, only the _L bits are used. If UNIFY = 0 in the CONFIG register, this register can be written to as two registers CAPCTRLn_L and CAPCTRLn_H. Both the L and H registers can be read or written individually or in a single 32-bit read or write operation. Each Capture Control register (L, H, or unified 32-bit) controls which events load the corresponding Capture register from the counter. Table 128. SCT capture control registers 0 to 4 (CAPCTRL[0:4], address 0x5000 4200 (CAPCTRL0) to 0x5000 4210 (CAPCTRL4)) bit description (REGMODEn bit = 1) UM10601 Preliminary user manual Bit Symbol Description 5:0 CAPCONm_L If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the 0 CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5). 15:6 - Reserved. 20:16 CAPCONm_H If bit m is one, event m causes the CAPn_H (UNIFY = 0) 0 register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 5 = bit 20). 31:17 - Reserved. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 Reset value - © NXP B.V. 2012. All rights reserved. 128 of 313 FT 10.6.20 SCT match reload registers 0 to 4 (REGMODEn bit = 0) A When UNIFY = 0, read the 16-bit counter value at which this 0 register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured. R VALCAP_L D 15:0 R Description R Symbol D D Bit F FT FT A A R R Table 126. SCT capture registers 0 to 4 (CAP[0:4], address 0x5000 4100 (CAP0) to 0x5000 4110 (CAP4)) bit description (REGMODEn bit = 1) D D D D D R R R R R FT FT FT FT FT UM10601 D R R FT FT FT FT A A A A R R D D D Chapter 10: LPC800 State Configurable Timer (SCT) D R R A FT FT FT A A R R D D D R A F FT D FT FT A A R R D Each event has one associated SCT event state mask register that allow this event to happen in one or more states of the counter selected by the HEVENT bit in the corresponding EVn_CTRL register. FT A A R R D D D 10.6.22 SCT event state mask registers 0 to 5 A A A A A NXP Semiconductors D D R A FT D R An event n is disabled when its EVn_STATE register contains all zeros, since it is masked regardless of the current state. A In simple applications that do not use states, write 0x01 to this register to enable an event. Since the state always remains at its reset value of 0, writing 0x01 permanently state-enables this event. Table 129. SCT event state mask registers 0 to 5 (EV[0:5]_STATE, addresses 0x5000 4300 (EV0_STATE) to 0x5000 4328 (EV5_STATE)) bit description Bit Symbol Description Reset value 1:0 STATEMSKm If bit m is one, event n (n= 0 to 5) happens in state m of the 0 counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1). 31:2 - Reserved. - 10.6.23 SCT event control registers 0 to 5 This register defines the conditions for event n to occur, other than the state variable which is defined by the state mask register. Most events are associated with a particular counter (high, low, or unified), in which case the event can depend on a match to that register. The other possible ingredient of an event is a selected input or output signal. When the UNIFY bit is 0, each event is associated with a particular counter by the HEVENT bit in its event control register. An event cannot occur when its related counter is halted nor when the current state is not enabled to cause the event as specified in its event mask register. An event is permanently disabled when its event state mask register contains all 0s. An enabled event can be programmed to occur based on a selected input or output edge or level and/or based on its counter value matching a selected match register (STOP bit = 0). An event can be enabled by the event counter’s HALT bit and STATE register. In bi-directional mode, events can also be enabled based on the direction of count. Each event can modify its counter STATE value. If more than one event associated with the same counter occurs in a given clock cycle, only the state change specified for the highest-numbered event among them takes place. Other actions dictated by any simultaneously occurring events all take place. Table 130. SCT event control register 0 to 5 (EV[0:5]_CTRL, address 0x5000 4304 (EV0_CTRL) to 0x5000 432C (EV5_CTRL)) bit description Bit Symbol Value Description 3:0 MATCHSEL - UM10601 Preliminary user manual Reset value Selects the Match register associated with this event (if any). A match can occur only 0 when the counter selected by the HEVENT bit is running. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 129 of 313 D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D A D D R A IOSEL D OUTSEL FT Selects the H state and the H match register selected by MATCHSEL. A 1 0 R Selects the L state and the L match register selected by MATCHSEL. D 9:6 FT 5 Select L/H counter. Do not set this bit if UNIFY = 1. 0 FT A A R R D Reset value F FT FT A A R R R Value Description D D D HEVENT FT FT FT FT 4 A A A A R R D D D Table 130. SCT event control register 0 to 5 (EV[0:5]_CTRL, address 0x5000 4304 (EV0_CTRL) to 0x5000 432C (EV5_CTRL)) bit description Symbol FT FT FT FT FT UM10601 Chapter 10: LPC800 State Configurable Timer (SCT) Bit A A A A A NXP Semiconductors Input/output select 0 0 Selects the inputs elected by IOSEL. 1 Selects the outputs selected by IOSEL. - Selects the input or output signal associated with this event (if any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event. 0 Bit 6 = 1: CTIN1/CTOUT0 selected. Bit 7 = 1: CTIN1/CTOU1 selected. Bit 8 = 1: CTIN2/CTOUT2 selected. BIt 9 = 1: CTIN3/CTOUT3 selected. 11:10 IOCOND Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period . 0x0 LOW 0x1 Rise 0x2 Fall 0x3 13:12 COMBMODE 14 0 HIGH Selects how the specified match and I/O condition are used and combined. 0x0 OR. The event occurs when either the specified match or I/O condition occurs. 0x1 MATCH. Uses the specified match only. 0x2 IO. Uses the specified I/O condition only. 0x3 AND. The event occurs when the specified match and I/O condition occur simultaneously. STATELD This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state. 0 STATEV value is added into STATE (the carry-out is ignored). 1 STATEV value is loaded into STATE. 19:15 STATEV This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value. 20 If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. MATCHMEM If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 130 of 313 D D D D D R R R R R D R R FT FT FT FT A A A A R R D D D D R R A FT FT FT A A R R D D D D R A D FT A 31:23 - R Counting down. This event is triggered only during down-counting when BIDIR = 1. D Counting up. This event is triggered only during up-counting when BIDIR = 1. 0x2 FT 0x1 A Direction independent. This event is triggered regardless of the count direction. R 0x0 D Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved. D 22:21 DIRECTION FT A A R R D Reset value F FT FT A Value Description A R R D D Table 130. SCT event control register 0 to 5 (EV[0:5]_CTRL, address 0x5000 4304 (EV0_CTRL) to 0x5000 432C (EV5_CTRL)) bit description Symbol FT FT FT FT FT UM10601 Chapter 10: LPC800 State Configurable Timer (SCT) Bit A A A A A NXP Semiconductors Reserved 10.6.24 SCT output set registers 0 to 3 Each output n has one set register that controls how events affect each output. Whether outputs are set or cleared depends on the setting of the SETCLRn field in the SCTOUTPUTDIRCTRL register. Table 131. SCT output set register (OUT[0:3]_SET, address 0x5000 4500 (OUT0_SET) to 0x5000 4518 (OUT3_SET)) bit description Bit Symbol Description Reset value 5:0 SET A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5. 31:6 - Reserved 10.6.25 SCT output clear registers 0 to 3 Each output n has one clear register that controls how events affect each output. Whether outputs are set or cleared depends on the setting of the SETCLRn field in the OUTPUTDIRCTRL register. Table 132. SCT output clear register (OUT[0:3]_CLR, address 0x5000 0504 (OUT0_CLR) to 0x5000 051C (OUT3_CLR)) bit description UM10601 Preliminary user manual Bit Symbol Description 5:0 CLR A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 5 = bit 5. 31:6 - Reserved All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 Reset value © NXP B.V. 2012. All rights reserved. 131 of 313 D D D D D R R R R R FT FT FT FT FT UM10601 D R R FT FT FT FT A A A A R R D D D Chapter 10: LPC800 State Configurable Timer (SCT) D R R A FT FT FT A A R R D D D R F D FT FT A A R R D 10.7.1 Match logic A FT FT A A R R D D D 10.7 Functional description A A A A A NXP Semiconductors D D R A FT D &RXQWHU+ R A 0DWFK 5HORDG L+ 0DWFK 5HJL+ 0DWFKL+ 81,)< 0DWFK 5HORDG L/ 0DWFK 5HJL/ 0DWFKL/ &RXQWHU/ Fig 10. Match logic 10.7.2 Capture logic 6&7FORFN Fig 11. Capture logic 10.7.3 Event selection State variables allow control of the SCT across more than one cycle of the counter. Counter matches, input/output edges, and state values are combined into a set of general-purpose events that can switch outputs, request interrupts, and change state values. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 132 of 313 D D D D D R R R R R D R R FT FT FT FT A A A A R R D D D D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D VHOHFW /PDWFKHV FT FT FT FT FT UM10601 Chapter 10: LPC800 State Configurable Timer (SCT) +PDWFKHV A A A A A NXP Semiconductors D D 0$7&+6(/L R FT HYHQW³L´ VHOHFW A D LQSXWV RXWSXWV R A ,26(/L 2876(/L ,2&21'L &20%02'(L 67$7(0$6.L VHOHFW +67$7( /67$7( +(9(17L Fig 12. Event selection 10.7.4 Output generation Figure 13 shows one output slice of the SCT. (YHQWV 6HW UHJLVWHU³L´ &OHDU UHJLVWHU³L´ 1R&KDQJH&RQIOLFW³L´ 6(7&/5L 2L5(6 6HOHFW 287 UHJ 2XWSXW³L´ 6&7FORFN Fig 13. Output slice i 10.7.5 Interrupt generation The SCT generates one interrupt to the NVIC. (YHQWV (QDEOH UHJLVWHU )ODJV UHJLVWHU 1R&KDQJH &RQIOLFW &RQIOLFWHYHQWV (QDEOH UHJLVWHU 6&7LQWHUUXSW &RQIOLFW )ODJV UHJLVWHU Fig 14. SCT interrupt generation UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 133 of 313 D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D Chapter 10: LPC800 State Configurable Timer (SCT) D R R A FT FT FT A A R R D D D R A F FT D FT FT A A R R D When enabled by a non-zero PRE field in the Control register, the prescaler acts as a clock divider for the counter, like a fractional part of the counter value. The prescaler is cleared whenever the counter is cleared or loaded for any of the following reasons: FT A A R R D D D 10.7.6 Clearing the prescaler FT FT FT UM10601 FT FT NXP Semiconductors D D R A Hardware reset FT D Software writing to the counter register R A • • • • Software writing a 1 to the CLRCTR bit in the control register an event selected by a 1 in the counter limit register when BIDIR = 0 When BIDIR is 0, a limit event caused by an I/O signal can clear a non-zero prescaler. However, a limit event caused by a Match only clears a non-zero prescaler in one special case as described Section 10.7.7. A limit event when BIDIR is 1 does not clear the prescaler. Rather it clears the DOWN bit in the Control register, and decrements the counter on the same clock if the counter is enabled in that clock. 10.7.7 Match vs. I/O events Counter operation is complicated by the prescaler and by clock mode 01 in which the SCT clock is the bus clock. However, the prescaler and counter are enabled to count only when a selected edge is detected on a clock input. • The prescaler is enabled when the clock mode is not 01, or when the input edge selected by the CLKSEL field is detected. • The counter is enabled when the prescaler is enabled, and (PRELIM=0 or the prescaler is equal to the value in PRELIM). An I/O component of an event can occur in any SCT clock when its counter HALT bit is 0. In general, a Match component of an event can only occur in a UT clock when its counter HALT and STOP bits are both 0 and the counter is enabled. Table 133 shows when the various kinds of events can occur. Table 133. Event conditions UM10601 Preliminary user manual COMBMODE IOMODE Event can occur on clock: IO Any Event can occur whenever HALT = 0 (type A). MATCH Any Event can occur when HALT = 0 and STOP = 0 and the counter is enabled (type C). OR Any From the IO component: Event can occur whenever HALT = 0 (A). From the match component: Event can occur when HALT = 0 and STOP = 0 and the counter is enabled (C). AND LOW or HIGH Event can occur when HALT = 0 and STOP = 0 and the counter is enabled (C). AND RISE or FALL Event can occur whenever HALT = 0 (A). All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 134 of 313 D D D D D R R R R R FT FT FT FT FT UM10601 D R R FT FT FT FT A A A A R R D D D Chapter 10: LPC800 State Configurable Timer (SCT) D R R A FT FT FT A A R R D D D R A FT FT A A R R D D In its simplest, single-state configuration, the SCT operates as an event controlled one- or bidirectional counter. Events can be configured to be counter match events, an input or output level, transitions on an input or output pin, or a combination of match and input/output behavior. In response to an event, the SCT output or outputs can transition, or the SCT can perform other actions such as creating an interrupt or starting, stopping, or resetting the counter. Multiple simultaneous actions are allowed for each event. Furthermore, any number of events can trigger one specific action of the SCT. F FT FT A A R R D D D 10.7.8 SCT operation A A A A A NXP Semiconductors D D R A 10.7.9 Configure the SCT To set up the SCT for multiple events and states, perform the following configuration steps: 10.7.9.1 Configure the counter 1. Configure the L and H counters in the CONFIG register by selecting two independent 16-bit counters (L counter and H counter) or one combined 32-bit counter in the UNIFY field. 2. Select the SCT clock source in the CONFIG register (fields CLKMODE and CLKSEL) from any of the inputs or an internal clock. 10.7.9.2 Configure the match and capture registers 1. Select how many match and capture registers the application uses (total of up to 5): – In the REGMODE register, select for each of the 5 match/capture register pairs whether the register is used as a match register or capture register. 2. Define match conditions for each match register selected: – Each match register MATCH sets one match value, if a 32-bit counter is used, or two match values, if the L and H 16-bit counters are used. – Each match reload register MATCHRELOAD sets a reload value that is loaded into the match register when the counter reaches a limit condition or the value 0. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 135 of 313 A • To configure the SCT, see Section 10.7.9. • To start, run, and stop the SCT, see Section 10.7.10. • To configure the SCT as simple event controlled counter/timer, see Section 10.7.11. R Once configured, the SCT can run continuously without software intervention and can generate multiple output patterns entirely under the control of events. D In a multi-state configuration, states change in response to events. A state change is an additional action that the SCT can perform when the event occurs. When an event is configured to change the state, the new state defines a new set of events resulting in different actions of the SCT. Through multiple cycles of the counter, events can change the state multiple times and thus create a large variety of event controlled transitions on the SCT outputs and/or interrupts. FT An action or multiple actions of the SCT uniquely define an event. A state is defined by which events are enabled to trigger an SCT action or actions in any stage of the counter. Events not selected for this state are ignored. D D D D D R R R R R FT FT FT FT FT UM10601 D R R FT FT FT FT A A A A R R D D D Chapter 10: LPC800 State Configurable Timer (SCT) D R R A FT FT FT A A R R D D D R A FT FT A A R R D D 1. Define when each event can occur in the following way in the EVn_CTRL registers (up to 6, one register per event): F FT FT A A R R D D D 10.7.9.3 Configure events and event responses A A A A A NXP Semiconductors D D R A A If using L and H counters, define whether the event occurs on matching the L or the H counter in field HEVENT. – For an SCT input or output level or transition: Select the input number or the output number that is associated with this event in fields IOSEL and OUTSEL. Define how the selected input or output triggers the event (edge or level sensitive) in field IOCOND. 2. Define what the effect of each event is on the SCT outputs in the OUTn_SET or OUTn_CLR registers (up to 4 outputs, one register per output): – For each SCT output, select which events set or clear this output. More than one event can change the output, and each event can change multiple outputs. 3. Define how each event affects the counter: – Set the corresponding event bit in the LIMIT register for the event to set an upper limit for the counter. When a limit event occurs in unidirectional mode, the counter is cleared to zero and begins counting up on the next clock edge. When a limit event occurs in bidirectional mode, the counter begins to count down from the current value on the next clock edge. – Set the corresponding event bit in the HALT register for the event to halt the counter. If the counter is halted, it stops counting and no new events can occur. The counter operation can only be restored by clearing the HALT_L and/or the HALT_H bits in the CTRL register. – Set the corresponding event bit in the STOP register for the event to stop the counter. If the counter is stopped, it stops counting. However, an event that is configured as a transition on an input/output can restart the counter. – Set the corresponding event bit in the START register for the event to restart the counting. Only events that are defined by an input changing can be used to restart the counter. 4. Define which events contribute to the SCT interrupt: – Set the corresponding event bit in the EVEN and the EVFLAG registers to enable the event to contribute to the SCT interrupt. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 R Select the match register that contains the match condition for the event to occur. Enter the number of the selected match register in field MATCHSEL. Preliminary user manual D – For a match condition: UM10601 FT – Select whether the event occurs on an input or output changing, on an input or output level, a match condition of the counter, or a combination of match and input/output conditions in field COMBMODE. © NXP B.V. 2012. All rights reserved. 136 of 313 D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D Chapter 10: LPC800 State Configurable Timer (SCT) D R R A FT FT FT A A R R D D D R A D FT FT A A R R D 1. In the EVn_STATE register for each event (up to 6 events, one register per event), select the state or states (up to 2) in which this event is allowed to occur. Each state can be selected for more than one event. F FT FT A A R R D D D 10.7.9.4 Configure multiple states FT FT FT UM10601 FT FT NXP Semiconductors D D R A 2. Determine how the event affects the system state: FT 10.7.9.5 Miscellaneous options • There are a certain (selectable) number of capture registers. Each capture register can be programmed to capture the counter contents when one or more events occur. • If the counter is in bidirectional mode, the effect of set and clear of an output can be made to depend on whether the counter is counting up or down by writing to the OUTPUTDIRCTRL register. 10.7.10 Run the SCT 1. Configure the SCT (see Section 10.7.9 “Configure the SCT”). 2. Write to the STATE register to define the initial state. By default the initial state is state 0. 3. To start the SCT, write to the CTRL register: – Clear the counters. – Clear or set the STOP_L and/or STOP_H bits. Remark: The counter starts counting once the STOP bit is cleared as well. If the STOP bit is set, the SCT waits instead for an event to occur that is configured to start the counter. – For each counter, select unidirectional or bidirectional counting mode (field BIDIR_L and/or BIDIR_H). – Select the prescale factor for the counter clock (CTRL register). – Clear the HALT_L and/or HALT_H bit. By default, the counters are halted and no events can occur. 4. To stop the counters by software at any time, stop or halt the counter (write to STOP_L and/or STOP_H bits or HALT_L and/or HALT_H bits in the CTRL register). – When the counters are stopped, both an event configured to clear the STOP bit or software writing a zero to the STOP bit can start the counter again. – When the counter are halted, only a software write to clear the HALT bit can start the counter again. No events can occur. – When the counters are halted, software can set any SCT output HIGH or LOW directly by writing to the OUT register. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 137 of 313 A If the STATEV and STATELD values are set to zero, the state does not change. R Remark: If there are higher numbered events in the current state, this event cannot change the state. D In the EVn_CTRL registers (up to 6 events, one register per event), set the new state value in the STATEV field for this event. If the event is the highest numbered in the current state, this value is either added to the existing state value or replaces the existing state value, depending on the field STATELD. D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D Chapter 10: LPC800 State Configurable Timer (SCT) D R R A FT FT FT A A R R D D D R A FT FT A A R R D D To change the current state by software (that is independently of any event occurring), set the HALT bit and write to the STATE register to change the state value. Writing to the STATE register is only allowed when the counter is halted (the HALT_L and/or HALT_H bits are set) and no events can occur. F FT FT A A R R D D D The current state can be read at any time by reading the STATE register. FT FT FT UM10601 FT FT NXP Semiconductors D D R A FT D R A 10.7.11 Configure the SCT without using states The SCT can be used as standard counter/timer with external capture inputs and match outputs without using the state logic. To operate the SCT without states, configure the SCT as follows: • Write zero to the STATE register (zero is the default). • Write zero to the STATELD and STATEV fields in the EVCTRL registers for each event. • Write 0x1 to the EVn_STATE register of each event. Writing 0x1 enables the event. In effect, the event is allowed to occur in a single state which never changes while the counter is running. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 138 of 313 D D R R R R R A A A A A FT FT FT FT FT D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D Chapter 11: LPC800 Multi-Rate Timer (MRT) R A F FT FT A A R R D D Preliminary user manual D Rev. 1.0 — 7 November 2012 D D D UM10601 D FT FT A A R R D D D 11.1 How to read this chapter R A FT D The MRT is available on all LPC800 parts. R A 11.2 Features • 24-bit interrupt timer • Four channels independently counting down from individually set values • Repeat and one-shot interrupt modes 11.3 Basic configuration Configure the MRT using the following registers: • In the SYSAHBCLKCTRL register, set bit 10 (Table 18) to enable the clock to the register interface. • Clear the MRT reset using the PRESETCTRL register (Table 7). • The global MRT interrupt is connected to interrupt #10 in the NVIC. 11.4 Pin description The MRT has no configurable pins. 11.5 General description The Multi-Rate Timer (MRT) provides a repetitive interrupt timer with four channels. Each channel can be programmed with an independent time interval. Each channel operates independently from the other channels in one of the following modes: • Repeat interrupt mode. See Section 11.5.1. • One-shot interrupt mode. See Section 11.5.2. The modes for each timer are set in the timer’s control register. See Table 137. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 139 of 313 D D D D D R R R R R A A A A A FT FT FT UM10601 FT FT D R R FT FT FT FT Chapter 11: LPC800 Multi-Rate Timer (MRT) A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D D D R A ' 4 ,54B*(1 ,54 A '(& R 08; D 4 FT =(526 ' 7,0(5 ,179$/ %86 &21752/ 67$7 &+$11(/ ,54>@ &+$11(/>@ Fig 15. MRT block diagram 11.5.1 Repeat interrupt mode The repeat interrupt mode generates repeated interrupts after a selected time interval. This mode can be used for software-based PWM or PPM applications. When the timer n is in idle state, writing a non-zero value IVALUE to the INTVALn register immediately loads the time interval value IVALUE - 1, and the timer begins to count down from this value. When the timer reaches zero, an interrupt is generated, the value in the INTVALn register IVALUE - 1 is reloaded automatically, and the timer starts to count down again. While the timer is running in repeat interrupt mode, you can perform the following actions: • Change the interval value on the next timer cycle by writing a new value (>0) to the INTVALn register and setting the LOAD bit to 0. An interrupt is generated when the timer reaches zero. On the next cycle, the timer counts down from the new value. • Change the interval value on-the-fly immediately by writing a new value (>0) to the INTVALn register and setting the LOAD bit to 1. The timer immediately starts to count down from the new timer interval value. An interrupt is generated when the timer reaches 0. • Stop the timer at the end of time interval by writing a 0 to the INTVALn register and setting the LOAD bit to 0. An interrupt is generated when the timer reaches zero. • Stop the timer immediately by writing a 0 to the INTVALn register and setting the LOAD bit to 1. No interrupt is generated when the INTVALn register is written. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 140 of 313 D D D D D R R R R R FT FT FT FT FT UM10601 D R R FT FT FT FT A A A A R R D D D Chapter 11: LPC800 Multi-Rate Timer (MRT) D R R A FT FT FT A A R R D D D R A FT FT A A R R D D The one-shot interrupt generates one interrupt after a one-time count. With this mode, you can generate a single interrupt at any point. This mode can be used to introduce a specific delay in a software task. F FT FT A A R R D D D 11.5.2 One-shot interrupt mode A A A A A NXP Semiconductors D D R A • Write a 0 to the INTVALn register and set the LOAD bit to 1. The timer immediately stops counting and moves to the idle state. No interrupt is generated when the INTVALn register is updated. 11.6 Register description The reset values shown in Table 134 are POR reset values. Table 134. Register overview: MRT (base address 0x4000 4000) Name Access Address Description offset Reset value Reference INTVAL0 R/W 0x0 MRT0 Time interval value register. This value is loaded into the TIMER0 register. 0 Table 135 TIMER0 R 0x4 MRT0 Timer register. This register reads the value of the down-counter. 0x00FF FFFF Table 136 CTRL0 R/W 0x8 MRT0 Control register. This register controls the MRT0 modes. 0 Table 137 STAT0 R/W 0xC MRT0 Status register. 0 Table 138 INTVAL1 R/W 0x10 MRT1 Time interval value register. This value is loaded into the TIMER1 register. 0 Table 135 TIMER1 R/W 0x14 MRT1 Timer register. This register reads the value of the down-counter. 0x00FF FFFF Table 136 CTRL1 R/W 0x18 MRT1 Control register. This register controls the MRT1 modes. 0 Table 137 STAT1 R/W 0x1C MRT1 Status register. 0 Table 138 INTVAL2 R/W 0x20 MRT2 Time interval value register. This value is loaded into the TIMER2 register. 0 Table 135 TIMER2 R/W 0x24 MRT2 Timer register. This register reads the value of the down-counter. 0x00FF FFFF Table 136 CTRL2 R/W 0x28 MRT2 Control register. This register controls the MRT2 modes. 0 Table 137 STAT2 R/W 0x2C MRT2 Status register. 0 Table 138 UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 141 of 313 A to 1. The timer immediately reloads the new time interval, and starts counting down from the new value. No interrupt is generated when the TIME_INTVALn register is updated. R • Update the INTVALn register with a new time interval value (>0) and set the LOAD bit D While the timer is running in the one-shot interrupt mode, you can perform the following actions: FT When the timer is in the idle state, writing a non-zero value IVALUE to the INTVALn register immediately loads the time interval value IVALUE - 1, and the timer starts to count down. When the timer reaches 0, an interrupt is generated and the timer stops and enters the idle state. D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R Reset value Reference INTVAL3 R/W 0x30 MRT3 Time interval value register. This value is loaded into the TIMER3 register. 0 TIMER3 R/W 0x34 MRT3 Timer register. This register reads the value of the down-counter. 0x00FF FFFF Table 136 CTRL3 R/W 0x38 MRT3 Control register. This register controls the MRT modes. 0 Table 137 STAT3 R/W 0x3C MRT3 Status register. 0 Table 138 IDLE_CH R 0xF4 Idle channel register. This register returns the number of the first idle channel. 0 Table 139 IRQ_FLAG R/W 0xF8 Global interrupt flag register 0 Table 140 D A A R R D FT FT Table 135 D D R A D R Table 135. Time interval register (INTVAL[0:3], address 0x4000 4000 (INTVAL0) to 0x4000 4030 (INTVAL3)) bit description Bit Symbol Value Description Reset value 23:0 IVALUE Time interval load value. This value is loaded into the TIMERn register and the MRTn starts counting down from IVALUE -1. 0 If the timer is idle, writing a non-zero value to this bit field starts the timer immediately. If the timer is running, writing a zero to this bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer stops at the end of the time interval. 30:24 - Reserved. 0 31 LOAD Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0. 0 0 No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the time interval if the repeat mode is selected. 1 Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running. © NXP B.V. 2012. All rights reserved. 142 of 313 A This register contains the MRT load value and controls how the timer is reloaded. The load value is IVALUE -1. Rev. 1.0 — 7 November 2012 FT 11.6.1 Time interval register All information provided in this document is subject to legal disclaimers. F FT FT Address Description offset A A A R R D D D Access Preliminary user manual FT FT FT FT Name UM10601 A A A A R R D D D Table 134. Register overview: MRT (base address 0x4000 4000) FT FT FT FT FT UM10601 Chapter 11: LPC800 Multi-Rate Timer (MRT) • • A A A A A NXP Semiconductors D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R R FT FT A A R D D INTVALn register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields returns -1 (0x00FF FFFF). 0 11.6.3 Control register The control register configures the the mode for each MRT and enables the interrupt. Table 137. Control register (CTRL[0:3], address 0x4000 4008 (CTRL0) to 0x4000 4038 (CTRL3)) bit description Symbol 0 INTEN Value 0 31:3 UM10601 Preliminary user manual Enable the TIMERn interrupt. 0 Enable. MODE - Reset value Disable. 1 2:1 Description Selects timer mode. 0x0 Repeat interrupt mode. 0x1 One-shot interrupt mode. 0x2 Reserved. 0x3 Reserved. Reserved. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 0 0 © NXP B.V. 2012. All rights reserved. 143 of 313 A INTVALn register is updated in the idle state. R 0x00FF FFFF D VALUE FT 23:0 A Reset value R Symbol Description Bit F D D Bit Holds the current timer value of the down-counter. The initial value of the TIMERn register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval or immediately in the following cases: A FT FT A A R R D D D Table 136. Timer register (TIMER[0:3], address 0x4000 4004 (TIMER0) to 0x4000 4034 (TIMER3)) bit description Reserved. FT FT FT FT The timer register holds the current timer value. This register is read-only. - A A A A R R D D D 11.6.2 Timer register FT FT FT FT FT UM10601 Chapter 11: LPC800 Multi-Rate Timer (MRT) 31:24 A A A A A NXP Semiconductors D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D Chapter 11: LPC800 Multi-Rate Timer (MRT) D R R A FT FT FT A A R R D D D A F D A A R R D This register indicates the status of each MRT. R FT FT A A R R D D D 11.6.4 Status register FT FT FT UM10601 FT FT NXP Semiconductors FT FT Table 138. Status register (STAT[0:3], address 0x4000 400C (STAT0) to 0x4000 403C (STAT3)) bit description D D R Monitors the interrupt flag. 0 0 No pending interrupt. Writing a zero is equivalent to no operation. 1 Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request. 1 31:2 RUN Indicates the state of TIMERn. This bit is read-only. 0 Idle state. TIMERn is stopped. 1 Running. TIMERn is running. - Reserved. 0 0 11.6.5 Idle channel register The idle channel register returns the lowest idle channel number. The channel is considered idle when both flags is the STATUS register (RUN and INTFLAG) are zero. In an application with multiple timers running independently, you can calculate the register offset of the next idle timer by reading the idle channel number in this register. The idle channel register allows you set up the next idle timer without checking the idle state of each timer. Table 139. Idle channel register (IDLE_CH, address 0x4000 40F4) bit description Bit UM10601 Preliminary user manual Symbol Description Reset value 3:0 - Reserved. 0 7:4 CHAN Idle channel. Reading the CHAN bits, returns the lowest idle timer channel. If all timer channels are running, CHAN = 0xF. 0 31:8 - Reserved. 0 All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 144 of 313 A Reset value R INTFLAG Description D 0 Value FT Symbol A Bit D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D Chapter 11: LPC800 Multi-Rate Timer (MRT) D R R A FT FT FT A A R R D D D R A F FT D FT FT A A R R D The global interrupt register combines the interrupt flags from the individual timer channels in one register. Setting and clearing each flag behaves in the same way as setting and clearing the INTFLAG bit in each of the STATUSn registers. FT A A R R D D D 11.6.6 Global interrupt flag register FT FT FT UM10601 FT FT NXP Semiconductors D D R Monitors the interrupt flag of TIMER0. 0 0 No pending interrupt. Writing a zero is equivalent to no operation. 1 Pending interrupt. The interrupt is pending because TIMER0 has reached the end of the time interval. If the INTEN bit in the CONTROL0 register is also set to 1, the interrupt for timer channel 0 and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request. 1 GFLAG1 Monitors the interrupt flag of TIMER1. 0 0 No pending interrupt. Writing a zero is equivalent to no operation. 1 Pending interrupt. The interrupt is pending because TIMER1 has reached the end of the time interval. If the INTEN bit in the CONTROL1 register is also set to 1, the interrupt for timer channel 1 and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request. 2 GFLAG2 Monitors the interrupt flag of TIMER2. 0 0 No pending interrupt. Writing a zero is equivalent to no operation. 1 Pending interrupt. The interrupt is pending because TIMER2 has reached the end of the time interval. If the INTEN bit in the CONTROL2 register is also set to 1, the interrupt for timer channel 2 and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request. 3 GFLAG3 Monitors the interrupt flag of TIMER3. 0 0 No pending interrupt. Writing a zero is equivalent to no operation. 1 Pending interrupt. The interrupt is pending because TIMER3 has reached the end of the time interval. If the INTEN bit in the CONTROL3 register is also set to 1, the interrupt for timer channel 3 and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request. 31:4 UM10601 Preliminary user manual - Reserved. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 0 © NXP B.V. 2012. All rights reserved. 145 of 313 A GFLAG0 Reset value R 0 Value Description D Symbol FT Bit A Table 140. Global interrupt flag register (IRQ_FLAG, address 0x4000 40F8) bit description D D D D D A A A A A FT FT FT FT FT D R R A A FT FT FT FT A A R R D D D R R A FT FT FT A A R R D D D D Chapter 12: LPC800 Windowed Watchdog Timer (WWDT) R A F FT FT A A R R D D Preliminary user manual D Rev. 1.0 — 7 November 2012 R R R R R UM10601 D FT FT A A R R D D D 12.1 How to read this chapter R A FT D The watchdog timer is identical on all LPC800 parts. R A 12.2 Features • Internally resets chip if not reloaded during the programmable time-out period. • Optional windowed operation requires reload to occur between a minimum and maximum time-out period, both programmable. • Optional warning interrupt can be generated at a programmable time prior to watchdog time-out. • Programmable 24-bit timer with internal fixed pre-scaler. • Selectable time period from 1,024 watchdog clocks (TWDCLK 256 4) to over 67 million watchdog clocks (TWDCLK 224 4) in increments of 4 watchdog clocks. • “Safe” watchdog operation. Once enabled, requires a hardware reset or a Watchdog reset to be disabled. • Incorrect feed sequence causes immediate watchdog event if enabled. • The watchdog reload value can optionally be protected such that it can only be changed after the “warning interrupt” time is reached. • • • • Flag to indicate Watchdog reset. The Watchdog clock (WDCLK) source is the WatchDog oscillator. The Watchdog timer can be configured to run in Deep-sleep or Power-down mode. Debug mode. 12.3 Basic configuration The WWDT is configured through the following registers: • Power to the register interface (WWDT PCLK clock): In the SYSAHBCLKCTRL register, set bit 17 in Table 18. • Enable the WWDT clock source (the watchdog oscillator) in the PDRUNCFG register (Table 37). This is the clock source for the timer base. • For waking up from a WWDT interrupt, enable the watchdog interrupt for wake-up in the STARTERP1 register (Table 34). 12.4 Pin description The WWDT has no external pins. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 146 of 313 D D D D D R R R R R FT FT FT FT FT UM10601 D R R FT FT FT FT A A A A R R D D D Chapter 12: LPC800 Windowed Watchdog Timer (WWDT) D R R A FT FT FT A A R R D D D R A D FT FT A A R R D The purpose of the Watchdog Timer is to reset or interrupt the microcontroller within a programmable time if it enters an erroneous state. When enabled, a watchdog reset is generated if the user program fails to feed (reload) the Watchdog within a predetermined amount of time. F FT FT A A R R D D D 12.5 General description A A A A A NXP Semiconductors D D R A FT D • Set the Watchdog timer constant reload value in the TC register. • Set the Watchdog timer operating mode in the MOD register. • Set a value for the watchdog window time in the WINDOW register if windowed operation is desired. • Set a value for the watchdog warning interrupt in the WARNINT register if a warning interrupt is desired. • Enable the Watchdog by writing 0xAA followed by 0x55 to the FEED register. • The Watchdog must be fed again before the Watchdog counter reaches zero in order to prevent a watchdog event. If a window value is programmed, the feed must also occur after the watchdog counter passes that value. When the Watchdog Timer is configured so that a watchdog event will cause a reset and the counter reaches zero, the CPU will be reset, loading the stack pointer and program counter from the vector table as for an external reset. The Watchdog time-out flag (WDTOF) can be examined to determine if the Watchdog has caused the reset condition. The WDTOF flag must be cleared by software. When the Watchdog Timer is configured to generate a warning interrupt, the interrupt will occur when the counter matches the value defined by the WARNINT register. 12.5.1 Block diagram The block diagram of the Watchdog is shown below in the Figure 16. The synchronization logic (PCLK - WDCLK) is not shown in the block diagram. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 147 of 313 A The Watchdog consists of a fixed (divide by 4) pre-scaler and a 24-bit counter which decrements when clocked. The minimum value from which the counter decrements is 0xFF. Setting a value lower than 0xFF causes 0xFF to be loaded in the counter. Hence the minimum Watchdog interval is (TWDCLK 256 4) and the maximum Watchdog interval is (TWDCLK 224 4) in multiples of (TWDCLK 4). The Watchdog should be used in the following manner: R When a watchdog window is programmed, an early watchdog feed is also treated as a watchdog event. This allows preventing situations where a system failure may still feed the watchdog. For example, application code could be stuck in an interrupt service that contains a watchdog feed. Setting the window such that this would result in an early feed will generate a watchdog event, allowing for system recovery. D D D D D R R R R R D R R FT D R FT FT A A R R A FT :'79 D :,1'2: D D R A :'3527(&7 02' > @ FRPSDUH :',179$/ FRPSDUH FRPSDUH XQGHUIORZ :'72) 02' >@ LQWHUUXSW FRPSDUH :',17 02' >@ :'5(6(7 02' >@ :'(1 02' >@ FKLSUHVHW ZDWFKGRJ LQWHUUXSW Fig 16. Windowed Watchdog timer block diagram 12.5.2 Clocking and power control The watchdog timer block uses two clocks: PCLK and WDCLK. PCLK is used for the APB accesses to the watchdog registers and is derived from the system clock (see Figure 3). The WDCLK is used for the watchdog timer counting and is derived from the watchdog oscillator. The synchronization logic between the two clock domains works as follows: When the MOD and TC registers are updated by APB operations, the new value will take effect in 3 WDCLK cycles on the logic in the WDCLK clock domain. When the watchdog timer is counting on WDCLK, the synchronization logic will first lock the value of the counter on WDCLK and then synchronize it with PCLK, so that the CPU can read the WDTV register. Remark: Because of the synchronization step, software must add a delay of three WDCLK clock cycles between the feed sequence and the time the WDPROTECT bit is enabled in the MOD register. The length of the delay depends on the selected watchdog clock WDCLK. UM10601 Preliminary user manual F D D HQDEOHFRXQW VKDGRZELW IHHGRN 02' UHJLVWHU A FT FT A A R R R 7&ZULWH IHHGRN IHHGHUURU R A D D LQ IHHGVHTXHQFH UDQJH GHWHFWDQG SURWHFWLRQ D R FT FT A A R R D D D ELWGRZQFRXQWHU )((' FT FT FT FT · A A A A R R D D D 7& IHHGRN FT FT FT FT FT UM10601 Chapter 12: LPC800 Windowed Watchdog Timer (WWDT) ZGBFON A A A A A NXP Semiconductors All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 148 of 313 D D D D D R R R R R FT FT FT FT FT UM10601 D R R FT FT FT FT A A A A R R D D D Chapter 12: LPC800 Windowed Watchdog Timer (WWDT) D R R A FT FT FT A A R R D D D R A FT FT A A R R D D The WWDT supports several lock features which can be enabled to ensure that the WWDT is running at all times: F FT FT A A R R D D D 12.5.3 Using the WWDT lock features A A A A A NXP Semiconductors D D • Disabling the WWDT clock source • Changing the WWDT reload value R A FT D R A 12.5.3.1 Disabling the WWDT clock source If bit 5 in the WWDT MOD register is set, the WWDT clock source is locked and can not be disbled either by software or by hardware when Sleep, Deep-sleep or Power-down modes are entered. Therefore, the user must ensure that the watchdog oscillator for each power mode is enabled before setting bit 5 in the MOD register. In Deep power-down mode, no clock locking mechanism is in effect because no clocks are running. However, an additional lock bit in the PMU can be set to prevent the part from even entering Deep power-down mode (see Table 42). 12.5.3.2 Changing the WWDT reload value If bit 4 is set in the WWDT MOD register, the watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW. The reload overwrite lock mechanism can only be disabled by a reset of any type. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 149 of 313 D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D Chapter 12: LPC800 Windowed Watchdog Timer (WWDT) D R R A FT FT FT A A R R D D D R F D FT FT A A R R D The Watchdog Timer contains the registers shown in Table 141. A FT FT A A R R D D D 12.6 Register description FT FT FT UM10601 FT FT NXP Semiconductors D D The reset value reflects the data stored in used bits only. It does not include the content of reserved bits. R A FT D R Name Access Address Description offset MOD R/W 0x000 Watchdog mode register. This 0 register contains the basic mode and status of the Watchdog Timer. Table 142 TC R/W 0x004 Watchdog timer constant register. This 24-bit register determines the time-out value. Table 144 FEED WO 0x008 Watchdog feed sequence register. NA Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. Table 145 TV RO 0x00C Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. 0xFF Table 146 - - 0x010 Reserved - - WARNINT R/W 0x014 Watchdog Warning Interrupt compare 0 value. WINDOW 0x018 Watchdog Window compare value. R/W Reset value A Table 141. Register overview: Watchdog timer (base address 0x4000 4000) 0xFF Reference Table 147 0xFF FFFF Table 148 12.6.1 Watchdog mode register The WDMOD register controls the operation of the Watchdog. Note that a watchdog feed must be performed before any changes to the WDMOD register take effect. Table 142. Watchdog mode register (MOD - 0x4000 4000) bit description Bit Symbol 0 WDEN 1 2 UM10601 Preliminary user manual Value Description Watchdog enable bit. Once this bit has been written with 0 a 1, it cannot be re-written with a 0. Once this bit is set to one, the watchdog timer starts running after a watchdog feed. 0 The watchdog timer is stopped. 1 The watchdog timer is running. WDRESET WDTOF Reset value Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0. 0 A watchdog time-out will not cause a chip reset. 1 A watchdog time-out will cause a chip reset. Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT. Cleared by software. Causes a chip reset if WDRESET = 1. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 0 0 (only after external reset) © NXP B.V. 2012. All rights reserved. 150 of 313 D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D 4 WDPROTECT Watchdog update mode. This bit can be set once by software and is only cleared by a reset. 0 FT D R A FT D R A 31:6 - D The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW. FT 1 A The watchdog time-out value (TC) can be changed at any time. A R R D 0 A 1 in this bit prevents disabling or powering down the watchdog oscillator. This bit can be set once by software and is only cleared by any reset. 0 Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA Once the WDEN, WDPROTECT, or WDRESET bits are set they can not be cleared by software. Both flags are cleared by an external reset or a Watchdog timer reset. WDTOF The Watchdog time-out flag is set when the Watchdog times out, when a feed error occurs, or when PROTECT =1 and an attempt is made to write to the TC register. This flag is cleared by software writing a 0 to this bit. WDINT The Watchdog interrupt flag is set when the Watchdog counter reaches the value specified by WARNINT. This flag is cleared when any reset occurs, and is cleared by software by writing a 0 to this bit. In all power modes except Deep power-down mode, a Watchdog reset or interrupt can occur when the watchdog is running and has an operating clock source. The watchdog oscillator can be configured to keep running in Sleep, Deep-sleep modes, and Power-down modes. If a watchdog interrupt occurs in Sleep, Deep-sleep mode, or Power-down mode, and the WWDT interrupt is enabled in the NVIC, the device will wake up. Note that in Deep-sleep and Power-down modes, the WWDT interrupt must be enabled in the STARTERP1 register in addition to the NVIC. See the following registers: Table 34 “Start logic 1 interrupt wake-up enable register (STARTERP1, address 0x4004 8214) bit description” UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 F 0 A Warning interrupt flag. Set when the timer reaches the value in WDWARNINT. Cleared by software. R WDINT D 3 FT Reset value FT A Symbol A R R D D D Bit LOCK FT FT FT FT Value Description A A A A R R D D D Table 142. Watchdog mode register (MOD - 0x4000 4000) bit description FT FT FT FT FT UM10601 Chapter 12: LPC800 Windowed Watchdog Timer (WWDT) 5 A A A A A NXP Semiconductors © NXP B.V. 2012. All rights reserved. 151 of 313 D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R FT FT A A R R Watchdog interrupt mode: the watchdog warning interrupt will be generated but watchdog reset will not. D D R A Table 144. Watchdog Timer Constant register (TC - 0x4000 4004) bit description Bit Symbol Description Reset Value 23:0 COUNT Watchdog time-out value. 0x00 00FF Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 12.6.3 Watchdog Feed register Writing 0xAA followed by 0x55 to this register will reload the Watchdog timer with the WDTC value. This operation will also start the Watchdog if it is enabled via the WDMOD register. Setting the WDEN bit in the WDMOD register is not sufficient to enable the Watchdog. A valid feed sequence must be completed after setting WDEN before the Watchdog is capable of generating a reset. Until then, the Watchdog will ignore feed errors. After writing 0xAA to WDFEED, access to any Watchdog register other than writing 0x55 to WDFEED causes an immediate reset/interrupt when the Watchdog is enabled, and sets the WDTOF flag. The reset will be generated during the second PCLK following an incorrect access to a Watchdog register during a feed sequence. It is good practice to disable interrupts around a feed sequence, if the application is such that an interrupt might result in rescheduling processor control away from the current task in the middle of the feed, and then lead to some other access to the WDT before control is returned to the interrupted task. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 152 of 313 A If the WDPROTECT bit in WDMOD = 1, an attempt to change the value of TC before the watchdog counter is below the values of WDWARNINT and WDWINDOW will cause a watchdog reset and set the WDTOF flag. R The TC register determines the time-out value. Every time a feed sequence occurs the value in the TC is loaded into the Watchdog timer. The TC resets to 0x00 00FF. Writing a value below 0xFF will cause 0x00 00FF to be loaded into the TC. Thus the minimum time-out interval is TWDCLK 256 4. D 12.6.2 Watchdog Timer Constant register FT Watchdog reset mode: both the watchdog interrupt and watchdog reset are enabled. When this mode is selected, the watchdog counter reaching the value specified by WDWARNINT will set the WDINT flag and the Watchdog interrupt request will be generated, and the watchdog counter reaching zero will reset the microcontroller. A watchdog feed prior to reaching the value of WDWINDOW will also cause a watchdog reset. Preliminary user manual F D D Debug/Operate without the Watchdog running. 0 When this mode is selected, the watchdog counter reaching the value specified by WDWARNINT will set the WDINT flag and the Watchdog interrupt request will be generated. UM10601 A FT FT A A R R D D D X (0 or 1) 1 31:24 - FT FT FT FT 0 1 A A A A R R D D D WDEN WDRESET Mode of Operation 1 FT FT FT FT FT UM10601 Chapter 12: LPC800 Windowed Watchdog Timer (WWDT) Table 143. Watchdog operating modes selection A A A A A NXP Semiconductors D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D Chapter 12: LPC800 Windowed Watchdog Timer (WWDT) D R R A FT FT FT A A R R D D D R Reset Value 7:0 FEED Feed value should be 0xAA followed by 0x55. NA 31:8 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA F Description D Symbol FT FT A A R R D Bit A FT FT A A R R D D D Table 145. Watchdog Feed register (FEED - 0x4000 4008) bit description FT FT FT UM10601 FT FT NXP Semiconductors D D R A FT D R A 12.6.4 Watchdog Timer Value register The WDTV register is used to read the current value of Watchdog timer counter. When reading the value of the 24-bit counter, the lock and synchronization procedure takes up to 6 WDCLK cycles plus 6 PCLK cycles, so the value of WDTV is older than the actual value of the timer when it's being read by the CPU. Table 146. Watchdog Timer Value register (TV - 0x4000 400C) bit description Bit Symbol Description Reset Value 23:0 COUNT Counter timer value. 0x00 00FF 31:24 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 12.6.5 Watchdog Timer Warning Interrupt register The WDWARNINT register determines the watchdog timer counter value that will generate a watchdog interrupt. When the watchdog timer counter matches the value defined by WARNINT, an interrupt will be generated after the subsequent WDCLK. A match of the watchdog timer counter to WARNINT occurs when the bottom 10 bits of the counter have the same value as the 10 bits of WARNINT, and the remaining upper bits of the counter are all 0. This gives a maximum time of 1,023 watchdog timer counts (4,096 watchdog clocks) for the interrupt to occur prior to a watchdog event. If WARNINT is 0, the interrupt will occur at the same time as the watchdog event. Table 147. Watchdog Timer Warning Interrupt register (WARNINT - 0x4000 4014) bit description Bit Symbol 9:0 WARNINT Watchdog warning interrupt compare value. 31:10 - Description Reset Value 0 Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 12.6.6 Watchdog Timer Window register The WINDOW register determines the highest WDTV value allowed when a watchdog feed is performed. If a feed sequence occurs when WDTV is greater than the value in WINDOW, a watchdog event will occur. WINDOW resets to the maximum possible WDTV value, so windowing is not in effect. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 153 of 313 D D D D D R R R R R D R R R A FT R F D A A R R D FT 0xFF FFFF FT D A NA R FT Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. D 31:24 - A FT Reset Value FT A A R R D D D WINDOW Watchdog window value. D R FT FT A A R R D D D 23:0 FT FT FT FT Description A A A A R R D D D Table 148. Watchdog Timer Window register (WINDOW - 0x4000 4018) bit description Symbol FT FT FT FT FT UM10601 Chapter 12: LPC800 Windowed Watchdog Timer (WWDT) Bit A A A A A NXP Semiconductors D R A 12.7 Functional description The following figures illustrate several aspects of Watchdog Timer operation. :'&/. :DWFKGRJ &RXQWHU $ (DUO\)HHG (YHQW :DWFKGRJ 5HVHW &RQGLWLRQV :,1'2: :$51,17 7& [ [)) [ Fig 17. Early watchdog feed with windowed mode enabled :'&/. :DWFKGRJ &RXQWHU )) )( )' )& ))) ))( ))' ))& &RUUHFW)HHG (YHQW :DWFKGRJ 5HVHW &RQGLWLRQV :':,1'2: [ :':$51,17 [)) :'7& [ Fig 18. Correct watchdog feed with windowed mode enabled :'&/. :DWFKGRJ &RXQWHU )) )( )' )& )% )$ ) :DWFKGRJ ,QWHUUXSW &RQGLWLRQV :,1'2: :$51,17 7& [ [)) [ Fig 19. Watchdog warning interrupt UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 154 of 313 D D R R R R R A A A A A FT FT FT FT FT D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D Chapter 13: LPC800 Analog comparator R A F FT FT A A R R D D Preliminary user manual D Rev. 1.0 — 7 November 2012 D D D UM10601 D FT FT A A R R D D D 13.1 How to read this chapter R A FT D The analog comparator is available on all LPC800 parts. R A 13.2 Features • Selectable external inputs can be used as either the positive or negative input of the comparator. • The Internal voltage reference (0.9 V bandgap reference) can be used as either the positive or negative input of the comparator. • 32-stage voltage ladder can be used as either the positive or negative input of the comparator. • Voltage ladder source selectable between the supply pin VDD or VDDCMP pin. • Voltage ladder can be separately powered down when not required. • Interrupt capability 13.3 Basic configuration Configure the analog comparator using the following registers: • In the SYSAHBCLKCTRL register, set bit 19 (Table 18) to enable the clock to the register interface. • You can enable or disable the power to the analog comparator through the PDRUNCFG register (Table 37). • Clear the analog comparator peripheral reset using the PRESETCTRL register (Table 7). • The analog comparator interrupt is connected to interrupt #11 in the NVIC. • Configure the analog comparator pin functions through the switch matrix. See Section 13.4. 13.3.1 Connect the comparator output to the SCT You can use the comparator output function (ACMP_O) to start or stop the SCT or, more generally, create an SCT event. To create an SCT event, connect AMP_O as follows: 1. Using the switch matrix, connect ACMP_O to a pin. See Table 149. 2. Using the switch matrix, connect any of the SCT input functions to the same pin. See Table 106. The selected SCT input can now monitor the ACMP_O function. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 155 of 313 D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D Chapter 13: LPC800 Analog comparator D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D 13.4 Pin description FT FT FT UM10601 FT FT NXP Semiconductors D FT FT A A R R D The analog comparator reference voltage, the inputs, and the output are assigned to external pins through the switch matrix. You can assign the analog comparator output to any pin on the package that is not a supply or ground pin. The comparator inputs and the reference voltage are fixed-pin functions that must be enabled through the switch matrix and can only be assigned to special pins on the package. D D R A FT D R A See Section 9.3.1 “Connect an internal signal to a package pin” to assign the analog comparator output to any pin on the LPC800 package. See Section 9.3.2 to enable the analog comparator inputs and the reference voltage input. Table 149. Analog comparator pin description Function Type Pin Description SWM register Reference ACMP_I1 I PIO0_0/ACMP_I1 Comparator input 1 PINENABLE0 Section 9.5.10 ACMP_I2 I PIO0_0/ACMP_I2/CLKIN Comparator input 2. Disable the CLKIN PINENABLE0 function in the PINSASSIGN1BIT0 register. Section 9.5.10 ACMP_O O any Comparator output PINASSIGN8 Section 9.5.9 VDDCMP I PIO0_6/VDDCMP External reference voltage source for 32-stage Voltage Ladder. PINENABLE0 Section 9.5.10 13.5 General description The analog comparator can compare voltage levels on external pins and internal voltages. The comparator has 8 inputs multiplexed separately to its positive and negative inputs. The multiplexers are controlled by the comparator register CTL (see Figure 20 and Table 151). Input 0 of the multiplexers is the programmable voltage ladder output. Bits 2:1 control the external inputs ACMP_I[2:1]. Bits 6 of the multiplexers controls internal reference voltage input. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 156 of 313 D D D D D R R R R R D R R FT FT FT FT D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D /$'5() A A A A R R D D D 9'' FT FT FT FT FT UM10601 Chapter 13: LPC800 Analog comparator H[W9''&03 A A A A A NXP Semiconductors D D R A /$'(1Q$&203B3' FT 92/7$*( /$''(5287 D R A &203B93B6(/ /$'6(/ $&203B3' $&03B, $&03B, EXI EXI 966 966 966 &20367$7 QF LQWHUQDO9%$1'*$3 966 +<6 '4 &203B90B6(/ ('*(6(/ $&203B567B1 &21752/67$7865(*,67(5%,76 '4 6<1& &2036$ 64 5 2) 6$03/,1* ('*('(7(&7 WR$&03B2 &203('*( WR,17(55837 ('*(&/5RU $&203B567B1 Fig 20. Comparator block diagram 13.5.1 Reference voltages The voltage ladder can use two reference voltages, from the VDDCMP or the VDD pin. The voltage ladder selects one of 32 steps between the pin voltage and VSS inclusive. The voltage on VDDCMP should not exceed that on VDD . 13.5.2 Settling times After the voltage ladder is powered on, it requires stabilization time until comparisons using it are accurate. Much shorter settling times apply after the LADSEL value is changed and when either or both voltage sources are changed. Software can deal with these factors by repeatedly reading the comparator output until a number of readings yield the same result. 13.5.3 Interrupts The interrupt output comes from edge detection circuitry in this module. Rising edges, falling edges, or both edges can set the COMPEDGE bit and thus request an interrupt. COMPEDGE and the interrupt request are cleared when software writes a 1 to EDGECLR. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 157 of 313 D D D D D R R R R R FT FT FT FT FT UM10601 D R R FT FT FT FT A A A A R R D D D Chapter 13: LPC800 Analog comparator D R R A FT FT FT A A R R D D D R A D FT FT A A R R D The comparator output (conditioned by COMPSA bit) can be routed to an external pin. When COMPSA is 0 and the comparator interrupt is disabled, the comparator can be used with the bus clock disabled (Table 18 “System clock control register (SYSAHBCLKCTRL, address 0x4004 8080) bit description”) to save power if the control registers don’t need to be written. F FT FT A A R R D D D 13.5.4 Comparator outputs A A A A A NXP Semiconductors D D R A FT D 13.6 Register description Table 150. Register overview: Analog comparator (base address 0x4002 4000) Name Access Address Description offset Reset value CTRL R/W 0x000 Comparator control register 0 LAD R/W 0x004 Voltage ladder register 0 13.6.1 Comparator control register This register enables the comparator, configures the interrupts, and controls the input multiplexers on both sides of the comparator. All bits not shown in Table 151 are reserved and should be written as 0. Table 151. Comparator control register (CTRL, address 0x4002 4000) bit description Bit Symbol 2:0 - Reserved. Write as 0. 0 4:3 EDGESEL This field controls which edges on the comparator output set the COMPEDGE bit (bit 23 below): 0 Preliminary user manual 0x0 Falling edges 0x1 Rising edges 0x2 Both edges 0x3 Both edges Reset value 5 - Reserved. Write as 0. 0 6 COMPSA Comparator output control 0 7 UM10601 Value Description - 0 Comparator output is used directly. 1 Comparator output is synchronized to the bus clock for output to other modules. Reserved. Write as 0. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 0 © NXP B.V. 2012. All rights reserved. 158 of 313 A The comparator output can be routed to the SCT via the switch matrix allowing to capture the time of a voltage crossing or to count crossings in either or both directions. See Section 13.3.1 “Connect the comparator output to the SCT”. R The status of the comparator output can be observed through the comparator status register bit. D D D D D R R R R R D R R R A FT R R Reserved Selects negative voltage input 0x0 Voltage ladder output 0x1 ACMP_I1 0x2 ACMP_I2 0x3 Reserved 0x4 Reserved 0x5 Reserved 0x6 Internal reference voltage 0x7 Reserved 0 19:14 - Reserved. Write as 0. 0 20 EDGECLR Interrupt clear bit. To clear the COMPEDGE bit and thus negate the interrupt request, toggle the EDGECLR bit by first writing a 1 and then a 0. 0 21 COMPSTAT Comparator status. This bit reflects the state of the comparator output. 0 22 - Reserved. Write as 0. 0 23 COMPEDGE Comparator edge-detect status. 0 24 - Reserved. Write as 0. 0 26:25 HYS 31:27 - Preliminary user manual A 0x7 R Internal reference voltage D 0x6 D Reserved FT Reserved 0x5 FT 0x4 A Reserved R 0x3 D ACMP_I2 0 FT 0x2 13:11 COMP_VM_SEL UM10601 A ACMP_I1 A R Voltage ladder output 0x1 Controls the hysteresis of the comparator. When the 0 comparator is outputting a certain state, this is the difference between the selected signals, in the opposite direction from the state being output, that will switch the output. 0x0 None (the output will switch as the voltages cross) 0x1 5 mV 0x2 10 mV 0x3 20 mV Reserved All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 F D D Selects positive voltage input 0x0 A FT Reset value FT A A R R D D D COMP_VP_SEL D R FT FT A A R R D D D 10:8 FT FT FT FT Value Description A A A A R R D D D Table 151. Comparator control register (CTRL, address 0x4002 4000) bit description Symbol FT FT FT FT FT UM10601 Chapter 13: LPC800 Analog comparator Bit A A A A A NXP Semiconductors - © NXP B.V. 2012. All rights reserved. 159 of 313 D D D D D R R R R R FT FT FT FT FT UM10601 D R R FT FT FT FT A A A A R R D D D Chapter 13: LPC800 Analog comparator D R R A FT FT FT A A R R D D D R A FT FT A A R R D D This register enables and controls the voltage ladder. The fraction of the reference voltage produced by the ladder is programmable in steps of 1/31. F FT FT A A R R D D D 13.6.2 Voltage ladder register A A A A A NXP Semiconductors Voltage ladder enable 0 5:1 LADSEL Voltage ladder value. The reference voltage Vref depends on the LADREF bit below. 00000 = VSS 00001 = 1 Vref/31 00010 = 2 Vref/31 ... 11111 = Vref 0 6 LADREF Selects the reference voltage Vref for the voltage ladder: 0 31:7 UM10601 Preliminary user manual - 0 Supply pin VDD 1 VDDCMP pin Reserved. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 0 © NXP B.V. 2012. All rights reserved. 160 of 313 A LADEN R Reset value D Description FT 0 Value A Symbol R Bit D D Table 152. Voltage ladder register (LAD, address 0x4002 4004) bit description D R R R R R A A A A A FT FT FT FT FT D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D Chapter 14: LPC800 Self wake-up timer (WKT) R A F FT FT A A R R D D Preliminary user manual D Rev. 1.0 — 7 November 2012 D D D D UM10601 D FT FT A A R R D D D 14.1 How to read this chapter R A FT D The self wake-up timer is available on all LPC800 parts. R A 14.2 Features • 32-bit loadable down-counter. Counter starts automatically when a count value is loaded. Time-out generates an interrupt/wake up request. • The WKT resides in a separate, always-on power domain. • The WKT supports two clock sources. One clock source originates from the always-on power domain. • The WKT can be used for waking up the part from any low power mode, including Deep power-down mode, or for general-purpose timing. 14.3 Basic configuration • In the SYSAHBCLKCTRL register, set bit 9 (Table 18) to enable the clock to the register interface. • • • • • Clear the WKT reset using the PRESETCTRL register (Table 7). The WKT interrupt is connected to interrupt #15 in the NVIC. Enable the low power oscillator in the PMU (Table 45). Enable the IRC and IRC output in the PDRUNCFG register (Table 37). See Section 5.7.1 to enable the various power down modes. 14.4 Pin description The WKT has no configurable pins. 14.5 General description The self wake-up timer is a 32-bit, loadable down-counter. Writing any non-zero value to this timer automatically enables the counter and launches a count-down sequence. When the counter is being used as a wake up timer, this write can occur just prior to entering a reduced power mode. When a starting count value is loaded, the self wake-up timer automatically turns on, counts from the pre-loaded value down to zero, generates an interrupt and/or a wake up request, and then turns itself off until re-launched by a subsequent software write. 14.5.1 WKT clock sources The self wake-up timer can be clocked from two alternative clock sources: • A 750 kHz clock derived from the IRC oscillator. This is the default clock, UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 161 of 313 D D D D D R R R R R A A A A A FT FT FT UM10601 FT FT D R R FT FT FT FT Chapter 14: LPC800 Self wake-up timer (WKT) A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D R A D FT FT A A R R D The IRC-derived clock is much more accurate than the alternative, low-power clock. However, the IRC is not available in most low-power modes. This clock must not be selected when the timer is being used to wake up from a power mode where the IRC is disabled. F FT FT A A R R D D D • A 10 kHz, low-power clock with a dedicated on-chip oscillator as clock source. D D R A Name Access Address Description offset Reset value Reference CTRL R/W 0x0 Self wake-up timer control register. 0 Table 154 COUNT R/W 0xC Counter register. 14.6.1 Control register The WKT interrupt must be enabled in the NVIC to wake up the part using the self wake-up counter. Table 154. Control register (CTRL, address 0x4000 8000) bit description Bit Symbol 0 CLKSEL Value 0 Description Reset value Select the self wake-up timer clock source. 0 Divided IRC clock. This clock runs at 750 kHz and provides time-out periods of up to approximately 95 minutes in 1.33 μs increments. Remark: This clock is not available in not available in Deep-sleep, power-down, deep power-down modes. Do not select this option if the timer is to be used to wake up from one of these modes. 1 Low power clock. This is the (nominally) 10 kHz clock and provides time-out periods of up to approximately 119 hours in 100 μs increments. The accuracy of this clock is limited to +/- 45 % over temperature and processing. Remark: This clock is available in all power modes. Prior to use, the low-power oscillator must be enabled. The oscillator must also be set to remain active in Deep power-down if needed. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 162 of 313 A Table 153. Register overview: WKT (base address 0x4000 8000) R 14.6 Register description D The Low-Power oscillator is not accurate (approximately +/- 45% over process and temperature). The frequency measurement feature (if available<tbd>) can be used to determine what the actual frequency is before selecting a time-out value to write into the self wake-up timer. The frequency may still drift, however, while counting is in progress particularly due to reduced chip temperature after a low-power mode is entered. FT The alternative clock source is a (nominally) 10 kHz, low-power clock, sourced from a dedicated oscillator. This oscillator resides in the always-on voltage domain, so it can be programmed to continue operating in Deep power-down mode when power is removed from the rest of the part. This clock is also be available during other low-power modes when the IRC clock is shut-down. D D D D D R R R R R D R R D R FT R R R A - D Clear the counter. Counting is halted until a new count value is loaded. D 1 FT No effect. Reading this bit always returns 0. FT 0 A Clears the self wake-up timer. R CLEARCTR D Time-out. The self wake-up timer has timed out. This flag generates an interrupt request which can wake up the part from any reduced power mode including Deep power-down if the clock source is the low power oscillator. Writing a 1 clears this status bit. FT No time-out. The self wake-up timer has not timed out. Writing a 0 to has no effect. 1 A 0 A R 31:3 - 0 Reserved. - 14.6.2 Count register Do not write to this register while the counting is in progress. Remark: In general, reading the timer state is not recommended. There is no mechanism to ensure that some bits of this register don't change while a read is in progress if the read happens to coincide with an self wake-up timer clock edge. If you must read this value, it is recommended to read it twice in succession. Table 155. Counter register (COUNT, address 0x4000 800C) bit description Bit Symbol Description Reset value 31:0 VALUE A write to this register pre-loads start count value into the timer and starts the count-down sequence. - A read reflects the current value of the timer. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 F D D 2 Wake-up or alarm timer flag. A FT Reset value FT A A R R D D D Description A FT FT A A R R R ALARMFLAG D D D 1 Value FT FT FT FT Symbol A A A A R R D D D Table 154. Control register (CTRL, address 0x4000 8000) bit description FT FT FT FT FT UM10601 Chapter 14: LPC800 Self wake-up timer (WKT) Bit A A A A A NXP Semiconductors © NXP B.V. 2012. All rights reserved. 163 of 313 D D R R R R R A A A A A FT FT FT FT FT D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D Chapter 15: LPC800 USART0/1/2 R A F FT FT A A R R D D Preliminary user manual D Rev. 1.0 — 7 November 2012 D D D UM10601 D FT FT A A R R D D D 15.1 How to read this chapter R A FT D USART0 and USART1 are available on all parts. USART2 is available on parts LPC812M101FDH16 and LPC812M101FDH20 only. R A Read this chapter for a description of the USART peripheral and the software interface. The LPC800 also provides an on-chip ROM-based USART API to configure and operate the USART. See Table 271. 15.2 Features • 7, 8, or 9 data bits and 1 or 2 stop bits • Synchronous mode with master or slave operation. Includes data phase selection and continuous clock option. • Multiprocessor/multidrop (9-bit) mode with software address compare. (RS-485 possible with software address detection and transceiver direction control.) • Parity generation and checking: odd, even, or none. • One transmit and one receive data buffer. • RTS/CTS for hardware signaling for automatic flow control. Software flow control can be performed using Delta CTS detect, Transmit Disable control, and any GPIO as an RTS output. • • • • • • Received data and status can optionally be read from a single register Break generation and detection. Receive data is 2 of 3 sample "voting". Status flag set when one sample differs. Built-in Baud Rate Generator. A fractional rate divider is shared among all UARTs. Interrupts available for Receiver Ready, Transmitter Ready, Receiver Idle, change in receiver break detect, Framing error, Parity error, Overrun, Underrun, Delta CTS detect, and receiver sample noise detected. • Separate data and flow control loopback modes for testing. • Baud rate clock can also be output in asynchronous mode. 15.3 Basic configuration Remark: The on-chip USART API provides software routines to configure and use the USART. See Table 271. Configure USART0/1/2 for receiving and transmitting data: • In the SYSAHBCLKCTRL register, set bit 14 to 16 (Table 18) to enable the clock to the register interface. • Clear the USART0/1/2 peripheral resets using the PRESETCTRL register (Table 7). UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 164 of 313 D D D D D R R R R R A A A A A FT FT FT UM10601 FT FT D R R FT FT FT FT Chapter 15: LPC800 USART0/1/2 A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D • Enable or disable the USART0/1/2 interrupts in slots #3 to 5 in the NVIC. • Configure the USART0/1/2 pin functions through the switch matrix. See Section 15.4. • Configure the USART clock and baud rate. See Section 15.3.1. D FT FT A A R R D D D Configure the USART0/1/2 to wake up the part from low power modes: R A A All three USARTs use a common peripheral clock (U_PCLK) and, if needed, a fractional baud rate generator.The peripheral clock and the fractional divider for the baud rate calculation are set up in the SYSCON block as follows (see Figure 21): 1. Configure the UART clock by writing a value UARTCLKDIV > 0 in the USART peripheral clock divider register. This is the divided main clock common to all USARTs. Section 4.6.14 “USART clock divider register” 2. If a fractional value is needed to obtain a particular baud rate, program the fractional divider. The fractional divider value is the fraction of MULT/DIV. The MULT value is programmed in the UARTFRGMULT register and the DIV value is programmed in the UARTFRGDIV register in the SYSCON block. U_PCLK = UARTCLKDIV/(1+MULT/DIV) The following rules apply for MULT and DIV: – Always set DIV to 256 by programming the UARTFRGDIV register with the value of 0xFF. – Program any value between 0 and 255 in the UARTFRGMULT register. – The fraction of MULT/DIV must be smaller than 1. Section 4.6.19 “USART fractional generator multiplier value register” Section 4.6.18 “USART fractional generator divider value register” 3. In asynchronous mode: Configure the baud rate divider BRGVAL in the USARTn BRG register. The baud rate divider divides the common USART peripheral clock by a factor of 16 multiplied by the baud rate value to provide the baud rate = U_PCLK/16 x BRGVAL. Section 15.6.9 “USART Baud Rate Generator register” 4. In synchronous mode: The serial clock is Un_SCLK = U_PCLK/BRGVAL Preliminary user manual R 15.3.1 Configure the USART clock and baud rate UM10601 D Section 15.3.2. FT • Configure the USART to receive and transmit data in synchronous slave mode. See All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 165 of 313 D D D D D R R R R R D R R FT FT FT FT D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D D )5* D 8$57&/.',9 A A A A R R D D D 8B3&/. 8$57&/.',908/7',9 PDLQFORFN FT FT FT FT FT UM10601 Chapter 15: LPC800 USART0/1/2 6<6&21EORFN A A A A A NXP Semiconductors R A FT 86$57 A 86$57 %$8'6(5,$/&/2&. *(1(5$725 R 8$57)5*',9 D 8$57)5*$'' 8B6&/. 86$57 86$57 %$8'6(5,$/&/2&. *(1(5$725 8B6&/. 86$57 86$57 %$8'6(5,$/&/2&. *(1(5$725 8B6&/. Fig 21. USART clocking For details on the clock configuration see: Section 15.7.1 “Clocking and Baud rates” 15.3.2 Configure the USART for wake-up The USART can wake up the system from sleep mode in asynchronous or synchronous mode on any enabled USART interrupt. If the USART is configured for synchronous slave mode, the USART block can create an interrupt on a received signal even when the USART block receives no clocks from the ARM Cortex-M0+ core - that is in Deep-sleep or Power-down mode. As long as the USART receives a clock signal from the master, it can receive up to one byte in the RXDATA register while in Deep-sleep or Power-down mode. Any interrupt raised as part of the receive data process can then wake up the part. 15.3.2.1 Wake-up from Sleep mode • Configure the USART in either asynchronous mode or synchronous mode. See Table 158. • Enable the USART interrupt in the NVIC. • Any USART interrupt wakes up the part from sleep mode. Enable the USART interrupt in the INTENSET register (Table 161). UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 166 of 313 D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D Chapter 15: LPC800 USART0/1/2 D R R A FT FT FT A A R R D D D R F FT FT A A R R D D • Configure the USART in synchronous slave mode. See Table 158. You must connect the SCLK function to a pin and connect the pin to the master. A FT FT A A R R D D D 15.3.2.2 Wake-up from Deep-sleep or Power-down mode FT FT FT UM10601 FT FT NXP Semiconductors D D • Enable the USART interrupt in the STARTERP1 register. See Table 34 “Start logic 1 R A interrupt wake-up enable register (STARTERP1, address 0x4004 8214) bit description”. FT D R that cause an interrupt and also are enabled in the INTENSET register. Typical wake-up events are: – A received start bit has been detected. – An address bit has been sent. – The RXDATA buffer has received one byte and is full. – Data are ready to be transmitted in the TXDATA buffer and a serial clock from the master has been received. – A change in the state of the CTS pin if the CTS function is connected. <tbd> – Remark: By enabling or disabling the interrupt in the INTENSET register (Table 161), you can customize when the wake-up occurs in the USART receive/transmit protocol. 15.4 Pin description The USART receive, transmit, and control signals are movable functions and are assigned to external pins through the switch matrix. See Section 9.3.1 “Connect an internal signal to a package pin” to assign the USART functions to pins on the LPC800 package. Table 156. USART pin description Function Direction Pin Description SWM register Reference U0_TXD O any Transmitter output for USART0. Serial transmit data. PINASSIGN0 Table 96 U0_RXD I any Receiver input for USART0. Serial receive data. PINASSIGN0 Table 96 U0_RTS O any Request To Send output for USART0. Active low signal for PINASSIGN0 supports inter-processor communication through the use of hardware flow control. This feature is active when the USART RTS signal is configured to appear on a device pin. Table 96 U0_CTS I any Clear To Send input for USART0. Active low signal indicates PINASSIGN0 if the external device that is in communication with the USART is ready to accept data. This feature is active when enabled by the CTSEn bit in CFG register and when configured to appear on a device pin. When deasserted (high) by the external device, the USART will complete transmitting any character already in progress, then stop until CTS is again asserted (low). Table 96 UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 167 of 313 A • Enable the USART interrupt in the NVIC. • The USART wakes up the part from Deep-sleep or Power-down mode on all events D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R Description Reference U0_SCLK I/O any Serial clock input/output for USART0 in synchronous mode. PINASSIGN1 Clock input or output in synchronous mode. If connected to a pin in asynchronous mode, will output the baud rate clock if the SYNCMST bit in CFG register is set to 1. Table 97 U1_TXD O any Transmitter output for USART1. Serial transmit data. PINASSIGN1 Table 97 U1_RXD I any Receiver input for USART1. PINASSIGN1 Table 97 U1_RTS O any Request To Send output for USART1. PINASSIGN1 Table 97 U1_CTS I any Clear To Send input for USART1. PINASSIGN2 Table 98 U1_SCLK I/O any Serial clock input/output for USART1 in synchronous mode. PINASSIGN2 Table 98 U2_TXD O any Transmitter output for USART2. Serial transmit data. PINASSIGN2 Table 98 D FT FT A A R R D D D R A PINASSIGN2 Table 98 Request To Send output for USART2. PINASSIGN3 Table 99 U2_CTS I any Clear To Send input for USART2. PINASSIGN3 Table 99 U0_SCLK I/O any Serial clock input/output for USART2 in synchronous mode. PINASSIGN3 Table 99 15.5 General description The USART receiver block monitors the serial input line, Un_RXD, for valid input. The receiver shift register assembles characters as they are received, after which they are passed to the receiver buffer register to await access by the CPU. The USART transmitter block accepts data written by the CPU and buffers the data in the transmit holding register. When the transmitter is available, the transmit shift register takes that data, formats it, and serializes it to the serial output, Un_TXD. The Baud Rate Generator block divides the incoming clock to create a 16x baud rate clock in the standard asynchronous operating mode. The BRG clock input source is the shared Fractional Rate Generator that runs from the common USART peripheral clock U_PCLK). In synchronous slave mode, data is transmitted and received using the serial clock directly. In synchronous master mode, data is transmitted and received using the baud rate clock without division. Status information from the transmitter and receiver is saved and provided via the Stat register. Many of the status flags are able to generate interrupts, as selected by software. Remark: The fractional value and the USART peripheral clock are shared between all USARTs. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 168 of 313 A Receiver input for USART2. any R any O D I U2_RTS FT U2_RXD All information provided in this document is subject to legal disclaimers. F FT FT Direction Pin A A A R R D D D Function Preliminary user manual FT FT FT FT SWM register A A A A R R D D D Table 156. USART pin description FT FT FT FT FT UM10601 Chapter 15: LPC800 USART0/1/2 UM10601 A A A A A NXP Semiconductors D D D D D R R R R R D R R D A FT R F D FT D R A 8B7;' D FT D 7UDQVPLWWHU 6KLIW 5HJLVWHU FT A A R R D 7UDQVPLWWHU +ROGLQJ 5HJLVWHU 8B3&/. A FT FT A A R R D D D )5* R R FT FT A A R R D D D 8$57&/.',9 FT FT FT FT 7UDQVPLWWHU A A A A R R D D D 6<6&21EORFN FT FT FT FT FT UM10601 Chapter 15: LPC800 USART0/1/2 PDLQFORFN A A A A A NXP Semiconductors R A 6&/. 287 8QB6&/. 6&/. %DXG5DWHDQG &ORFNLQJ*HQHUDWLRQ ,1 8QB&76 ,QWHUUXSW*HQHUDWLRQ6WDWXV )ORZ&RQWURO%UHDNSDULW\ JHQHUDWLRQGHWHFWLRQ 86$57LQWHUUXSW 5HFHLYHU 5HFHLYHU %XIIHU 5HJLVWHU 8QB576 5HFHLYHU 6KLIW 5HJLVWHU 8QB5;' 86$57EORFN 86$57EORFN 86$57EORFN U_PCLK = UARTCLKDIV/(1+MULT/DIV) Fig 22. USART block diagram UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 169 of 313 D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D Chapter 15: LPC800 USART0/1/2 D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D 15.6 Register description FT FT FT UM10601 FT FT NXP Semiconductors D FT FT A A R R D The reset value reflects the data stored in used bits only. It does not include the content of reserved bits. D D R A FT D Table 157: Register overview: USART (base address 0x4006 4000 (USART0), 0x4006 8000 (USART1), 0x4006 C000 (USART2)) R Access Offset Description Reset value Reference CFG R/W 0x000 USART Configuration register. Basic USART configuration settings that typically are not changed during operation. 0 Table 158 CTRL R/W 0x004 USART Control register. USART control settings that are more likely to change during operation. 0 Table 159 STAT R/W 0x008 USART Status register. The complete status value can be read here. Writing 1s clears some bits in the register. Some bits can be cleared by writing a 1 to them. 0x000E Table 160 INTENSET R/W 0x00C Interrupt Enable read and Set register. Contains an individual 0 interrupt enable bit for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. Table 161 INTENCLR W 0x010 Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. Table 162 RXDATA R 0x014 Receiver Data register. Contains the last character received. - Table 163 RXDATASTAT R 0x018 Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows software to recover incoming data and status together. Table 164 TXDATA R/W 0x01C Transmit Data register. Data to be transmitted is written here. 0 Table 165 BRG R/W 0x020 Baud Rate Generator register. 16-bit integer baud rate divisor value. 0 Table 166 INTSTAT R 0x024 Interrupt status register. Reflects interrupts that are currently enabled. 0x0005 Table 167 UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 170 of 313 A Name D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D Chapter 15: LPC800 USART0/1/2 D R R A FT FT FT A A R R D D D R A D FT FT A A R R D The CFG register contains communication and mode settings for aspects of the USART that would normally be configured once in an application. F FT FT A A R R D D D 15.6.1 USART Configuration register FT FT FT UM10601 FT FT NXP Semiconductors D D Remark: If software needs to change configuration values, the following sequence should be used: 1) Make sure the USART is not currently sending or receiving data. 2) Disable the USART by writing a 0 to the Enable bit (0 may be written to the entire register). 3) Write the new configuration value, with the ENABLE bit set to 1. R A ENABLE USART Enable. 0 Enabled. The USART is enabled for operation. 1 - Reserved. Read value is undefined, only zero should be written. NA 3:2 DATALEN Selects the data size for the USART. 00 5:4 0x0 7 bit Data length. 0x1 8 bit Data length. 0x2 9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTRL register. 0x3 Reserved. PARITYSEL Selects what type of parity is used by the USART. 0x0 6 Preliminary user manual 0 Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts are disabled. When Enable is set again, CFG and most other control bits remain unchanged. For instance, when re-enabled, the USART will immediately generate a TxRdy interrupt if enabled because the transmitter has been reset and is therefore available. 1 UM10601 Reset Value No parity. 0x1 Reserved. 0x2 Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even. 0x3 Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd. STOPLEN 00 Number of stop bits appended to transmitted data. Only a single stop bit is required for received data. 0 1 stop bit. 1 2 stop bits. This setting should only be used for asynchronous communication. 7 - Reserved. Only write 0 to this bit. 8 - Reserved. Read value is undefined, only zero should be written. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 0 NA © NXP B.V. 2012. All rights reserved. 171 of 313 A 0 Value Description R Symbol D Bit FT Table 158. USART Configuration register (CFG, address 0x4006 4000 (USART0), 0x4006 8000 (USART1), 0x4006 C000 (USART2)) bit description D D D D D R R R R R A A A A A FT FT FT UM10601 FT FT D R R FT FT FT FT Chapter 15: LPC800 USART0/1/2 A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D R A F D R A CTSEN Reset Value 11 SYNCEN Selects synchronous or asynchronous operation. 0 0 1 12 CLKPOL Asynchronous mode is selected. Synchronous mode is selected. Selects the clock polarity and sampling edge of received data in synchronous mode. 0 Falling edge. Un_RXD is sampled on the falling edge of SCLK. 1 Rising edge. Un_RXD is sampled on the rising edge of SCLK. 0 13 - Reserved. Read value is undefined, only zero should be written. NA 14 SYNCMST Synchronous mode Master select. 0 15 0 Slave. When synchronous mode is enabled, the USART is a slave. 1 Master. When synchronous mode is enabled, the USART is a master. In asynchronous mode, the baud rate clock will be output on SCLK if it is connected to a pin. LOOP 31:16 - Selects data loopback mode. 0 0 Normal operation. 1 Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN. Reserved. Read value is undefined, only zero should be written. NA 15.6.2 USART Control register The CTRL register controls aspects of USART operation that are more likely to change during operation. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 172 of 313 A NA R Reserved. Read value is undefined, only zero should be written. D - D 10 FT Flow control enabled. The transmitter uses external or internal CTS for flow control purposes. A 1 R No flow control. The transmitter does not receive any automatic flow control signal. D 0 FT CTS Enable. Determines whether CTS is used for flow 0 control. CTS can be from the input pin, or from the USART’s own RTS if loopback mode is enabled. See Section 15.7.3 for more information. FT A 9 Value Description R Symbol D Bit D FT FT A A R R D D Table 158. USART Configuration register (CFG, address 0x4006 4000 (USART0), 0x4006 8000 (USART1), 0x4006 C000 (USART2)) bit description …continued D D D D D R R R R R D R R FT D F R FT FT A A R Reset Value D D Value Description A FT FT A A R R R D R A FT 0 A 0 Normal operation. 1 Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTRL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN. 2 ADDRDET Preliminary user manual 0 0 Enabled. The USART receiver is enabled for all incoming data. 1 Disabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally. - Reserved. Read value is undefined, only zero should be written. 6 TXDIS Transmit Disable. 0 Not disabled. USART transmitter is not disabled. 1 Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This feature can be used to facilitate software flow control. - Reserved. Read value is undefined, only zero should be written. 8 CC Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode. 0 Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received. 1 Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD). CLRCC Clear Continuous Clock. No affect on the CC bit. 1 Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time. Reserved. Read value is undefined, only zero should be written. Rev. 1.0 — 7 November 2012 NA 0 0 0 All information provided in this document is subject to legal disclaimers. NA 0 7 31:10 - UM10601 Enable address detect mode. 5:3 9 R Break Enable. NA D Reserved. Read value is undefined, only zero should be written. D TXBRKEN R A D D 1 D R FT FT A A R R D D D - FT FT FT FT 0 A A A A R R D D D Table 159. USART Control register (CTRL, address 0x4006 4004 (USART0), 0x4006 8004 (USART1), 0x4006 C004 (USART2)) bit description Symbol FT FT FT FT FT UM10601 Chapter 15: LPC800 USART0/1/2 Bit A A A A A NXP Semiconductors NA © NXP B.V. 2012. All rights reserved. 173 of 313 D D D D D R R R R R A A A A A FT FT FT UM10601 FT FT D R R FT FT FT FT Chapter 15: LPC800 USART0/1/2 A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D 15.6.3 USART Status register D D The STAT register primarily provides a complete set of USART status flags for software to read. Flags other than read-only flags may be cleared by writing ones to corresponding bits of STAT. R A FT D R Table 160. USART Status register (STAT, address 0x4006 4008 (USART0), 0x4006 8008 (USART1), 0x4006 C008(USART2)) bit description Bit Symbol Description 0 RXRDY Receiver Ready flag. When 1, indicates that data is available to be read from the 0 receiver buffer. Cleared after a read of the RXDATA or RXDATASTAT registers. RO 1 RXIDLE Receiver Idle. When 0, indicates that the receiver is currently in the process of 1 receiving data. When 1, indicates that the receiver is not currently in the process of receiving data. RO 2 TXRDY Transmitter Ready flag. When 1, this bit indicates that data may be written to the 1 transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDATA until the data is moved to the transmit shift register. RO 3 TXIDLE Transmitter Idle. When 0, indicates that the transmitter is currently in the process 1 of sending data.When 1, indicate that the transmitter is not currently in the process of sending data. RO 4 CTS This bit reflects the current state of the CTS signal, regardless of the setting of the CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode is enabled. RO 5 DELTACTS This bit is set when a change in the state is detected for the CTS flag above. This 0 bit is cleared by software. W1 6 TXDISINT Transmitter Disabled Interrupt flag. When 1, this bit indicates that the USART transmitter is fully idle after being disabled via the TXDIS in the CFG register (TXDIS = 1). 0 RO 7 - Reserved. Read value is undefined, only zero should be written. NA NA 8 OVERRUNINT 0 Overrun Error interrupt flag. This flag is set when a new character is received while the receiver buffer is still in use. If this occurs, the newly received character in the shift register is lost. W1 9 - Reserved. Read value is undefined, only zero should be written. NA 10 RXBRK Received Break. This bit reflects the current state of the receiver break detection 0 logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also be set when this condition occurs because the stop bit(s) for the character would be missing. RXBRK is cleared when the Un_RXD pin goes high. RO 11 DELTARXBRK This bit is set when a change in the state of receiver break detection occurs. Cleared by software. 0 W1 12 START This bit is set when a start is detected on the receiver input and subsequently confirmed by a mid-bit sample. Its purpose is primarily to allow wakeup from Power-down mode immediately when a start is detected. Cleared by software. 0 W1 UM10601 Preliminary user manual Reset Acces value s[1] All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 NA NA © NXP B.V. 2012. All rights reserved. 174 of 313 A The error flags (for received noise, parity error, framing error, and overrun) are set immediately upon detection and remain set until cleared by software action in STAT. D D D D D R R R R R A A A A A FT FT FT UM10601 FT FT D R R FT FT FT FT Chapter 15: LPC800 USART0/1/2 A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R A Reset Acces value s[1] 13 FRAMERRINT Framing Error interrupt flag. This flag is set when a character is received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source. 0 W1 14 PARITYERRINT Parity Error interrupt flag. This flag is set when a parity error is detected in a received character, if parity is enabled via the Parity field in the CFG register. 0 W1 15 RXNOISEINT Received Noise interrupt flag. This bit is valid when there is a character to be 0 read in the RXDATA register and reflects the status of that character. Three samples of received data are taken in order to determine the value of each received data bit, except in synchronous mode. This acts as a noise filter if one sample disagrees. The Noise bit is set when a received data bit contains one disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or loss of synchronization during data reception. RXNOISEINT is not updated during a received break. W1 Reserved. Read value is undefined, only zero should be written. NA D D R A FT D RO = Read-only, W1 = write 1 to clear. 15.6.4 USART Interrupt Enable read and set register The INTENSET register is used to enable various USART interrupt sources. Enable bits in INTENSET are mapped in locations that correspond to the flags in the STAT register. The complete set of interrupt enables may be read from this register. Writing ones to implemented bits in this register causes those bits to be set. The INTENCLR register is used to clear bits in this register. Table 161. USART Interrupt Enable read and set register (INTENSET, address 0x4006 400C(USART0), 0x4006 800C (USART1), 0x4006 C00C(USART2)) bit description UM10601 Preliminary user manual Bit Symbol Description 0 RXRDYEN When 1, enables an interrupt when there is a received character available to be read from the RXDATA register. 0 1 - Reserved. Read value is undefined, only zero should be written. NA 2 TXRDYEN When 1, enables an interrupt when the TXDATA register is available to take another character to transmit. 4:3 - Reserved. Read value is undefined, only zero should be written. 5 DELTACTSEN When 1, enables an interrupt when there is a change in the state of the CTS input. 0 6 TXDISINTEN When 1, enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details. 0 7 - Reserved. Read value is undefined, only zero should be written. NA 8 OVERRUNEN When 1, enables an interrupt when an overrun error occurred. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 Reset Value 0 NA 0 © NXP B.V. 2012. All rights reserved. 175 of 313 A NA R [1] FT 31:16 - FT A A R R Description D Symbol D Bit F FT FT A A R R D D Table 160. USART Status register (STAT, address 0x4006 4008 (USART0), 0x4006 8008 (USART1), 0x4006 C008(USART2)) bit description D D D D D R R R R R A A A A A FT FT FT UM10601 FT FT D R R FT FT FT FT Chapter 15: LPC800 USART0/1/2 A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R A Reset Value 10:9 - Reserved. Read value is undefined, only zero should be written. NA 11 DELTARXBRKEN When 1, enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted). 0 12 STARTEN When 1, enables an interrupt when a received start bit has been detected. 0 13 FRAMERREN When 1, enables an interrupt when a framing error has been detected. 0 14 PARITYERREN When 1, enables an interrupt when a parity error has been detected. 0 15 RXNOISEEN When 1, enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 160. 0 D D R A A Table 162. USART Interrupt Enable clear register (INTENCLR, address 0x4006 4010(USART0), 0x4006 8010 (USART1), 0x4006 C010(USART2)) bit description Bit Symbol Description 0 RXRDYCLR Writing 1 clears the corresponding bit in the INTENSET register. 0 1 - Reserved. Read value is undefined, only zero should be written. NA 2 TXRDYCLR Writing 1 clears the corresponding bit in the INTENSET register. 0 4:3 - Reserved. Read value is undefined, only zero should be written. NA 5 DELTACTSCLR Writing 1 clears the corresponding bit in the INTENSET register. 0 6 TXDISINTCLR Writing 1 clears the corresponding bit in the INTENSET register. 0 7 - Reserved. Read value is undefined, only zero should be written. NA 8 OVERRUNCLR Writing 1 clears the corresponding bit in the INTENSET register. 0 10:9 - Reserved. Read value is undefined, only zero should be written. NA 11 DELTARXBRKCLR Writing 1 clears the corresponding bit in the INTENSET register. 0 All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 R The INTENCLR register is used to clear bits in the INTENSET register. Preliminary user manual D NA 15.6.5 USART Interrupt Enable Clear register UM10601 FT Reserved. Read value is undefined, only zero should be written. FT 31:16 - FT A A R R Description D Symbol D Bit F FT FT A A R R D D Table 161. USART Interrupt Enable read and set register (INTENSET, address 0x4006 400C(USART0), 0x4006 800C (USART1), 0x4006 C00C(USART2)) bit description Reset Value © NXP B.V. 2012. All rights reserved. 176 of 313 D D D D D R R R R R A A A A A FT FT FT UM10601 FT FT D R R FT FT FT FT Chapter 15: LPC800 USART0/1/2 A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R STARTCLR Writing 1 clears the corresponding bit in the INTENSET register. 13 FRAMERRCLR Writing 1 clears the corresponding bit in the INTENSET register. 0 14 PARITYERRCLR Writing 1 clears the corresponding bit in the INTENSET register. 0 15 RXNOISECLR Writing 1 clears the corresponding bit in the INTENSET register. 0 Reserved. Read value is undefined, only zero should be written. NA F 12 FT D R 0 D A A Remark: Reading this register changes the status flags in the RXDATASTAT register. Table 163. USART Receiver Data register (RXDATA, address 0x4006 4014 (USART0), 0x4006 8014 (USART1), 0x4006 C014 (USART2)) bit description 8:0 RXDAT The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings. 31:9 - Reserved, the value read from a reserved bit is not defined. Reset Value 0 NA 15.6.7 USART Receiver Data with Status register The RXDATASTAT register contains the next complete character to be read and its relevant status flags. This allows getting all information related to a received character with one 16-bit read. Remark: Reading this register changes the status flags. Table 164. USART Receiver Data with Status register (RXDATASTAT, address 0x4006 4018 (USART0), 0x4006 8018 (USART1), 0x4006 C018 (USART2)) bit description UM10601 Preliminary user manual Bit Symbol Description 8:0 RXDAT The USART Receiver Data register contains the next received character. The number of bits that are relevant depends on the USART configuration settings. 12:9 - Reserved, the value read from a reserved bit is not defined. 13 FRAMERR Framing Error status flag. This bit is valid when there is a character to be read in the RXDATA register and reflects the status of that character. This bit will set when the character in RXDAT was received with a missing stop bit at the expected location. This could be an indication of a baud rate or configuration mismatch with the transmitting source. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 R The RXDATA register contains the last character received before any overrun. Symbol Description D 15.6.6 USART Receiver Data register Bit FT 31:16 - FT A A R R Reset Value D Description D Symbol A FT Bit FT A A R R D D Table 162. USART Interrupt Enable clear register (INTENCLR, address 0x4006 4010(USART0), 0x4006 8010 (USART1), 0x4006 C010(USART2)) bit description Reset Value 0 NA 0 © NXP B.V. 2012. All rights reserved. 177 of 313 D D D D D R R R R R A A A A A FT FT FT UM10601 FT FT D R R FT FT FT FT Chapter 15: LPC800 USART0/1/2 A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R A Reset Value 14 PARITYERR Parity Error status flag. This bit is valid when there is a character to be read in the RXDATA register and reflects the status of that character. This bit will be set when a parity error is detected in a received character. 15 RXNOISE Received Noise flag. See description of the RxNoiseInt bit in Table 160. 0 Reserved, the value read from a reserved bit is not defined. NA FT D R 0 D A FT D R A 31:16 - FT A A R R Description D Symbol D Bit F FT FT A A R R D D Table 164. USART Receiver Data with Status register (RXDATASTAT, address 0x4006 4018 (USART0), 0x4006 8018 (USART1), 0x4006 C018 (USART2)) bit description 15.6.8 USART Transmitter Data Register The TXDATA register is written in order to send data via the USART transmitter. That data will be transferred to the transmit shift register when it is available, and another character may then be written to TXDATA. Table 165. USART Transmitter Data Register (TXDATA, address 0x4006 401C (USART0), 0x4006 801C (USART1), 0x4006 C01C (USART2)) bit description UM10601 Preliminary user manual Bit Symbol Description 8:0 TXDAT Writing to the USART Transmit Data Register causes the data to be transmitted as soon as the transmit shift register is available. 31:9 - Reserved. Only zero should be written. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 Reset Value 0 NA © NXP B.V. 2012. All rights reserved. 178 of 313 D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D Chapter 15: LPC800 USART0/1/2 D R R A FT FT FT A A R R D D D R A FT FT A A R R D D The Baud Rate Generator is a simple 16-bit integer divider controlled by the BRG register. The BRG register contains the value used to divide the base clock in order to produce the clock used for USART internal operations. F FT FT A A R R D D D 15.6.9 USART Baud Rate Generator register FT FT FT UM10601 FT FT NXP Semiconductors D D R A Table 166. USART Baud Rate Generator register (BRG, address 0x4006 4020 (USART0), 0x4006 8020 (USART1), 0x4006 C020 (USART2)) bit description Bit Symbol Description Reset Value 15:0 BRGVAL This value is used to divide the USART input clock to determine the baud rate, based on the input clock from the FRG. 0 0 = The FRG clock is used directly by the USART function. 1 = The FRG clock is divided by 2 before use by the USART function. 2 = The FRG clock is divided by 3 before use by the USART function. ... 0xFFFF = The FRG clock is divided by 65,536 before use by the USART function. 31:16 - Reserved. Read value is undefined, only zero should be written. NA 15.6.10 USART Interrupt Status register The read-only INTSTAT register provides a view of those interrupt flags that are currently enabled. This can simplify software handling of interrupts. See Table 160 for detailed descriptions of the interrupt flags. Table 167. USART Interrupt Status register (INTSTAT, address 0x4006 4024 (USART0), 0x4006 8024 (USART1), 0x4006 C024(USART2)) bit description UM10601 Preliminary user manual Bit Symbol Description 0 RXRDY Receiver Ready flag. 1 - Reserved. Read value is undefined, only zero should be written. 2 TXRDY Transmitter Ready flag. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 Reset Value 0 NA 1 © NXP B.V. 2012. All rights reserved. 179 of 313 A Remark: If software needs to change the baud rate, the following sequence should be used: 1) Make sure the USART is not currently sending or receiving data. 2) Disable the USART by writing a 0 to the Enable bit (0 may be written to the entire registers). 3) Write the new BRGVAL. 4) Write to the CFG register to set the Enable bit to 1. R Details on how to select the right values for BRG can be found later in this chapter, see Section 15.7.1. D Typically, the baud rate clock is 16 times the actual baud rate. This overclocking allows for centering the data sampling time within a bit cell, and for noise reduction and detection by taking three samples of incoming data. FT A 16-bit value allows producing standard baud rates from 300 baud and lower at the highest frequency of the device, up to 921,600 baud from a base clock as low as 14.7456 MHz. D D D D D R R R R R A A A A A FT FT FT UM10601 FT FT D R R FT FT FT FT Chapter 15: LPC800 USART0/1/2 A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R A Reset Value 4:3 - Reserved. Read value is undefined, only zero should be written. 5 DELTACTS This bit is set when a change in the state of the CTS input is detected. 6 TXDISINT Transmitter Disabled Interrupt flag. 7 - Reserved. Read value is undefined, only zero should be written. 8 OVERRUNINT Overrun Error interrupt flag. 10:9 - Reserved. Read value is undefined, only zero should be written. 11 DELTARXBRK This bit is set when a change in the state of receiver break detection occurs. 12 START This bit is set when a start is detected on the receiver input. 0 13 FRAMERRINT Framing Error interrupt flag. 0 14 PARITYERRINT Parity Error interrupt flag. 0 15 RXNOISEINT Received Noise interrupt flag. 0 FT D R NA D A A NA 0 NA 0 NA 15.7 Functional description 15.7.1 Clocking and Baud rates In order to use the USART, clocking details must be defined such as setting up the BRG, and typically also setting up the FRG. See Figure 21. 15.7.1.1 Fractional Rate Generator (FRG) The Fractional Rate Generator can be used to obtain more precise baud rates when the peripheral clock is not a good multiple of standard (or otherwise desirable) baud rates. The FRG is typically set up to produce an integer multiple of the highest required baud rate, or a very close approximation. The BRG is then used to obtain the actual baud rate needed. The FRG register controls the USART Fractional Rate Generator, which provides the base clock for the USART. The Fractional Rate Generator creates a lower rate output clock by suppressing selected input clocks. When not needed, the value of 0 can be set for the FRG, which will then not divide the input clock. The FRG output clock is defined as the inputs clock divided by 1 + (MULT / 256), where MUTL is in the range of 1 to 255. This allows producing an output clock that ranges from the input clock divided by 1+1/256 to 1+255/256 (just more than 1 to just less than 2). Any further division can be done specific to each USART block by the integer BRG divider contained in each USART. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 R 0 Reserved. Read value is undefined, only zero should be written. D 0 FT 31:16 - FT A A R R Description D Symbol D Bit F FT FT A A R R D D Table 167. USART Interrupt Status register (INTSTAT, address 0x4006 4024 (USART0), 0x4006 8024 (USART1), 0x4006 C024(USART2)) bit description © NXP B.V. 2012. All rights reserved. 180 of 313 D D D D D R R R R R A A A A A FT FT FT UM10601 FT FT D R R FT FT FT FT Chapter 15: LPC800 USART0/1/2 A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D The base clock produced by the FRG cannot be perfectly symmetrical, so the FRG distributes the output clocks as evenly as is practical. Since the USART normally uses 16x overclocking, the jitter in the fractional rate clock in these cases tends to disappear in the ultimate USART output. D FT FT A A R R D D D R For setting up the fractional divider use the following registers: A FT 15.7.1.2 Baud Rate Generator (BRG) The Baud Rate Generator (see Section 15.6.9) is used to divide the base clock to produce a rate 16 times the desired baud rate. Typically, standard baud rates can be generated by integer divides of higher baud rates. 15.7.1.3 Baud rate calculations Base clock rates are 16x for asynchronous mode and 1x for synchronous mode. 15.7.2 Synchronous mode Remark: Sync mode transmit and receive operate at the incoming clock rate in slave mode and the BRG selected rate (not divided by 16) in master mode. 15.7.3 Flow control The USART supports both hardware and software flow control. 15.7.3.1 Hardware flow control The USART supports hardware flow control using RTS and/or CTS signalling. If RTS is configured to appear on a device pin so that it can be sent to an external device, it indicates to an external device the ability of the receiver to receive more data. It can also be used internally to throttle the transmitter from the receiver, which can be especially useful if loopback mode is enabled. If connected to a pin, and if enabled to do so, the CTS input can allow an external device to throttle the USART transmitter. Both internal and external CTS can be used separately or together. Figure 23 shows an overview of RTS and CTS within the USART. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 181 of 313 A For details see Section 15.3.1 “Configure the USART clock and baud rate”. R Table 24 “USART fractional generator multiplier value register (UARTFRGMULT, address 0x4004 80F4) bit description” D Table 23 “USART fractional generator divider value register (UARTFRGDIV, address 0x4004 80F0) bit description” D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R R FT FT A A R D D R &)* >&76(1@ A FT D R 7UDQVPLWWHU A 8QB576 5HFHLYHU Fig 23. Hardware flow control using RTS and CTS 15.7.3.2 Software flow control Software flow control could include XON / XOFF flow control, or other mechanisms. these are supported by the ability to check the current state of the CTS input, and/or have an interrupt when CTS changes state (via the CTS and DELTACTS bits, respectively, in the STAT register), and by the ability of software to gracefully turn off the transmitter (via the TXDIS bit in the CTRL register). UM10601 Preliminary user manual F D D 67$7 >'(/7$&76@ A FT FT A A R R D D D 8QB&76 FT FT FT FT &)* >/223@ A A A A R R D D D FKDQJH GHWHFW FT FT FT FT FT UM10601 Chapter 15: LPC800 USART0/1/2 67$7 >&76@ A A A A A NXP Semiconductors All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 182 of 313 A A A A A FT FT FT FT FT D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D Preliminary user manual D Rev. 1.0 — 7 November 2012 R R R R R Chapter 16: LPC800 I2C-bus interface D D D D D UM10601 D FT FT A A R R D D D 16.1 How to read this chapter R A FT D The I2C-bus interface is available on all parts. R A Read this chapter if you want to understand the I2C operation and the software interface and want to learn how to use the I2C for wake-up from reduced power modes. The LPC800 provides an on-chip ROM-based I2C API to configure and operate the I2C. See Table 250 “I2C API calls”. 16.2 Features • • • • Independent Master, Slave, and Monitor functions. Supports both Multi-master and Multi-master with Slave functions. Multiple I2C slave addresses supported in hardware. One slave address can be selectively qualified with a bit mask or an address range in order to respond to multiple I2C bus addresses. • 10-bit addressing supported with software assist. • Supports SMBus. 16.3 Basic configuration Configure I2C using the following registers: • In the SYSAHBCLKCTRL register, set bit 5 (Table 18) to enable the clock to the register interface. • • • • Clear the I2C peripheral reset using the PRESETCTRL register (Table 7). Enable/disable the I2C interrupt in interrupt slots #8 in the NVIC. Configure the I2C pin functions through the switch matrix. See Section 16.4. The peripheral clock for the I2C is the system clock (see Figure 24). ,& 6<6&21 ',99$/ ,&B3&/. V\VWHPFORFN &ORFNGLYLGHU ',9 ,&FORFN 6<6$+%&/.&75/>@ ,&FORFNHQDEOH Fig 24. I2C clocking UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 183 of 313 D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D Chapter 16: LPC800 I2C-bus interface D R R A FT FT FT A A R R D D D R A D FT FT A A R R D The I2C pins are movable pin functions and are assigned to pins on the LPC800 packages through the switch matrix. You have two choices to connect the I2C pins: F FT FT A A R R D D D 16.4 Pin description FT FT FT UM10601 FT FT NXP Semiconductors D D R A 1. Connect to special I2C open-drain pins (PIO0_10 and PIO0_11). FT D 2. Connect to any other pin that can host a movable function.. R A When the I2C function is connected to specialized I2C pins, it completely supports the I2C-bus specification up to Fast Mode Plus (up to 1 MHz I2C). When the I2C function is connected to standard pins that are set to open-drain mode, a functional I2C-bus can be used in this way, but some aspects of the I2C-bus specification may not be met. This can have an impact on the bus speed, noise filtering, and the capability of powering down the device without affecting the bus. See Section 9.3.1 “Connect an internal signal to a package pin” to assign the I2C pins to any pin on the LPC800 package. Table 168. I2C-bus pin description Function Type Pin Description SWM register Reference I2C0_SCL I/O any; use pin PIO0_10 or PIO0_11 for compatibility with the full I2C-bus specification. I2C0 serial clock. PINASSIGN8 Table 104 I2C0_SDA I/O any; use pin PIO0_10 or PIO0_11 for compatibility with the full I2C-bus specification. I2C0 serial data. PINASSIGN7 Table 103 16.5 General description The architecture of the I2C-bus interface is shown in Figure 25. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 184 of 313 D D D D D R R R R R FT FT FT FT FT UM10601 D R R FT FT FT FT A A A A R R D D D Chapter 16: LPC800 I2C-bus interface D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D 0RQLWRU IXQFWLRQ A A A A A NXP Semiconductors D FT FT A A R R D D D R A FT , &PDVWHU IXQFWLRQ D 6&/ 6'$ RXWSXW ORJL F R A 7LPLQJ JHQH UDWLRQ , &VODYH IXQFWLRQ 7LPHRXW ,&B6'$ ,&B6&/ &)*>/223@ Fig 25. I2C block diagram 16.6 Register description The register functionalities can be grouped as follows: • Common registers: – Table 170 “I2C Configuration register (CFG, address 0x4005 0000) bit description” – Table 171 “I2C Status register (STAT, address 0x4005 0004) bit description” – Table 178 “I2C Interrupt Status register (INTSTAT, address 0x4005 0018) bit description” – Table 174 “Interrupt Enable Set and read register (INTENSET, address 0x4005 0008) bit description” – Table 175 “Interrupt Enable Clear register (INTENCLR, address 0x4005 000C) bit description” – Table 176 “time-out register (TIMEOUT, address 0x4005 0010) bit description” – Table 177 “I2C Clock Divider register (DIV, address 0x4005 0014) bit description” • Master function registers: – Table 179 “Master Control register (MSTCTL, address 0x4005 0020) bit description” – Table 180 “Master Time register (MSTTIME, address 0x4005 0024) bit description” UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 185 of 313 D D D D D R R R R R FT FT FT FT FT UM10601 D R R FT FT FT FT A A A A R R D D D Chapter 16: LPC800 I2C-bus interface D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D – Table 181 “Master Data register (MSTDAT, address 0x4005 0028) bit description” • Slave function registers: A A A A A NXP Semiconductors D FT FT A A R R D – Table 182 “Slave Control register (SLVCTL, address 0x4005 0040) bit description” D D – Table 182 “Slave Control register (SLVCTL, address 0x4005 0040) bit description” R A FT – Table 184 “Slave Address registers (SLVADR[0:3]- address 0x4005 0048 (SLVADR0) to 0x4005 0054 (SLVADR3)) bit description” D R • Monitor function register: Table 186 “Monitor data register (MONRXDAT, address 0x4005 0080) bit description” UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 186 of 313 A – Table 185 “Slave address Qualifier 0 register (SLVQUAL0, address 0x4005 0058) bit description” D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R Reference CFG R/W 0x00 Configuration for shared functions. 0 Table 170 STAT R/W 0x04 Status register for Master, Slave, and Monitor functions. 0x00080 Table 171 1 INTENSET R/W 0x08 Interrupt Enable Set and read register. 0 Table 174 INTENCLR W 0x0C Interrupt Enable Clear register. NA Table 175 TIMEOUT R/W 0x10 Time-out value register. 0xFFFF Table 176 FT FT A A R R D D D INTSTAT R 0x18 Interrupt Status register for Master, Slave, and Monitor functions. 0 Table 178 MSTCTL R/W 0x20 Master control register. 0 Table 179 MSTTIME R/W 0x24 Master timing configuration. 0x77 Table 180 MSTDAT R/W 0x28 Combined Master receiver and transmitter data register. NA Table 181 SLVCTL R/W 0x40 Slave control register. 0 Table 182 SLVDAT R/W 0x44 Combined Slave receiver and transmitter data register. NA Table 183 SLVADR0 R/W 0x48 Slave address 0. 0x01 Table 184 SLVADR1 R/W 0x4C Slave address 1. 0x01 Table 184 SLVADR2 R/W 0x50 Slave address 2. 0x01 Table 184 SLVADR3 R/W 0x54 Slave address 3. 0x01 Table 184 SLVQUAL0 R/W 0x58 Slave Qualification for address 0. 0 Table 185 MONRXDAT RO 0x80 Monitor receiver data register. 0 Table 186 16.6.1 I2C Configuration register The CFG register contains mode settings that apply to Master, Slave, and Monitor functions. Table 170. I2C Configuration register (CFG, address 0x4005 0000) bit description 1 UM10601 Preliminary user manual Value Description Reset Value Master Enable. When disabled, configurations settings for the Master function are not changed, but the Master function is internally reset. 0 Disabled. The I2C Master function is disabled. 1 Enabled. The I2C Master function is enabled. SLVEN 0 Slave Enable. When disabled, configurations settings for 0 the Slave function are not changed, but the Slave function is internally reset. 0 Disabled. The I2C slave function is disabled. 1 Enabled. The I2C slave function is enabled. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 187 of 313 A Table 177 R 0 D Clock pre-divider for the entire block. This determines what time increments are used for the MSTTIME and SLVTIME registers. FT 0x14 A R/W R DIV MSTEN F Reset value D Description 0 A FT FT A A R R D D D Access Offset Symbol FT FT FT FT Name Bit A A A A R R D D D Table 169: Register overview: I2C (base address 0x4005 0000) FT FT FT FT FT UM10601 Chapter 16: LPC800 I2C-bus interface I2C A A A A A NXP Semiconductors D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R R D R A Disabled. Time-out function is disabled. 1 Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause interrupts if they are enabled. Typically, only one time-out will be used in a system. Monitor function Clock Stretching. 0 0 0 Disabled. The monitor function will not perform clock stretching. Software may not always be able to read data provided by the monitor function before it is overwritten. This mode may be used when non-invasive monitoring is critical. 1 Enabled. The monitor function will perform clock stretching in order to ensure that software can read all incoming data supplied by the monitor function. Reserved. Read value is undefined, only zero should be written. Rev. 1.0 — 7 November 2012 D 0 All information provided in this document is subject to legal disclaimers. FT I2C bus Time-out Enable. When disabled, time-out flags will be automatically cleared. MONCLKSTR FT Enabled. The I2C monitor function is enabled. A 1 R Disabled. The I2C monitor function is disabled. D 0 FT Preliminary user manual A UM10601 Monitor Enable. When disabled, configurations settings for 0 the Monitor function are not changed, but the Monitor function is internally reset. TIMEOUTEN 31:5 - A R 4 F D D 3 A FT Reset Value FT A A R R D D D MONEN FT FT FT FT 2 Value Description A A A A R R D D D Table 170. I2C Configuration register (CFG, address 0x4005 0000) bit description Symbol FT FT FT FT FT UM10601 Chapter 16: LPC800 I2C-bus interface Bit A A A A A NXP Semiconductors NA © NXP B.V. 2012. All rights reserved. 188 of 313 D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D Chapter 16: LPC800 I2C-bus interface D R R A FT FT FT A A R R D D D R A FT FT A A R R D D The STAT register provides status flags and state information about all of the functions of the I2C block. Some information in this register is read-only, some flags can be cleared by writing a 1 to them. F FT FT A A R R D D D 16.6.2 I2C Status register FT FT FT UM10601 FT FT NXP Semiconductors D D R A FT Access to bits in this register varies. RO = Read-only, W1 = write 1 to clear. D Bit Symbol 0 MSTPENDING 3:1 4 Value Description Reset Acce value ss 1 RO 0 RO Master Arbitration Loss flag. This flag can be cleared by software writing 0 a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. W1 Master Pending. Indicates whether the Master function needs software service. This flag will cause an interrupt when set if enabled via the INTENSET register. The MSTPENDING flag is automatically cleared when a 1 is written to the MSTCONTINUE bit in the MSTCTL register. 0 No service needed. The Master function does not currently need service. 1 Service needed. The Master function needs service. Information on what is needed can be found in the adjacent MSTSTATE field. MSTSTATE Master State code. Each value of this field indicates a specific required service for the Master function. All other values are reserved. 0x0 Idle. The Master function is available to be used for a new transaction. 0x1 Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave. 0x2 Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave. 0x3 Address. Slave Nacked address. 0x4 Data. Slave Nacked transmitted data. MSTARBLOSS 0 No loss. No Arbitration Loss has occurred. 1 Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, or by sending a Start in order to attempt to gain control of the bus when it next becomes idle. 5 - Reserved. Read value is undefined, only zero should be written. NA NA 6 MSTSTSTPERR Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MstContinue. 0 W1 0 No Start/Stop Error has occurred. 1 Start/stop error has occurred. The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an idle state, no action is required. A request for a Start could be made, or software could attempt to insure that the bus has not stalled. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 189 of 313 A Table 171. I2C Status register (STAT, address 0x4005 0004) bit description R Details on the master and slave states described in the MSTSTATE and SLVSTATE bits in this register are listed in Table 172 and Table 173. D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R Reset Acce value ss 7 - Reserved. Read value is undefined, only zero should be written. NA 8 SLVPENDING Slave Pending. Indicates whether the Slave function needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is read-only and is automatically cleared when a 1 is written to the SLVCONTINUE bit in the MSTCTL register. 0 RO 0 RO 1 RO Slave address match Index. This field is valid when the I2C slave function 0 has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers, and provides an identification of the address that was matched. It is possible that more than one address could be matched, but only one match can be reported here. RO D Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in real time. 0 Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time. 1 Not stretching. The slave function is not currently stretching the I2C bus clock. Deep-sleep or Power-down mode could be entered at this time. 13:12 SLVIDX 14 0x0 Slave address 0 was matched. 0x1 Slave address 1 was matched. 0x2 Slave address 2 was matched. 0x3 Slave address 3 was matched. SLVSEL UM10601 Preliminary user manual A SLVNOTSTR R Reserved. D 0x3 Slave selected flag. SLVSEL is set after an address match when 0 software tells the Slave function to acknowledge the address. It is cleared when another address cycle presents an address that does not match an enabled address on the Slave function, when slave software decides to Nack a matched address, or when there is a Stop detected on the bus. SLVSEL is not cleared if software Nacks data. 0 Not selected. The Slave function is not currently selected. 1 Selected. The Slave function is currently selected. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 D Data ready for transmit. Data can be transmitted (Slave Transmitter mode). FT Data available. Received data is available (Slave Receiver mode). 0x2 FT 0x1 A Received. Address plus R/W received. At least one of the four slave addresses has been matched by hardware. R 0x0 D Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. NA FT SLVSTATE A Service needed. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field. A R 1 R D 11 No service needed. The Slave function does not currently need service. F FT FT Symbol A A A R R D D D Bit 0 FT FT FT FT Value Description A A A A R R D D D Table 171. I2C Status register (STAT, address 0x4005 0004) bit description …continued FT FT FT FT FT UM10601 Chapter 16: LPC800 I2C-bus interface 10:9 A A A A A NXP Semiconductors RO © NXP B.V. 2012. All rights reserved. 190 of 313 D D D D D R R R R R D R R D R A FT FT FT A A R R R R D 0 No overrun. Monitor data has not overrun. 1 Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag. MONACTIVE Monitor Active flag. This flag indicates when the Monitor function considers the I2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop. 0 Inactive. The Monitor function considers the I2C bus to be inactive. 1 Active. The Monitor function considers the I2C bus to be active. Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the INTENSET register . The flag can be cleared by writing a 1 to this bit. MONIDLE 0 Not idle. The I2C bus is not idle, or this flag has been cleared by software. 1 Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software. A Monitor Overflow flag. R MONOV D Data waiting. The Monitor function has data waiting to be read. 0 RO 0 W1 0 RO 0 W1 NA NA 23:20 - Reserved. Read value is undefined, only zero should be written. 24 Event Time-out Interrupt flag. Indicates when the time between events 0 has been longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock edges. The case of SCL remaining low longer than TIMEOUT is not reported by this flag, it is reported in by the SCL Time-out flag. The flag is cleared by writing a 1 to this bit. 25 EVENTTIMEOUT 0 No time-out. I2C bus events have not caused a time-out. 1 Event time-out. The time between I2C bus events has been longer than the time specified by the I2C TIMEOUT register. SCLTIMEOUT 31:26 UM10601 Preliminary user manual SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit. 0 No time-out. SCL low time has not caused a time-out. 1 Time-out. SCL low time has caused a time-out. Reserved. Read value is undefined, only zero should be written. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 D 1 FT No data. The Monitor function does not currently have data available. FT 0 A Monitor Ready. This flag is cleared when the MONRXDAT register is read. R MONRDY D Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag changing from 1 to 0. See the description of SLVSEL for details on when that event occurs. W1 FT 19 1 A 18 Not deselected. The Slave function has not become deselected. This does not mean that it is currently selected. That information can be found in the SLVSEL flag. A R 17 0 R D 16 Slave Deselected flag. This flag will cause an interrupt when set if 0 enabled via INTENSET. This flag can be cleared by writing a 1 to this bit. F FT FT Reset Acce value ss A A A R R D D D SLVDESEL D D D 15 Value Description FT FT FT FT Symbol A A A A R R D D D Table 171. I2C Status register (STAT, address 0x4005 0004) bit description …continued FT FT FT FT FT UM10601 Chapter 16: LPC800 I2C-bus interface Bit A A A A A NXP Semiconductors W1 0 W1 NA NA © NXP B.V. 2012. All rights reserved. 191 of 313 D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R R FT FT A A R Received data is available (Master Receiver mode). Address Read data and either continue, send a Stop, or plus Read was previously sent and Acknowledged by slave. send a Repeated Start. 2 Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave. Send data and continue, or send a Stop or Repeated Start. 3 Slave Nacked address. Send a Stop or Repeated Start. 4 Slave Nacked transmitted data. Send a Stop or Repeated Start. D Send a Start or disable MstPending interrupt if the Master function is not needed currently. D 1 R A Software can further check the address if needed, for instance if a subset of addresses qualified by SLVQUAL0 is to be used. Software can Ack or Nack the address by writing 1 to either SLVCONTINUE or SLVNACK. Also see Section 16.7.3 regarding 10-bit addressing. 1 Received data is available (Slave Receiver mode). Read data reply with an Ack or a Nack. 2 Data can be transmitted (Slave Transmitter mode). Send data. 3 Reserved. - All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 192 of 313 A Address plus R/W received. At least one of the 4 slave addresses has been matched by hardware. R 0 D Actions FT Table 173: Slave function state codes (SLVSTATE) Preliminary user manual F D D Idle. The Master function is available to be used for a new transaction. UM10601 A FT FT A A R R D D D 0 SlvState Description FT FT FT FT Actions A A A A R R D D D Table 172: Master function state codes (MSTSTATE) FT FT FT FT FT UM10601 Chapter 16: LPC800 I2C-bus interface MstState Description A A A A A NXP Semiconductors D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D Chapter 16: LPC800 I2C-bus interface D R R A FT FT FT A A R R D D D R A FT FT A A R R D D The INTENSET register controls which I2C status flags generate interrupts. Writing a 1 to a bit position in this register enables an interrupt in the corresponding position in the STAT register, if an interrupt is supported there. Reading INTENSET indicates which interrupts are currently enabled. F FT FT A A R R D D D 16.6.3 Interrupt Enable Set and read register FT FT FT UM10601 FT FT NXP Semiconductors D D R A FT Value Description 0 MSTPENDINGEN Master Pending interrupt Enable. 0 1 The MstPending interrupt is disabled. The MstPending interrupt is enabled. - Reserved. Read value is undefined, only zero should be written. NA 4 MSTARBLOSSEN Master Arbitration Loss interrupt Enable. 0 5 - 6 MSTSTSTPERREN 0 The MstArbLoss interrupt is disabled. 1 The MstArbLoss interrupt is enabled. Reserved. Read value is undefined, only zero should be written. NA Master Start/Stop Error interrupt Enable. 0 0 The MstStStpErr interrupt is disabled. 1 The MstStStpErr interrupt is enabled. 7 - Reserved. Read value is undefined, only zero should be written. NA 8 SLVPENDINGEN Slave Pending interrupt Enable. 0 0 The SlvPending interrupt is disabled. 1 The SlvPending interrupt is enabled. 10:9 - Reserved. Read value is undefined, only zero should be written. NA 11 SLVNOTSTREN Slave Not Stretching interrupt Enable. 0 0 The SlvNotStr interrupt is disabled. 1 The SlvNotStr interrupt is enabled. 14:12 - Reserved. Read value is undefined, only zero should be written. NA 15 Slave Deselect interrupt Enable. 0 SLVDESELEN 0 The SlvDeSel interrupt is disabled. 1 The SlvDeSel interrupt is enabled. MONRDYEN Monitor data Ready interrupt Enable. 0 1 17 18 Preliminary user manual 0 3:1 16 UM10601 Reset value MONOVEN - 0 The MonRdy interrupt is disabled. The MonRdy interrupt is enabled. Monitor Overrun interrupt Enable. 0 The MonOv interrupt is disabled. 1 The MonOv interrupt is enabled. 0 Reserved. Read value is undefined, only zero should be written. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 NA © NXP B.V. 2012. All rights reserved. 193 of 313 A Symbol R Bit D Table 174. Interrupt Enable Set and read register (INTENSET, address 0x4005 0008) bit description D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D A D FT D R A 23:20 - Reserved. Read value is undefined, only zero should be written. NA 24 Event time-out interrupt Enable. 0 25 EVENTTIMEOUTEN 0 The Event time-out interrupt is disabled. 1 The Event time-out interrupt is enabled. SCLTIMEOUTEN 31:26 - SCL time-out interrupt Enable. 0 The SCL time-out interrupt is disabled. 1 The SCL time-out interrupt is enabled. D A The MonIdle interrupt is enabled. R 1 0 D The MonIdle interrupt is disabled. FT Monitor Idle interrupt Enable. 0 FT A A R R D Reset value F FT FT A A R R R Value Description D D D MONIDLEEN FT FT FT FT 19 A A A A R R D D D Table 174. Interrupt Enable Set and read register (INTENSET, address 0x4005 0008) bit description Symbol FT FT FT FT FT UM10601 Chapter 16: LPC800 I2C-bus interface Bit A A A A A NXP Semiconductors 0 Reserved. Read value is undefined, only zero should be written. NA 16.6.4 Interrupt Enable Clear register Writing a 1 to a bit position in INTENCLR clears the corresponding position in the INTENSET register, disabling that interrupt. INTENCLR is a write-only register. Bits that do not correspond to defined bits in INTENSET are reserved and only zeroes should be written to them. Table 175. Interrupt Enable Clear register (INTENCLR, address 0x4005 000C) bit description Bit Symbol Description Reset value 0 MSTPENDINGCLR Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented. 0 3:1 - Reserved. Read value is undefined, only zero should be written. NA 4 MSTARBLOSSCLR Master Arbitration Loss interrupt clear. 0 5 - Reserved. Read value is undefined, only zero should be written. NA 6 MSTSTSTPERRCLR Master Start/Stop Error interrupt clear. 0 7 - Reserved. Read value is undefined, only zero should be written. NA 8 SLVPENDINGCLR Slave Pending interrupt clear. 0 10:9 - Reserved. Read value is undefined, only zero should be written. NA 11 SLVNOTSTRCLR Slave Not Stretching interrupt clear. 0 Reserved. Read value is undefined, only zero should be written. NA 14:12 - UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 194 of 313 D D D D D R R R R R D R R FT FT FT FT D R R A FT FT FT A A R R D D D A F D FT 0 18 - Reserved. Read value is undefined, only zero should be written. NA 19 MONIDLECLR Monitor Idle interrupt clear. 0 Reserved. Read value is undefined, only zero should be written. NA 24 EVENTTIMEOUTCLR Event time-out interrupt clear. 0 25 SCLTIMEOUTCLR SCL time-out interrupt clear. 0 Reserved. Read value is undefined, only zero should be written. NA 31:26 - 16.6.5 Time-out value register The TIMEOUT register allows setting an upper limit to certain I2C bus times, informing by status flag and/or interrupt when those times are exceeded. Two time-outs are generated, software can elect to use either of them. EVENTTIMEOUT checks the time between bus events while the bus is not idle: Start, SCL rising, SCL falling, and Stop. The EVENTTIMEOUT status flag in the STAT register is set if the time between any two events becomes longer than the time configured in the TIMEOUT register. The EVENTTIMEOUT status flag can cause an interrupt if enabled to do so by the EVENTTIMEOUTEN bit in the INTENSET register. SCLTIMEOUT checks only the time that the SCL signal remains low, while the bus is not idle. The SCLTIMEOUT status flag in the STAT register is set if SCL remains low longer than the time configured in the TIMEOUT register. The SCLTIMEOUT status flag can cause an interrupt if enabled to do so by the SCLTIMEOUTEN bit in the INTENSET register. Also see Section 16.7.2 “Time-out”. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 195 of 313 A Monitor Overrun interrupt clear. R MONOVCLR D 17 D 0 FT 0 Monitor data Ready interrupt clear. A Slave Deselect interrupt clear. MONRDYCLR R SLVDESELCLR 16 D 15 23:20 - FT A A R R Reset value D Description R FT FT A A R R D D D Symbol A A A A R R D D D Table 175. Interrupt Enable Clear register (INTENCLR, address 0x4005 000C) bit description …continued FT FT FT FT FT UM10601 Chapter 16: LPC800 I2C-bus interface Bit A A A A A NXP Semiconductors D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks. 15:4 TO Time-out time value. Specifies the time-out interval value in increments 0xFFF of 16 I2C function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation, disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. A A R FT FT 0xF D D R A FT 0xFFF = A time-out will occur after 65,536 counts of the I2C function clock. NA 16.6.6 I2C Clock Divider register The CLKDIV register divides down the Peripheral Clock (PCLK) to produce the I2C function clock that is used to time various aspects of the I2C interface. The I2C function clock is used for some internal operations in the I2C block and to generate the timing required by the I2C bus specification, some of which are user configured in the MSTTIME register for Master operation and the SLVTIME register for Slave operation. See Section 16.7.1.1 “Rate calculations” for details on bus rate setup. Table 177. I2C Clock Divider register (DIV, address 0x4005 0014) bit description DIVVAL Reset value This field controls how the clock (PCLK) is used by the I2C functions that need an internal clock in order to operate. 0 0x0000 = PCLK is used directly by the I2C function. 0x0001 = PCLK is divided by 2 before use by the I2C function. 0x0002 = PCLK is divided by 3 before use by the I2C function. ... 0xFFFF = PCLK is divided by 65,536 before use by the I2C function. 31:16 - Reserved. Read value is undefined, only zero should be written. NA 16.6.7 I2C Interrupt Status register The INTSTAT register provides register provides a view of those interrupt flags that are currently enabled. This can simplify software handling of interrupts. See Table 171 for detailed descriptions of the interrupt flags. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 196 of 313 A ... R 0x001 = A time-out will occur after 32 counts of the I2C function clock. D 0x000 = A time-out will occur after 16 counts of the I2C function clock. 15:0 F TOMIN R 3:0 D Reset value D Description Reserved. Read value is undefined, only zero should be written. A FT FT A A R R D D D Symbol Symbol Description FT FT FT FT Bit Bit A A A A R R D D D Table 176. time-out register (TIMEOUT, address 0x4005 0010) bit description FT FT FT FT FT UM10601 Chapter 16: LPC800 I2C-bus interface 31:16 - A A A A A NXP Semiconductors D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R Master Pending. 3:1 - Reserved. 4 MSTARBLOSS Master Arbitration Loss flag. 0 5 - Reserved. Read value is undefined, only zero should be written. NA 6 MSTSTSTPERR Master Start/Stop Error flag. 0 7 - Reserved. Read value is undefined, only zero should be written. NA 8 SLVPENDING Slave Pending. 0 10:9 - Reserved. Read value is undefined, only zero should be written. NA 11 SLVNOTSTR FT FT A A R 1 D D R A SLVDESEL Slave Deselected flag. 0 16 MONRDY Monitor Ready. 0 17 MONOV Monitor Overflow flag. 0 18 - Reserved. Read value is undefined, only zero should be written. NA 19 MONIDLE Monitor Idle flag. 0 23:20 - Reserved. Read value is undefined, only zero should be written. NA 24 EVENTTIMEOUT Event time-out Interrupt flag. 0 25 SCLTIMEOUT SCL time-out Interrupt flag. 0 Reserved. Read value is undefined, only zero should be written. NA 16.6.8 Master Control register The MSTCTL register contains bits that control various functions of the I2C Master interface. Table 179. Master Control register (MSTCTL, address 0x4005 0020) bit description UM10601 Preliminary user manual Value Description Reset value Master Continue. This bit is write-only. 0 0 No effect. 1 Continue. Informs the Master function to continue to the next operation. This must done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation. Master Start control. This bit is write-only. 0 0 No effect. 1 Start. A Start will be generated on the I2C bus at the next allowed time. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 197 of 313 A 15 R NA D 1 Reserved. Read value is undefined, only zero should be written. FT Slave Not Stretching status. 14:12 - MSTSTART F MSTPENDING R 0 D Reset value D Description 1 A FT FT A A R R D D D Symbol MSTCONTINUE FT FT FT FT Bit 0 A A A A R R D D D Table 178. I2C Interrupt Status register (INTSTAT, address 0x4005 0018) bit description Bit Symbol FT FT FT FT FT UM10601 Chapter 16: LPC800 I2C-bus interface 31:26 - A A A A A NXP Semiconductors D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R R FT FT A A R 0 D D No effect. 1 Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a Nack to the slave if the master is receiving data from the slave (Master Receiver mode). R 0 A FT D R A Reserved. Read value is undefined, only zero should be written. NA 16.6.9 Master Time The MSTTIME register allows programming of certain times that may be controlled by the Master function. These include the clock (SCL) high and low times, repeated Start setup time, and transmitted data setup time. The I2C clock pre-divider is described in Table 177. Table 180. Master Time register (MSTTIME, address 0x4005 0024) bit description UM10601 Preliminary user manual Bit Symbol 2:0 MSTSCLLOW Value Description Reset value Master SCL Low time. Specifies the minimum low time 0 that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter tLOW in the I2C bus specification. I2C bus specification parameters tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW. 0x0 2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider. 0x1 3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider. 0x2 4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider. 0x3 5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider. 0x4 6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider. 0x5 7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider. 0x6 8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider. 0x7 9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 F D D Master Stop control. This bit is write-only. 31: 2 A FT Reset value FT A A R R D D D MSTSTOP FT FT FT FT 2 A A A A R R D D D Table 179. Master Control register (MSTCTL, address 0x4005 0020) bit description Value Description FT FT FT FT FT UM10601 Chapter 16: LPC800 I2C-bus interface Bit Symbol A A A A A NXP Semiconductors © NXP B.V. 2012. All rights reserved. 198 of 313 D D D D D R R R R R A A A A A FT FT FT UM10601 FT FT D R R FT FT FT FT Chapter 16: LPC800 I2C-bus interface A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R A 6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider. 0x5 7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider. 0x6 8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider. 0x7 9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider. - Reserved. Read value is undefined, only zero should be written. A 0x4 R 5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider. D 0x3 D 4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider. FT 0x2 A 3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider . R 0x1 D 2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider. FT 0x0 FT A Master SCL High time. Specifies the minimum high time 0 that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH. NA 16.6.10 Master Data register The MSTDAT register provides the means to read the most recently received data for the Master function, and to transmit data using the Master function. Table 181. Master Data register (MSTDAT, address 0x4005 0028) bit description Bit Symbol Description 7:0 DATA Master function data register. Reset value 0 Read: read the most recently received data for the Master function. Write: transmit data using the Master function. 31:8 - Reserved. Read value is undefined, only zero should be written. NA 16.6.11 Slave Control register The SLVCTL register contains bits that control various functions of the I2C Slave interface. UM10601 Preliminary user manual F R R 31:7 A D MSTSCLHIGH D 6:4 Reset value FT Value Description FT Symbol A Bit A R R D D Table 180. Master Time register (MSTTIME, address 0x4005 0024) bit description …continued All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 199 of 313 D D D D D R R R R R D R R R A FT R R A FT FT 0 D D No effect. 1 Continue. Informs the Slave function to continue to the next operation. This must done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation. R 0 A FT D R A Slave Nack. 0 0 No effect. 1 Nack. Causes the Slave function to Nack the master when the slave is receiving data from the master (Slave Receiver mode). - A R 31:2 Slave Continue. SlvNack Reserved. Read value is undefined, only zero should be written. NA 16.6.12 Slave Data register The SLVDAT register provides the means to read the most recently received data for the Slave function and to transmit data using the Slave function. Table 183. Slave Data register (SLVDAT, address 0x4005 0044) bit description Bit Symbol Description 7:0 DATA Slave function data register. Reset Value 0 Read: read the most recently received data for the Slave function. Write: transmit data using the Slave function. 31:8 UM10601 Preliminary user manual - Reserved. Read value is undefined, only zero should be written. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 F D Reset Value D 1 A FT FT A A R R D D D SlvContinue D R FT FT A A R R D D D 0 FT FT FT FT Value Description A A A A R R D D D Table 182. Slave Control register (SLVCTL, address 0x4005 0040) bit description Symbol FT FT FT FT FT UM10601 Chapter 16: LPC800 I2C-bus interface Bit A A A A A NXP Semiconductors NA © NXP B.V. 2012. All rights reserved. 200 of 313 D D D D D R R R R R FT FT FT FT FT UM10601 D R R FT FT FT FT A A A A R R D D D Chapter 16: LPC800 I2C-bus interface D R R A FT FT FT A A R R D D D R A FT FT A A R R D D The SLVADR[0:3] registers allow enabling and defining one of the addresses that can be automatically recognized by the I2C slave hardware. The value in the SLVADR0 register is qualified by the setting of the SLVQUAL0 register. F FT FT A A R R D D D 16.6.13 Slave Address registers A A A A A NXP Semiconductors D D R A FT D R When the slave address is compared to the receive address, the compare can be affected by the setting of the SLVQUAL0 register (see Section 16.6.14). A The I2C slave function has 4 address comparators. The additional 3 address comparators do not include the address qualifier feature. For handling of the general call address, one of the 4 address registers can be programmed to respond to address 0. Table 184. Slave Address registers (SLVADR[0:3]- address 0x4005 0048 (SLVADR0) to 0x4005 0054 (SLVADR3)) bit description Bit Symbol Value Description 0 SADISABLE Reset value Slave Address n Disable. 1 0 Enabled. Slave Address n is enabled and will be recognized with any changes specified by the SLVQUAL0 register. 1 Ignored Slave Address n is ignored. 7:1 SLVADR Seven bit slave address that is compared to received addresses if enabled. 0 31:8 - Reserved. Read value is undefined, only zero should be written. NA 16.6.14 Slave address Qualifier 0 register The SLVQUAL0 register can alter how Slave Address 0 is interpreted. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 201 of 313 D D D D D R R R R R D R R D A FT R A D FT FT A A R R D Reset Value F FT FT A A R R D D D Value Description R R FT FT A A R R D D D QUALMODE0 FT FT FT FT 0 A A A A R R D D D Table 185. Slave address Qualifier 0 register (SLVQUAL0, address 0x4005 0058) bit description Symbol FT FT FT FT FT UM10601 Chapter 16: LPC800 I2C-bus interface Bit A A A A A NXP Semiconductors D R A SLVQUAL0 D The SLVQUAL0 field is used to extend address 0 matching in a range of addresses. FT 1 A The SLVQUAL0 field is used as a logical mask for matching address 0. R 0 0 D 7:1 Reserved. Read value is undefined, only zero should be written. Slave address Qualifier for address 0. A value of 0 causes 0 the address in SLVADR0 to be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is set to 1 will cause an automatic match of the corresponding bit of the received address when it is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1]). 31:8 - Reserved. Read value is undefined, only zero should be written. NA 16.6.15 Monitor data register The read-only MONRXDAT register provides information about events on the I2C bus, primarily to facilitate debugging of the I2C during application development. All data addresses and data passing on the bus and whether these were acknowledged, as well as Start and Stop events, are reported. The Monitor function must be enabled by the MONEN bit in the CFG register. Monitor mode can be configured to stretch the I2C clock if data is not read from the MONRXDAT register in time to prevent it, via the MONCLKSTR bit in the CFG register. This can help ensure that nothing is missed but can cause the monitor function to be somewhat intrusive (by potentially adding clock delays, depending on software response time). In order to improve the chance of collecting all Monitor information if clock stretching is not enabled, Monitor data is buffered such that it is available until the end of the next piece of information from the I2C bus. Table 186. Monitor data register (MONRXDAT, address 0x4005 0080) bit description UM10601 Preliminary user manual Bit Symbol Value Description Reset value 7:0 MONRXDAT Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins, and adds indication of Start, Repeated Start, and data Nack. 0 8 MONSTART Monitor Received Start. 0 0 No detect. The monitor function has not detected a Start event on the I2C bus. 1 Start detect. The monitor function has detected a Start event on the I2C bus. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 202 of 313 D D D D D R R R R R D R R R A FT R R A Not acknowledged. The data currently being provided by the monitor function was not acknowledged by any receiver. R 1 Monitor Received Nack. D Acknowledged. The data currently being provided by the monitor function was acknowledged by at least one master or slave receiver. D 0 FT Repeated start detect. The monitor function has detected a Repeated Start event on the I2C bus. A 1 R No start detect. The monitor function has not detected a Repeated Start event on the I2C bus. D 0 FT 0 FT A 31:11 - A R Monitor Received Repeated Start. MONNACK 0 Reserved. Read value is undefined, only zero should be NA written. 16.7 Functional description 16.7.1 Bus rates and timing considerations Due to the nature of the I2C bus, it is generally not possible to guarantee a specific clock rate on the SCL pin. The clock can be stretched by any slave device, extended by software overhead time, etc. In a multi-master system, the master that provides the shortest SCL high time will cause that time to appear on SCL as long as that master is participating in I2C traffic (i.e. when it is the only master on the bus, or during arbitration between masters). Rate calculations give a base frequency that represents the fastest that the I2C bus could operate if nothing slows it down. 16.7.1.1 Rate calculations SCL high time (in I2C function clocks) = (CLKDIV + 1) * (MSTSCLHIGH + 2) SCL low time (in I2C function clocks) = (CLKDIV + 1) * (MSTSCLLOW + 2) Nominal SCL rate = I2C function clock rate / (SCL high time + SCL low time) 16.7.2 Time-out A time-out feature on an I2C interface can be used to detect a “stuck” bus and potentially do something to alleviate the condition. Two different types of time-out are supported. Both types apply whenever the I2C block and the time-out function are both enabled, Master, Slave, or Monitor functions do not need to be enabled. In the first type of time-out, reflected by the EVENTTIMEOUT flag in the STAT register, the time between bus events governs the time-out check. These events include Start, Stop, and all changes on the I2C clock (SCL). This time-out is asserted when the time between UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 F D D 10 A FT Reset value FT A A R R D D D MONRESTART D R FT FT A A R R D D D 9 FT FT FT FT Value Description A A A A R R D D D Table 186. Monitor data register (MONRXDAT, address 0x4005 0080) bit description Symbol FT FT FT FT FT UM10601 Chapter 16: LPC800 I2C-bus interface Bit A A A A A NXP Semiconductors © NXP B.V. 2012. All rights reserved. 203 of 313 D D D D D R R R R R A A A A A FT FT FT UM10601 FT FT D R R FT FT FT FT Chapter 16: LPC800 I2C-bus interface A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D any of these events is longer than the time configured in the TIMEOUT register. This time-out could be useful in monitoring an I2C bus within a system as part of a method to keep the bus running of problems occur. D FT FT A A R R D D D The second type of I2C time-out is reflected by the SCLTIMEOUT flag in the STAT register. This time-out is asserted when the SCL signal remains low longer than the time configured in the TIMEOUT register. This corresponds to SMBus time-out parameter TTIMEOUT. In this situation, a slave could reset its own I2C interface in case it is the offending device. If all listening slaves (including masters that can be addressed as slaves) do this, then the bus will be released unless it is a current master causing the problem. Refer to the SMBus specification for more details. R A For the Slave function, the first part of the address is automatically matched in the same fashion as 7-bit addressing. The Slave address qualifier feature (see Section 16.6.14) can be used to intercept all potential 10-bit addresses (first address byte values F0 through F6), or just one. In the case of Slave Receiver mode, data is received in the normal fashion after software matches the first data byte to the remaining portion of the 10-bit address. The Slave function should record the fact that it has been addressed, in case there is a follow-up read operation. For Slave Transmitter mode, the slave function responds to the initial address in the same fashion as for Slave Receiver mode, and checks that it has previously been addressed with a full 10-bit address. If the address matched is address 0, and address qualification is enabled, software must check that the first part of the 10-bit address is a complete match to the previous address before acknowledging the address. 16.7.4 Clocking and power considerations The Master function of the I2C always requires a peripheral clock to be running in order to operate. The Slave function can operate without any internal clocking when the slave is not currently addressed. This means that reduced power modes up to Power-down mode can be entered, and the device will wake up when the I2C Slave function recognizes an address. Monitor mode can similarly wake up the device from a reduced power mode when information becomes available. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 204 of 313 A For the Master function, the I2C is simply instructed to perform the 2-byte addressing as a normal write operation, followed either by more write data, or by a Repeated Start with a repeat of the first part of the 10-bit slave address and then reading in the normal fashion. R Ten-bit addressing is accomplished by the I2C master sending a second address byte to extend a particular range of standard 7-bit addresses. In the case of the master writing to the slave, the I2C frame simply continues with data after the 2 address bytes. For the master to read from a slave, it needs to reverse the data direction after the second address byte. This is done by sending a Repeated Start, followed by a repeat of the same standard 7-bit address, with a Read bit. The slave must remember that it had been addressed by the previous write operation and stay selected for the subsequent read with the correct partial I2C address. D 16.7.3 Ten-bit addressing FT Both types of time-out are generated when the I2C bus is considered busy. D D D D D R R R R R FT FT FT FT FT UM10601 D R R FT FT FT FT A A A A R R D D D Chapter 16: LPC800 I2C-bus interface D R R A FT FT FT A A R R D D D R A FT FT A A R R D D The I2C provides a single interrupt output that handles all interrupts for Master, Slave, and Monitor functions. F FT FT A A R R D D D 16.7.5 lnterrupts A A A A A NXP Semiconductors D D R A FT D R A UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 205 of 313 A A A A A FT FT FT FT FT D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D Preliminary user manual D Rev. 1.0 — 7 November 2012 R R R R R Chapter 17: LPC800 SPI0/1 D D D D D UM10601 D FT FT A A R R D D D 17.1 How to read this chapter R A • Control information can optionally be written along with data. This allows very versatile operation, including “any length” frames. • One Slave Select input/output with selectable polarity and flexible usage. Remark: Texas Instruments SSI and National Microwire modes are not supported. 17.3 Basic configuration Configure SPI0/1 using the following registers: • In the SYSAHBCLKCTRL register, set bit 11 and 12 (Table 18) to enable the clock to the register interface. • • • • Clear the SPI0/1 peripheral resets using the PRESETCTRL register (Table 7). Enable/disable the SPI0/1 interrupts in interrupt slots #0 and 1 in the NVIC. Configure the SPI0/1 pin functions through the switch matrix. See Section 17.4. The peripheral clock for both SPIs is the system clock (see Figure 3 “LPC800 clock generation”). 63, 6<6&21 'LY9DO 63,B3&/. V\VWHPFORFN &ORFNGLYLGHU 63,UDWH FORFN 6<6$+%&/.&75/>@ 63,FORFNHQDEOH Fig 26. SPI clocking 17.3.1 Configure the SPIs for wake-up The SPI can wake up the system from sleep mode in master or slave mode. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 206 of 313 A be useful while setting up an SPI memory, for instance. R • Data frames of 1 to 16 bits supported directly. Larger frames supported by software. • Master and slave operation. • Data can be transmitted to a slave without the need to read incoming data. This can D 17.2 Features FT SPI0 is available on all parts. SPI1 is available on parts LPC812M101FDH16 and LPC812M101FDH20 only. D D D D D R R R R R A A A A A FT FT FT UM10601 FT FT D R R FT FT FT FT Chapter 17: LPC800 SPI0/1 A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D If the SPI is configured for slave mode, the SPI block can create an interrupt on a received signal even when the SPI receives no clocks from the ARM Cortex-M0+ core, which is the case when the system is in deep-sleep or power-down mode. D FT FT A A R R D D D 17.3.1.1 Wake-up from Sleep mode R A to a pin and connect the pin to the master. • Enable the SPI interrupt in the STARTERP1 register. See Table 34 “Start logic 1 interrupt wake-up enable register (STARTERP1, address 0x4004 8214) bit description”. • Enable the SPI interrupt in the NVIC. • The SPI wakes up the part from Deep-sleep or Power-down mode on the following events that cause an interrupt: – A change in the state of the SSEL pin. – <tbd>. Remark: Enable the interrupt for each wake-up event in the INTENSET register (Table 192). 17.4 Pin description The SPI signals are movable functions and are assigned to external pins through the switch matrix. See Section 9.3.1 “Connect an internal signal to a package pin” to assign the SPI functions to pins on the LPC800 package. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 207 of 313 A • Configure the SPI in slave mode. See Table 189. You must connect the SCK function R 17.3.1.2 Wake-up from Deep-sleep or Power-down mode D INTENSET register (Table 192). FT • Configure the SPI in either master or slave mode. See Table 189. • Enable the SPI interrupt in the NVIC. • Any SPI interrupt wakes up the part from sleep mode. Enable the SPI interrupt in the D D D D D R R R R R D R R D A FT R D A A R R D Table 99 SPI0_MOSI I/O any Master Out Slave In. The MOSI signal transfers serial data from the master to the slave. When the SPI is a master, it outputs serial data on this signal. When the SPI is a slave, it clocks in serial data from this signal. MOSI is driven whenever the Master bit in SPInCfg equals 1, regardless of the state of the Enable bit. PINASSIGN4 Table 100 SPI0_MISO I/O any Master In Slave Out. The MISO signal transfers serial data PINASSIGN4 from the slave to the master. When the SPI is a master, serial data is input from this signal. When the SPI is a slave, serial data is output to this signal. MISO is driven when the SPI block is enabled, the Master bit in CFG equals 0, and when the slave is selected by one or more SSEL signals. Table 100 SPI0_SSEL I/O any Slave Select . When the SPI interface is a master, it will drive PINASSIGN4 the SSEL signals to an active state before the start of serial data and then release them to an inactive state after the serial data has been sent. By default, this signal is active low but can be selected to operate as active high. When the SPI is a slave, any SSEL in an active state indicates that this slave is being addressed. The SSEL pin is driven whenever the Master bit in the CFG register equals 1, regardless of the state of the Enable bit. Table 100 SPI1_SCK I/O any Serial Clock. PINASSIGN4 Table 100 SPI1_MOSI I/O any Master Out Slave In. PINASSIGN5 Table 101 SPI1_MISO I/O any Master In Slave Out. PINASSIGN5 Table 101 SPI1_SSEL I/O any Slave Select. PINASSIGN5 Table 101 FT D D R A FT D R A Rev. 1.0 — 7 November 2012 FT any Serial Clock. SCK is a clock signal used to synchronize the PINASSIGN3 transfer of data. It is driven by the master and received by the slave. When the SPI interface is used, the clock is programmable to be active-high or active-low. SCK only switches during a data transfer. It is driven whenever the Master bit in CFG equals 1, regardless of the state of the Enable bit. All information provided in this document is subject to legal disclaimers. F FT FT I/O Preliminary user manual A A A R R D D D Reference SPI0_SCK UM10601 R R FT FT A A R R D D D SWM register FT FT FT FT Direct Pin Description ion A A A A R R D D D Table 187: SPI Pin Description FT FT FT FT FT UM10601 Chapter 17: LPC800 SPI0/1 Function A A A A A NXP Semiconductors © NXP B.V. 2012. All rights reserved. 208 of 313 D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D Chapter 17: LPC800 SPI0/1 D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D 17.5 General description FT FT FT UM10601 FT FT NXP Semiconductors D FT FT A A R R D D D R A FT D R A 7[6KLIW5HJL VWHU 6WDWH0DFKLQH 63,QB7;'$7 6&. 7[ LQWHUUXSWV 63,LQWHUUXSW 026, ,QWHUUXSW FRQWURO 5[ LQWHUUXSWV 5[6KLIW5HJL VWHU 6WDWH0DFKLQH 63,QB5;'$7 66(/SLQ OHYHOV 5[66(/66$66' 5[5G\5[2Y 3DGLQWHUIDFH *HQHUDOFRQWUROV IRUPDWFRQILJXUDWLRQV 0,62 66(/ 632/ 'LY9DO 63,B3&/. 66(/ILHOG &ORFNGLYLGHU LQWHUQDO FORFNV (1) Includes CPOL, CPHA, LSBF, FLEN, master, enable, transfer_delay, frame_delay, pre_delay, post_delay, SOT, EOT, EOF, RXIgnore, individual interrupt enables. Fig 27. SPI block diagram 17.6 Register description The Reset Value reflects the data stored in used bits only. It does not include reserved bits content. Table 188. Register overview: SPI (base address 0x4005 8000 (SPI0) and 0x4008 C000 (SPI1)) UM10601 Preliminary user manual Name Access Offset Description Reset value Reference CFG R/W 0x000 SPI Configuration register 0 Table 189 DLY R/W 0x004 SPI Delay register 0 Table 190 STAT R/W 0x008 SPI Status. Some status flags can be cleared by writing a 1 to that bit position 0x0102 Table 191 All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 209 of 313 D D D D D R R R R R A A A A A FT FT FT UM10601 FT FT D R R FT FT FT FT Chapter 17: LPC800 SPI0/1 A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D A Reset value Reference INTENSET R/W 0x00C SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. 0 Table 192 INTENCLR W 0x010 SPI Interrupt Enable Clear. Writing a 1 NA to any implemented bit position causes the corresponding bit in INTENSET to be cleared. Table 193 RXDAT R 0x014 SPI Receive Data NA Table 194 TXDATCTL R/W 0x018 SPI Transmit Data with Control 0 Table 195 TXDAT R/W 0x01C SPI Transmit Data 0 Table 196 F Description R FT FT A A R D D R A FT D R A TXCTL R/W 0x020 SPI Transmit Control 0 Table 197 DIV R/W 0x024 SPI clock Divider 0 Table 198 INTSTAT R 0x028 SPI Interrupt Status 0x02 Table 199 Rev. 1.0 — 7 November 2012 R Offset D Access D Name All information provided in this document is subject to legal disclaimers. D FT Preliminary user manual FT A …continued UM10601 A R R D D Table 188. Register overview: SPI (base address 0x4005 8000 (SPI0) and 0x4008 C000 (SPI1)) © NXP B.V. 2012. All rights reserved. 210 of 313 D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D Chapter 17: LPC800 SPI0/1 D R R A FT FT FT A A R R D D D R A FT FT A A R R D D The CFG register contains information for the general configuration of the SPI. Typically, this information is not changed during operation. Some configurations, such as CPOL, CPHA, and LSBF should not be made while the SPI is not fully idle. See the description of the Idle status (in Table 191) for more information. F FT FT A A R R D D D 17.6.1 SPI Configuration register FT FT FT UM10601 FT FT NXP Semiconductors D D R A 0 Enable 1 - 2 Master 3 4 5 Value Description Reset value SPI enable. 0 0 Disabled. The SPI is disabled and the internal state machine and counters are reset. 1 Enabled. The SPI is enabled for operation. Reserved. Read value is undefined, only zero should be written. NA Master mode select. 0 0 Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output. 1 Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input. LSBF LSB First mode enable. 0 Standard. Data is transmitted and received in standard MSB first order. 1 Reverse. Data is transmitted and received in reverse order (LSB first). CPHA 0 Clock Phase select. 0 0 Change. The SPI captures serial data on the first clock transition of the frame (when the clock changes away from the rest state). Data is changed on the following edge. 1 Capture. The SPI changes serial data on the first clock transition of the frame (when the clock changes away from the rest state). Data is captured on the following edge. CPOL Clock Polarity select. 0 0 Low. The rest state of the clock (between frames) is low. 1 High. The rest state of the clock (between frames) is high. 6 - Reserved. Read value is undefined, only zero should be written. NA 7 LOOP Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit and receive data connected together to allow simple software testing. 0 0 1 8 31:9 SPOL Disabled. Enabled. SSEL Polarity select. 0 0 Low. The SSEL pin is active low. The value in the SSEL fields of the RXDAT, TXDATCTL, and TXCTL registers related to SSEL is not inverted relative to the pins. 1 High. The SSEL pin is active high. The value in the SSEL fields of the RXDAT, TXDATCTL, and TXCTL registers related to SSEL is inverted relative to the pins. - UM10601 Preliminary user manual Reserved. Read value is undefined, only zero should be written. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 NA © NXP B.V. 2012. All rights reserved. 211 of 313 A Symbol R Bit D Table 189. SPI Configuration register (CFG, addresses 0x4005 8000 (SPI0) , 0x4005 C000 (SPI1)) bit description FT Remark: If the interface is re-configured from Master mode to Slave mode or the reverse (an unusual case), the SPI should be disabled and re-enabled with the new configuration. D D D D D R R R R R FT FT FT FT FT UM10601 D R R FT FT FT FT A A A A R R D D D Chapter 17: LPC800 SPI0/1 D R R A FT FT FT A A R R D D D R A FT FT A A R R D D The DLY register controls several programmable delays related to SPI signalling. These delays apply only to master mode, and are all stated in SPI clocks. F FT FT A A R R D D D 17.6.2 SPI Delay register A A A A A NXP Semiconductors D D Timing details are shown in: R A FT D Section 17.7.2.1 “Pre_delay and Post_delay” R A Section 17.7.2.2 “Frame_delay” Section 17.7.2.3 “Transfer_delay” Table 190. SPI Delay register (DLY, addresses 0x4005 8004 (SPI0) , 0x4005 C004 (SPI1)) bit description Bit Symbol Description Reset value 3:0 PRE_DELAY Controls the amount of time between SSEL assertion and the beginning of a data frame. 0 There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. ... 0xF = 15 SPI clock times are inserted. 7:4 POST_DELAY Controls the amount of time between the end of a data frame and SSEL deassertion. 0 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. ... 0xF = 15 SPI clock times are inserted. 11:8 FRAME_DELAY 0 Controls the minimum amount of time between adjacent data frames. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. ... 0xF = 15 SPI clock times are inserted. 15:12 TRANSFER_DELAY Controls the minimum amount of time that the SSEL is deasserted between transfers. 0 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that SSEL is deasserted is 3 SPI clock times. ... 0xF = The minimum time that SSEL is deasserted is 16 SPI clock times. 31:16 - UM10601 Preliminary user manual Reserved. Read value is undefined, only zero should be written. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 NA © NXP B.V. 2012. All rights reserved. 212 of 313 D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D Chapter 17: LPC800 SPI0/1 D R R A FT FT FT A A R R D D D R A FT FT A A R R D D The STAT register provides SPI status flags for software to read, and a control bit for forcing an end of transfer. Flags other than read-only flags may be cleared by writing ones to corresponding bits of STAT. F FT FT A A R R D D D 17.6.3 SPI Status register FT FT FT UM10601 FT FT NXP Semiconductors D D R A Symbol Description Reset Access value [1] 0 RXRDY Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT register. 0 RO 1 TXRDY Transmitter Ready flag. When 1, this bit indicates that data may be written to 1 the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT or TXDATCTL until the data is moved to the transmit shift register. RO 2 RXOV Receiver Overrun interrupt flag. This flag is set when the beginning of a received character is detected while the receiver buffer is still in use. If this occurs, the receiver buffer contents are preserved, and the incoming data is lost. Data received by the SPI should be considered undefined if RxOv is set. 0 W1 3 TXUR Transmitter Underrun interrupt flag. This flag applies only to slave mode 0 (Master = 0). In this case, the transmitter must begin sending new data on the next input clock if the transmitter is idle. If that data is not available in the transmitter holding register at that point, there is no data to transmit and the TxUr flag is set. Data transmitted by the SPI should be considered undefined if TxUr is set. W1 4 SSA Slave Select Assert. This flag is set whenever any slave select transitions from 0 deasserted to asserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy, and allows waking up the device from reduced power modes when a slave mode access begins. This flag is cleared by software. W1 5 SSD Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software. 0 W1 6 STALLED Stalled status flag. This indicates whether the SPI is currently in a stall condition. 0 RO 7 ENDTRANSFER End Transfer control bit. Software can set this bit to force an end to the current 0 transfer when the transmitter finishes any activity already in progress, as if the EOT flag had been set prior to the last transmission. This capability is included to support cases where it is not known when transmit data is written that it will be the end of a transfer. The bit is cleared when the transmitter becomes Idle as the transfer comes to an end. Forcing an end of transfer in this manner causes any specified FrameDelay and TransferDelay to be inserted. RO/W1 8 IDLE Idle status flag. This bit is 1 whenever the SPI master function is fully idle. This 1 means that the transmit holding register is empty and the transmitter is not in the process of sending data. RO 31:9 - Reserved. Read value is undefined, only zero should be written. NA UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 NA © NXP B.V. 2012. All rights reserved. 213 of 313 A Bit R Table 191. SPI Status register (STAT, addresses 0x4005 8008 (SPI0) , 0x4005 C008 (SPI1)) bit description D In this register, the following notation is used: RO = Read-only, W1 = write 1 to clear.. FT STAT contains 2 error flags. RXOV and TXUR. These are receiver overrun and transmit underrun, respectively. If either of these errors occur during operation, the SPI should be disabled, then re-enabled in order to make sure all internal states are cleared before attempting to resume operation. D D D D D R R R R R D R R FT FT FT FT A A A A R R D D D D R R A FT FT FT A A R R D D D A F FT FT A A R R R D FT The INTENSET register is used to enable various SPI interrupt sources. Enable bits in INTENSET are mapped in locations that correspond to the flags in the STAT register. The complete set of interrupt enables may be read from this register. Writing ones to implemented bits in this register causes those bits to be set. The INTENCLR register is used to clear bits in this register. See Table 191 for details of the interrupts. FT A A R R D 17.6.4 SPI Interrupt Enable read and Set register D D D RO = Read-only, W1 = write 1 to clear. FT FT FT FT FT UM10601 Chapter 17: LPC800 SPI0/1 [1] A A A A A NXP Semiconductors D D R A RXRDYEN 1 2 Reset value Determines whether an interrupt occurs when receiver data is available. 0 0 No interrupt will be generated when receiver data is available. 1 An interrupt will be generated when receiver data is available in the RXDAT register. TXRDYEN Determines whether an interrupt occurs when the transmitter holding register is available. 0 No interrupt will be generated when the transmitter holding register is available. 1 An interrupt will be generated when data may be written to TXDAT. RXOVEN 0 Determines whether an interrupt occurs when a receiver overrun occurs. This happens in slave mode when there is a need for the receiver to move newly received data to the RXDAT register when it is already in use. 0 The interface prevents receiver overrun in Master mode by not allowing a new transmission to begin when a receiver overrun would otherwise occur. 3 4 5 31:6 0 No interrupt will be generated when a receiver overrun occurs. 1 An interrupt will be generated if a receiver overrun occurs. TXUREN Determines whether an interrupt occurs when a transmitter underrun occurs. This happens in slave mode when there is a need to transmit data when none is available. 0 No interrupt will be generated when the transmitter underruns. 1 An interrupt will be generated if the transmitter underruns. SSAEN 0 Determines whether an interrupt occurs when the Slave Select is asserted. 0 0 No interrupt will be generated when any Slave Select transitions from deasserted to asserted. 1 An interrupt will be generated when any Slave Select transitions from deasserted to asserted. SSDEN Determines whether an interrupt occurs when the Slave Select is deasserted. 0 0 No interrupt will be generated when all asserted Slave Selects transition to deasserted. 1 An interrupt will be generated when all asserted Slave Selects transition to deasserted. - UM10601 Preliminary user manual Reserved. Read value is undefined, only zero should be written. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 NA © NXP B.V. 2012. All rights reserved. 214 of 313 A 0 Value Description R Symbol D Bit FT Table 192. SPI Interrupt Enable read and Set register (INTENSET, addresses 0x4005 800C (SPI0) , 0x4005 C00C (SPI1)) bit description D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D Chapter 17: LPC800 SPI0/1 D R R A FT FT FT A A R R D D D R A FT Table 193. SPI Interrupt Enable clear register (INTENCLR, addresses 0x4005 8010 (SPI0) , 0x4005 C010 (SPI1)) bit description FT A A R R D D The INTENCLR register is used to clear interrupt enable bits in the INTENSET register. F FT FT A A R R D D D 17.6.5 SPI Interrupt Enable Clear register FT FT FT UM10601 FT FT NXP Semiconductors D D 0 1 TXRDYEN Writing 1 clears the corresponding bits in the INTENSET register. 0 2 RXOVEN Writing 1 clears the corresponding bits in the INTENSET register. 0 3 TXUREN Writing 1 clears the corresponding bits in the INTENSET register. 0 4 SSAEN Writing 1 clears the corresponding bits in the INTENSET register. 0 5 SSDEN Writing 1 clears the corresponding bits in the INTENSET register. 0 31:6 - Reserved. Read value is undefined, only zero should be written. NA 17.6.6 SPI Receiver Data register The read-only RXDAT register provides the means to read the most recently received data. The value of SSEL can be read along with the data. For details on the slave select process, see Section 17.7.4. Table 194. SPI Receiver Data register (RXDAT, addresses 0x4005 8014 (SPI0) , 0x4005 C014 (SPI1)) bit description Bit Symbol Description 15:0 RXDAT Receiver Data. This contains the next piece of received data. undefined The number of bits that are used depends on the FLen setting in TXCTL / TXDATCTL. 16 RXSSELN Slave Select for receive. This field allows the state of the SSEL undefined pin to be saved along with received data. The value will reflect the SSEL pin for both master and slave operation. A zero indicates that a slave select is active. The actual polarity of each slave select pin is configured by the related SPOL bit in CFG. 19:17 - Reserved. 20 Start of Transfer flag. This flag will be 1 if this is the first frame after SSEL went from deasserted to asserted (i.e., any previous transfer has ended). This information can be used to identify the first piece of data in cases where the frame length is greater than 16 bit. SOT 31:21 - UM10601 Preliminary user manual Reset value - Reserved, the value read from a reserved bit is not defined. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 NA © NXP B.V. 2012. All rights reserved. 215 of 313 A RXRDYEN Writing 1 clears the corresponding bits in the INTENSET register. R 0 D Reset value FT Description A Symbol R Bit D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D Chapter 17: LPC800 SPI0/1 D R R A FT FT FT A A R R D D D R A FT FT A A R R D D The TXDATCTL register provides a location where both transmit data and control information can be written simultaneously. This allows detailed control of the SPI without a separate write of control information for each piece of data. F FT FT A A R R D D D 17.6.7 SPI Transmitter Data and Control register FT FT FT UM10601 FT FT NXP Semiconductors D D R A Bit Symbol 15:0 16 Value Description Reset value TXDAT Transmit Data. This field provides from 1 to 16 bits of data to be transmitted. 0 TXSSELN Transmit Slave Select . This field controls what is output for SSEL in master mode. 0 Remark: The active state of the SSEL function is configured by bits in the CFG register. 0 1 SSEL asserted. SSEL not asserted. 19:17 - Reserved. 20 End of Transfer. The asserted SSEL will be deasserted at the end of a transfer, and remain so for at least the time specified by the Transfer_delay value in the DLY register. 21 22 EOT 0 0 SSEL not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data. 1 SSEL deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data. EOF End of Frame. Between frames, a delay may be inserted, as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the FRAME_DELAY value = 0. This control can be used as part of the support for frame lengths greater than 16 bits. 0 Data not EOF. This piece of data transmitted is not treated as the end of a frame. 1 Data EOF. This piece of data is treated as the end of a frame, causing the FRAME_DELAY time to be inserted before subsequent data is transmitted. RXIGNORE 0 Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver to simplify the transmit process. 0 0 Read received data. Received data must be read in order to allow transmission to progress. In slave mode, an overrun error will occur if received data is not read before new data is received. 1 Ignore received data. Received data is ignored, allowing transmission without reading unneeded received data. No receiver flags are generated. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 216 of 313 A Table 195. SPI Transmitter Data and Control register (TXDATCTL, addresses 0x4005 8018 (SPI0) , 0x4005 C018 (SPI1)) bit description R For details on using multiple consecutive frames for frame lengths larger than 16 bit, see Section 17.7.5 “Data lengths greater than 16 bits”. D For details on the slave select process, see Section 17.7.4. FT When control information remains static during transmit, the TXDAT register should be used (see Section 17.6.8) instead of the TXDATCTL register. Control information can then be written separately via the TXCTL register (see Section 17.6.9). The upper part of TXDATCTL (bits 27 to 16) are the same bits contained in the TXCTL register. The two registers simply provide two ways to access them. D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D A D FT NA 0x0 D Reserved. Read value is undefined, only zero should be written. Frame Length. Specifies the frame length from 1 to 16 bits. Note that frame lengths greater than 16 bits are supported by implementing multiple sequential frames. D R A D R A Note that if a 1-bit frame is selected, the master function will always insert a delay with a length of one SCK time following the single clock seen on the SCK pin. 0x0 = Data frame is 1 bit in length. 0x1 = Data frame is 2 bits in length. 0x2 = Data frame is 3 bits in length. ... 0xF = Data frame is 16 bits in length. 31:28 - Reserved. Read value is undefined, only zero should be written. NA 17.6.8 SPI Transmitter Data Register The TXDAT register is written in order to send data via the SPI transmitter when control information is not changing during the transfer (see Section 17.6.7). That data will be sent to the transmit shift register when it is available, and another character may then be written to TXDAT. Table 196. SPI Transmitter Data Register (TXDAT, addresses 0x4005 801ST (SPI0) , 0x4005 C00C (SPI1)) bit description Bit Symbol Description Reset value 15:0 DATA Transmit Data. This field provides from 4 to 16 bits of data to be transmitted. 0 Reserved. Only zero should be written. NA 31:16 - 17.6.9 SPI Transmitter Control register The TXCTL register provides a way to separately access control information for the SPI. These bits are another view of the same-named bits in the TXDATCTL register (see Section 17.6.7). Changing bits in TXCTL has no effect unless data is later written to the TXDAT register. Data written to TXDATCTL overwrites the TXCTL register. When control information needs to be changed during transmission, the TXDATCTL register should be used (see Section 17.6.7) instead of TXDAT. Control information can then be written along with data. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 FT 27:24 FLEN FT A A R R D Reset value F FT FT A A R R R Description D D D - FT FT FT FT 23 Value A A A A R R D D D Table 195. SPI Transmitter Data and Control register (TXDATCTL, addresses 0x4005 8018 (SPI0) , 0x4005 C018 (SPI1)) bit description …continued Symbol FT FT FT FT FT UM10601 Chapter 17: LPC800 SPI0/1 Bit A A A A A NXP Semiconductors © NXP B.V. 2012. All rights reserved. 217 of 313 D D D D D R R R R R A A A A A FT FT FT UM10601 FT FT D R R FT FT FT FT Chapter 17: LPC800 SPI0/1 A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D D D R A D D Description Reset value 15:0 - Reserved. Read value is undefined, only zero should be written. NA 16 TX SSEL Transmit Slave Select. 0x0 19:17 - Reserved. 0x0 20 EOT End of Transfer. 0 21 EOF End of Frame. 0 22 RXIGNORE Receive Ignore. 23 - R Symbol FT FT A A R Bit F FT FT A A R R Table 197. SPI Transmitter Control register (TXCTL, addresses 0x4005 8020 (SPI0) , 0x4005 C020 (SPI1)) bit description D D R A FT D R A 0 Reserved. Read value is undefined, only zero should be written. NA 27:24 FLEN Frame Length. 0x0 31:28 - Reserved. Read value is undefined, only zero should be written. NA 17.6.10 SPI Divider register The DIV register determines the clock used by the SPI in master mode. For details on clocking, see Section 17.7.3 “Clocking and data rates”. Table 198. SPI Divider register (DIV, addresses 0x4005 8024 (SPI0) , 0x4005 C024(SPI1)) bit description Bit Symbol Description Reset Value 15:0 DIVVAL Rate divider value,1. Specifies how the PCLK for the SPI is divided to produce the SPI clock rate in master mode. 0 DIVVAL is -1 encoded such that the value 0 results in PCLK/1, the value 1 results in PCLK/2, up to the maximum possible divide value of 0xFFFF, which results in PCLK/65536. 31:16 - Reserved. Read value is undefined, only zero should be written. NA 17.6.11 SPI Interrupt Status register The read-only INTSTAT register provides a view of those interrupt flags that are currently enabled. This can simplify software handling of interrupts. See Table 191 for detailed descriptions of the interrupt flags. Table 199. SPI Interrupt Status register (INTSTAT, addresses 0x4005 8028 (SPI0) , 0x4005 C028 (SPI1)) bit description UM10601 Preliminary user manual Bit Symbol Description Reset value 0 RXRDY Receiver Ready flag. 0 1 TXRDY Transmitter Ready flag. 1 2 RXOV Receiver Overrun interrupt flag. 0 3 TXUR Transmitter Underrun interrupt flag. 0 All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 218 of 313 D D D D D R R R R R D R R FT FT FT FT A A A A R R D D D D R R A FT FT FT A A R R D D D D R A D Reserved. Read value is undefined, only zero should be written. NA All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 219 of 313 A - R 31:6 D 0 D 0 Slave Select Deassert. FT Slave Select Assert. SSD A SSA 5 R 4 D Preliminary user manual FT UM10601 FT A A R R D Reset value F FT Description FT A A R R D D Table 199. SPI Interrupt Status register (INTSTAT, addresses 0x4005 8028 (SPI0) , 0x4005 C028 (SPI1)) bit description Symbol FT FT FT FT FT UM10601 Chapter 17: LPC800 SPI0/1 Bit A A A A A NXP Semiconductors D D D D D R R R R R A A A A A D R R FT FT FT FT D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D 17.7.1 Operating modes: clock and phase selection A A A A R R D D D Chapter 17: LPC800 SPI0/1 17.7 Functional description FT FT FT UM10601 FT FT NXP Semiconductors D D SPI interfaces typically allow configuration of clock phase and polarity. These are sometimes referred to as numbered SPI modes, as described in Table 200 and shown in Figure 28. CPOL and CPHA are configured by bits in the CFG register (Section 17.6.1). R A FT D R A Table 200: SPI mode summary CPOL CPHA SPI Description Mode SCK rest SCK data SCK data state change edge sample edge 0 0 0 The SPI captures serial data on the first clock transition of the frame (when the clock changes away from the rest state). Data is changed on the following edge. low falling rising 0 1 1 The SPI changes serial data on the first clock transition of the frame (when the clock changes away from the rest state). Data is captured on the following edge. low rising falling 1 0 2 Same as mode 0 with SCK inverted. high rising falling 1 1 3 Same as mode 1 with SCK inverted. high falling rising &3+$ 0RGH&32/ 6&. 0RGH&32/ 6&. 66(/ 026, 06% /6% 0,62 06% /6% 'DWDIUDPH &3+$ 0RGH&32/ 6&. 0RGH&32/ 6&. 66(/ 026, 06% /6% 0,62 06% /6% 'DWDIUDPH Fig 28. Basic SPI operating modes UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 220 of 313 D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R R FT FT A A R D D R A FT D Frame_delay: delay between data frames when SSEL is not deasserted Pre_delay and Post_delay are illustrated by the examples in Figure 29. The Pre_delay value controls the amount of time between SSEL being asserted and the beginning of the subsequent data frame. The Post_delay value controls the amount of time between the end of a data frame and the deassertion of SSEL. 3UH DQGSRVW GHOD\ &3+$ 3UHBGHOD\ 3RVWBGHOD\ 0RGH&32/ 6&. 0RGH&32/ 6&. 66(/ 06% /6% 0,62 06% /6% 3UHBGHOD\ 'DWDIUDPH 3RVWBGHOD\ 3UH DQGSRVW GHOD\ &3+$ 3UHBGHOD\ 3RVWBGHOD\ 0RGH&32/ 6&. 0RGH&32/ 6&. 66(/ 3UHBGHOD\ 06% /6% 06% /6% 'DWDIUDPH 3RVWBGHOD\ Fig 29. Pre_delay and Post_delay UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 221 of 313 A 17.7.2.1 Pre_delay and Post_delay R Transfer_delay: minimum duration of SSEL in the deasserted state between transfers 026, F D D Post_delay: delay at the end of a data frame before SSEL is deasserted A FT FT A A R R D D D Pre_delay: delay after SSEL is asserted before data clocking begins FT FT FT FT Several delays can be specified for SPI frames. These include: A A A A R R D D D 17.7.2 Frame delays FT FT FT FT FT UM10601 Chapter 17: LPC800 SPI0/1 • • • • A A A A A NXP Semiconductors D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D Chapter 17: LPC800 SPI0/1 D R R A FT FT FT A A R R D D D R A FT The Frame_delay value controls the amount of time at the end of each frame. This delay is inserted when the EOF bit = 1. Frame_delay is illustrated by the examples in Figure 30. Note that frame boundaries occur only where specified. This is because frame lengths can be any size, involving multiple data writes. See Section 17.7.5 for more information. F FT A A R R D D D 17.7.2.2 Frame_delay FT FT FT UM10601 FT FT NXP Semiconductors D FT FT A A R R D D D R A FT D R A )UDPHGHOD\ &3+$ )UDPH BGHOD\ 3UHBGHOD\ 3RVWBGHOD\ 0RGH&32/ 6&. 0RGH&32/ 6&. 66(/ 026, 06% /6% 06% /6% 0,62 06% /6% 06% /6% )LUVWGDWDIUDPH )UDPHBGHOD\ 6HFRQGGDWDIUDPH )UDPHGHOD\ &3+$ )UDPH BGHOD\ 3UHBGHOD\ 3RVWBGHOD\ 0RGH&32/ 6&. 0RGH&32/ 6&. 66(/ 026, 06% /6% 06% /6% 0,62 06% /6% 06% /6% )LUVWGDWDIUDPH )UDPHBGHOD\ 6HFRQGGDWDIUDPH Fig 30. Frame_delay UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 222 of 313 D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D Chapter 17: LPC800 SPI0/1 D R R A FT FT FT A A R R D D D R A FT FT FT A A R R D D The Transfer_delay value controls the minimum amount of time that SSEL is deasserted between transfers, because the EOT bit = 1. When Transfer_delay = 0, SSEL may be deasserted for a minimum of one SPI clock time. Transfer_delay is illustrated by the examples in Figure 31. F FT A A R R D D D 17.7.2.3 Transfer_delay FT FT FT UM10601 FT FT NXP Semiconductors D D R A FT D R A )UDPHGHOD\ &3+$ )UDPH BGHOD\ 3UHBGHOD\ 3RVWBGHOD\ 0RGH&32/ 6&. 0RGH&32/ 6&. 66(/ 026, 06% /6% 06% /6% 0,62 06% /6% 06% /6% )LUVWGDWDIUDPH )UDPHBGHOD\ 6HFRQGGDWDIUDPH )UDPHGHOD\ &3+$ )UDPH BGHOD\ 3UHBGHOD\ 3RVWBGHOD\ 0RGH&32/ 6&. 0RGH&32/ 6&. 66(/ 026, 06% /6% 06% /6% 0,62 06% /6% 06% /6% )LUVWGDWDIUDPH )UDPHBGHOD\ 6HFRQGGDWDIUDPH Fig 31. Transfer_delay UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 223 of 313 D D D D D R R R R R FT FT FT FT FT UM10601 D R R FT FT FT FT A A A A R R D D D Chapter 17: LPC800 SPI0/1 D R R A FT FT FT A A R R D D D R A F FT D FT FT A A R R D In order to use the SPI, clocking details must be defined. This includes configuring the system clock and selection of the clock divider value in DIV. See Figure 26. FT A A R R D D D 17.7.3 Clocking and data rates A A A A A NXP Semiconductors D D R 17.7.3.1 Data rate calculations A In slave mode, the clock is taken from the SCK input and the SPI clock divider is not used. 17.7.4 Slave select The SPI block provides for one Slave Select input in slave mode or output in master mode. The SSEL can be set for normal polarity (active low), or can be inverted (active high). Representation of the SSEL in a register is always active low. If the SSEL is inverted, this is done as the signal leaves/enters the SPI block. In slave mode, the asserted SSEL that is connected to a pin will activate the SPI. In master mode, the SSEL that is connected to a pin will be output as defined in the SPI registers. In master mode, the Slave Select is configured by the TXSSE LN field, which appears in both the CCD and DETECT registers. In slave mode, the state of the SSEL is saved along with received data in the RXSSELN field of the RXDAT register. 17.7.5 Data lengths greater than 16 bits The SPI interface handles data frame sizes from 1 to 16 bits directly. Larger sizes can be handled by splitting data up into groups of 16 bits or less. For example, 24 bits can be supported as 2 groups of 16 bits and 8 bits or 2 groups of 12 bits, among others. Frames of any size, including greater than 32 bits, can supported in the same way. Details of how to handle larger data widths depend somewhat on other SPI configuration options. For instance, if it is intended for Slave Selects to be deasserted between frames, then this must be suppressed when a larger frame is split into more than one part. Sending 2 groups of 12 bits with SSEL deasserted between 24-bit increments, for instance, would require changing the value of the EOF bit on alternate 12-bit frames. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 224 of 313 A The SPI clock divider is an integer divider. The SPI in master mode can be set to run at the same speed as the selected PCLK, or at lower integer divide rates. The SPI rate will be = PCLK_SPIn / DIVVAL. R In master mode, the SPI rate clock produced by the SPI clock divider is used directly as the outgoing SCK. Again, the upper rate limit depends on the speed of the logic and pin electronics, and signalling quality in the external connections. D In slave mode, this means that the SCK from the external master is used directly to run the transmit and receive shift registers and other logic. The upper rate limit depends on the speed of the logic and pin electronics, and signalling quality in the external connections. FT The SPI interface is designed to operate asynchronously from any on-chip clocks, and without the need for overclocking. D D D D D R R R R R FT FT FT FT FT UM10601 D R R FT FT FT FT A A A A R R D D D Chapter 17: LPC800 SPI0/1 D R R A FT FT FT A A R R D D D R A FT FT A A R R D D A stall for Master transmit data can happen in modes 0 and 2 when SCK cannot be returned to the rest state until the MSB of the next data frame can be driven on MOSI. In this case, the stall happens just before the final clock edge of data if the next piece of data is not yet available. F FT FT A A R R D D D 17.7.6 Data stalls A A A A A NXP Semiconductors D D R A Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 225 of 313 A UM10601 R Stalls are reflected in the STAT register by the Stalled status flag, which indicates the current SPI status. D In modes 1 and 3, the same kind of receiver stall can occur, but just before the final clock edge of the received data. Also, a transmitter stall will not happen in modes 1 and 3 because the transmitted data is complete at the point where a stall would otherwise occur, so it is not needed. FT A stall for Master receive can happen when a receiver overrun would otherwise occur if the transmitter was not stalled. In modes 0 and 2, this occurs if the previously received data is not read before the end of the next piece of is received. This stall happens one clock edge earlier than the transmitter stall. D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D Chapter 17: LPC800 SPI0/1 D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D 7UDQVPLWWHUVWDOO&3+$ )UDPH BGHOD\ 3UHBGHOD\ 3RVWBGHOD\ FORFNVWDOO FT FT FT UM10601 FT FT NXP Semiconductors D FT FT A A R R D 0RGH&32/ 6&. D D R A FT 0RGH&32/ 6&. D /6% 06% /6% 0,62 06% /6% 06% /6% )LUVWGDWDIUDPH A 06% R 026, 6HFRQGGDWDIUDPH 5HFHLYHUVWDOO&3+$ )UDPH BGHOD\ 3UHBGHOD\ 3RVWBGHOD\ FORFNVWDOO 0RGH&32/ 6&. 0RGH&32/ 6&. 026, 06% /6% 06% /6% 0,62 06% /6% 06% /6% )LUVWGDWDIUDPH 6HFRQGGDWDIUDPH 5HFHLYHUVWDOO&3+$ )UDPH BGHOD\ 3UHBGHOD\ 3RVWBGHOD\ FORFNVWDOO 0RGH&32/ 6&. 0RGH&32/ 6&. 026, 06% /6% 06% /6% 0,62 06% /6% 06% /6% )LUVWGDWDIUDPH 6HFRQGGDWDIUDPH Fig 32. Examples of data stalls UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 226 of 313 D D D D D R R R R R A A A A A FT FT FT FT FT D R R A A FT FT FT FT A A R R D D D UM10601 D D D R R A FT FT R A F FT FT A A R R D D Preliminary user manual D Rev. 1.0 — 7 November 2012 FT A A R R D Chapter 18: LPC800 Cyclic Redundancy Check (CRC) engine D FT FT A A R R D D D 18.1 How to read this chapter R A FT D The CRC engine is available on all LPC800 parts. R A 18.2 Features • Supports three common polynomials CRC-CCITT, CRC-16, and CRC-32. – CRC-CCITT: x16 + x12 + x5 + 1 – CRC-16: x16 + x15 + x2 + 1 – CRC-32: x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1 • Bit order reverse and 1’s complement programmable setting for input data and CRC sum. • Programmable seed number setting. • Supports CPU PIO back-to-back transfer. • Accept any size of data width per write: 8, 16 or 32-bit. – 8-bit write: 1-cycle operation – 16-bit write: 2-cycle operation (8-bit x 2-cycle) – 32-bit write: 4-cycle operation (8-bit x 4-cycle) 18.3 Basic configuration Enable the clock to the CRC engine in the SYSAHBCLKCTRL register (Table 18, bit 13). 18.4 Pin description The CRC engine has no configurable pins. 18.5 General description The Cyclic Redundancy Check (CRC) generator with programmable polynomial settings supports several CRC standards commonly used. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 227 of 313 D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D Chapter 18: LPC800 Cyclic Redundancy Check (CRC) engine D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D 18.6 Description FT FT FT UM10601 FT FT NXP Semiconductors D FT FT A A R R D D D R A FT &5 & 02'( D R A &5 & 6((' &&,7 7 32/< &5&, ' $+%%86 % % % 08 ; V &203 &5& 32/< %,7 5(9(56( % 08 ; 08 ; ' 4 &5 & 5(* ( V &203 %,7 5(9(56( &5& 32/< &5&:5 %8) &5 & )60 &5& 680 Fig 33. CRC block diagram 18.7 Register description Table 201. Register overview: CRC engine (base address 0x5000 0000) UM10601 Preliminary user manual Name Access Address Description offset Reset value MODE R/W 0x00 CRC mode register 0x0000 0000 SEED R/W 0x04 CRC seed register 0x0000 FFFF SUM RO 0x08 CRC checksum register 0x0000 FFFF WR_DATA WO 0x08 CRC data register - All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 228 of 313 D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R R 1:0 CRC_POLY CRC polynom: 00 FT Reset value FT A A R Description D D R A FT 1X= CRC-32 polynomial D R 01= CRC-16 polynomial A 00= CRC-CCITT polynomial Data bit order: 0 1= Bit order reverse for CRC_WR_DATA (per byte) 0= No bit order reverse for CRC_WR_DATA (per byte) Data complement: 0 1= 1’s complement for CRC_WR_DATA 0= No 1’s complement for CRC_WR_DATA 4 BIT_RVS_SUM 0 CRC sum bit order: 1= Bit order reverse for CRC_SUM 0= No bit order reverse for CRC_SUM 5 CMPL_SUM CRC sum complement: 0 1= 1’s complement for CRC_SUM 0=No 1’s complement for CRC_SUM 31:6 Reserved Always 0 when read 0x0000000 18.7.2 CRC seed register Table 203. CRC seed register (SEED, address 0x5000 0004) bit description Bit Symbol Description 31:0 CRC_SEED A write access to this register will load CRC seed value to 0x0000 FFFF CRC_SUM register with selected bit order and 1’s complement pre-processes. Reset value Remark: A write access to this register will overrule the CRC calculation in progresses. 18.7.3 CRC checksum register This register is a Read-only register containing the most recent checksum. The read request to this register is automatically delayed by a finite number of wait states until the results are valid and the checksum computation is complete. Table 204. CRC checksum register (SUM, address 0x5000 0008) bit description Bit Symbol Description Reset value 31:0 CRC_SUM The most recent CRC sum can be read through this register with selected bit order and 1’s complement post-processes. 0x0000 FFFF 18.7.4 CRC data register This register is a Write-only register containing the data block for which the CRC sum will be calculated. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 F D D Symbol CMPL_WR A FT FT A A R R D D D Bit 3 FT FT FT FT Table 202. CRC mode register (MODE, address 0x5000 0000) bit description BIT_RVS_WR A A A A R R D D D 18.7.1 CRC mode register FT FT FT FT FT UM10601 Chapter 18: LPC800 Cyclic Redundancy Check (CRC) engine 2 A A A A A NXP Semiconductors © NXP B.V. 2012. All rights reserved. 229 of 313 D D D D D R R R R R A A A A A FT FT FT UM10601 FT FT D R R FT FT FT FT Chapter 18: LPC800 Cyclic Redundancy Check (CRC) engine A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D R Data written to this register will be taken to perform CRC calculation with selected bit order and 1’s complement pre-process. Any write size 8, 16 or 32-bit are allowed and accept back-to-back transactions. R FT FT A A R D D R A R CRC_WR_DATA D 31:0 F Reset value FT Description D Symbol D Bit A FT FT A A R R D D D Table 205. CRC data register (WR_DATA, address 0x5000 0008) bit description A UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 230 of 313 D D D D D R R R R R FT FT FT FT FT UM10601 D R R FT FT FT FT A A A A R R D D D Chapter 18: LPC800 Cyclic Redundancy Check (CRC) engine D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D 18.8 Functional description A A A A A NXP Semiconductors D D FT FT A A R R The following sections describe the register settings for each supported CRC standard: D D R A 18.8.1 CRC-CCITT set-up FT D Polynomial = x16 + x12 + x5 + 1 R A Seed Value = 0xFFFF Bit order reverse for data input: NO 1's complement for data input: NO Bit order reverse for CRC sum: NO 1's complement for CRC sum: NO CRC_MODE = 0x0000 0000 CRC_SEED = 0x0000 FFFF 18.8.2 CRC-16 set-up Polynomial = x16 + x15 + x2 + 1 Seed Value = 0x0000 Bit order reverse for data input: YES 1's complement for data input: NO Bit order reverse for CRC sum: YES 1's complement for CRC sum: NO CRC_MODE = 0x0000 0015 CRC_SEED = 0x0000 0000 18.8.3 CRC-32 set-up Polynomial = x32+ x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1 Seed Value = 0xFFFF FFFF Bit order reverse for data input: YES 1's complement for data input: NO Bit order reverse for CRC sum: YES 1's complement for CRC sum: YES CRC_MODE = 0x0000 0036 CRC_SEED = 0xFFFF FFFF UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 231 of 313 D R A A A A A FT FT FT FT FT D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D Preliminary user manual D Rev. 1.0 — 7 November 2012 R R R R Chapter 19: LPC800 Flash controller D D D D UM10601 D FT FT A A R R D D D 19.1 How to read this chapter R A FT D The flash controller is identical on all LPC800 parts. R A 19.2 Features • Controls flash access time. • Provides registers for flash signature generation. 19.3 General description The flash controller is accessible for programming flash wait states and for generating the the flash signature. 19.4 Register description Table 206. Register overview: FMC (base address 0x4004 0000) Name Access Address Description offset Reset Reference value FLASHCFG R/W 0x010 Flash configuration register <tbd> Table 207 FMSSTART R/W 0x020 Signature start address register 0 Table 208 FMSSTOP R/W 0x024 Signature stop-address register 0 Table 209 FMSW0 R 0x02C Signature word - Table 210 19.4.1 Flash configuration register Depending on the system clock frequency, access to the flash memory can be configured with various access times by writing to the FLASHCFG register at address 0x4003 C010. Remark: Improper setting of this register may result in incorrect operation of the flash memory. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 232 of 313 D D D D D R R R R R A A A A A FT FT FT UM10601 FT FT D R R FT FT FT FT Chapter 19: LPC800 Flash controller A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D D D D D R A Reserved. User software must not change the value of these bits. Bits 31:2 must be written back exactly as read. - 19.4.2 Flash signature start address register Table 208. Flash Module Signature Start register (FMSSTART - 0x4003 C020) bit description Bit Symbol Description Reset value 16:0 START Signature generation start address (corresponds to AHB byte address bits[20:4]). 0 31:17 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 19.4.3 Flash signature stop address register Table 209. Flash Module Signature Stop register (FMSSTOP - 0x4003 C024) bit description Bit Symbol 16:0 Value Description Reset value STOPA Stop address for signature generation (the word specified by STOPA is included in the address range). The address is in units of memory words, not bytes. 0 30:17 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 0 31 STRTBIST When this bit is written to 1, signature generation starts. At the end of signature generation, this bit is automatically cleared. 0 19.4.4 Flash signature generation result register The signature generation result register returns the flash signature produced by the embedded signature generator. The generated flash signature can be used to verify the flash memory contents. The generated signature can be compared with an expected signature and thus makes saves time and code space. The method for generating the signature is described in Section 19.5.1. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 F Reserved. - A 0x3 FT Reserved. FT 0x2 A 2 system clocks flash access time (for system clock frequencies of up to 30 MHz). R 0x1 D 1 system clock flash access time (for system clock frequencies of up to 20 MHz). 10 FT 0x0 A 31:2 - Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access. A R R FLASHTIM Reset value D 1:0 Description R Value D Symbol FT Bit FT A A R R Table 207. Flash configuration register (FLASHCFG, address 0x4003 C010) bit description © NXP B.V. 2012. All rights reserved. 233 of 313 D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D Chapter 19: LPC800 Flash controller D R R A FT FT FT A A R R D D D R A Symbol Description Reset value 31:0 SIG 32-bit signature. - FT FT A A R R D D Bit F FT FT A A R R D D D Table 210. FMSW0 register bit description (FMSW0, address: 0x4003 C02C) FT FT FT UM10601 FT FT NXP Semiconductors D D R A 19.5 Functional description FT D R A 19.5.1 Flash signature generation The flash module contains a built-in signature generator. This generator can produce a 32-bit signature from a range of flash memory. A typical usage is to verify the flashed contents against a calculated signature (e.g. during programming). The address range for generating a signature must be aligned on flash-word boundaries, i.e. 32-bit boundaries. Once started, signature generation completes independently. While signature generation is in progress, the flash memory cannot be accessed for other purposes, and an attempted read will cause a wait state to be asserted until signature generation is complete. Code outside of the flash (e.g. internal RAM) can be executed during signature generation. This can include interrupt services, if the interrupt vector table is re-mapped to memory other than the flash memory. The code that initiates signature generation should also be placed outside of the flash memory. 19.5.1.1 Signature generation address and control registers These registers control automatic signature generation. A signature can be generated for any part of the flash memory contents. The address range to be used for generation is defined by writing the start address to the signature start address register (FMSSTART) and the stop address to the signature stop address register (FMSSTOP. The start and stop addresses must be aligned to 32-bit boundaries. Signature generation is started by setting the STRTBIST bit in the FMSSTOP register. Setting the STRTBIST bit is typically combined with the signature stop address in a single write. Table 208 and Table 209 show the bit assignments in the FMSSTART and FMSSTOP registers respectively. 19.5.1.2 Signature generation A signature can be generated for any part of the flash contents. The address range to be used for signature generation is defined by writing the start address to the FMSSTART register, and the stop address to the FMSSTOP register. The signature generation is started by writing a 1 to the SIG_START bit in the FMSSTOP register. Starting the signature generation is typically combined with defining the stop address, which is done in the STOP bits of the same register. The time that the signature generation takes is proportional to the address range for which the signature is generated. Reading of the flash memory for signature generation uses a self-timed read mechanism and does not depend on any configurable timing settings for the flash. A safe estimation for the duration of the signature generation is: Duration = int((60 / tcy) + 3) x (FMSSTOP - FMSSTART + 1) UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 234 of 313 D D D D D R R R R R A A A A A FT FT FT UM10601 FT FT D R R FT FT FT FT Chapter 19: LPC800 Flash controller A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D When signature generation is triggered via software, the duration is in AHB clock cycles, and tcy is the time in ns for one AHB clock. The SIG_DONE bit in FMSTAT can be polled by software to determine when signature generation is complete. D FT FT A A R R D D D After signature generation, a 32-bit signature can be read from the FMSW0 register. The 32-bit signature reflects the corrected data read from the flash and the flash parity bits and check bit values. R A FT D R A 19.5.1.3 Content verification The signature as it is read from the FMSW0 register must be equal to the reference signature. The following pseudo-code shows the algorithm to derive the reference signature: sign = 0 FOR address = FMSSTART.START to FMSSTOP.STOPA { FOR i = 0 TO 30{ nextSign[i] = f_Q[addredd[i] XOR sign[i + 1] nextSign[31] = f_q[address[31] XOR sign[0] XOR sign[10] XOR sign[30] XOR sign[31] sign = nextSign } } signature32 = sign UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 235 of 313 D D R R R R R A A A A A FT FT FT FT FT D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D Chapter 20: LPC800 Boot ROM R A F FT FT A A R R D D Preliminary user manual D Rev. 1.0 — 7 November 2012 D D D UM10601 D FT FT A A R R D D D 20.1 How to read this chapter R A FT D The Boot ROM is identical for all LPC800 parts. R A 20.2 Features • 8 kB on-chip boot ROM • Contains the boot loader with In-System Programming (ISP) facility and the following APIs: – In Application Programming (IAP) of flash memory – Power profiles for optimizing power consumption and system performance – USART drivers – I2C drivers 20.3 General description 20.3.1 Boot loader The boot loader controls initial operation after reset and also provides the means to accomplish programming of the flash memory via USART. This could be initial programming of a blank device, erasure and re-programming of a previously programmed device, or programming of the flash memory by the application program in a running system. The boot loader code is executed every time the part is powered on or reset. The boot loader can execute the ISP command handler or the user application code. A LOW level after reset at the PIO0_1 pin is considered as an external hardware request to start the ISP command handler via USART. For details on the boot process, see Section 20.4.3 “Boot process”. Remark: SRAM location 0x1000 0000 to 0x1000 0050 is not used by the bootloader and the memory content in this area is retained during reset. SRAM memory is not retained when the part powers down or enters Deep power-down mode. Assuming that power supply pins are on their nominal levels when the rising edge on RESET pin is generated, it may take up to <tbd>3 ms before PIO0_1 is sampled and the decision whether to continue with user code or ISP handler is made. If PIO0_1 is sampled low and the watchdog overflow flag is set, the external hardware request to start the ISP command handler is ignored. If there is no request for the ISP command handler execution (PIO0_1 is sampled HIGH after reset), a search is made for a valid user program. If a valid user program is found then the execution control is transferred to it. If a valid user program is not found, the auto-baud routine is invoked. Remark: The sampling of pin PIO0_1 can be disabled through programming flash location 0x0000 02FC (see Section 21.3.3 “Code Read Protection (CRP)”). UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 236 of 313 D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D Chapter 20: LPC800 Boot ROM D R R A FT FT FT A A R R D D D R A FT FT A A R R D D Once the part has booted, the user can access several APIs located in the boot ROM to access the flash memory, optimize power consumption, and operate the USART and I2C peripherals. F FT FT A A R R D D D 20.3.2 ROM-based APIs FT FT FT UM10601 FT FT NXP Semiconductors D D R A FT The structure of the boot ROM APIs is shown in D R A 3WUWR520 [))))) )ODVK,$3 3WUWR520'ULYHUWDEOH [))))) 520'ULYHU7DEOH [ 3WUWR'HYLFH7DEOH 5HVHUYHG [ 3WUWR'HYLFH7DEOH 5HVHUYHG [ 3WUWR'HYLFH7DEOH 5HVHUYHG [& 'HYLFH 3RZHUSURILOHV$3,IXQFWLRQWDEOH 3WUWR'HYLFHSRZHUSURILOH IXQFWLRQWDEOH [ 3WUWR'HYLFH7DEOH 5HVHUYHG [ 'HYLFH ,&GULYHUURXWLQHVIXQFWLRQWDEOH 3WUWR,&GULYHUURXWLQHIXQFWLRQ WDEOH 'HYLFHQ 3WUWR)XQFWLRQ « 3WUWR)XQFWLRQ 3WUWR'HYLFH 7DEOHQ 3WUWR)XQFWLRQ « 3WUWR)XQFWLRQQ Fig 34. Boot ROM structure Table 211. API calls UM10601 Preliminary user manual API Description Flash IAP Flash In-Application programming Table 234 Power profiles API Configure system clock and power consumption Table 247 I2C driver I2C ROM Driver Table 250 UART driver UART get memory size Table 271 All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 Reference © NXP B.V. 2012. All rights reserved. 237 of 313 D D D D D R R R R R D R R FT FT FT FT A A A A R R D D D D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D 20.4.1 Boot pins FT FT FT FT FT UM10601 Chapter 20: LPC800 Boot ROM 20.4 Functional description A A A A A NXP Semiconductors D D When pin PIO0_1 is pulled LOW on reset, the part enters ISP mode and the ISP command handler starts up. In ISP mode, pins PIO0_0 is connected to function U0_RXD and pin PIO0_4 is connected to function U0_TXD on the USART0 block. R A FT D R A 20.4.2 Memory map after any reset The boot block is 8 kB in size. The boot block is located in the memory region starting from the address 0x1FFF 0000. The bootloader is designed to run from this memory area, but both the ISP and IAP software use parts of the on-chip RAM. The RAM usage is described later in this chapter. The interrupt vectors residing in the boot block of the on-chip flash memory also become active after reset, i.e., the bottom 512 bytes of the boot block are also visible in the memory region starting from the address 0x0000 0000. 20.4.3 Boot process During the boot process, the boot loader checks if there is valid user code in flash. The criterion for valid user code is as follows: The reserved Cortex-M0+ exception vector location 7 (offset 0x0000 001C in the vector table) should contain the 2’s complement of the check-sum of table entries 0 through 6. This causes the checksum of the first 8 table entries to be 0. The bootloader code checksums the first 8 locations in sector 0 of the flash. If the result is 0, then execution control is transferred to the user code. If the signature is not valid, the auto-baud routine synchronizes with the host via serial port USART0. The host should send a ’?’ (0x3F) as a synchronization character and wait for a response. The host side serial port settings should be 8 data bits, 1 stop bit and no parity. The auto-baud routine measures the bit time of the received synchronization character in terms of its own frequency (the 12 MHz IRC frequency) and programs the baud rate generator of the serial port. It also sends an ASCII string ("Synchronized<CR><LF>") to the host. In response, the host should send the same string ("Synchronized<CR><LF>"). The boot loader auto-baud routine looks at the received characters to verify synchronization. If synchronization is verified then "OK<CR><LF>" string is sent to the host. The host should respond by sending the crystal frequency (in kHz) at which the part is running. The response is required for backward compatibility of the boot loader code and, on the LPC800, is ignored. The boot loader configures the part to run at the 12 MHz IRC frequency. Once the crystal frequency response is received, the part is initialized and the ISP command handler is invoked. For safety reasons an "Unlock" command is required before executing the commands resulting in flash erase/write operations and the "Go" command. The rest of the commands can be executed without the unlock command. The Unlock command is required to be executed once per ISP session. The Unlock command is explained in Table 218 “UART ISP Unlock command”. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 238 of 313 D D D D D R R R R R FT FT FT FT FT UM10601 D R R FT FT FT FT A A A A R R D D D Chapter 20: LPC800 Boot ROM D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D 20.4.4 Boot process flowchart A A A A A NXP Semiconductors D FT FT A A R R D 5(6(7 D D R A FT D ,1,7,$/,=( R A &53 (1$%/('" QR (1$%/('(%8* \HV :$7&+'2* )/$*6(7" $ \HV QR &5312B,63 (1$%/('" 86(5&2'( 9$/,'" QR \HV QR \HV (17(5,63 02'(" 3,2B /2: QR (;(&87(,17(51$/ 86(5&2'( \HV 86(5&2'( 9$/,'" QR QR ERRWIURP 8$57 581$872%$8' \HV $ QR $872%$8' 68&&(66)8/" \HV 5(&(,9(&5<67$/)5(48(1&< 5818$57,63&200$1'+$1'/(5 (1) This step is included for backward compatibility and the response is ignored by the boot loader. Fig 35. Boot process flowchart UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 239 of 313 R R R R R A A A A A FT FT FT FT FT D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D Chapter 21: LPC800 Flash ISP and IAP programming R A F FT FT A A R R D D Preliminary user manual D Rev. 1.0 — 7 November 2012 D D D D D UM10601 D FT FT A A R R D D D 21.1 How to read this chapter R A FT D See Table 212 for different flash configurations. R A Table 212. LPC800 flash configurations Type number Flash LPC810M021FN8 4 kB LPC811M001FDH16 8 kB LPC812M101FDH16 16 kB LPC812M101FD20 16 kB LPC812M101FDH20 16 kB 21.2 Features • In-System Programming: In-System programming (ISP) is programming or reprogramming the on-chip flash memory, using the bootloader software and UART serial port. • In-Application Programming: In-Application (IAP) programming is performing erase and write operation on the on-chip flash memory, as directed by the end-user application code. • You can use ISP and IAP when the part resides in the end-user board. • Flash page write and erase supported. 21.3 General description 21.3.1 Flash configuration Most IAP and ISP commands operate on sectors and specify sector numbers. In addition a page erase command is supported. The following table shows the correspondence between page numbers, sector numbers, and memory addresses. The size of a sector is 1 kB and the size of a page is 64 Byte. One sector contains 16 pages. Table 213. LPC800 flash configuration UM10601 Preliminary user manual Sector number Sector size [kB] Page number Address range 4 kB 8 kB 16 kB 0 1 0 -15 0x0000 0000 - 0x0000 03FF yes yes yes 1 1 16 - 31 0x0000 0400 - 0x0000 07FF yes yes yes 2 1 32 - 47 0x0000 0800 - 0x0000 0BFF - yes yes 3 1 48 - 63 0x0000 0C00 - 0x0000 0FFF - yes yes 4 1 64 - 79 0x0000 1000 - 0x0000 13FF - yes yes 5 1 80 - 95 0x0000 1400 - 0x0000 17FF - yes yes All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 240 of 313 D D D D D R R R R R D R R D R D FT FT A A R R D 8 1 128 - 143 0x0000 2000 - 0x0000 23FF - yes yes 9 1 144 - 159 0x0000 2400 - 0x0000 27FF yes yes yes 10 1 160 - 175 0x0000 2800 - 0x0000 2BFF yes yes yes 11 1 176 - 191 0x0000 2C00 - 0x0000 2FFF yes yes yes 12 1 192 - 207 0x0000 3000 - 0x0000 33FF yes yes yes 13 1 208 - 223 0x0000 3400 - 0x0000 37FF yes yes yes 14 1 224 - 239 0x0000 3800 - 0x0000 3BFF yes yes yes 15 1 240 - 255 0x0000 3C00 - 0x0000 3FFF yes yes yes The ECC first decodes data words read from the memory into output data words. Then, the ECC encodes data words to be written to the memory. The error correction capability consists of single bit error correction with Hamming code. The operation of the ECC is transparent to the running application. The ECC content itself is stored in a flash memory not accessible by the user’s code to either read from it or write into it on its own. 6 bit of ECC corresponds to every consecutive 32 bit of the user accessible Flash. Consequently, Flash bytes from 0x0000 0000 to 0x0000 0003 are protected by the first 6 bit ECC, Flash bytes from 0x0000 0004 to 0x0000 0007 are protected by the second 6-bit ECC byte, etc. Whenever the CPU requests a read from the user accessible Flash, both 32 bits of raw data containing the specified memory location and the matching ECC byte are evaluated. If the ECC mechanism detects a single error in the fetched data, a correction will be applied before data are provided to the CPU. When a write request into the user accessible Flash is made, writing the user specified content is accompanied by a matching ECC value calculated and stored in the ECC memory. When a sector of Flash memory is erased, the corresponding ECC bits are also erased. Once a 6-bit ECC is written, it can not be updated unless it is erased first. Therefore, for the implemented ECC mechanism to perform properly, data must be written into the flash memory in groups of 4 bytes (or multiples of 4), aligned as described above. 21.3.3 Code Read Protection (CRP) Code Read Protection is a mechanism that allows the user to enable different levels of security in the system so that access to the on-chip flash and use of the ISP can be restricted. When needed, CRP is invoked by programming a specific pattern in flash location at 0x0000 02FC. IAP commands are not affected by the code read protection. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 241 of 313 A yes R yes yes D yes - D - 0x0000 1C00 - 0x0000 1FFF FT 0x0000 1800 - 0x0000 1BFF 112 - 127 A 96 - 111 1 R 1 7 D 6 The part is equipped with the Error Correction Code (ECC) capable Flash memory. The purpose of an error correction module is twofold: Preliminary user manual F FT FT 16 kB 21.3.2 Flash content protection mechanism UM10601 A A A 8 kB FT R R 4 kB R A D D Address range D R FT FT A A R R D D D Page number FT FT FT FT Sector size [kB] A A A A R R D D D Sector number FT FT FT FT FT UM10601 Chapter 21: LPC800 Flash ISP and IAP programming Table 213. LPC800 flash configuration A A A A A NXP Semiconductors D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R R FT FT A A R Prevents sampling of pin PIO0_1 for entering ISP mode. PIO0_1 is available for other uses. CRP1 0x12345678 Access to chip via the SWD pins is disabled. This mode allows partial flash update using the following ISP commands and restrictions: D 0x4E69 7370 D NO_ISP R A FT D • • • • Copy RAM to flash command can not write to Sector 0. Erase command can erase Sector 0 only when all sectors are selected for erase. Compare command is disabled. Read Memory command is disabled. Access to chip via the SWD pins is disabled. The following ISP commands are disabled: Read Memory Write to RAM Go Copy RAM to flash Compare When CRP2 is enabled the ISP erase command only allows erasure of all user sectors. Access to chip via the SWD pins is disabled. ISP entry by pulling PIO0_1 LOW is disabled if a valid user code is present in flash sector 0. This mode effectively disables ISP override using PIO0_1 pin. It is up to the user’s application to provide a flash update mechanism using IAP calls or call reinvoke ISP command to enable flash update via UART. Caution: If CRP3 is selected, no future factory testing can be performed on the device. Table 215. Code Read Protection hardware/software interaction Preliminary user manual CRP option User Code Valid PIO0_1 pin at SWD enabled Part enters reset ISP mode partial flash update in ISP mode None No x Yes Yes Yes None Yes High Yes No NA None Yes Low Yes Yes Yes CRP1 Yes High No No NA CRP1 Yes Low No Yes Yes CRP2 Yes High No No NA CRP2 Yes Low No Yes No CRP3 Yes x No No NA CRP1 No x No Yes Yes CRP2 No x No Yes No CRP3 No x No Yes No All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 242 of 313 A Write to RAM command should not access RAM below 0x1000 0300. Access to addresses below 0x1000 0200 is disabled. R • This mode is useful when CRP is required and flash field updates are needed but all sectors can not be erased. Since compare command is disabled in case of partial updates the secondary loader should implement checksum mechanism to verify the integrity of the flash. UM10601 F D D Pattern Description programmed in 0x0000 02FC 0x43218765 A FT FT A A R R D D D Name CRP3 FT FT FT FT Table 214. Code Read Protection options • • • • • A A A A R R D D D Important: any CRP change becomes effective only after the device has gone through a power cycle. 0x87654321 FT FT FT FT FT UM10601 Chapter 21: LPC800 Flash ISP and IAP programming CRP2 A A A A A NXP Semiconductors D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R n/a Set Baud Rate yes yes n/a Echo yes yes n/a Write to RAM yes; above 0x1000 0300 only no n/a Read Memory no no n/a Prepare sector(s) for write operation yes yes n/a Copy RAM to flash yes; not to sector 0 no n/a Go no no n/a Erase sector(s) yes; sector 0 can only be erased when all sectors are erased. yes; all sectors only n/a Blank check sector(s) no no n/a Read Part ID yes yes n/a Read Boot code version yes yes n/a Compare no no n/a ReadUID yes yes n/a F yes FT FT A A R R yes D Unlock D CRP3 (no entry in ISP mode allowed) D D R A FT D R A In addition to the three CRP modes, the user can prevent the sampling of pin PIO0_1 for entering ISP mode and thereby release pin PIO0_1 for other uses. This is called the NO_ISP mode. The NO_ISP mode can be entered by programming the pattern 0x4E69 7370 at location 0x0000 02FC. 21.4 API description 21.4.1 UART ISP commands The following commands are accepted by the ISP command handler. Detailed status codes are supported for each command. The command handler sends the return code INVALID_COMMAND when an undefined command is received. Commands and return codes are in ASCII format. CMD_SUCCESS is sent by ISP command handler only when received ISP command has been completely executed and the new ISP command can be given by the host. Exceptions from this rule are "Set Baud Rate", "Write to RAM", "Read Memory", and "Go" commands. Rev. 1.0 — 7 November 2012 A FT FT A A R R D D D CRP2 All information provided in this document is subject to legal disclaimers. FT FT FT FT CRP1 21.3.3.1 ISP entry protection Preliminary user manual A A A A R R D D D ISP command In case a CRP mode is enabled and access to the chip is allowed via the ISP, an unsupported or restricted ISP command will be terminated with return code CODE_READ_PROTECTION_ENABLED. UM10601 FT FT FT FT FT UM10601 Chapter 21: LPC800 Flash ISP and IAP programming Table 216. ISP commands allowed for different CRP levels A A A A A NXP Semiconductors © NXP B.V. 2012. All rights reserved. 243 of 313 D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R Table 220 Write to RAM W <start address> <number of bytes> Table 221 Read Memory R <address> <number of bytes> Table 222 Prepare sector(s) for write operation P <start sector number> <end sector number> Table 223 Copy RAM to flash C <Flash address> <RAM address> <number of bytes> Table 224 A FT FT A I <start sector number> <end sector number> Table 227 Read Part ID J Table 228 Read Boot code version K Table 230 Compare M <address1> <address2> <number of bytes> Table 231 ReadUID N Table 232 D Blank check sector(s) 21.4.1.1 Unlock <Unlock code> Table 218. UART ISP Unlock command Unlock code: 2313010 Return Code CMD_SUCCESS | INVALID_CODE | PARAM_ERROR Description This command is used to unlock Flash Write, Erase, and Go commands. Example "U 23130<CR><LF>" unlocks the Flash Write/Erase & Go commands. 21.4.1.2 Set Baud Rate <Baud Rate> <stop bit> Table 219. UART ISP Set Baud Rate command Command B Input Baud Rate: 9600 | 19200 | 38400 | 57600 | 115200 Stop bit: 1 | 2 Return Code CMD_SUCCESS | INVALID_BAUD_RATE | INVALID_STOP_BIT | PARAM_ERROR UM10601 Preliminary user manual Description This command is used to change the baud rate. The new baud rate is effective after the command handler sends the CMD_SUCCESS return code. Example "B 57600 1<CR><LF>" sets the serial port to baud rate 57600 bps and 1 stop bit. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 244 of 313 FT Table 226 A Table 225 E <start sector number> <end sector number> R G <address> <Mode> Erase sector(s) D Go A A <setting> R Echo D Table 219 R Table 218 B <Baud Rate> <stop bit> R U <Unlock Code> Input F D D Unlock U A FT FT A A R R D D D Described in Set Baud Rate Command FT FT FT FT Usage A A A A R R D D D ISP Command FT FT FT FT FT UM10601 Chapter 21: LPC800 Flash ISP and IAP programming Table 217. UART ISP command summary A A A A A NXP Semiconductors D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R R FT D D R A FT CMD_SUCCESS | FT A A R Setting: ON = 1 | OFF = 0 Return Code D R PARAM_ERROR A Description The default setting for echo command is ON. When ON the ISP command handler sends the received serial data back to the host. Example "A 0<CR><LF>" turns echo off. 21.4.1.4 Write to RAM <start address> <number of bytes> The host should send the plain binary code after receiving the CMD_SUCCESS return code. This ISP command handler responds with “OK<CR><LF>” when the transfer has finished. Table 221. UART ISP Write to RAM command Command W Input Start Address: RAM address where data bytes are to be written. This address should be a word boundary. Number of Bytes: Number of bytes to be written. Count should be a multiple of 4 CMD_SUCCESS | ADDR_ERROR (Address not on word boundary) | ADDR_NOT_MAPPED | COUNT_ERROR (Byte count is not multiple of 4) | PARAM_ERROR | CODE_READ_PROTECTION_ENABLED Description This command is used to download data to RAM. This command is blocked when code read protection levels 2 or 3 are enabled. Writing to addresses below 0x1000 0300 is disabled for CRP1. Example "W 268436224 4<CR><LF>" writes 4 bytes of data to address 0x1000 0300. 21.4.1.5 Read Memory <address> <number of bytes> Reads the the plain binary code of the data stream, followed by the CMD_SUCCESS return code. UM10601 Preliminary user manual F D D Input Return Code A FT FT A A R R D D D A FT FT FT FT Command A A A A R R D D D Table 220. UART ISP Echo command FT FT FT FT FT UM10601 Chapter 21: LPC800 Flash ISP and IAP programming 21.4.1.3 Echo <setting> A A A A A NXP Semiconductors All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 245 of 313 D D D D D R R R R R FT FT FT FT FT UM10601 D R R FT FT FT FT A A A A R R D D D Chapter 21: LPC800 Flash ISP and IAP programming D R R A FT FT FT A A R R D D D R A Input Start Address: Address from where data bytes are to be read. This address should be a word boundary. D R FT FT A A R R D Command F FT FT A A R R D D D Table 222. UART ISP Read Memory command A A A A A NXP Semiconductors D D A FT CMD_SUCCESS followed by <actual data (plain binary)> | D Return Code R Number of Bytes: Number of bytes to be read. Count should be a multiple of 4. R A ADDR_ERROR (Address not on word boundary) | ADDR_NOT_MAPPED | COUNT_ERROR (Byte count is not a multiple of 4) | PARAM_ERROR | CODE_READ_PROTECTION_ENABLED Description This command is used to read data from RAM or flash memory. This command is blocked when code read protection is enabled. Example "R 268435456 4<CR><LF>" reads 4 bytes of data from address 0x1000 0000. 21.4.1.6 Prepare sector(s) for write operation <start sector number> <end sector number> This command makes flash write/erase operation a two step process. Table 223. UART ISP Prepare sector(s) for write operation command Command P Input Start Sector Number End Sector Number: Should be greater than or equal to start sector number. Return Code CMD_SUCCESS | BUSY | INVALID_SECTOR | PARAM_ERROR Description This command must be executed before executing "Copy RAM to flash" or "Erase Sector(s)" command. Successful execution of the "Copy RAM to flash" or "Erase Sector(s)" command causes relevant sectors to be protected again. The boot block can not be prepared by this command. To prepare a single sector use the same "Start" and "End" sector numbers. Example "P 0 0<CR><LF>" prepares the flash sector 0. 21.4.1.7 Copy RAM to flash <Flash address> <RAM address> <no of bytes> When writing to the flash, the following limitations apply: 1. The smallest amount of data that can be written to flash by the copy RAM to flash command is 64 byte (equal to one page). 2. One page consists of 16 flash words (lines), and the smallest amount that can be modified per flash write is one flash word (one line). This limitation follows from the application of ECC to the flash write operation, see Section 21.3.2. 3. To avoid write disturbance (a mechanism intrinsic to flash memories), an erase should be performed after following 16 consecutive writes inside the same page. Note that the erase operation then erases the entire sector. Remark: Once a page has been written to 16 times, it is still possible to write to other pages within the same sector without performing a sector erase (assuming that those pages have been erased previously). UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 246 of 313 D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D Chapter 21: LPC800 Flash ISP and IAP programming D R R A FT FT FT A A R R D D D R A Input Flash Address (DST): Destination flash address where data bytes are to be written. The destination address should be a 64 byte boundary. D C FT FT A A R R D Command F FT FT A A R R D D D Table 224. UART ISP Copy RAM to flash command FT FT FT UM10601 FT FT NXP Semiconductors D D R RAM Address (SRC): Source RAM address from where data bytes are to be read. A SRC_ADDR_NOT_MAPPED | DST_ADDR_NOT_MAPPED | COUNT_ERROR (Byte count is not 64 | 128 | 256 | 512 | 1024) | SECTOR_NOT_PREPARED_FOR WRITE_OPERATION | BUSY | CMD_LOCKED | PARAM_ERROR | CODE_READ_PROTECTION_ENABLED Description This command is used to program the flash memory. The "Prepare Sector(s) for Write Operation" command should precede this command. The affected sectors are automatically protected again once the copy command is successfully executed. The boot block cannot be written by this command. This command is blocked when code read protection is enabled. Example "C 0 268467504 512<CR><LF>" copies 512 bytes from the RAM address 0x1000 0800 to the flash address 0. 21.4.1.8 Go <address> <mode> Table 225. UART ISP Go command Command G Input Address: Flash or RAM address from which the code execution is to be started. This address should be on a word boundary. Mode: T (Execute program in Thumb Mode). Return Code CMD_SUCCESS | ADDR_ERROR | ADDR_NOT_MAPPED | CMD_LOCKED | PARAM_ERROR | CODE_READ_PROTECTION_ENABLED UM10601 Preliminary user manual Description This command is used to execute a program residing in RAM or flash memory. It may not be possible to return to the ISP command handler once this command is successfully executed. This command is blocked when code read protection is enabled. The command must be used with an address of 0x0000 0200 or greater. Example "G 512 T<CR><LF>" branches to address 0x0000 0200 in Thumb mode. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 247 of 313 A DST_ADDR_ERROR (Address not on correct boundary) | R SRC_ADDR_ERROR (Address not on word boundary) | D Return Code CMD_SUCCESS | FT Number of Bytes: Number of bytes to be written. Should be 64 | 128 | 256 | 512 | 1024. D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R R FT FT A A R Start Sector Number D D R A D R Return Code CMD_SUCCESS | A BUSY | INVALID_SECTOR | SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION | CMD_LOCKED | PARAM_ERROR | CODE_READ_PROTECTION_ENABLED Description This command is used to erase one or more sector(s) of on-chip flash memory. The boot block can not be erased using this command. This command only allows erasure of all user sectors when the code read protection is enabled. Example "E 2 3<CR><LF>" erases the flash sectors 2 and 3. 21.4.1.10 Blank check sector(s) <sector number> <end sector number> Table 227. UART ISP Blank check sector command Command I Input Start Sector Number: End Sector Number: Should be greater than or equal to start sector number. Return Code CMD_SUCCESS | SECTOR_NOT_BLANK (followed by <Offset of the first non blank word location> <Contents of non blank word location>) | INVALID_SECTOR | PARAM_ERROR This command is used to blank check one or more sectors of on-chip flash memory. Blank check on sector 0 always fails as first 64 bytes are re-mapped to flash boot block. When CRP is enabled, the blank check command returns 0 for the offset and value of sectors which are not blank. Blank sectors are correctly reported irrespective of the CRP setting. Example "I 2 3<CR><LF>" blank checks the flash sectors 2 and 3. 21.4.1.11 Read Part Identification number Table 228. UART ISP Read Part Identification command Command J Input None. Return Code CMD_SUCCESS followed by part identification number in ASCII (see Table 229). Description UM10601 Preliminary user manual This command is used to read the part identification number. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 FT End Sector Number: Should be greater than or equal to start sector number. Description F D D Input A FT FT A A R R D D D E FT FT FT FT Table 226. UART ISP Erase sector command A A A A R R D D D 21.4.1.9 Erase sector(s) <start sector number> <end sector number> FT FT FT FT FT UM10601 Chapter 21: LPC800 Flash ISP and IAP programming Command A A A A A NXP Semiconductors © NXP B.V. 2012. All rights reserved. 248 of 313 D D D D D R R R R R D R R FT R A FT D D R A FT D R A Table 230. UART ISP Read Boot Code version number command K Input None Return Code CMD_SUCCESS followed by 2 bytes of boot code version number in ASCII format. It is to be interpreted as <byte1(Major)>.<byte0(Minor)>. Description This command is used to read the boot code version number. 21.4.1.13 Compare <address1> <address2> <no of bytes> Table 231. UART ISP Compare command Command M Input Address1 (DST): Starting flash or RAM address of data bytes to be compared. This address should be a word boundary. Address2 (SRC): Starting flash or RAM address of data bytes to be compared. This address should be a word boundary. Number of Bytes: Number of bytes to be compared; should be a multiple of 4. Return Code CMD_SUCCESS | (Source and destination data are equal) COMPARE_ERROR | (Followed by the offset of first mismatch) COUNT_ERROR (Byte count is not a multiple of 4) | ADDR_ERROR | ADDR_NOT_MAPPED | PARAM_ERROR Description This command is used to compare the memory contents at two locations. Example "M 8192 268468224 4<CR><LF>" compares 4 bytes from the RAM address 0x1000 8000 to the 4 bytes from the flash address 0x2000. 21.4.1.14 ReadUID Table 232. UART ISP ReadUID command Command N Input None Return Code CMD_SUCCESS followed by four 32-bit words of E-sort test information in ASCII format. The word sent at the lowest address is sent first. Description UM10601 Preliminary user manual This command is used to read the unique ID. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 F D FT 21.4.1.12 Read Boot code version number Command A FT 0x0000 8122 A LPC812M101FDH20 R 0x0000 8121 D LPC812M101FD20 FT 0x0000 8120 R A A LPC812M101FDH16 D R R 0x0000 8110 R A D D 0x0000 8100 LPC811M001FDH16 D R FT FT A A R R D D D LPC810M021FN8 FT FT FT FT Hex coding A A A A R R D D D Table 229. Part identification numbers FT FT FT FT FT UM10601 Chapter 21: LPC800 Flash ISP and IAP programming Device A A A A A NXP Semiconductors © NXP B.V. 2012. All rights reserved. 249 of 313 D D D D D R R R R R D R R FT FT FT FT D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D A R R D Table 233. UART ISP Return Codes Summary Description 0 CMD_SUCCESS Command is executed successfully. Sent by ISP handler only when command given by the host has been completely and successfully executed. 1 INVALID_COMMAND Invalid command. 2 SRC_ADDR_ERROR Source address is not on word boundary. 3 DST_ADDR_ERROR Destination address is not on a correct boundary. 4 SRC_ADDR_NOT_MAPPED Source address is not mapped in the memory map. Count value is taken in to consideration where applicable. 5 DST_ADDR_NOT_MAPPED Destination address is not mapped in the memory map. Count value is taken in to consideration where applicable. 6 COUNT_ERROR Byte count is not multiple of 4 or is not a permitted value. 7 INVALID_SECTOR Sector number is invalid or end sector number is greater than start sector number. 8 SECTOR_NOT_BLANK Sector is not blank. 9 SECTOR_NOT_PREPARED_FOR_ Command to prepare sector for write operation WRITE_OPERATION was not executed. FT FT A Return Mnemonic Code D D R PARAM_ERROR Insufficient number of parameters or invalid parameter. 13 ADDR_ERROR Address is not on word boundary. 14 ADDR_NOT_MAPPED Address is not mapped in the memory map. Count value is taken in to consideration where applicable. 15 CMD_LOCKED Command is locked. 16 INVALID_CODE Unlock code is invalid. 17 INVALID_BAUD_RATE Invalid baud rate setting. 18 INVALID_STOP_BIT Invalid stop bit setting. 19 CODE_READ_PROTECTION_ ENABLED Code read protection enabled. For in application programming the IAP routine should be called with a word pointer in register r0 pointing to memory (RAM) containing command code and parameters. Result of the IAP command is returned in the result table pointed to by register r1. The user can reuse the command table for result by passing the same pointer in registers r0 and r1. The parameter table should be big enough to hold all the results in case the number of results are more than number of parameters. Parameter passing is illustrated in the Figure 36. The number of parameters and results vary according to the IAP command. The maximum number of parameters is 5, passed to the "Copy RAM to FLASH" command. The maximum number of results is 4, returned by the "ReadUID" command. The All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 250 of 313 A 12 R Flash programming hardware interface is busy. D Source and destination data not equal. BUSY FT COMPARE_ERROR 11 A 10 21.4.2 IAP commands Preliminary user manual A A A A R R D D D 21.4.1.15 UART ISP Return Codes FT FT FT FT FT UM10601 Chapter 21: LPC800 Flash ISP and IAP programming UM10601 A A A A A NXP Semiconductors D D D D D R R R R R A A A A A FT FT FT UM10601 FT FT D R R FT FT FT FT Chapter 21: LPC800 Flash ISP and IAP programming A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D command handler sends the status code INVALID_COMMAND when an undefined command is received. The IAP routine resides at 0x1FFF 1FF0 location and it is thumb code. D FT FT A A R R D D D The IAP function could be called in the following way using C. R A or unsigned long * command; unsigned long * result; command=(unsigned long *) 0x... result= (unsigned long *) 0x... Define pointer to function type, which takes two parameters and returns void. Note the IAP returns the result with the base address of the table residing in R1. typedef void (*IAP)(unsigned int [],unsigned int[]); IAP iap_entry; Setting function pointer: iap_entry=(IAP) IAP_LOCATION; Whenever you wish to call IAP you could use the following statement. iap_entry (command, result); As per the ARM specification (The ARM Thumb Procedure Call Standard SWS ESPC 0002 A-05) up to 4 parameters can be passed in the r0, r1, r2 and r3 registers respectively. Additional parameters are passed on the stack. Up to 4 parameters can be returned in the r0, r1, r2 and r3 registers respectively. Additional parameters are returned indirectly via memory. Some of the IAP calls require more than 4 parameters. If the ARM suggested scheme is used for the parameter passing/returning then it might create problems due to difference in the C compiler implementation from different vendors. The suggested parameter passing scheme reduces such risk. The flash memory is not accessible during a write or erase operation. IAP commands, which results in a flash write/erase operation, use 32 bytes of space in the top portion of the on-chip RAM for execution. The user program should not be use this space if IAP flash programming is permitted in the application. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 251 of 313 A unsigned long command[5]; unsigned long result[4]; R Define data structure or pointers to pass IAP command table and result table to the IAP function: D #define IAP_LOCATION 0x1fff1ff1 FT Define the IAP location entry point. Since the 0th bit of the IAP location is set there will be a change to Thumb instruction set when the program counter branches to this address. D D D D D R R R R R D R R FT 58 (decimal) Table 243 Erase page 59 (decimal) Table 244 A Read UID R Table 242 D 57 (decimal) D Reinvoke ISP &200$1'&2'( 3$5$0(7(5 $505(*,67(5U $505(*,67(5U FRPPDQG SDUDPHWHUWDEOH 3$5$0(7(5 3$5$0(7(5Q 67$786&2'( 5(68/7 5(68/7 FRPPDQG UHVXOWWDEOH 5(68/7Q Fig 36. IAP parameter passing 21.4.2.1 Prepare sector(s) for write operation (IAP) This command makes flash write/erase operation a two step process. Table 235. IAP Prepare sector(s) for write operation command Command Prepare sector(s) for write operation Input Command code: 50 (decimal) Param0: Start Sector Number Param1: End Sector Number (should be greater than or equal to start sector number). UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 F Table 241 FT 56 (decimal) FT Compare A Table 240 A Table 239 55 (decimal) R 54 (decimal) Read Boot code version R Read Part ID D Table 238 D 53 (decimal) FT Blank check sector(s) A Table 237 R 52 (decimal) D Erase sector(s) A FT FT Table 236 R A A Table 235 51 (decimal) D R R 50 (decimal) R A D D Prepare sector(s) for write operation D R FT FT A A R R D D D Described in Copy RAM to flash FT FT FT FT Command Code A A A A R R D D D IAP Command FT FT FT FT FT UM10601 Chapter 21: LPC800 Flash ISP and IAP programming Table 234. IAP Command Summary A A A A A NXP Semiconductors © NXP B.V. 2012. All rights reserved. 252 of 313 D D D D D R R R R R D R R D R FT FT FT A A A R R FT FT A A R D D R A FT None Description This command must be executed before executing "Copy RAM to flash" or "Erase Sector(s)" command. Successful execution of the "Copy RAM to flash" or "Erase Sector(s)" command causes relevant sectors to be protected again. The boot sector can not be prepared by this command. To prepare a single sector use the same "Start" and "End" sector numbers. D Result Table 236. IAP Copy RAM to flash command Command Copy RAM to flash Input Command code: 51 (decimal) Param0(DST): Destination flash address where data bytes are to be written. This address should be a 64 byte boundary. Param1(SRC): Source RAM address from which data bytes are to be read. This address should be a word boundary. Param2: Number of bytes to be written. Should be 64 | 128 | 256 | 512 | 1024. Param3: System Clock Frequency (CCLK) in kHz. CMD_SUCCESS | SRC_ADDR_ERROR (Address not a word boundary) | DST_ADDR_ERROR (Address not on correct boundary) | SRC_ADDR_NOT_MAPPED | DST_ADDR_NOT_MAPPED | COUNT_ERROR (Byte count is not 256 | 512 | 1024 | 4096) | SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION | BUSY Preliminary user manual Result None Description This command is used to program the flash memory. The affected sectors should be prepared first by calling "Prepare Sector for Write Operation" command. The affected sectors are automatically protected again once the copy command is successfully executed. The boot sector can not be written by this command. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 253 of 313 A See Section 21.4.1.4 for limitations on the write-to-flash process. R 21.4.2.2 Copy RAM to flash (IAP) UM10601 F D D INVALID_SECTOR Return Code A FT FT A A R R D D D BUSY | R R R CMD_SUCCESS | D D D Return Code FT FT FT FT Prepare sector(s) for write operation A A A A R R D D D Table 235. IAP Prepare sector(s) for write operation command FT FT FT FT FT UM10601 Chapter 21: LPC800 Flash ISP and IAP programming Command A A A A A NXP Semiconductors D D D D D R R R R R D R R FT D R FT FT A A R D D R A FT BUSY | SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION | INVALID_SECTOR Result None Description This command is used to erase a sector or multiple sectors of on-chip flash memory. The boot sector can not be erased by this command. To erase a single sector use the same "Start" and "End" sector numbers. 21.4.2.4 Blank check sector(s) (IAP) Table 238. IAP Blank check sector(s) command Blank check sector(s) Input Command code: 53 (decimal) Param0: Start Sector Number Param1: End Sector Number (should be greater than or equal to start sector number). Return Code CMD_SUCCESS | BUSY | SECTOR_NOT_BLANK | INVALID_SECTOR Result Result0: Offset of the first non blank word location if the Status Code is SECTOR_NOT_BLANK. Result1: Contents of non blank word location. Description This command is used to blank check a sector or multiple sectors of on-chip flash memory. To blank check a single sector use the same "Start" and "End" sector numbers. 21.4.2.5 Read Part Identification number (IAP) Table 239. IAP Read Part Identification command Command Read part identification number Input Command code: 54 (decimal) Parameters: None UM10601 Preliminary user manual Return Code CMD_SUCCESS Result Result0: Part Identification Number. Description This command is used to read the part identification number. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 254 of 313 A CMD_SUCCESS | R Param2: System Clock Frequency (CCLK) in kHz. D Param1: End Sector Number (should be greater than or equal to start sector number). Command F D D Param0: Start Sector Number Return Code A FT FT A A R R R Command code: 52 (decimal) R A D D Input D R FT FT A A R R D D D Erase Sector(s) FT FT FT FT Command A A A A R R D D D Table 237. IAP Erase Sector(s) command FT FT FT FT FT UM10601 Chapter 21: LPC800 Flash ISP and IAP programming 21.4.2.3 Erase Sector(s) (IAP) A A A A A NXP Semiconductors D D D D D R R R R R D R R FT D R FT FT A A R R A R A This command is used to read the boot code version number. D Description FT Result0: 2 bytes of boot code version number. Read as <byte1(Major)>.<byte0(Minor)> D D Result 21.4.2.7 Compare <address1> <address2> <no of bytes> (IAP) Table 241. IAP Compare command Command Compare Input Command code: 56 (decimal) Param0(DST): Starting flash or RAM address of data bytes to be compared. This address should be a word boundary. Param1(SRC): Starting flash or RAM address of data bytes to be compared. This address should be a word boundary. Param2: Number of bytes to be compared; should be a multiple of 4. Return Code CMD_SUCCESS | COMPARE_ERROR | COUNT_ERROR (Byte count is not a multiple of 4) | ADDR_ERROR | ADDR_NOT_MAPPED UM10601 Preliminary user manual Result Result0: Offset of the first mismatch if the Status Code is COMPARE_ERROR. Description This command is used to compare the memory contents at two locations. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 F D D CMD_SUCCESS A FT FT A A R R R Parameters: None Return Code R A D D Command code: 55 (decimal) D R FT FT A A R R D D D Input FT FT FT FT Table 240. IAP Read Boot Code version number command Read boot code version number A A A A R R D D D 21.4.2.6 Read Boot code version number (IAP) FT FT FT FT FT UM10601 Chapter 21: LPC800 Flash ISP and IAP programming Command A A A A A NXP Semiconductors © NXP B.V. 2012. All rights reserved. 255 of 313 D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R F D A R R D Input Command code: 57 (decimal) Return Code None Result None. Description This command is used to invoke the bootloader in ISP mode. It maps boot vectors, sets PCLK = CCLK, and configures USART0 pins U0_RXD and U0_TXD. This command may be used when a valid user program is present in the internal flash memory and the PIO0_1 pin is not accessible to force the ISP mode. FT FT A Compare D D R A FT D R A Table 243. IAP ReadUID command Command Compare Input Command code: 58 (decimal) Return Code CMD_SUCCESS Result Result0: The first 32-bit word (at the lowest address). Result1: The second 32-bit word. Result2: The third 32-bit word. Result3: The fourth 32-bit word. Description This command is used to read the unique ID. 21.4.2.10 Erase page Table 244. IAP Erase page command Command Erase page Input Command code: 59 (decimal) Param0: Start page number. Param1: End page number (should be greater than or equal to start page) Param2: System Clock Frequency (CCLK) in kHz. CMD_SUCCESS | BUSY | SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION | INVALID_SECTOR Result None Description This command is used to erase a page or multiple pages of on-chip flash memory. To erase a single page use the same "start" and "end" page numbers. 21.4.2.11 IAP Status Codes Table 245. IAP Status Codes Summary Preliminary user manual A FT FT A A R R D D D Command 21.4.2.9 ReadUID (IAP) UM10601 FT FT FT FT Table 242. IAP Reinvoke ISP A A A A R R D D D 21.4.2.8 Reinvoke ISP (IAP) FT FT FT FT FT UM10601 Chapter 21: LPC800 Flash ISP and IAP programming Return Code A A A A A NXP Semiconductors Status Mnemonic Code Description 0 CMD_SUCCESS Command is executed successfully. 1 INVALID_COMMAND Invalid command. 2 SRC_ADDR_ERROR Source address is not on a word boundary. 3 DST_ADDR_ERROR Destination address is not on a correct boundary. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 256 of 313 D D D D D R R R R R D R R FT FT FT FT D R R A FT FT FT A A R R D D D R SRC_ADDR_NOT_MAPPED Source address is not mapped in the memory map. Count value is taken in to consideration where applicable. 5 DST_ADDR_NOT_MAPPED Destination address is not mapped in the memory map. Count value is taken in to consideration where applicable. 6 COUNT_ERROR Byte count is not multiple of 4 or is not a permitted value. 7 INVALID_SECTOR Sector number is invalid. 8 SECTOR_NOT_BLANK Sector is not blank. 9 SECTOR_NOT_PREPARED_ FOR_WRITE_OPERATION Command to prepare sector for write operation was not executed. 10 COMPARE_ERROR Source and destination data is not same. 11 BUSY Flash programming hardware interface is busy. F FT FT 4 A A A R R D D D Description D FT FT A A R R D D D R A 21.5.1.2 UART ISP response format "Return_Code<CR><LF>Response_0<CR><LF>Response_1<CR><LF> ... Response_n<CR><LF>" "Data" (Data only for Read commands). 21.5.1.3 UART ISP data format The data stream is in plain binary format. 21.5.2 Memory and interrupt use for ISP and IAP 21.5.2.1 Interrupts during UART ISP The boot block interrupt vectors located in the boot block of the flash are active after any reset. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 257 of 313 A "Command Parameter_0 Parameter_1 ... Parameter_n<CR><LF>" "Data" (Data only for Write commands). R 21.5.1.1 UART ISP command format D All UART ISP commands should be sent as single ASCII strings. Strings should be terminated with Carriage Return (CR) and/or Line Feed (LF) control characters. Extra <CR> and <LF> characters are ignored. All ISP responses are sent as <CR><LF> terminated ASCII strings. Data is sent and received in plain binary format. FT 21.5.1 UART Communication protocol Preliminary user manual A A A A R R D D D Status Mnemonic Code 21.5 Functional description UM10601 FT FT FT FT FT UM10601 Chapter 21: LPC800 Flash ISP and IAP programming Table 245. IAP Status Codes Summary A A A A A NXP Semiconductors D D D D D R R R R R FT FT FT FT FT UM10601 D R R FT FT FT FT A A A A R R D D D Chapter 21: LPC800 Flash ISP and IAP programming D R R A FT FT FT A A R R D D D R A FT The on-chip flash memory is not accessible during erase/write operations. When the user application code starts executing the interrupt vectors from the user flash area are active. Before making any IAP call, either disable the interrupts or ensure that the user interrupt vectors are active in RAM and that the interrupt handlers reside in RAM. The IAP code does not use or disable interrupts. F FT A A R R D D D 21.5.2.2 Interrupts during IAP A A A A A NXP Semiconductors D FT FT A A R R D D D R A FT D R A 21.5.2.3 RAM used by ISP command handler The stack of ISP commands is located at 0x1000 0270. The maximum stack usage is 540 byte and grows downwards. 21.5.2.4 RAM used by IAP command handler The maximum stack usage in the user allocated stack space is 148 bytes and grows downwards. 21.5.3 Debugging 21.5.3.1 Comparing flash images Depending on the debugger used and the IDE debug settings, the memory that is visible when the debugger connects might be the boot ROM, the internal SRAM, or the flash. To help determine which memory is present in the current debug environment, check the value contained at flash address 0x0000 0004. This address contains the entry point to the code in the ARM Cortex-M0+ vector table, which is the bottom of the boot ROM, the internal SRAM, or the flash memory respectively. Table 246. Memory mapping in debug mode Memory mapping mode Memory start address visible at 0x0000 0004 Bootloader mode 0x1FFF 0000 User flash mode 0x0000 0000 User SRAM mode 0x1000 0000 21.5.3.2 Serial Wire Debug (SWD) flash programming interface Debug tools can write parts of the flash image to RAM and then execute the IAP call "Copy RAM to flash" repeatedly with proper offset. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 258 of 313 R R R R R A A A A A FT FT FT FT FT D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D Chapter 22: LPC800 Power profile API ROM driver R A F FT FT A A R R D D Preliminary user manual D Rev. 1.0 — 7 November 2012 D D D D D UM10601 D FT FT A A R R D D D 22.1 How to read this chapter R A FT D The power profiles are available for all LPC800 parts. R A 22.2 Features • Includes ROM-based application services • Power Management services • Clocking services 22.3 General description The power consumption in Active and Sleep modes can be optimized for the application through simple calls to the power profile. The power configuration routine configures the LPC800 for one of the following power modes: • Default mode corresponding to power configuration after reset. • CPU performance mode corresponding to optimized processing capability. • Efficiency mode corresponding to optimized balance of current consumption and CPU performance. • Low-current mode corresponding to lowest power consumption. In addition, the power profile includes routines to select the optimal PLL settings for a given system clock and PLL input clock. Remark: Disable all interrupts before making calls to the power profile API. You can re-enable the interrupts after the power profile API calls have completed. The API calls to the ROM are performed by executing functions which are pointed by a pointer within the ROM Driver Table. Figure 37 shows the pointer structure used to call the Power Profiles API. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 259 of 313 D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D D D R A VHWBSRZHU FT D FT FT FT FT 3RZHU$3,IXQFWLRQWDEOH VHWBSOO A A A A R R D D D FT FT FT FT FT UM10601 Chapter 22: LPC800 Power profile API ROM driver 3WUWR520'ULYHUWDEOH [))))) A A A A A NXP Semiconductors R A 520'ULYHU7DEOH [ 3WUWR'HYLFH7DEOH [ 3WUWR'HYLFH7DEOH [ 3WUWR'HYLFH7DEOH [& 3WUWR3RZHU$3,7DEOH « 3WUWR'HYLFH 7DEOHQ Fig 37. Power profiles pointer structure PDLQFORFN &/2&. ',9,'(5 V\VWHPFORFN 520 6<6$+%&/.',9 LUFBRVFBFON $50 &257(;0 6<6$+%&/.&75/>@ 520HQDEOH ZGWBRVFBFON Q 6<6$+%&/.&75/>Q@ QHQDEOH 0$,1&/.6(/ V\VBSOOFONRXW LUFBRVFBFON V\VBRVFBFON &/.,1 V\VBSOOFONLQ P 6<63// &/2&. ',9,'(5 3HULSKHUDOV 6<63//&/.6(/ Fig 38. LPC800 clock configuration for power API use 22.4 API description The power profile API provides functions to configure the system clock and optimize the system setting for lowest power consumption. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 260 of 313 D D D D D R R R R R D R R FT FT FT FT A A A A R R D D D D R R A FT FT FT A A R R D D D A F FT FT A A R R R Description D D D API call FT FT FT FT FT UM10601 Chapter 22: LPC800 Power profile API ROM driver Table 247. Power profile API calls A A A A A NXP Semiconductors Reference D Table 248 Table 249 FT FT A A R Power API set pll routine Power API set power routine R D set_pll(command, result) set_power(command, result) D D R A FT The following elements have to be defined in an application that uses the power profiles: D R A typedef struct _PWRD { void (*set_pll)(unsigned int cmd[], unsigned int resp[]); void (*set_power)(unsigned int cmd[], unsigned int resp[]); } PWRD; typedef struct _ROM { const PWRD * pWRD; } ROM; ROM ** rom = (ROM **) (0x1FFF1FF8 + 3 * sizeof(ROM**)); unsigned int command[4], result[2]; 22.4.1 set_pll This routine sets up the system PLL according to the calling arguments. If the expected clock can be obtained by simply dividing the system PLL input, set_pll bypasses the PLL to lower system power consumption. Remark: Before this routine is invoked, the PLL clock source (IRC/system oscillator) must be selected (Table 13), the main clock source must be set to the input clock to the system PLL (Table 8) and the system/AHB clock divider must be set to 1 (Table 15). set_pll attempts to find a PLL setup that matches the calling parameters. Once a combination of a feedback divider value (SYSPLLCTRL, M), a post divider ratio (SYSPLLCTRL, P) and the system/AHB clock divider (SYSAHBCLKDIV) is found, set_pll applies the selected values and switches the main clock source selection to the system PLL clock out (if necessary). The routine returns a result code that indicates if the system PLL was successfully set (PLL_CMD_SUCCESS) or not (in which case the result code identifies what went wrong). The current system frequency value is also returned. The application should use this information to adjust other clocks in the device (the SSP, UART, and WDT clocks, and/or clockout). Table 248. set_pll routine Routine set_pll Input Param0: system PLL input frequency (in kHz) Param1: expected system clock (in kHz) Param2: mode (CPU_FREQ_EQU, CPU_FREQ_LTE, CPU_FREQ_GTE, CPU_FREQ_APPROX) Param3: system PLL lock time-out Result Result0: PLL_CMD_SUCCESS | PLL_INVALID_FREQ | PLL_INVALID_MODE | PLL_FREQ_NOT_FOUND | PLL_NOT_LOCKED Result1: system clock (in kHz) The following definitions are needed when making set_pll power routine calls: /* set_pll mode options */ UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 261 of 313 D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D D D R A FT D R A 22.4.1.1 Param0: system PLL input frequency and Param1: expected system clock set_pll looks for a setup in which the system PLL clock does not exceed 50 MHz. It easily finds a solution when the ratio between the expected system clock and the system PLL input frequency is an integer value, but it can also find solutions in other cases. The system PLL input frequency (Param0) must be between 10000 to 25000 kHz (10 MHz to 25 MHz) inclusive. The expected system clock (Param1) must be between 1 and 50000 kHz inclusive. If either of these requirements is not met, set_pll returns PLL_INVALID_FREQ and returns Param0 as Result1 since the PLL setting is unchanged. 22.4.1.2 Param2: mode The first priority of set_pll is to find a setup that generates the system clock at exactly the rate specified in Param1. If it is unlikely that an exact match can be found, input parameter mode (Param2) should be used to specify if the actual system clock can be less than or equal, greater than or equal or approximately the value specified as the expected system clock (Param1). A call specifying CPU_FREQ_EQU will only succeed if the PLL can output exactly the frequency requested in Param1. CPU_FREQ_LTE can be used if the requested frequency should not be exceeded (such as overall current consumption and/or power budget reasons). CPU_FREQ_GTE helps applications that need a minimum level of CPU processing capabilities. CPU_FREQ_APPROX results in a system clock that is as close as possible to the requested value (it may be greater than or less than the requested value). If an illegal mode is specified, set_pll returns PLL_INVALID_MODE. If the expected system clock is out of the range supported by this routine, set_pll returns PLL_FREQ_NOT_FOUND. In these cases the current PLL setting is not changed and Param0 is returned as Result1. Preliminary user manual FT FT FT FT 0 1 2 3 4 For a simplified clock configuration scheme see Figure 38. For more details see Figure 3. UM10601 A A A A R R D D D 0 1 2 3 FT FT FT FT FT UM10601 Chapter 22: LPC800 Power profile API ROM driver #define CPU_FREQ_EQU #define CPU_FREQ_LTE #define CPU_FREQ_GTE #define CPU_FREQ_APPROX /* set_pll result0 options */ #define PLL_CMD_SUCCESS #define PLL_INVALID_FREQ #define PLL_INVALID_MODE #define PLL_FREQ_NOT_FOUND #define PLL_NOT_LOCKED A A A A A NXP Semiconductors All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 262 of 313 D D D D D R R R R R FT FT FT FT FT UM10601 D R R FT FT FT FT A A A A R R D D D Chapter 22: LPC800 Power profile API ROM driver D R R A FT FT FT A A R R D D D R F FT FT It should take no more than 100 s for the system PLL to lock if a valid configuration is selected. If Param3 is zero, set_pll will wait indefinitely for the PLL to lock. A non-zero value indicates how many times the code will check for a successful PLL lock event before it returns PLL_NOT_LOCKED. In this case the PLL settings are unchanged and Param0 is returned as Result1. A A A R R D D D 22.4.1.3 Param3: system PLL lock time-out A A A A A NXP Semiconductors D FT FT A A R R D D D R A FT D 22.4.2 set_power This routine configures the device’s internal power control settings according to the calling arguments. The goal is to reduce active power consumption while maintaining the feature of interest to the application close to its optimum. Remark: The set_power routine was designed for systems employing the configuration of SYSAHBCLKDIV = 1 (System clock divider register, see Table 17 and Figure 38). Using this routine in an application with the system clock divider not equal to 1 might not improve microcontroller’s performance as much as in setups when the main clock and the system clock are running at the same rate. set_power returns a result code that reports whether the power setting was successfully changed or not. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 263 of 313 A Hint: setting Param3 equal to the system PLL frequency [Hz] divided by 10000 will provide more than enough PLL lock-polling cycles. R Remark: The time it takes the PLL to lock depends on the selected PLL input clock source (IRC/system oscillator) and its characteristics. The selected source can experience more or less jitter depending on the operating conditions such as power supply and/or ambient temperature. This is why it is suggested that when a good known clock source is used and a PLL_NOT_LOCKED response is received, the set_pll routine should be invoked several times before declaring the selected PLL clock source invalid. D D D D D R R R R R FT FT FT FT FT UM10601 D R R FT FT FT FT A A A A R R D D D Chapter 22: LPC800 Power profile API ROM driver D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D XVLQJSRZHUSURILOHVDQG FKDQJLQJV\VWHPFORFN A A A A A NXP Semiconductors D D R A FT D R FXUUHQWBFORFN QHZBFORFN QHZBPRGH A XVHSRZHUURXWLQHFDOO WRFKDQJHPRGHWR '()$8/7 XVHHLWKHUFORFNLQJURXWLQHFDOORU FXVWRPFRGHWRFKDQJHV\VWHPFORFN IURPFXUUHQWBFORFNWRQHZBFORFN XVHSRZHUURXWLQHFDOO WRFKDQJHPRGHWR QHZBPRGH HQG Fig 39. Power profiles usage Table 249. set_power routine Routine set_power Input Param0: main clock (in MHz) Param1: mode (PWR_DEFAULT, PWR_CPU_PERFORMANCE, PWR_ EFFICIENCY, PWR_LOW_CURRENT) Param2: system clock (in MHz) Result Result0: PWR_CMD_SUCCESS | PWR_INVALID_FREQ | PWR_INVALID_MODE The following definitions are needed for set_power routine calls: /* set_power mode options */ #define PWR_DEFAULT #define PWR_CPU_PERFORMANCE #define PWR_EFFICIENCY #define PWR_LOW_CURRENT /* set_power result0 options */ #define PWR_CMD_SUCCESS #define PWR_INVALID_FREQ #define PWR_INVALID_MODE UM10601 Preliminary user manual 0 1 2 3 0 1 2 All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 264 of 313 D D D D D R R R R R A A A A A FT FT FT UM10601 FT FT D R R FT FT FT FT Chapter 22: LPC800 Power profile API ROM driver A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R A F FT D FT The main clock is the clock rate the microcontroller uses to source the system’s and the peripherals’ clock. It is configured by either a successful execution of the clocking routine call or a similar code provided by the user. This operand must be an integer between 1 to 50 MHz inclusive. If a value out of this range is supplied, set_power returns PWR_INVALID_FREQ and does not change the power control system. FT A A R R D 22.4.2.1 Param0: main clock FT A A R R D D For a simplified clock configuration scheme see Figure 38. For more details see Figure 3. D D R A PWR_EFFICIENCY setting was designed to find a balance between active current and the CPU’s ability to execute code and process data. In this mode the device outperforms the default mode both in terms of providing higher CPU performance and lowering active current. PWR_LOW_CURRENT is intended for those solutions that focus on lowering power consumption rather than CPU performance. 22.4.2.3 Param2: system clock The system clock is the clock rate at which the microcontroller core is running when set_power is called. This parameter is an integer between from 1 and 50 MHz inclusive. 22.5 Functional description 22.5.1 Clock control See Section 22.5.1.1 to Section 22.5.1.6 for examples of the clock control API. 22.5.1.1 Invalid frequency (device maximum clock rate exceeded) command[0] = 12000; command[1] = 60000; command[2] = CPU_FREQ_EQU; command[3] = 0; (*rom)->pWRD->set_pll(command, result); The above code specifies a 12 MHz PLL input clock and a system clock of exactly 60 MHz. The application was ready to infinitely wait for the PLL to lock. But the expected system clock of 60 MHz exceeds the maximum of 50 MHz. Therefore set_pll returns PLL_INVALID_FREQ in result[0] and 12000 in result[1] without changing the PLL settings. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 265 of 313 A PWR_CPU_PERFORMANCE configures the microcontroller so that it can provide more processing capability to the application. CPU performance is 30% better than the default option. R PWR_DEFAULT keeps the device in a baseline power setting similar to its reset state. D The input parameter mode (Param1) specifies one of four available power settings. If an illegal selection is provided, set_power returns PWR_INVALID_MODE and does not change the power control system. FT 22.4.2.2 Param1: mode D D D D D R R R R R D R R FT FT FT FT A A A A R R D D D D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D 22.5.1.2 Invalid frequency selection (system clock divider restrictions) FT FT FT FT FT UM10601 Chapter 22: LPC800 Power profile API ROM driver D FT FT A A R R D D D R A FT D command[0] = 12000; command[1] = 40; command[2] = CPU_FREQ_LTE; command[3] = 0; (*rom)->pWRD->set_pll(command, result); A A A A A NXP Semiconductors R 22.5.1.3 Exact solution cannot be found (PLL) command[0] = 12000; command[1] = 25000; command[2] = CPU_FREQ_EQU; command[3] = 0; (*rom)->pWRD->set_pll(command, result); The above code specifies a 12 MHz PLL input clock and a system clock of exactly 25 MHz. The application was ready to infinitely wait for the PLL to lock. Since there is no valid PLL setup within earlier mentioned restrictions, set_pll returns PLL_FREQ_NOT_FOUND in result[0] and 12000 in result[1] without changing the PLL settings. 22.5.1.4 System clock less than or equal to the expected value command[0] = 12000; command[1] = 25000; command[2] = CPU_FREQ_LTE; command[3] = 0; (*rom)->pWRD->set_pll(command, result); The above code specifies a 12 MHz PLL input clock, a system clock of no more than 25 MHz and no locking time-out. set_pll returns PLL_CMD_SUCCESS in result[0] and 24000 in result[1]. The new system clock is 24 MHz. 22.5.1.5 System clock greater than or equal to the expected value command[0] = 12000; command[1] = 25000; command[2] = CPU_FREQ_GTE; command[3] = 0; (*rom)->pWRD->set_pll(command, result); The above code specifies a 12 MHz PLL input clock, a system clock of at least 25 MHz and no locking time-out. set_pll returns PLL_CMD_SUCCESS in result[0] and 36000 in result[1]. The new system clock is 36 MHz. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 266 of 313 A The above code specifies a 12 MHz PLL input clock, a system clock of no more than 40 kHz and no time-out while waiting for the PLL to lock. Since the maximum divider value for the system clock is 255 and running at 40 kHz would need a divide by value of 300, set_pll returns PLL_INVALID_FREQ in result[0] and 12000 in result[1] without changing the PLL settings. D D D D D R R R R R D R R FT FT FT FT A A A A R R D D D D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D D D R A FT D command[0] = 12000; command[1] = 16500; command[2] = CPU_FREQ_APPROX; command[3] = 0; (*rom)->pWRD->set_pll(command, result); FT FT FT FT FT UM10601 Chapter 22: LPC800 Power profile API ROM driver 22.5.1.6 System clock approximately equal to the expected value A A A A A NXP Semiconductors R 22.5.2 Power control See Section 22.5.1.1 and Section 22.5.2.2 for examples of the power control API. 22.5.2.1 Invalid frequency (device maximum clock rate exceeded) command[0] = 30; command[1] = PWR_CPU_PERFORMANCE; command[2] = 40; (*rom)->pWRD->set_power(command, result); The above setup would be used in a system running at the main and system clock of 30 MHz, with a need for maximum CPU processing power. Since the specified 40 MHz clock is above the 30 MHz maximum, set_power returns PWR_INVALID_FREQ in result[0] without changing anything in the existing power setup. 22.5.2.2 An applicable power setup command[0] = 24; command[1] = PWR_CPU_EFFICIENCY; command[2] = 24; (*rom)->pWRD->set_power(command, result); The above code specifies that an application is running at the main and system clock of 24 MHz with emphasis on efficiency. set_power returns PWR_CMD_SUCCESS in result[0] after configuring the microcontroller’s internal power control features. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 267 of 313 A The above code specifies a 12 MHz PLL input clock, a system clock of approximately 16.5 MHz and no locking time-out. set_pll returns PLL_CMD_SUCCESS in result[0] and 16000 in result[1]. The new system clock is 16 MHz. D D R R A A A A A FT FT FT FT FT D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D Preliminary user manual D Rev. 1.0 — 7 November 2012 R R R Chapter 23: LPC800 I2C-bus ROM API D D D UM10601 D FT FT A A R R D D D 23.1 How to read this chapter R A FT D The I2C-bus ROM API is available on all LPC800 parts. R A 23.2 Features • Simple I2C drivers to send and receive data on the I2C-bus. • Polled and interrupt-driven receive and transmit functions for master and slave modes. 23.3 General description The drivers are callable for use by any application program to send or receive data on the I2C bus. With the I2C drivers it is easy to produce working projects using the I2C interface. The ROM routines allow the user to operate the I2C interface as a Master or a Slave. The software routines do not implement arbitration to make a Master switch to a Slave mode in the midst of a transmission. Although multi-master arbitration is not implemented in these I2C drivers, it is possible to use them in a system design with more than one master. If the flag returned from the driver indicates that the message was not successful due to loss of arbitration, the application just resends the message. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 268 of 313 D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R R FT FT A A R D D R A FT D R A VLGLYPRG LFBJHWBVWDWXV XLGLYPRG VLGLYPRG [ 3WUWR'HYLFH7DEOH [ XLGLYPRG 3WUWR'HYLFH7DEOH [ 3WUWR'HYLFH7DEOH [& 3WUWR'HYLFH7DEOH [ 3WUWR'HYLFH7DEOH [ 3WUWR,&GULYHUURXWLQHV « 3WUWR'HYLFH 7DEOHQ Fig 40. I2C-bus driver routines pointer structure 23.4 API description The I2C API contains functions to configure the I2C and send and receive data in master and slave modes. Table 250. I2C API calls API call Description Reference void i2c_isr_handler(I2C_HANDLE_T*) I2C ROM Driver interrupt service routine. Table 251 ErrorCode_t i2c_master_transmit_poll(I2C_HANDLE_T*, I2C_PARAM*, I2C_RESULT* ) I2C Master Transmit Polling Table 252 ErrorCode_t i2c_master_receive_poll(I2C_HANDLE_T* , I2C_PARAM* , I2C Master Receive Polling I2C_RESULT*) Table 253 ErrorCode_t i2c_master_tx_rx_poll(I2C_HANDLE_T* , I2C_PARAM* , I2C_RESULT*) Table 254 I2C Master Transmit and Receive Polling ErrorCode_t i2c_master_transmit_intr(I2C_HANDLE_T* , I2C_PARAM* , I2C Master Transmit Interrupt I2C_RESULT*) Table 255 ErrorCode_t i2c_master_receive_intr(I2C_HANDLE_T* , I2C_PARAM* , I2C_RESULT*) I2C Master Receive Interrupt Table 256 ErrorCode_t i2c_master_tx_rx_intr(I2C_HANDLE_T* , I2C_PARAM* , I2C_RESULT*) I2C Master Transmit Receive Interrupt Table 257 UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 F D D LFBPDVWHUBWUDQVPLWBSROO A FT FT A A R R D D D LFBLVUBKDQGOHU 520'ULYHU7DEOH FT FT FT FT ,&GULYHUURXWLQHVIXQFWLRQWDEOH A A A A R R D D D FT FT FT FT FT UM10601 Chapter 23: LPC800 I2C-bus ROM API 3WUWR520'ULYHUWDEOH [))))) A A A A A NXP Semiconductors © NXP B.V. 2012. All rights reserved. 269 of 313 D D D D D R R R R R D R R FT FT FT FT D R R A FT FT FT A A R R D D D R Reference ErrorCode_t i2c_slave_receive_poll(I2C_HANDLE_T* , I2C_PARAM* , I2C_RESULT*) I2C Slave Receive Polling Table 258 ErrorCode_t i2c_slave_transmit_poll(I2C_HANDLE_T* , I2C_PARAM* , I2C_RESULT*) I2C Slave Transmit Polling Table 259 ErrorCode_t i2c_slave_receive_intr(I2C_HANDLE_T* , I2C_PARAM* , I2C_RESULT*) I2C Slave Receive Interrupt Table 260 ErrorCode_t i2c_slave_transmit_intr(I2C_HANDLE_T* , I2C_PARAM* , I2C_RESULT*) I2C Slave Transmit Interrupt Table 261 ErrorCode_t i2c_set_slave_addr(I2C_HANDLE_T*, slave_addr_0_3, slave_mask_0_3) I2C Set Slave Address Table 262 uint32_t i2c_get_mem_size(void) I2C Get Memory Size Table 263 I2C_HANDLE_T* i2c_setup(i2c_base_addr, *start_of_ram) I2C Setup Table 264 ErrorCode_t i2c_set_bitrate(I2C_HANDLE_T*, P_clk_in_hz, bitrate_in_bps) I2C Set Bit Rate Table 265 uint32_t i2c_get_firmware_version(void ) I2C Get Firmware Version Table 266 I2C_MODE_T i2c_get_status(I2C_HANDLE_T* ) I2C Get Status Table 267 ErrorCode_t i2c_set_timeout(I2C_HANDLE_T* h_i2c, uint32_t timeout) I2C time-out value Table 268 F FT FT Description A A A R R D D D API call D FT FT A A R R D D D R A FT Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 270 of 313 A All information provided in this document is subject to legal disclaimers. R typedef struct I2CD_API { // index of all the i2c driver functions void (*i2c_isr_handler) (I2C_HANDLE_T* h_i2c) ; // ISR interrupt service request // MASTER functions *** ErrorCode_t (*i2c_master_transmit_poll)(I2C_HANDLE_T* h_i2c, I2C_PARAM* ptp, I2C_RESULT* ptr ); ErrorCode_t (*i2c_master_receive_poll)(I2C_HANDLE_T* h_i2c, I2C_PARAM* ptp, I2C_RESULT* ptr ); ErrorCode_t (*i2c_master_tx_rx_poll)(I2C_HANDLE_T* h_i2c, I2C_PARAM* ptp, I2C_RESULT* ptr ) ; ErrorCode_t (*i2c_master_transmit_intr)(I2C_HANDLE_T* h_i2c, I2C_PARAM* ptp, I2C_RESULT* ptr ) ; ErrorCode_t (*i2c_master_receive_intr)(I2C_HANDLE_T* h_i2c, I2C_PARAM* ptp, I2C_RESULT* ptr ) ; ErrorCode_t (*i2c_master_tx_rx_intr)(I2C_HANDLE_T* h_i2c, I2C_PARAM* ptp, I2C_RESULT* ptr ) ; // SLAVE functions *** ErrorCode_t (*i2c_slave_receive_poll)(I2C_HANDLE_T* h_i2c, I2C_PARAM* ptp, I2C_RESULT* ptr ) ; ErrorCode_t (*i2c_slave_transmit_poll)(I2C_HANDLE_T* h_i2c, I2C_PARAM* ptp, I2C_RESULT* ptr ) ; ErrorCode_t (*i2c_slave_receive_intr)(I2C_HANDLE_T* h_i2c, I2C_PARAM* ptp, I2C_RESULT* ptr ) ; ErrorCode_t (*i2c_slave_transmit_intr)(I2C_HANDLE_T* h_i2c, I2C_PARAM* ptp, I2C_RESULT* ptr ) ; ErrorCode_t (*i2c_set_slave_addr)(I2C_HANDLE_T* h_i2c, uint32_t slave_addr_0_3, uint32_t slave_mask_0_3) ; // OTHER functions uint32_t (*i2c_get_mem_size)(void) ; //ramsize_in_bytes memory needed by I2C drivers D The following structure has to be defined to use the I2C API: Preliminary user manual A A A A R R D D D Table 250. I2C API calls FT FT FT FT FT UM10601 Chapter 23: LPC800 I2C-bus ROM API UM10601 A A A A A NXP Semiconductors D D D D D R R R R R A A A A A FT FT FT UM10601 FT FT D R R FT FT FT FT Chapter 23: LPC800 I2C-bus ROM API A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D D D R A FT I2C_HANDLE_T* (*i2c_setup)(uint32_t i2c_base_addr, uint32_t *start_of_ram ) ; ErrorCode_t (*i2c_set_bitrate)(I2C_HANDLE_T* h_i2c, uint32_t P_clk_in_hz, uint32_t bitrate_in_bps) ; uint32_t (*i2c_get_firmware_version)() ; I2C_MODE_T (*i2c_get_status)(I2C_HANDLE_T* h_i2c ) ; } I2CD_API_T ; D R A 23.4.1 ISR handler Table 251. ISR handler Routine ISR handler Prototype void i2c_isr_handler(I2C_HANDLE_T*) Input parameter I2C_HANDLE_T - Handle to the allocated SRAM area. Return None. Description I2C ROM Driver interrupt service routine. This function must be called from the I2C ISR when using I2C Rom Driver interrupt mode. 23.4.2 I2C Master Transmit Polling Table 252. I2C Master Transmit Polling Routine I2C Master Transmit Polling Prototype ErrorCode_t i2c_master_transmit_poll(I2C_HANDLE_T*, I2C_PARAM*, I2C_RESULT* ) Input parameter I2C_HANDLE_T - Handle to the allocated SRAM area. I2C_PARAM - Pointer to the I2C PARAM struct. I2C_RESULT - Pointer to the I2C RESULT struct. Return ErrorCode. Description Transmits bytes in the send buffer to a slave. The slave address with the R/W bit =0 is expected in the first byte of the send buffer. STOP condition is sent at end unless stop_flag =0. When the task is completed, the function returns to the line after the call. 23.4.3 I2C Master Receive Polling Table 253. I2C Master Receive Polling Routine I2C Master Receive Polling Prototype ErrorCode_t i2c_master_receive_poll(I2C_HANDLE_T* , I2C_PARAM* , I2C_RESULT*) Input parameter I2C_HANDLE_T - Handle to the allocated SRAM area. I2C_PARAM - Pointer to the I2C PARAM struct. I2C_RESULT - Pointer to the I2C RESULT struct. UM10601 Preliminary user manual Return ErrorCode. Description Receives bytes from slave and put into receive buffer. The slave address with the R/W bit =0 is expected in the first byte of the send buffer. After the task is finished, the slave address with the R/W bit =1 is in the first byte of the receive buffer. STOP condition is sent at end unless stop_flag =0. When the task is completed, the function returns to the line after the call. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 271 of 313 D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R R I2C_HANDLE_T - Handle to the allocated SRAM area. FT Input parameter FT A A R ErrorCode_t i2c_master_tx_rx_poll(I2C_HANDLE_T* , I2C_PARAM* , I2C_RESULT*) D D R A D R A ErrorCode. Description First, transmit bytes in the send buffer to a slave and secondly, receives bytes from slave and store it in the receive buffer. The slave address with the R/W bit =0 is expected in the first byte of the send buffer. After the task is finished, the slave address with the R/W bit =1 is in the first byte of the receive buffer. STOP condition is sent at end unless stop_flag =0. When the task is completed, the function returns to the line after the call. 23.4.5 I2C Master Transmit Interrupt Table 255. I2C Master Transmit Interrupt Routine I2C Master Transmit Interrupt Prototype ErrorCode_t i2c_master_transmit_intr(I2C_HANDLE_T* , I2C_PARAM* , I2C_RESULT*) Input parameter I2C_HANDLE_T - Handle to the allocated SRAM area. I2C_PARAM - Pointer to the I2C PARAM struct. I2C_RESULT - Pointer to the I2C RESULT struct. Return ErrorCode. Description Transmits bytes in the send buffer to a slave. The slave address with the R/W bit =0 is expected in the first byte of the send buffer. STOP condition is sent at end unless stop_flag =0. Program control will be returned immediately and task will be completed on an interrupt-driven basis. When task is completed, the callback function is called. 23.4.6 I2C Master Receive Interrupt Table 256. I2C Master Receive Interrupt Routine I2C Master Receive Interrupt Prototype ErrorCode_t i2c_master_receive_intr(I2C_HANDLE_T* , I2C_PARAM* , I2C_RESULT*) I2C_HANDLE_T - Handle to the allocated SRAM area. I2C_PARAM - Pointer to the I2C PARAM struct. I2C_RESULT - Pointer to the I2C RESULT struct. Return ErrorCode. Description Receives bytes from slave and put into receive buffer. After the task is finished, the slave address with the R/W bit =1 is in the first byte of the receive buffer. STOP condition is sent at end unless stop_flag =0. Program control will be returned immediately and task will be completed on an interrupt-driven basis. When task is completed, the callback function is called. Rev. 1.0 — 7 November 2012 FT Return All information provided in this document is subject to legal disclaimers. F D D Prototype I2C_RESULT - Pointer to the I2C RESULT struct. Preliminary user manual A FT FT A A R R D D D I2C Master Transmit and Receive Polling I2C_PARAM - Pointer to the I2C PARAM struct. UM10601 FT FT FT FT Routine Input parameter A A A A R R D D D Table 254. I2C Master Transmit and Receive Polling FT FT FT FT FT UM10601 Chapter 23: LPC800 I2C-bus ROM API 23.4.4 I2C Master Transmit and Receive Polling A A A A A NXP Semiconductors © NXP B.V. 2012. All rights reserved. 272 of 313 D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R R I2C_HANDLE_T - Handle to the allocated SRAM area. FT Input parameter FT A A R ErrorCode_t i2c_master_tx_rx_intr(I2C_HANDLE_T* , I2C_PARAM* , I2C_RESULT*) D D R A FT D R A Return ErrorCode. Description First, transmits bytes in the send buffer to a slave and secondly, receives bytes from slave and store it in the receive buffer. The slave address with the R/W bit =0 is expected in the first byte of the send buffer. After the task is finished, the slave address with the R/W bit =1 is in the first byte of the receive buffer. STOP condition is sent at end unless stop_flag =0. Program control will be returned immediately and task will be completed on an interrupt-driven basis. When task is completed, the callback function is called. 23.4.8 I2C Slave Receive Polling Table 258. I2C Slave Receive Polling Routine I2C Slave Receive Polling Prototype ErrorCode_t i2c_slave_receive_poll(I2C_HANDLE_T* , I2C_PARAM* , I2C_RESULT*) Input parameter I2C_HANDLE_T - Handle to the allocated SRAM area. I2C_PARAM - Pointer to the I2C PARAM struct. I2C_RESULT - Pointer to the I2C RESULT struct. Return ErrorCode. Description Receives data from master. When the task is completed, the function returns to the line after the call. 23.4.9 I2C Slave Transmit Polling Table 259. I2C Slave Transmit Polling Routine I2C Slave Transmit Polling Prototype ErrorCode_t i2c_slave_transmit_poll(I2C_HANDLE_T* , I2C_PARAM* , I2C_RESULT*) Input parameter I2C_HANDLE_T - Handle to the allocated SRAM area. I2C_PARAM - Pointer to the I2C PARAM struct. I2C_RESULT - Pointer to the I2C RESULT struct. Return ErrorCode. Description Sends data bytes back to master. When the task is completed, the function returns to the line after the call. Rev. 1.0 — 7 November 2012 F D D Prototype All information provided in this document is subject to legal disclaimers. A FT FT A A R R D D D I2C Master Transmit Receive Interrupt I2C_RESULT - Pointer to the I2C RESULT struct. Preliminary user manual FT FT FT FT Routine I2C_PARAM - Pointer to the I2C PARAM struct. UM10601 A A A A R R D D D Table 257. I2C Master Transmit Receive Interrupt FT FT FT FT FT UM10601 Chapter 23: LPC800 I2C-bus ROM API 23.4.7 I2C Master Transmit Receive Interrupt A A A A A NXP Semiconductors © NXP B.V. 2012. All rights reserved. 273 of 313 D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R R Input parameter I2C_HANDLE_T - Handle to the allocated SRAM area. FT ErrorCode_t i2c_slave_receive_intr(I2C_HANDLE_T* , I2C_PARAM* , I2C_RESULT*) FT A A R Prototype D D R A D R A I2C_RESULT - Pointer to the I2C RESULT struct. Return ErrorCode. Description Receives data from master. Program control will be returned immediately and task will be completed on an interrupt-driven basis. When task is completed, the callback function is called. 23.4.11 I2C Slave Transmit Interrupt Table 261. I2C Slave Transmit Interrupt Routine I2C Slave Transmit Interrupt Prototype ErrorCode_t i2c_slave_transmit_intr(I2C_HANDLE_T* , I2C_PARAM* , I2C_RESULT*) Input parameter I2C_HANDLE_T - Handle to the allocated SRAM area. I2C_PARAM - Pointer to the I2C PARAM struct. I2C_RESULT - Pointer to the I2C RESULT struct. Return ErrorCode. Description Sends data to the Master. Program control will be returned immediately and task will be completed on an interrupt-driven basis. When task is completed, the callback function is called. 23.4.12 I2C Set Slave Address Table 262. I2C Set Slave Address Routine I2C Set Slave Address Prototype ErrorCode_t i2c_set_slave_addr(I2C_HANDLE_T*, slave_addr_0_3, slave_mask_0_3) I2C_HANDLE_T - Handle to the allocated SRAM area. Slave_addr_0_3 - unint32 variable. 7-bit slave address . Slave_mask_0_3 - unint32 variable. Slave address mask. Return ErrorCode. Description Sets the slave address and associated mask. The set_slave_addr() function supports four 7-bit slave addresses and masks. 23.4.13 I2C Get Memory Size Table 263. I2C Get Memory Size UM10601 Preliminary user manual I2C Get Memory Size All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 FT I2C_PARAM - Pointer to the I2C PARAM struct. uint32_t i2c_get_mem_size(void) F D D I2C Slave Receive Interrupt Prototype A FT FT A A R R D D D Routine Routine FT FT FT FT Table 260. I2C Slave Receive Interrupt A A A A R R D D D 23.4.10 I2C Slave Receive Interrupt FT FT FT FT FT UM10601 Chapter 23: LPC800 I2C-bus ROM API Input parameter A A A A A NXP Semiconductors © NXP B.V. 2012. All rights reserved. 274 of 313 D D D D D R R R R R A A A A A D R R D A FT F Returns the number of bytes in SRAM needed by the I2C driver. FT Description FT uint32. A A A Return R R R None. D D D Input parameter R R FT FT A A R R D D D I2C Get Memory Size FT FT FT FT Routine A A A A R R D D D Chapter 23: LPC800 I2C-bus ROM API Table 263. I2C Get Memory Size FT FT FT UM10601 FT FT NXP Semiconductors D FT FT A A R R D D D R A FT D R A 23.4.14 I2C Setup Table 264. I2C Setup Routine I2C Setup Prototype I2C_HANDLE_T* i2c_setup(i2c_base_addr, *start_of_ram) Input parameter I2C_base addr - unint32 variable. Base address for I2C peripherals. Start_of_ram - unint32 pointer. Pointer to allocated SRAM. Return I2C_Handle. Description Returns a handle to the allocated SRAM area. 23.4.15 I2C Set Bit Rate Table 265. I2C Set Bit Rate Routine I2C Set Bit Rate Prototype ErrorCode_t i2c_set_bitrate(I2C_HANDLE_T*, P_clk_in_hz, bitrate_in_bps) Input parameter I2C_HANDLE_T - Handle to the allocated SRAM area. P_clk_in_hz - unint32 variable. The Peripheral Clock in Hz. Bitrate_in_bps - unint32 variable. Requested I2C operating frequency in Hz. Return ErrorCode. Description Configures the I2C duty-cycle registers (SCLH and SCLL). 23.4.16 I2C Get Firmware Version Table 266. I2C Get Firmware Version Routine I2C Get Firmware Version Prototype uint32_t i2c_get_firmware_version(void ) Input parameter None. Return I2C ROM Driver version number. Description Returns the version number. The firmware version is an unsigned 32-bit number. 23.4.17 I2C Get Status Table 267. I2C Get Status UM10601 Preliminary user manual Routine I2C Get Status Prototype I2C_MODE_T i2c_get_status(I2C_HANDLE_T* ) Input parameter I2C_HANDLE_T - Handle to the allocated SRAM area. Return Status code. Description Returns status code. The status code indicates the state of the I2C bus. Refer to I2C Status Code Table. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 275 of 313 D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R R FT FT A A R ErrorCode_t i2c_set_timeout(I2C_HANDLE_T* h_i2c, uint32_t timeout) D D R A FT I2C_HANDLE_T - Handle to the allocated SRAM area. Returns status code. The status code indicates the state of the I2C bus. Refer to I2C Status Code Table. 23.4.19 Error codes Table 269. Error codes Error Code Description Comment 0 Successful completion Function was completed successfully. 1 General error - 0x0006 0001 ERR_I2C_NAK - 0x0006 0002 ERR_I2C_BUFFER_OVERFLOW - 0x0006 0003 ERR_I2C_BYTE_COUNT_ERR - 0x0006 0004 ERR_I2C_LOSS_OF_ARBRITRATION - 0x0006 0005 ERR_I2C_SLAVE_NOT_ADDRESSED - 0x0006 0006 ERR_I2C_LOSS_OF_ARBRITRATION_NAK_BIT - 0x0006 0007 ERR_I2C_GENERAL_FAILURE Failure detected on I2C bus. 0x0006 0008 ERR_I2C_REGS_SET_TO_DEFAULT I2C clock frequency could not be set. Default value of 0x04 is loaded into SCLH and SCLL. 23.4.20 I2C Status code Table 270. I2C Status code IDLE 1 MASTER_SEND 2 MASTER_RECEIVE 3 SLAVE_SEND 4 SLAVE_RECEIVE 23.4.21 I2C ROM driver variables The I2C ROM driver requires specific variables to be declared and initialized for proper usage. Depending on the operating mode, some variables can be omitted. 23.4.21.1 I2C Handle The I2C handle is a pointer allocated for the I2C ROM driver. The handle needs to be defined as an I2C handle TYPE: typedef void* I2C_HANDLE_T UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 276 of 313 A Status code. Description R Return D uint32_t timeout - time value is timeout*16 i2c function clock. If timeout = 0, timeout feature is disabled. 0 F D D Prototype Description A FT FT A A R R D D D I2C time-out value Status code FT FT FT FT Routine Input parameter A A A A R R D D D Table 268. I2C time-out value FT FT FT FT FT UM10601 Chapter 23: LPC800 I2C-bus ROM API 23.4.18 I2C time-out value A A A A A NXP Semiconductors D D D D D R R R R R A A A A A FT FT FT UM10601 FT FT D R R FT FT FT FT Chapter 23: LPC800 I2C-bus ROM API A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D After the definition of the handle, the handle must be initialized with I2C base address and RAM reserved for the I2C ROM driver by making a call to the i2c_setup() function. D R R D FT FT A A The callback function type must be defined if interrupts for the I2C ROM driver are used: D D R typedef void (*I2C_CALLBK_T) (uint32_t err_code, uint32_t n) A typedef struct i2c_A { //parameters passed to ROM function uint32_t num_bytes_send ; uint32_t num_bytes_rec ; uint8_t *buffer_ptr_send ; uint8_t *buffer_ptr_rec ; I2C_CALLBK_T func_pt; // callback function pointer uint8_t stop_flag; uint8_t dummy[3] ; // required for word alignment } I2C_PARAM ; The RESULT structure is as follows: typedef struct i2c_R { // RESULTs struct--results are here when returned uint32_t n_bytes_sent ; uint32_t n_bytes_recd ; } I2C_RESULT ; 23.4.23 Error structure The error code returned by the I2C ROM driver is an enum structure. The Error structure is as follows: typedef enum { LPC_OK=0, /**< enum value returned on Success */ ERROR, ERR_I2C_BASE = 0x00060000, /*0x00060001*/ ERR_I2C_NAK=ERR_I2C_BASE+1, /*0x00060002*/ ERR_I2C_BUFFER_OVERFLOW, /*0x00060003*/ ERR_I2C_BYTE_COUNT_ERR, /*0x00060004*/ ERR_I2C_LOSS_OF_ARBRITRATION, /*0x00060005*/ ERR_I2C_SLAVE_NOT_ADDRESSED, /*0x00060006*/ ERR_I2C_LOSS_OF_ARBRITRATION_NAK_BIT, /*0x00060007*/ ERR_I2C_GENERAL_FAILURE, /*0x00060008*/ ERR_I2C_REGS_SET_TO_DEFAULT UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 277 of 313 A The PARAM structure is as follows: R The I2C ROM driver input parameters consist of two structures, a PARAM structure and a RESULT structure. The PARAM structure contains the parameters passed to the I2C ROM driver and the RESULT structure contains the results after the I2C ROM driver is called. D 23.4.22 PARAM and RESULT structure FT The callback function will be called by the I2C ROM driver upon completion of a task when interrupts are used. D D D D D R R R R R A A A A A D R R FT FT FT FT D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D 23.4.24 I2C Mode A A A A R R D D D Chapter 23: LPC800 I2C-bus ROM API } ErrorCode_t; FT FT FT UM10601 FT FT NXP Semiconductors D D R A D R typedef enum I2C_mode { IDLE, MASTER_SEND, MASTER_RECEIVE, SLAVE_SEND, SLAVE_RECEIVE } I2C_MODE_T ; A 23.4.25 I2C ROM driver pointer The I2C ROM driver resides in the address 0x1FFF1FF8. The address must be declared to allow access to the ROM driver: #define ROM_DRIVERS_PTR ((ROM *)(*((unsigned int *)0x1FFF1FF8))) 23.5 Functional description 23.5.1 I2C Set-up Before calling any setup functions in the I2C ROM, the application program is responsible for doing the following: 1. Enable the clock to the I2C peripheral. 2. Enable the two pins required for the SCL and SDA outputs of the I2C peripheral. 3. Allocate a RAM area for dedicated use of the I2C ROM Driver. After the I2C block is configured, the I2C ROM driver variables have to be set up: 1. Initialize pointer to the I2C API function table. 2. Declare the PARAM and RESULT struct. 3. Declare Error Code struct. 4. Declare the transmit and receive buffer. If interrupts are used, then additional driver variables have to be set up: 1. Declare the I2C_CALLBK_ T type. 2. Declare callback functions. 3. Declare I2C ROM Driver ISR within the I2C ISR. 4. Enable I2C interrupt. 23.5.2 I2C Master mode set-up The I2C ROM Driver support polling and interrupts. In the master mode, 7-bit and 10-bit addressing are supported. The setup is as follows: UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 FT The i2c_get_status() function returns the current status of the I2C engine. The return codes can be defined as an enum structure: © NXP B.V. 2012. All rights reserved. 278 of 313 D D D D D R R R R R A A A A A FT FT FT UM10601 FT FT D R R FT FT FT FT Chapter 23: LPC800 I2C-bus ROM API A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R F D FT FT A A R R D 2. Create the I2C handle by making a call to the i2c_setup() function. A FT FT A A R R D D 1. Allocate SRAM for the I2C ROM Driver by making a call to the i2c_get_mem_size() function. D D 3. Set the I2C operating frequency by making a call to the i2c_set_bitrate() function. R A FT pI2cApi = ROM_DRIVERS_PTR->pI2CD; //setup I2C function table pointer size_in_bytes = pI2cApi->i2c_get_mem_size(); i2c_handle = pI2cApi->i2c_setup(LPC_I2C_BASE, (uint32_t *)&I2C_Handle[0] ); error_code = pI2cApi->i2c_set_bitrate((I2C_HANDLE_T*)i2c_handle, PCLK_in_Hz, bps_in_hz); D R A 23.5.3 I2C Slave mode set-up The I2C ROM Driver support polling and interrupts in the slave mode. In the slave mode, only 7-bit addressing is supported. The set-up is as follows: 1. Allocate SRAM for the I2C ROM Driver by making a call to the i2c_get_mem_size() function. 2. Create the I2C handle by making a call to the i2c_setup() function. 3. Set the I2C operating frequency by making a call to the i2c_set_bitrate() function. 4. Set the slave address by making a call to the i2c_set_slave_addr() function. The I2C ROM driver allows setting up to 4 slave addresses and 4 address masks as well as possibly enabling the General Call address. The four slave address bytes are packed into the 4 byte variable. Slave address byte 0 is the least significant byte and Slave address byte 3 is the most significant byte. The Slave address mask bytes are ordered the same way in the other 32 bit variable. When in slave receive mode, all of these addresses (or groups if masks are used) will be monitored for a match. If the General Call bit (least significant bit of any of the four slave address bytes) is set, then the General Call address of 0x00 is monitored as well. ϯϭϮϱ Ϯϰ Ϯϯ ϭϳ ϭϲ ϭϱ ^ůĂǀĞĚĚƌĞƐƐϯ ' ^ůĂǀĞĚĚƌĞƐƐϮ ' ϭ Ϭ ^ůĂǀĞĚĚƌĞƐƐϬ ' ϵ ϴ ϳ ^ůĂǀĞĚĚƌĞƐƐϭ ' Fig 41. I2C slave mode set-up address packing pI2cApi = ROM_DRIVERS_PTR->pI2CD; //setup I2C function table pointer size_in_bytes = pI2cApi->i2c_get_mem_size(); i2c_handle = pI2cApi->i2c_setup(LPC_I2C_BASE, (uint32_t *)&I2C_Handle[0] ); error_code = pI2cApi->i2c_set_bitrate((I2C_HANDLE_T*)i2c_handle, PCLK_in_Hz, bps_in_hz); error_code = pI2cApi->i2c_set_slave_addr((I2C_HANDLE_T*)i2c_handle, slave_addr, slave_addr_mask) ; UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 279 of 313 D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D Chapter 23: LPC800 I2C-bus ROM API D R R A FT FT FT A A R R D D D R A FT FT A A R R D D The Master mode drivers give the user the choice of either polled (wait for the message to finish) or interrupt driven routines (non-blocking). Polled routines are recommended for testing purposes or very simple I2C applications. These routines allow the Master to send to Slaves with 7-bit or 10-bit addresses. F FT FT A A R R D D D 23.5.4 I2C Master Transmit/Receive FT FT FT UM10601 FT FT NXP Semiconductors D D R A FT D The following routines are polled routines : R A err_code i2c_master_transmit_poll(I2C_HANDLE_T*, I2C_PARAM*, I2C_RESULT*) err_code i2c_master_receive_poll(I2C_HANDLE_T*, I2C_PARAM*, I2C_RESULT*) err_code i2c_master_tx_rx_poll (I2C_HANDLE_T*, I2C_PARAM*, I2C_RESULT*) The following routines are interrupt driven routines: err_code i2c_master_transmit_intr(I2C_HANDLE_T*, I2C_PARAM*, I2C_RESULT*) err_code i2c_master_receive_intr(I2C_HANDLE_T*, I2C_PARAM*, I2C_RESULT*) err_code i2c_master_tx_rx_intr(I2C_HANDLE_T*, I2C_PARAM*, I2C_RESULT*) Where: • err_code is the return state of the function. An “0” indicates success. All non-zero indicates an error. Refer to Error Table. • I2C_PARM* is a structure with parameters passed to the function. Refer to Section 23.4.22. • I2C_RESULT* is a containing the results after the function executes. To initiate a master mode write/read the I2C_PARAM has to be setup. The I2C_PARAM is a structure with various variables needed by the I2C ROM Driver to operate correctly. The structure contains the following: • • • • • • Number of bytes to be transmitted. Number of bytes to be receive. Pointer to the transmit buffer. Pointer to the receive buffer. Pointer to callback function. Stop flag. The RESULT structure contains the results after the function executes. The structure contains the following: • Number of bytes transmitted. • Number of bytes received. Remark: The number of bytes transmitted will be updated for i2c_master_transmit_intr() and i2c_master_transmit_poll(). The number of bytes received will only be update on i2c_master_receive_poll(), i2c_master_receive_intr(), i2c_master_tx_rx_poll(), and i2c_master_tx_rx_intr(). UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 280 of 313 D D D D D R R R R R A A A A A FT FT FT UM10601 FT FT D R R FT FT FT FT Chapter 23: LPC800 I2C-bus ROM API A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D In all the master mode routines, the transmit buffer’s first byte must be the slave address with the R/W bit set to “0”. To enable a master read, the receive buffer’s first byte must be the slave address with the R/W bit set to “1”. D FT FT A A R R D D D The following conditions must be fulfilled to use the I2C driver routines in master mode: R A • For 10-bit address, the first byte of the transmit buffer must have the slave address most significant 2 bits with the (R/W) bit =0. The second byte must contain the remaining 8-bit of the slave address. • For 10-bit address, the first byte of the receive buffer must have the slave address most significant 2 bits with the (R/W) bit =1. The second byte must contain the remaining 8-bit of the slave address. • The number of bytes to be transmitted should include the first byte of the buffer which is the slave address byte. Example: 2 data bytes + 7-bit slave addr = 3. • The application program must enable I2C interrupts. When I2C interrupt occurs, the i2c_isr_handler function must be called from the application program. When using the interrupt function calls, the callback functions must be define. Upon the completion of a read/write as specified by the PARAM structure, the callback functions will be invoked. 23.5.5 I2C Slave Mode Transmit/Receive In slave mode, polled routines are intended for testing purposes. It is up to the user to decide whether to use the polled or interrupt driven mode. While operating the Slave driver in polled mode can be useful for program development and debugging, most applications will need the interrupt-driven versions of Slave Receive and Transmit in the final software. The following routines are polled routines: err_code i2c_slave_receive_poll(I2C_HANDLE_T*, I2C_PARAM*, I2C_RESULT*) err_code i2c_slave_transmit_poll(I2C_HANDLE_T*, I2C_PARAM*, I2C_RESULT*) The following routines are interrupt driven routines: err_code i2c_slave_receive_intr(I2C_HANDLE_T*, I2C_PARAM*, I2C_RESULT*) err_code i2c_slave_transmit_intr(I2C_HANDLE_T*, I2C_PARAM*, I2C_RESULT*) Where: • err_code is the return state of the function. An 0 indicates success. All non-zero indicates an error. Refer to the Error Code Table. • I2C_PARM is a structure with parameters passed to the function. Section 23.4.22. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 281 of 313 A the most significant 7 bits and the least significant (R/W) bit = 1. Example: Slave Addr 0x53, first byte 0xA7. R • For 7-bit addressing, the first byte of the receive buffer must have the slave address in D the most significant 7 bits and the least significant (R/W) bit = 0. Example: Slave address 0x53, first byte is 0xA6. FT • For 7-bit addressing, the first byte of the send buffer must have the slave address in D D D D D R R R R R A A A A A FT FT FT UM10601 FT FT D R R FT FT FT FT Chapter 23: LPC800 I2C-bus ROM API A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R A FT FT A A R R D D To initiate a master-mode write/read the I2C_PARAM has to be setup. The I2C_PARAM is a structure with various variables needed by the I2C ROM Driver to operate correctly. The structure contains the following: F FT FT A A R R D D • I2C_RESULT is a containing the results after the function executes. Section 23.4.22. D D R A Number of bytes to be transmitted. FT D Number of bytes to be received. R A • • • • • • Pointer to the transmit buffer. Pointer to the receive buffer. Pointer to callback function. Stop flag. The RESULT structure contains the results after the function executes. The structure contains the following: • Number of bytes transmitted. • Number of bytes received. Remark: The number of bytes transmitted is updated only for i2c_slave_send_poll() and i2c_slave_send_intr(). The number of bytes received is updated only for i2c_slave_receive_poll() and i2c_slave_receive_intr(). To initiate a slave mode communication, the receive function is called. This can be either the polling or interrupt driven function, i2c_slave_receive_poll() or i2c_slave_receive_intr(), respectively. The receive buffer should be as large or larger than any data or command that will be received. If the amount of data exceed the receive buffer size, an error code will be returned. In slave-receive mode, the driver receives data until one of the following are true: • Address matching set in the set_slave_addr() function with the R/W bit set to 1 • STOP or repeated START is received • An error condition is detected When using the interrupt function calls, the callback functions must be define. Upon the completion of a read/write as specified by the PARAM structure, the callback functions will be invoked. 23.5.6 I2C time-out feature //timeout: Timeout time value. Specifies the timeout interval value in increments of // 16 I2C function clocks (Min value is 16). // if timeout = 0, timeout feature is disabled // if timeout != 0, time value is timeout*16 i2c function clock. ErrorCode_t i2c_set_timeout(I2C_HANDLE_T* h_i2c, uint32_t timeout) { I2C_DRIVER_TypeDef *h ; // declare pointer to i2c structure [handle] h = (I2C_DRIVER_TypeDef*) h_i2c ; //assign handle pointer address if (timeout != 0){ h->i2c_base->TimeOut = (timeout - 1)<<4; UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 282 of 313 D D D D D R R R R R D R R FT FT FT FT A A A A R R D D D D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D } else FT FT FT FT FT UM10601 Chapter 23: LPC800 I2C-bus ROM API // Enable timeout feature h->i2c_base->CFG |= BI2C_TIMEOUT_EN; A A A A A NXP Semiconductors D D R A FT // disable timeout feature h->i2c_base->CFG &= ~BI2C_TIMEOUT_EN; D R UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 A return(LPC_OK) ; }//i2c_set_timeout © NXP B.V. 2012. All rights reserved. 283 of 313 R R R R R A A A A A FT FT FT FT FT D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D Chapter 24: LPC800 USART API ROM driver routines R A F FT FT A A R R D D Preliminary user manual D Rev. 1.0 — 7 November 2012 D D D D D UM10601 D FT FT A A R R D D D 24.1 How to read this chapter R A FT D The USART ROM driver routines are available on all LPC800 parts. R A 24.2 Features • Send and receive characters in asynchronus UART mode • Send and receive multiple characters (line) in asynchronous UART mode 24.3 General description The UART API handles sending and receiving characters using any of the USART blocks in asynchronous mode. Remark: Because all USARTS share a common fractional divider, the uart_init routine returns the value for the common divider. 8$57GULYHUURXWLQHVIXQFWLRQWDEOH XDUWBJHWBPHPBVL]H 3WUWR520'ULYHUWDEOH [))))) XDUWBVHWXS VLGLYPRG XDUWBLVU XLGLYPRG [ 520'ULYHU7DEOH 3WUWR'HYLFH7DEOH [ [ 3WUWR'HYLFH7DEOH 3WUWR'HYLFH7DEOH [& [ 3WUWR'HYLFH7DEOH 3WUWR'HYLFH7DEOH [ [ 3WUWR8$57GULYHUURXWLQHV « 3WUWR'HYLFH 7DEOHQ Fig 42. USART driver routines pointer structure UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 284 of 313 D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D Chapter 24: LPC800 USART API ROM driver routines D R R A FT FT FT A A R R D D D R A D FT FT A A R R D The UART API contains functions to send and receive characters via any of the USART blocks. F FT FT A A R R D D D 24.4 API description FT FT FT UM10601 FT FT NXP Semiconductors D D R A FT Table 271. UART API calls uint32_t ramsize_in_bytes uart_get_mem_size( void) ; UART get memory size Table 272 UART_HANDLE_T* uart_setup(uint32_t base_addr, uint8_t *ram) ; UART set-up Table 273 uint32_t uart_init(UART_HANDLE_T* handle, UART_CONFIG set); UART init Table 274 uint8_t uart_get_char(UART_HANDLE_T* handle); UART get character Table 275 void uart_put_char(UART_HANDLE_T* handle, uint8_t data); UART put character Table 276 uint32_t uart_get_line(UART_HANDLE_T* handle, UART_PARAM_T param); UART get line Table 277 uint32_t uart_put_line(UART_HANDLE_T* handle, UART_PARAM_T param); UART put line Table 278 void uart_isr(UART_HANDLE_T* handle); UART interrupt service routine Table 279 The following structure has to be defined to use the UART API: typedef struct UARTD_API { // index of all the uart driver functions uint32_t (*uart_get_mem_size)(void); UART_HANDLE_T (*uart_setup)(uint32_t base_addr, uint8_t *ram); uint32_t (*uart_init)(UART_HANDLE_T handle, UART_CONFIG_T *set); //--polling functions--// uint8_t (*uart_get_char)(UART_HANDLE_T handle); void (*uart_put_char)(UART_HANDLE_T handle, uint8_t data); uint32_t (*uart_get_line)(UART_HANDLE_T handle, UART_PARAM_T * param); uint32_t (*uart_put_line)(UART_HANDLE_T handle, UART_PARAM_T * param); //--interrupt functions--// void (*uart_isr)(UART_HANDLE_T handle); } UARTD_API_T ; // end of structure 24.4.1 UART get memory size Table 272. uart_get_mem_size UM10601 Preliminary user manual Routine uart_get_mem_size Prototype uint32_t Input parameter None. Return Memory size in bytes. Description Get the memory size needed by one Min UART instance. ramsize_in_bytes uart_get_mem_size( void) ; All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 285 of 313 A Reference R Description D API call D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R R FT UART_HANDLE_T* uart_setup(uint32_t base_addr, uint8_t *ram) ; FT A A R Prototype D D R A FT base_addr: Base address of register for this uart block. Table 274. uart_init Routine uart_init Prototype uint32_t uart_init(UART_HANDLE_T* handle, UART_CONFIG set); Input parameter handle: The handle to the uart instance. set: configuration for uart operation. Return Fractional divider value if System clock is not integer multiples of baud rate. Description Setup baud rate and operation mode for uart, then enable uart. 24.4.4 UART get character Table 275. uart_get_char Routine uart_get_char Prototype uint8_t uart_get_char(UART_HANDLE_T* handle); Input parameter handle: The handle to the uart instance. Return Received data Description Receive one Char from uart. This functions is only returned after Char is received. In case Echo is enabled, the received data is sent out immediately. 24.4.5 UART put character Table 276. uart_put_char Routine uart_put_char Prototype void uart_put_char(UART_HANDLE_T* handle, uint8_t data); Input parameter handle: The handle to the uart instance. data: data to be sent out. Return None. Description Send one Char through uart. This function is only returned after data is sent. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 286 of 313 A Setup Min UART instance with provided memory and return the handle to this instance. R The handle to corresponding uart instance. Description D Return All information provided in this document is subject to legal disclaimers. F D D uart_setup 24.4.3 UART init Preliminary user manual A FT FT A A R R D D D Routine ram: Pointer to the memory space for uart instance. The size of the memory space can be obtained by the uart_get_mem_size function. UM10601 FT FT FT FT Table 273. uart_setup A A A A R R D D D 24.4.2 UART setup FT FT FT FT FT UM10601 Chapter 24: LPC800 USART API ROM driver routines Input parameter A A A A A NXP Semiconductors D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R R Input parameter handle: The handle to the uart instance. FT uint32_t uart_get_line(UART_HANDLE_T* handle, UART_PARAM_T param); FT A A R Prototype D D R A D R A ERR_UART_RECEIVE_ON - UART receive is ongoing. Receive multiple bytes from UART. 24.4.7 UART put line Table 278. uart_put_line Routine uart_put_line Prototype uint32_t uart_put_line(UART_HANDLE_T* handle, UART_PARAM_T param); handle: The handle to the uart instance. param: Return Refer to UART_PARAM_T definition. Error code: ERR_UART_SEND_ON - UART sending is ongoing. Description Send string (end with \0) or raw data through UART. 24.4.8 UART interrupt service routine Table 279. uart_isr Routine uart_isr Prototype void uart_isr(UART_HANDLE_T* handle); Input parameter handle: The handle to the uart instance. Return None. Description UART interrupt service routine. To use this routine, the corresponding USART interrupt must be enabled. This function is invoked by the user ISR. 24.4.9 Error codes Table 280. Error codes UM10601 Preliminary user manual Return code Error Code Description 0x0008 0001 ERR_UART_RXD_BUSY = ERR_UART_BASE+1, UART receive is busy 0x0008 0002 ERR_UART_TXD_BUSY UART transmit is busy 0x0008 0003 ERR_UART_OVERRUN_FRA ME_PARITY_NOISE Overrun error, Frame error, parity error, RxNoise error 0x0008 0004 ERR_UART_UNDERRUN Underrun error 0x0008 0005 ERR_UART_PARAM Parameter error All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 FT Refer to UART_PARAM_T definition. Error code: Input parameter F D D uart_get_line Description A FT FT A A R R D D D Routine Return FT FT FT FT Table 277. uart_get_line A A A A R R D D D 24.4.6 UART get line FT FT FT FT FT UM10601 Chapter 24: LPC800 USART API ROM driver routines param: A A A A A NXP Semiconductors © NXP B.V. 2012. All rights reserved. 287 of 313 D D D D D R R R R R D R R FT FT FT FT A A A A R R D D D D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT D D R A FT D R A Typdef struct UART_CONFIG { uint32_t sys_clk_in_hz; // Sytem clock in hz. uint32_t baudrate_in_hz; // Baudrate in hz uint8_t config; //bit1:0 // 00: 7 bits length, 01: 8 bits lenght, others: reserved //bit3:2 // 00: No Parity, 01: reserved, 10: Even, 11: Odd //bit4 // 0: 1 Stop bit, 1: 2 Stop bits uint8_t sync_mod; //bit0: 0(Async mode), 1(Sync mode) //bit1: 0(Un_RXD is sampled on the falling edge of SCLK) // 1(Un_RXD is sampled on the rising edge of SCLK) //bit2: 0(Start and stop bits are transmitted as in asynchronous // mode) // 1(Start and stop bits are not transmitted) //bit3: 0(the UART is a slave on Sync mode) // 1(the UART is a master on Sync mode) uint16_t error_en; //Bit0: OverrunEn, bit1: UnderrunEn, bit2: FrameErrEn, // bit3: ParityErrEn, bit4: RxNoiseEn } FT A A R R D 24.4.10.1 UART_CONFIG structure FT FT FT FT FT UM10601 Chapter 24: LPC800 USART API ROM driver routines 24.4.10 UART ROM driver variables A A A A A NXP Semiconductors 24.4.10.2 UART_HANDLE_T The handle to the instance of the UART driver. Each UART has one handle, so there can be several handles for up to three UART blocks. This handle is created by Init API and used by the transfer functions for the corresponding UART block. typedef void UART_HANDLE_T ; // define TYPE for uart handle pointer 24.4.10.3 UART_PARAM_T typedef struct uart_A { // parms passed to uart driver function uint8_t * buffer ; // The pointer of buffer. // For uart_get_line function, buffer for receiving data. // For uart_put_line function, buffer for transmitting data. uint32_t size; // [IN] The size of buffer. //[OUT] The number of bytes transmitted/received. uint16_t transfer_mode ; // 0x00: For uart_get_line function, transfer without // termination. // For uart_put_line function, transfer without termination. // 0x01: For uart_get_line function, stop transfer when // <CR><LF> are received. // For uart_put_line function, transfer is stopped after // reaching \0. <CR><LF> characters are sent out after that. // 0x02: For uart_get_line function, stop transfer when <LF> // is received. // For uart_put_line function, transfer is stopped after // reaching \0. A <LF> character is sent out after that. //0x03: For uart_get_line function, RESERVED. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 288 of 313 D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R R FT FT A A R D D R A FT D R A All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 F D D <tbd> Preliminary user manual A FT FT A A R R D D D 24.5 Functional description UM10601 FT FT FT FT UART_CALLBK_T } UART_PARAM_T ; //0x00: Polling mode, function is blocked until transfer is // finished. // 0x01: Intr mode, function exit immediately, callback function // is invoked when transfer is finished. //0x02: RESERVED callback_func_pt; // callback function A A A A R R D D D uint16_t driver_mode; FT FT FT FT FT UM10601 Chapter 24: LPC800 USART API ROM driver routines // For uart_put_line function, transfer is stopped after // reaching \0. A A A A A NXP Semiconductors © NXP B.V. 2012. All rights reserved. 289 of 313 D R R R R R A A A A A FT FT FT FT FT D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D Chapter 25: LPC800 Debugging R A F FT FT A A R R D D Preliminary user manual D Rev. 1.0 — 7 November 2012 D D D D UM10601 D FT FT A A R R D D D 25.1 How to read this chapter R A FT D The debug functionality is identical for all LPC800 parts. R A 25.2 Features • • • • • • • Supports ARM Serial Wire Debug mode. Direct debug access to all memories, registers, and peripherals. No target resources are required for the debugging session. Four breakpoints. Two data watchpoints that can also be used as triggers. Supports JTAG boundary scan. Micro Trace Buffer (MTB) supported. 25.3 General description Debug functions are integrated into the ARM Cortex-M0+. Serial wire debug functions are supported. The ARM Cortex-M0+ is configured to support up to four breakpoints and two watchpoints. Support for boundary scan and Micro Trace Buffer is available. 25.4 Pin description The SWD functions are assigned to pins through the switch matrix. The SWD functions are fixed-pin functions that are enabled through the switch matrix and can only be assigned to special pins on the package. The SWD functions are enabled by default. See Section 9.3.2 to enable the analog comparator inputs and the reference voltage input. Table 281. SWD pin description Function Type Pin Description SWM register Reference SWCLK I/O SWCLK/PIO0_3/ Serial Wire Clock. This pin is the clock for SWD TCLK debug logic when in the Serial Wire Debug mode (SWD). This pin is pulled up internally. PINENABLE0 Table 105 SWDIO I/O SWDIO/PIO0_2/ Serial wire debug data input/output. The SWDIO TMS pin is used by an external debug tool to communicate with and control the LPC800. This pin is pulled up internally. PINENABLE0 Table 105 The boundary scan mode and the pins needed are selected by hardware (see Section 25.5.3). There is no access to the boundary scan pins through the switch matrix. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 290 of 313 D D D D D R R R R R D R R FT FT FT FT D R R A FT FT FT A A R R D D D R A I JTAG Test Clock. This pin is the clock for JTAG boundary scan when the RESET pin is LOW. TMS SWDIO/PIO0_2/ TMS I JTAG Test Mode Select. The TMS pin selects the next state in the TAP state machine. This pin includes an internal pull-up and is used for JTAG boundary scan when the RESET pin is LOW. TDI PIO0_1/ACMP_I2/ I CLKIN/TDI JTAG Test Data In. This is the serial data input for the shift register. This pin includes an internal pull-up and is used for JTAG boundary scan when the RESET pin is LOW. TDO PIO0_0/ACMP_I1/ O TDO JTAG Test Data Output. This is the serial data output from the shift register. Data is shifted out of the device on the negative edge of the TCK signal. This pin is used for JTAG boundary scan when the RESET pin is LOW. TRST PIO0_4/ WAKEUP/TRST JTAG Test Reset. The TRST pin can be used to reset the test logic within the debug logic. This pin includes an internal pull-up and is used for JTAG boundary scan when the RESET pin is LOW. FT FT A A R R SWCLK/PIO0_3/ TCK D TCK D Description F FT FT A A R R D D D Type D D R A 25.5.2 Debug connections for SWD For debugging purposes, it is useful to provide access to the ISP entry pin PIO0_1. This pin can be used to recover the part from configurations which would disable the SWD port such as improper PLL configuration, reconfiguration of SWD pins, entry into Deep power-down mode out of reset, etc. This pin can be used for other functions such as GPIO, but it should not be held LOW on power-up or reset. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 291 of 313 A During a debugging session, the System Tick Timer is automatically stopped whenever the CPU is stopped. Other peripherals are not affected. R It is recommended not to use the debug mode during Deep-sleep or Power-down mode mode. D 25.5.1 Debug limitations FT I 25.5 Functional description Preliminary user manual A A A A R R D D D Function Pin name UM10601 FT FT FT FT FT UM10601 Chapter 25: LPC800 Debugging Table 282. JTAG boundary scan pin description A A A A A NXP Semiconductors D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D Chapter 25: LPC800 Debugging D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D 9'' FT FT FT UM10601 FT FT NXP Semiconductors D FT FT A A R R D D D A FT D R A 6LJQDOVIURP6:'FRQQHFWRU R /3& 975() 6:',2 6:&/. 6:',2 6:&/. Q6567 5(6(7 *1' 3,2B *QG ,63HQWU\ The VTREF pin on the SWD connector enables the debug connector to match the target voltage. Fig 43. Connecting the SWD pins to a standard SWD connector 25.5.3 Boundary scan The RESET pin selects between the JTAG boundary scan (RESET = LOW) and the ARM SWD debug (RESET = HIGH). The ARM SWD debug port is disabled while the LPC11Uxx is in reset. To perform boundary scan testing, follow these steps: 1. Erase any user code residing in flash. 2. Power up the part with the RESET pin pulled HIGH externally. 3. Wait for at least 250 s. 4. Pull the RESET pin LOW externally. 5. Perform boundary scan operations. 6. Once the boundary scan operations are completed, assert the TRST pin to enable the SWD debug mode and release the RESET pin (pull HIGH). Remark: The JTAG interface cannot be used for debug purposes. Remark: POR, BOD reset, or a LOW on the TRST pin puts the test TAP controller in the Test-Logic Reset state. The first TCK clock while RESET = HIGH places the test TAP in Run-Test Idle mode. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 292 of 313 R R R R R A A A A A FT FT FT FT FT D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D Chapter 26: LPC800 Packages and pin description R A F FT FT A A R R D D Preliminary user manual D Rev. 1.0 — 7 November 2012 D D D D D UM10601 D FT FT A A R R D D D 26.1 Packages R A FT D R A 5(6(73,2B 3,2B:$.(837567 6:&/.3,2B7&. 6:',23,2B706 ',3 3,2B$&03B,7'2 966 9'' 3,2B$&03B,&/.,17', DDD Fig 44. Pin configuration DIP8 package (LPC810M021FN8) 3,2B 3,2B$&03B,7'2 3,2B 3,2B9''&03 5(6(73,2B 3,2B:$.(837567 6:&/.3,2B7&. 6:',23,2B706 3,2B;7$/,1 3,2B 3,2B;7$/287 3,2B 3,2B /3&0)'+ /3&0)'+ 76623 966 9'' 3,2B$&03B,&/.,17', DDD Fig 45. Pin configuration TSSOP16 package 3,2B 3,2B 3,2B 3,2B$&03B,7'2 3,2B 3,2B9''&03 5(6(73,2B 3,2B 3,2B:$.(837567 6:&/.3,2B7&. 6:',23,2B706 3,2B;7$/,1 3,2B 3,2B;7$/287 3,2B 3,2B$&03B&/.,17', 62 3,2B 966 9'' 3,2B DDD Fig 46. Pin configuration SO20 package (LPC812M101FD20) UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 293 of 313 D D D D D R R R R R D R R FT D FT D R 9'' A 3,2B Pin configuration TSSOP20 package 26.2 Pin description The pin description table Table 283 shows the pin functions that are fixed to specific pins on each package. These fixed-pin functions are selectable between the GPIO, comparator, SWD, and the XTAL pins. By default, the GPIO function is selected except on pins PIO0_2, PIO0_3, and PIO0_5. JTAG functions are available in boundary scan mode only. Movable function for the I2C, USART, SPI, and SCT pin functions can be assigned through the switch matrix to any pin that is not power or ground in place of the pin’s fixed functions. The following exceptions apply: For full I2C-bus compatibility, assign the I2C functions to the open-drain pins PIO0_11 and PIO0_10. Do not assign more than one output to any pin. However, more than one input can be assigned to a pin. Pin PIO0_4 triggers a wake-up from Deep power-down mode. If you need to wake up from Deep power-down mode via an external pin, do not assign any movable function to this pin. The JTAG functions TDO, TDI, TCK, TMS, and TRST are selected on pins PIO0_0 to PIO0_4 by hardware when the part is in boundary scan mode. UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 F A 966 DDD Fig 47. A R 3,2B FT 3,2B$&03B,&/.,17', 3,2B /3&0)'+ 76623 A R 3,2B;7$/287 3,2B D D 3,2B;7$/,1 3,2B FT FT 6:',23,2B706 A R 6:&/.3,2B7&. D FT 3,2B:$.(837567 R A A D R R 3,2B9''&03 5(6(73,2B R A D D D R FT FT A A R R D D D 3,2B$&03B,7'2 3,2B FT FT FT FT 3,2B A A A A R R D D D 3,2B FT FT FT FT FT UM10601 Chapter 26: LPC800 Packages and pin description 3,2B A A A A A NXP Semiconductors © NXP B.V. 2012. All rights reserved. 294 of 313 D D D D D R R R R R D R R FT A FT FT A D D R I/O I; PU PIO0_0 — General purpose digital input/output port 0 pin 0. 4 [2] SWCLK/PIO0_3/ TCK 6 5 3 [2] PIO0_4/WAKEUP/ TRST 5 4 2 [6] A 6 R SWDIO/PIO0_2/TMS 7 D 5 [5] AI - ACMP_I1 — Analog comparator input 1. I/O I; PU PIO0_1 — General purpose digital input/output pin. ISP entry pin. A LOW level on this pin during reset starts the ISP command handler. In boundary scan mode: TDI (Test Data In). AI - ACMP_I2 — Analog comparator input 2. I - CLKIN — External clock input. I/O I; PU SWDIO — Serial Wire Debug I/O. SWDIO is enabled by default on this pin. In boundary scan mode: TMS (Test Mode Select). I/O - PIO0_2 — General purpose digital input/output pin. I/O I; PU SWCLK — Serial Wire Clock. SWCLK is enabled by default on this pin. In boundary scan mode: TCK (Test Clock). I/O - PIO0_3 — General purpose digital input/output pin. I/O I; PU PIO0_4 — General purpose digital input/output pin. In ISP mode, this is the USART0 transmit pin U0_TXD. In boundary scan mode: TRST (Test Reset). This pin triggers a wake-up from Deep power-down mode. If you need to wake up from Deep power-down mode via an external pin, do not assign any movable function to this pin. Pull this pin HIGH externally to enter Deep power-down mode. Pull this pin LOW to exit Deep power-down mode. A LOW-going pulse as short as 50 ns wakes up the part. RESET/PIO0_5 PIO0_6/VDDCMP PIO0_7 PIO0_8/XTALIN PIO0_9/XTALOUT PIO0_10 UM10601 Preliminary user manual 4 18 17 14 13 9 3 15 14 11 10 8 1 [4] - [9] I/O I; PU RESET — External reset input: A LOW-going pulse as short as 50 ns on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. I - PIO0_5 — General purpose digital input/output pin. I/O I; PU PIO0_6 — General purpose digital input/output pin. AI - VDDCMP — Alternate reference voltage for the analog comparator. - [2] I/O I; PU PIO0_7 — General purpose digital input/output pin. - [8] I/O I; PU PIO0_8 — General purpose digital input/output pin. I - XTALIN — Input to the oscillator circuit and internal clock generator circuits. Input voltage must not exceed 1.95 V. I/O I; PU PIO0_9 — General purpose digital input/output pin. O - XTALOUT — Output from the oscillator circuit. I IA PIO0_10 — General purpose digital input/output pin. Assign I2C functions to this pin when true open-drain pins are needed for a signal compliant with the full I2C specification. - [8] - [3] All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 FT [5] A DIP8 R R 9 F D D [1] In ISP mode, this is the USART0 receive pin U0_RXD. In boundary scan mode: TDO (Test Data Out). 12 A FT FT TSSOP16 R A A SO20/ TSSOP20 D R R 8 R A D D 16 D R FT FT A A R R D D D PIO0_1/ACMP_I2/ CLKIN/TDI 19 FT FT FT FT PIO0_0/ACMP_I1/ TDO Type Reset Description state A A A A R R D D D Table 283. Pin description table (fixed pins) FT FT FT FT FT UM10601 Chapter 26: LPC800 Packages and pin description Symbol A A A A A NXP Semiconductors © NXP B.V. 2012. All rights reserved. 295 of 313 D D D D D R R R R R D R R D A FT R SO20/ TSSOP20 TSSOP16 DIP8 [3] I IA PIO0_11 — General purpose digital input/output pin. Assign I2C functions to this pin when true open-drain pins are needed for a signal compliant with the full I2C specification. PIO0_12 3 2 - [2] I/O I; PU PIO0_12 — General purpose digital input/output pin. FT R - I/O I; PU PIO0_15 — General purpose digital input/output pin. - [7] I/O I; PU PIO0_16 — General purpose digital input/output pin. [7] I/O I; PU PIO0_17 — General purpose digital input/output pin. - - 3.3 V supply voltage. - Ground. 1 - - VDD 15 12 6 VSS 16 13 7 [1] Pin state at reset for default function: I = Input; AI = Analog Input; O = Output; PU = internal pull-up enabled (pins pulled up to full VDD level ); IA = inactive, no pull-up/down enabled. [2] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis; includes high-current output driver. [3] True open-drain pin. I2C-bus pins compliant with the I2C-bus specification for I2C standard mode, I2C Fast-mode, and I2C Fast-mode Plus. Do not use this pad for high-speed applications like the SPI clock. [4] RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode. [5] 5 V tolerant pin providing standard digital I/O functions with configurable modes, configurable hysteresis, and analog input. When configured as an analog input, the digital section of the pin is disabled, and the pin is not 5 V tolerant. [6] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis. In Deep power-down mode, pulling this pin LOW wakes up the chip. [7] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis. [8] 5 V tolerant pin providing standard digital I/O functions with configurable modes, configurable hysteresis, and analog I/O for the system oscillator. When configured as an analog I/O, the digital section of the pin is disabled, and the pin is not 5 V tolerant. [9] Not a 5 V tolerant pin due to special analog functionality. Pin provides standard digital I/O functions with configurable modes, configurable hysteresis, and analog I/O. When configured as an analog I/O, the digital section of the pin is disabled Table 284. Movable functions (assign to pins PIO0_0 to PIO_17 through switch matrix) UM10601 Preliminary user manual Function name Type Description U0_TXD O Transmitter output for USART0. U0_RXD I Receiver input for USART0. U0_RTS O Request To Send output for USART0. U0_CTS I Clear To Send input for USART0. U0_SCLK I/O Serial clock input/output for USART0 in synchronous mode. U1_TXD O Transmitter output for USART1. U1_RXD I Receiver input for USART1. U1_RTS O Request To Send output for USART1. U1_CTS I Clear To Send input for USART1. U1_SCLK I/O Serial clock input/output for USART1 in synchronous mode. U2_TXD O Transmitter output for USART2. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 296 of 313 A PIO0_14 — General purpose digital input/output pin. [7] R I; PU D PIO0_13 — General purpose digital input/output pin. I/O FT I; PU [7] A I/O - PIO0_17 D D - - FT A 1 20 10 A R 2 PIO0_14 PIO0_16 R D PIO0_13 [2] - F - D 7 [1] A FT FT A A R R D D D 8 11 R R FT FT A A R R D D D PIO0_11 PIO0_15 FT FT FT FT Type Reset Description state A A A A R R D D D Symbol FT FT FT FT FT UM10601 Chapter 26: LPC800 Packages and pin description Table 283. Pin description table (fixed pins) A A A A A NXP Semiconductors D D D D D R R R R R D R R I/O Serial clock for SPI0. SPI0_MOSI I/O Master Out Slave In for SPI0. D R A FT FT A D D R A FT D R A Preliminary user manual R Master Out Slave In for SPI1. D I/O SPI1_MISO I/O Master In Slave Out for SPI1. SPI1_SSEL I/O Slave select for SPI1. CTIN_0 I SCT input 0. CTIN_1 I SCT input 1. CTIN_2 I SCT input 2. CTIN_3 I SCT input 3. CTOUT_0 O SCT output 0. CTOUT_1 O SCT output 1. CTOUT_2 O SCT output 2. CTOUT_3 O SCT output 3. I2C0_SCL I/O I2C-bus clock input/output (open-drain if assigned to pin PIO0_10). High-current sink only if assigned to PIO0_10 and if I2C Fast-mode Plus is selected in the I/O configuration register. I2C0_SDA I/O I2C-bus data input/output (open-drain if assigned to pin PIO0_11). High-current sink only if assigned to pin PIO0_11 and if I2C Fast-mode Plus is selected in the I/O configuration register. ACMP_O O Analog comparator output. CLKOUT O Clock output. Output of the pattern match engine. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 F SPI0_SCK A Serial clock input/output for USART2 in synchronous mode. SPI1_MOSI R Clear To Send input for USART2. I/O R I U2_SCLK D U2_CTS Serial clock for SPI1. FT Request To Send output for USART2. FT O I/O A U2_RTS FT Receiver input for USART2. GPIO_INT_BMAT O UM10601 A I SPI1_SCK R R U2_RXD Master In Slave Out for SPI0. A D D Description Slave select for SPI0. D R FT FT A A R R D D D Type I/O FT FT FT FT Function name I/O A A A A R R D D D Table 284. Movable functions (assign to pins PIO0_0 to PIO_17 through switch matrix) SPI0_SSEL FT FT FT FT FT UM10601 Chapter 26: LPC800 Packages and pin description SPI0_MISO A A A A A NXP Semiconductors © NXP B.V. 2012. All rights reserved. 297 of 313 D D R R A A A A A FT FT FT FT FT D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D Preliminary user manual D Rev. 1.0 — 7 November 2012 R R R Chapter 27: Supplementary information D D D UM10601 D FT FT A A R R D D D 27.1 Abbreviations R A FT Advanced High-performance Bus APB Advanced Peripheral Bus BOD BrownOut Detection GPIO General-Purpose Input/Output PLL Phase-Locked Loop RC Resistor-Capacitor SPI Serial Peripheral Interface SMBus System Management Bus TEM Transverse ElectroMagnetic UART Universal Asynchronous Receiver/Transmitter A Description AHB R Acronym D Table 285. Abbreviations 27.2 References [1] UM10601 Preliminary user manual DDI0484B_cortex_m0p_r0p0_trm — ARM Cortex-M0+ Technical Reference Manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 298 of 313 D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. R D Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 27.3.3 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 299 of 313 A NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. R Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. D Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected D Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. FT Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. A In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. R Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. D 27.3.2 Disclaimers Preliminary user manual FT FT FT FT Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. UM10601 A A A A R R D D D 27.3.1 Definitions FT FT FT FT FT UM10601 Chapter 27: Supplementary information 27.3 Legal information A A A A A NXP Semiconductors D D D D D R R R R R D R R FT Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 300 of 313 A All information provided in this document is subject to legal disclaimers. R Preliminary user manual D UM10601 D Table 25. F Table 24. FT Table 23. FT Table 22. A Table 21. A Table 20. R Table 19. R Table 18. D Table 17. D Table 16. FT Table 15. A Table 14. description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 26. POR captured PIO status register 0 (PIOPORCAP0, address 0x4004 8100) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 27. IOCON glitch filter clock divider registers 6 to 0 (IOCONCLKDIV[6:0], address 0x4004 8134 (IOCONCLKDIV6) to 0x004 814C (IOCONFILTCLKDIV0)) bit description . . . . . . 30 Table 28. BOD control register (BODCTRL, address 0x4004 8150) bit description. . . . . . . . . . . . . . . . . . . . . 30 Table 29. System tick timer calibration register (SYSTCKCAL, address 0x4004 8154) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 30. IRQ latency register (IRQLATENCY, address 0x4004 8170) bit description . . . . . . . . . . . . . . 32 Table 31. NMI source selection register (NMISRC, address 0x4004 8174) bit description . . . . . . . . . . . . . . 32 Table 32. Pin interrupt select registers (PINTSEL[0:7], address 0x4004 8178 (PINTSEL0) to 0x4004 8194 (PINTSEL7)) bit description . . . . . . . . . . 33 Table 33. Start logic 0 pin wake-up enable register 0 (STARTERP0, address 0x4004 8204) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 34. Start logic 1 interrupt wake-up enable register (STARTERP1, address 0x4004 8214) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 35. Deep-sleep configuration register (PDSLEEPCFG, address 0x4004 8230) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 36. Wake-up configuration register (PDAWAKECFG, address 0x4004 8234) bit description . . . . . . 36 Table 37. Power configuration register (PDRUNCFG, address 0x4004 8238) bit description . . . . . . 37 Table 38. Device ID register (DEVICE_ID, address 0x4004 83F4) bit description . . . . . . . . . . . . . . . . . . . . 38 Table 39. PLL frequency parameters. . . . . . . . . . . . . . . . 39 Table 40. PLL configuration examples. . . . . . . . . . . . . . . 40 Table 41. Wake-up sources for reduced power modes . . 43 Table 42. Register overview: PMU (base address 0x4002 0000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 43. Power control register (PCON, address 0x4002 0000) bit description . . . . . . . . . . . . . . . . . . . . 44 Table 44. General purpose registers 0 to 3 (GPREG[0:3], address 0x4002 0004 (GPREG0) to 0x4002 0010 (GPREG3)) bit description . . . . . . . . . . . . . . . 44 Table 45. Deep power down control register (DPDCTRL, address 0x4002 0014) bit description . . . . . . 45 Table 46. Peripheral configuration in reduced power modes 46 Table 47. Pinout summary . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 48. Register overview: I/O configuration (base address 0x4004 4000) . . . . . . . . . . . . . . . . . . . 57 Table 49. PIO0_17 register (PIO0_17, address 0x4004 4000) bit description. . . . . . . . . . . . . . . . . . . . . 57 Table 50. PIO0_13 register (PIO0_13, address 0x4004 4004) bit description . . . . . . . . . . . . . . . . . . . . 59 R Table 13. D Table 12. A FT FT Table 11. R A A Table 10. D R R Table 9. R A D D Table 8. D R FT FT A A R R D D D Table 7. FT FT FT FT Table 6. Ordering information . . . . . . . . . . . . . . . . . . . . .5 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . .5 Connection of interrupt sources to the NVIC . .10 SYSCON pin description . . . . . . . . . . . . . . . . .15 Register overview: System configuration (base address 0x4004 8000) . . . . . . . . . . . . . . . . . .17 System memory remap register (SYSMEMREMAP, address 0x4004 8000) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Peripheral reset control register (PRESETCTRL, address 0x4004 8004) bit description. . . . . . . .19 System PLL control register (SYSPLLCTRL, address 0x4004 8008) bit description . . . . . . .21 System PLL status register (SYSPLLSTAT, address 0x4004 800C) bit description . . . . . . .21 System oscillator control register (SYSOSCCTRL, address 0x4004 8020) bit description. . . . . . . .21 Watchdog oscillator control register (WDTOSCCTRL, address 0x4004 8024) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 System reset status register (SYSRSTSTAT, address 0x4004 8030) bit description. . . . . . . .23 System PLL clock source select register (SYSPLLCLKSEL, address 0x4004 8040) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 System PLL clock source update enable register (SYSPLLCLKUEN, address 0x4004 8044) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Main clock source select register (MAINCLKSEL, address 0x4004 8070) bit description. . . . . . . .24 Main clock source update enable register (MAINCLKUEN, address 0x4004 8074) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 System clock divider register (SYSAHBCLKDIV, address 0x4004 8078) bit description. . . . . . . .25 System clock control register (SYSAHBCLKCTRL, address 0x4004 8080) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .25 USART clock divider register (UARTCLKDIV, address 0x4004 8094) bit description. . . . . . . .27 CLKOUT clock source select register (CLKOUTSEL, address 0x4004 80E0) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 CLKOUT clock source update enable register (CLKOUTUEN, address 0x4004 80E4) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 CLKOUT clock divider registers (CLKOUTDIV, address 0x4004 80E8) bit description . . . . . . .28 USART fractional generator divider value register (UARTFRGDIV, address 0x4004 80F0) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 USART fractional generator multiplier value register (UARTFRGMULT, address 0x4004 80F4) bit description . . . . . . . . . . . . . . . . . . . . . . . . . .29 External trace buffer command register (EXTTRACECMD, address 0x4004 80FC) bit A A A A R R D D D Table 1. Table 2. Table 3. Table 4. Table 5. FT FT FT FT FT UM10601 Chapter 27: Supplementary information 27.4 Tables A A A A A NXP Semiconductors D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D FT FT A A R R D D D R A R A 301 of 313 D © NXP B.V. 2012. All rights reserved. FT Rev. 1.0 — 7 November 2012 D Table 80. Pin interrupt mode register (ISEL, address 0xA000 4000) bit description . . . . . . . . . . . . . 86 Table 81. Pin interrupt level or rising edge interrupt enable register (IENR, address 0xA000 4004) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 82. Pin interrupt level or rising edge interrupt set register (SIENR, address 0xA000 4008) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 83. Pin interrupt level or rising edge interrupt clear register (CIENR, address 0xA000 400C) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 84. Pin interrupt active level or falling edge interrupt enable register (IENF, address 0xA000 4010) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 85. Pin interrupt active level or falling edge interrupt set register (SIENF, address 0xA000 4014) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Table 86. Pin interrupt active level or falling edge interrupt clear register (CIENF, address 0xA000 4018) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Table 87. Pin interrupt rising edge register (RISE, address 0xA000 401C) bit description . . . . . . . . . . . . . 89 Table 88. Pin interrupt falling edge register (FALL, address 0xA000 4020) bit description . . . . . . . . . . . . . 90 Table 89. Pin interrupt status register (IST, address 0xA000 4024) bit description . . . . . . . . . . . . . . . . . . . . 90 Table 90. Pattern match interrupt control register (PMCTRL, address 0x4004 C028) bit description. . . . . . . . . . . . . . . . . . . . . . . . . . 91 Table 91. Pattern match bit-slice source register (PMSRC, address 0x4004 C02C) bit description. . . . . . . . . . . . . . . . . . . . . . . . . . 91 Table 92. Pattern match bit slice configuration register (PMCFG, address 0x4004 C030) bit description 94 Table 93. Pin interrupt registers for edge- and level-sensitive pins . . . . . . . . . . . . . . . . . . . . . 98 Table 94. Movable functions (assign to pins PIO0_0 to PIO_17 through switch matrix). . . . . . . . . . . . 102 Table 95. Register overview: Switch matrix (base address 0x4000 C000) . . . . . . . . . . . . . . . . . . . . . . . 104 Table 96. Pin assign register 0 (PINASSIGN0, address 0x4000 C000) bit description . . . . . . . . . . . . . 105 Table 97. Pin assign register 1 (PINASSIGN1, address 0x4000 C004) bit description . . . . . . . . . . . . . 105 Table 98. Pin assign register 2 (PINASSIGN2, address 0x4000 C008) bit description . . . . . . . . . . . . . 106 Table 99. Pin assign register 3 (PINASSIGN3, address 0x4000 C00C) bit description. . . . . . . . . . . . . 106 Table 100. Pin assign register 4 (PINASSIGN4, address 0x4000 C010) bit description . . . . . . . . . . . . . 106 Table 101. Pin assign register 5 (PINASSIGN5, address 0x4000 C014) bit description . . . . . . . . . . . . . 107 Table 102. Pin assign register 6 (PINASSIGN6, address 0x4000 C018) bit description . . . . . . . . . . . . . 107 Table 103. Pin assign register 7 (PINASSIGN7, address 0x4000 C01C) bit description. . . . . . . . . . . . . 108 Table 104. Pin assign register 8 (PINASSIGN8, address All information provided in this document is subject to legal disclaimers. FT FT FT FT Preliminary user manual A A A A R R D D D UM10601 FT FT FT FT FT UM10601 Chapter 27: Supplementary information Table 51. PIO0_12 register (PIO0_12, address 0x4004 4008) bit description . . . . . . . . . . . . . . . . . . . .60 Table 52. PIO0_5 register (PIO0_5, address 0x4004 400C) bit description . . . . . . . . . . . . . . . . . . . . . . . . .61 Table 53. PIO0_4 register (PIO0_4, address 0x4004 4010) bit description . . . . . . . . . . . . . . . . . . . . . . . . .62 Table 54. PIO0_3 register (PIO0_3, address 0x4004 4014) bit description . . . . . . . . . . . . . . . . . . . . . . . . .63 Table 55. PIO0_2 register (PIO0_2, address 0x4004 4018) bit description . . . . . . . . . . . . . . . . . . . . . . . . .64 Table 56. PIO0_11 register (PIO0_11, address 0x4004 401C) bit description. . . . . . . . . . . . . . . . . . . . .65 Table 57. PIO0_10 register (PIO0_10, address 0x4004 4020) bit description . . . . . . . . . . . . . . . . . . . .66 Table 58. PIO0_16 register (PIO0_16, address 0x4004 4024) bit description . . . . . . . . . . . . . . . . . . . .67 Table 59. PIO0_15 register (PIO0_15, address 0x4004 4028) bit description . . . . . . . . . . . . . . . . . . . .68 Table 60. PIO0_1 register (PIO0_1, address 0x4004 402C) bit description . . . . . . . . . . . . . . . . . . . . . . . . .69 Table 61. PIO0_9 register (PIO0_9, address 0x4004 4034) bit description . . . . . . . . . . . . . . . . . . . . . . . . .70 Table 62. PIO0_8 register (PIO0_8, address 0x4004 4038) bit description . . . . . . . . . . . . . . . . . . . . . . . . .71 Table 63. PIO0_7 register (PIO0_7, address 0x4004 403C) bit description . . . . . . . . . . . . . . . . . . . . . . . . .72 Table 64. PIO0_6 register (PIO0_6, address 0x4004 4040) bit description . . . . . . . . . . . . . . . . . . . . . . . . .73 Table 65. PIO0_0 register (PIO0_0, address 0x4004 4044) bit description . . . . . . . . . . . . . . . . . . . . . . . . .74 Table 66. PIO0_14 register (PIO0_14, address 0x4004 4048) bit description . . . . . . . . . . . . . . . . . . . .75 Table 67. GPIO pins available . . . . . . . . . . . . . . . . . . . . .76 Table 68. Register overview: GPIO port (base address 0xA000 0000) . . . . . . . . . . . . . . . . . . . . . . . . . .77 Table 69. GPIO port 0 byte pin registers (B[0:17], addresses 0xA000 0000 (B0) to 0xA000 0012 (B17)) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 Table 70. GPIO port 0 word pin registers (W[0:17], addresses 0xA000 1000 (W0) to 0x5000 1048 (W17)) bit description . . . . . . . . . . . . . . . . . . . .78 Table 71. GPIO direction port 0 register (DIR0, address 0xA000 2000) bit description . . . . . . . . . . . . . .78 Table 72. GPIO mask port 0 register (MASK0, address 0xA000 2080) bit description . . . . . . . . . . . . . .78 Table 73. GPIO port 0 pin register (PIN0, address 0xA000 2100) bit description . . . . . . . . . . . . . . . . . . . . .79 Table 74. GPIO masked port 0 pin register (MPIN0, address 0xA000 2180) bit description . . . . . . . . . . . . . .79 Table 75. GPIO set port 0 register (SET0, address 0xA000 2200) bit description . . . . . . . . . . . . . . . . . . . . .79 Table 76. GPIO clear port 0 register (CLR0, address 0xA000 2280) bit description . . . . . . . . . . . . . . . . . . . . .80 Table 77. GPIO toggle port 0 register (NOT0, address 0xA000 2300) bit description . . . . . . . . . . . . . .80 Table 78. SCT pin description . . . . . . . . . . . . . . . . . . . . .83 Table 79. Register overview: Pin interrupts/pattern match engine (base address: 0xA000 4000). . . . . . . .86 A A A A A NXP Semiconductors D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D FT FT A A R R D D D R A R A 302 of 313 D © NXP B.V. 2012. All rights reserved. FT Rev. 1.0 — 7 November 2012 D (EV[0:5]_STATE, addresses 0x5000 4300 (EV0_STATE) to 0x5000 4328 (EV5_STATE)) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Table 130. SCT event control register 0 to 5 (EV[0:5]_CTRL, address 0x5000 4304 (EV0_CTRL) to 0x5000 432C (EV5_CTRL)) bit description . . . . . . . . 129 Table 131. SCT output set register (OUT[0:3]_SET, address 0x5000 4500 (OUT0_SET) to 0x5000 4518 (OUT3_SET)) bit description . . . . . . . . . . . . . 131 Table 132. SCT output clear register (OUT[0:3]_CLR, address 0x5000 0504 (OUT0_CLR) to 0x5000 051C (OUT3_CLR)) bit description . . . . . . . . 131 Table 133. Event conditions . . . . . . . . . . . . . . . . . . . . . . 134 Table 134. Register overview: MRT (base address 0x4000 4000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Table 135. Time interval register (INTVAL[0:3], address 0x4000 4000 (INTVAL0) to 0x4000 4030 (INTVAL3)) bit description . . . . . . . . . . . . . . . 142 Table 136. Timer register (TIMER[0:3], address 0x4000 4004 (TIMER0) to 0x4000 4034 (TIMER3)) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Table 137. Control register (CTRL[0:3], address 0x4000 4008 (CTRL0) to 0x4000 4038 (CTRL3)) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Table 138. Status register (STAT[0:3], address 0x4000 400C (STAT0) to 0x4000 403C (STAT3)) bit description 144 Table 139. Idle channel register (IDLE_CH, address 0x4000 40F4) bit description . . . . . . . . . . . . . . . . . . . 144 Table 140. Global interrupt flag register (IRQ_FLAG, address 0x4000 40F8) bit description . . . . . . . . . . . . . 145 Table 141. Register overview: Watchdog timer (base address 0x4000 4000) . . . . . . . . . . . . . . . . . . 150 Table 142. Watchdog mode register (MOD - 0x4000 4000) bit description. . . . . . . . . . . . . . . . . . . . . . . . . 150 Table 143. Watchdog operating modes selection . . . . . . 152 Table 144. Watchdog Timer Constant register (TC - 0x4000 4004) bit description. . . . . . . . . . . . . . . . . . . . 152 Table 145. Watchdog Feed register (FEED - 0x4000 4008) bit description. . . . . . . . . . . . . . . . . . . . . . . . . 153 Table 146. Watchdog Timer Value register (TV - 0x4000 400C) bit description . . . . . . . . . . . . . . . . . . . 153 Table 147. Watchdog Timer Warning Interrupt register (WARNINT - 0x4000 4014) bit description. . . 153 Table 148. Watchdog Timer Window register (WINDOW 0x4000 4018) bit description . . . . . . . . . . . . . 154 Table 149. Analog comparator pin description . . . . . . . . 156 Table 150. Register overview: Analog comparator (base address 0x4002 4000) . . . . . . . . . . . . . . . . . . 158 Table 151. Comparator control register (CTRL, address 0x4002 4000) bit description . . . . . . . . . . . . . 158 Table 152. Voltage ladder register (LAD, address 0x4002 4004) bit description. . . . . . . . . . . . . . . . . . . . 160 Table 153. Register overview: WKT (base address 0x4000 8000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Table 154. Control register (CTRL, address 0x4000 8000) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Table 155. Counter register (COUNT, address 0x4000 800C) All information provided in this document is subject to legal disclaimers. FT FT FT FT Preliminary user manual A A A A R R D D D UM10601 FT FT FT FT FT UM10601 Chapter 27: Supplementary information 0x4000 C020) bit description . . . . . . . . . . . . .108 Table 105. Pin enable register 0 (PINENABLE0, address 0x4000 C1C0) bit description . . . . . . . . . . . . .108 Table 106. SCT pin description . . . . . . . . . . . . . . . . . . . . 112 Table 107. Register overview: State Configurable Timer (base address 0x5000 4000) . . . . . . . . . . . . 115 Table 108. SCT configuration register (CONFIG, address 0x5000 4000) bit description . . . . . . . . . . . . 117 Table 109. SCT control register (CTRL, address 0x5000 4004) bit description . . . . . . . . . . . . . . . . . . . . 118 Table 110. SCT limit register (LIMIT, address 0x5000 4008) bit description . . . . . . . . . . . . . . . . . . . . . . . . .120 Table 111. SCT halt condition register (HALT, address 0x5004 400C) bit description . . . . . . . . . . . .120 Table 112. SCT stop condition register (STOP, address 0x5000 4010) bit description . . . . . . . . . . . .121 Table 113. SCT start condition register (START, address 0x5000 4014) bit description . . . . . . . . . . . .121 Table 114. SCT counter register (COUNT, address 0x5000 4040) bit description . . . . . . . . . . . . . . . . . . . .122 Table 115. SCT state register (STATE, address 0x5000 4044) bit description . . . . . . . . . . . . . . . . . . . .122 Table 116. SCT input register (INPUT, address 0x5000 4048) bit description . . . . . . . . . . . . . . . . . . . .123 Table 117. SCT match/capture registers mode register (REGMODE, address 0x5000 404C) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .124 Table 118. SCT output register (OUTPUT, address 0x5000 4050) bit description . . . . . . . . . . . . . . . . . . . .124 Table 119. SCT bidirectional output control register (OUTPUTDIRCTRL, address 0x5000 4054) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .124 Table 120. SCT conflict resolution register (RES, address 0x5000 4058) bit description . . . . . . . . . . . .125 Table 121. SCT flag enable register (EVEN, address 0x5000 40F0) bit description . . . . . . . . . . . . . . . . . . . .126 Table 122. SCT event flag register (EVFLAG, address 0x5000 40F4) bit description . . . . . . . . . . . . .126 Table 123. SCT conflict enable register (CONEN, address 0x5000 40F8) bit description . . . . . . . . . . . . .126 Table 124. SCT conflict flag register (CONFLAG, address 0x5000 40FC) bit description . . . . . . . . . . . . .127 Table 125. SCT match registers 0 to 4 (MATCH[0:4], address 0x5000 4100 (MATCH0) to 0x5000 4110 (MATCH4)) bit description (REGMODEn bit = 0) . 127 Table 126. SCT capture registers 0 to 4 (CAP[0:4], address 0x5000 4100 (CAP0) to 0x5000 4110 (CAP4)) bit description (REGMODEn bit = 1) . . . . . . . . . .128 Table 127. SCT match reload registers 0 to 4 (MATCHREL[0:4], address 0x5000 4200 (MATCHREL0) to 0x5000 4210 (MATCHREL4) bit description (REGMODEn bit = 0) . . . . . . . . . .128 Table 128. SCT capture control registers 0 to 4 (CAPCTRL[0:4], address 0x5000 4200 (CAPCTRL0) to 0x5000 4210 (CAPCTRL4)) bit description (REGMODEn bit = 1) . . . . . . . . . .128 Table 129. SCT event state mask registers 0 to 5 A A A A A NXP Semiconductors D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D FT FT A A R R D D D R A R A 303 of 313 D © NXP B.V. 2012. All rights reserved. FT Rev. 1.0 — 7 November 2012 D 0010) bit description. . . . . . . . . . . . . . . . . . . . 196 Table 177. I2C Clock Divider register (DIV, address 0x4005 0014) bit description. . . . . . . . . . . . . . . . . . . . 196 Table 178. I2C Interrupt Status register (INTSTAT, address 0x4005 0018) bit description . . . . . . . . . . . . . 197 Table 179. Master Control register (MSTCTL, address 0x4005 0020) bit description . . . . . . . . . . . . . 197 Table 180. Master Time register (MSTTIME, address 0x4005 0024) bit description . . . . . . . . . . . . . . . . . . . 198 Table 181. Master Data register (MSTDAT, address 0x4005 0028) bit description. . . . . . . . . . . . . . . . . . . . 199 Table 182. Slave Control register (SLVCTL, address 0x4005 0040) bit description. . . . . . . . . . . . . . . . . . . . 200 Table 183. Slave Data register (SLVDAT, address 0x4005 0044) bit description. . . . . . . . . . . . . . . . . . . . 200 Table 184. Slave Address registers (SLVADR[0:3]- address 0x4005 0048 (SLVADR0) to 0x4005 0054 (SLVADR3)) bit description . . . . . . . . . . . . . . 201 Table 185. Slave address Qualifier 0 register (SLVQUAL0, address 0x4005 0058) bit description . . . . . . 202 Table 186. Monitor data register (MONRXDAT, address 0x4005 0080) bit description . . . . . . . . . . . . . 202 Table 187: SPI Pin Description . . . . . . . . . . . . . . . . . . . . 208 Table 188. Register overview: SPI (base address 0x4005 8000 (SPI0) and 0x4008 C000 (SPI1)) . . . . . 209 Table 189. SPI Configuration register (CFG, addresses 0x4005 8000 (SPI0) , 0x4005 C000 (SPI1)) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Table 190. SPI Delay register (DLY, addresses 0x4005 8004 (SPI0) , 0x4005 C004 (SPI1)) bit description. 212 Table 191. SPI Status register (STAT, addresses 0x4005 8008 (SPI0) , 0x4005 C008 (SPI1)) bit description 213 Table 192. SPI Interrupt Enable read and Set register (INTENSET, addresses 0x4005 800C (SPI0) , 0x4005 C00C (SPI1)) bit description . . . . . . . 214 Table 193. SPI Interrupt Enable clear register (INTENCLR, addresses 0x4005 8010 (SPI0) , 0x4005 C010 (SPI1)) bit description . . . . . . . . . . . . . . . . . . 215 Table 194. SPI Receiver Data register (RXDAT, addresses 0x4005 8014 (SPI0) , 0x4005 C014 (SPI1)) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Table 195. SPI Transmitter Data and Control register (TXDATCTL, addresses 0x4005 8018 (SPI0) , 0x4005 C018 (SPI1)) bit description . . . . . . . 216 Table 196. SPI Transmitter Data Register (TXDAT, addresses 0x4005 801ST (SPI0) , 0x4005 C00C (SPI1)) bit description . . . . . . . . . . . . . . . . . . 217 Table 197. SPI Transmitter Control register (TXCTL, addresses 0x4005 8020 (SPI0) , 0x4005 C020 (SPI1)) bit description . . . . . . . . . . . . . . . . . . 218 Table 198. SPI Divider register (DIV, addresses 0x4005 8024 (SPI0) , 0x4005 C024(SPI1)) bit description . 218 Table 199. SPI Interrupt Status register (INTSTAT, addresses 0x4005 8028 (SPI0) , 0x4005 C028 (SPI1)) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 Table 200: SPI mode summary. . . . . . . . . . . . . . . . . . . . 220 Table 201. Register overview: CRC engine (base address All information provided in this document is subject to legal disclaimers. FT FT FT FT Preliminary user manual A A A A R R D D D UM10601 FT FT FT FT FT UM10601 Chapter 27: Supplementary information bit description . . . . . . . . . . . . . . . . . . . . . . . . .163 Table 156. USART pin description. . . . . . . . . . . . . . . . . .167 Table 157: Register overview: USART (base address 0x4006 4000 (USART0), 0x4006 8000 (USART1), 0x4006 C000 (USART2)) . . . . . . . . . . . . . . . .170 Table 158. USART Configuration register (CFG, address 0x4006 4000 (USART0), 0x4006 8000 (USART1), 0x4006 C000 (USART2)) bit description . . .171 Table 159. USART Control register (CTRL, address 0x4006 4004 (USART0), 0x4006 8004 (USART1), 0x4006 C004 (USART2)) bit description . . . . . . . . . . .173 Table 160. USART Status register (STAT, address 0x4006 4008 (USART0), 0x4006 8008 (USART1), 0x4006 C008(USART2)) bit description . . . . . . . . . . .174 Table 161. USART Interrupt Enable read and set register (INTENSET, address 0x4006 400C(USART0), 0x4006 800C (USART1), 0x4006 C00C(USART2)) bit description . . . . . . . . . .175 Table 162. USART Interrupt Enable clear register (INTENCLR, address 0x4006 4010(USART0), 0x4006 8010 (USART1), 0x4006 C010(USART2)) bit description . . . . . . . . . . . . . . . . . . . . . . . .176 Table 163. USART Receiver Data register (RXDATA, address 0x4006 4014 (USART0), 0x4006 8014 (USART1), 0x4006 C014 (USART2)) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .177 Table 164. USART Receiver Data with Status register (RXDATASTAT, address 0x4006 4018 (USART0), 0x4006 8018 (USART1), 0x4006 C018 (USART2)) bit description. . . . . . . . . . . . . . . .177 Table 165. USART Transmitter Data Register (TXDATA, address 0x4006 401C (USART0), 0x4006 801C (USART1), 0x4006 C01C (USART2)) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .178 Table 166. USART Baud Rate Generator register (BRG, address 0x4006 4020 (USART0), 0x4006 8020 (USART1), 0x4006 C020 (USART2)) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .179 Table 167. USART Interrupt Status register (INTSTAT, address 0x4006 4024 (USART0), 0x4006 8024 (USART1), 0x4006 C024(USART2)) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .179 Table 168. I2C-bus pin description . . . . . . . . . . . . . . . . .184 Table 169: Register overview: I2C (base address 0x4005 0000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187 Table 170. I2C Configuration register (CFG, address 0x4005 0000) bit description . . . . . . . . . . . . . . . . . . . .187 Table 171. I2C Status register (STAT, address 0x4005 0004) bit description . . . . . . . . . . . . . . . . . . . . . . . .189 Table 172: Master function state codes (MSTSTATE) . . .192 Table 173: Slave function state codes (SLVSTATE) . . . .192 Table 174. Interrupt Enable Set and read register (INTENSET, address 0x4005 0008) bit description 193 Table 175. Interrupt Enable Clear register (INTENCLR, address 0x4005 000C) bit description . . . . . . . . . . . . . . . . . . . . . . . . . .194 Table 176. time-out register (TIMEOUT, address 0x4005 A A A A A NXP Semiconductors D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D FT FT A A R R D D D R A R A 304 of 313 D © NXP B.V. 2012. All rights reserved. FT Rev. 1.0 — 7 November 2012 D Table 244. IAP Erase page command . . . . . . . . . . . . . . 256 Table 245. IAP Status Codes Summary . . . . . . . . . . . . . 256 Table 246. Memory mapping in debug mode . . . . . . . . . 258 Table 247. Power profile API calls . . . . . . . . . . . . . . . . . 261 Table 248. set_pll routine . . . . . . . . . . . . . . . . . . . . . . . . 261 Table 249. set_power routine . . . . . . . . . . . . . . . . . . . . . 264 Table 250. I2C API calls . . . . . . . . . . . . . . . . . . . . . . . . . 269 Table 251. ISR handler . . . . . . . . . . . . . . . . . . . . . . . . . . 271 Table 252. I2C Master Transmit Polling . . . . . . . . . . . . . 271 Table 253. I2C Master Receive Polling . . . . . . . . . . . . . 271 Table 254. I2C Master Transmit and Receive Polling . . . 272 Table 255. I2C Master Transmit Interrupt . . . . . . . . . . . . 272 Table 256. I2C Master Receive Interrupt . . . . . . . . . . . . 272 Table 257. I2C Master Transmit Receive Interrupt . . . . . 273 Table 258. I2C Slave Receive Polling. . . . . . . . . . . . . . . 273 Table 259. I2C Slave Transmit Polling . . . . . . . . . . . . . . 273 Table 260. I2C Slave Receive Interrupt . . . . . . . . . . . . . 274 Table 261. I2C Slave Transmit Interrupt . . . . . . . . . . . . . 274 Table 262. I2C Set Slave Address . . . . . . . . . . . . . . . . . 274 Table 263. I2C Get Memory Size . . . . . . . . . . . . . . . . . . 274 Table 264. I2C Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 Table 265. I2C Set Bit Rate . . . . . . . . . . . . . . . . . . . . . . 275 Table 266. I2C Get Firmware Version. . . . . . . . . . . . . . . 275 Table 267. I2C Get Status . . . . . . . . . . . . . . . . . . . . . . . 275 Table 268. I2C time-out value . . . . . . . . . . . . . . . . . . . . . 276 Table 269. Error codes . . . . . . . . . . . . . . . . . . . . . . . . . . 276 Table 270. I2C Status code. . . . . . . . . . . . . . . . . . . . . . . 276 Table 271. UART API calls . . . . . . . . . . . . . . . . . . . . . . . 285 Table 272. uart_get_mem_size. . . . . . . . . . . . . . . . . . . . 285 Table 273. uart_setup . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 Table 274. uart_init . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 Table 275. uart_get_char . . . . . . . . . . . . . . . . . . . . . . . . 286 Table 276. uart_put_char . . . . . . . . . . . . . . . . . . . . . . . . 286 Table 277. uart_get_line . . . . . . . . . . . . . . . . . . . . . . . . . 287 Table 278. uart_put_line . . . . . . . . . . . . . . . . . . . . . . . . . 287 Table 279. uart_isr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 Table 280. Error codes . . . . . . . . . . . . . . . . . . . . . . . . . . 287 Table 281. SWD pin description . . . . . . . . . . . . . . . . . . . 290 Table 282. JTAG boundary scan pin description. . . . . . . 291 Table 283. Pin description table (fixed pins) . . . . . . . . . . 295 Table 284. Movable functions (assign to pins PIO0_0 to PIO_17 through switch matrix). . . . . . . . . . . . 296 Table 285. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . 298 All information provided in this document is subject to legal disclaimers. FT FT FT FT Preliminary user manual A A A A R R D D D UM10601 FT FT FT FT FT UM10601 Chapter 27: Supplementary information 0x5000 0000) . . . . . . . . . . . . . . . . . . . . . . . . .228 Table 202. CRC mode register (MODE, address 0x5000 0000) bit description . . . . . . . . . . . . . . . . . . . .229 Table 203. CRC seed register (SEED, address 0x5000 0004) bit description . . . . . . . . . . . . . . . . . . . .229 Table 204. CRC checksum register (SUM, address 0x5000 0008) bit description . . . . . . . . . . . . . . . . . . . .229 Table 205. CRC data register (WR_DATA, address 0x5000 0008) bit description . . . . . . . . . . . . . . . . . . . .230 Table 206. Register overview: FMC (base address 0x4004 0000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232 Table 207. Flash configuration register (FLASHCFG, address 0x4003 C010) bit description . . . . . .233 Table 208. Flash Module Signature Start register (FMSSTART - 0x4003 C020) bit description .233 Table 209. Flash Module Signature Stop register (FMSSTOP - 0x4003 C024) bit description . . . . . . . . . . . .233 Table 210. FMSW0 register bit description (FMSW0, address: 0x4003 C02C) . . . . . . . . . . . . . . . . .234 Table 211. API calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237 Table 212. LPC800 flash configurations . . . . . . . . . . . . .240 Table 213. LPC800 flash configuration . . . . . . . . . . . . . .240 Table 214. Code Read Protection options . . . . . . . . . . . .242 Table 215. Code Read Protection hardware/software interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . .242 Table 216. ISP commands allowed for different CRP levels . 243 Table 217. UART ISP command summary . . . . . . . . . . .244 Table 218. UART ISP Unlock command . . . . . . . . . . . . .244 Table 219. UART ISP Set Baud Rate command . . . . . . .244 Table 220. UART ISP Echo command . . . . . . . . . . . . . .245 Table 221. UART ISP Write to RAM command . . . . . . . .245 Table 222. UART ISP Read Memory command . . . . . . .246 Table 223. UART ISP Prepare sector(s) for write operation command . . . . . . . . . . . . . . . . . . . . . . . . . . . .246 Table 224. UART ISP Copy RAM to flash command. . . .247 Table 225. UART ISP Go command . . . . . . . . . . . . . . . .247 Table 226. UART ISP Erase sector command . . . . . . . .248 Table 227. UART ISP Blank check sector command . . .248 Table 228. UART ISP Read Part Identification command248 Table 229. Part identification numbers . . . . . . . . . . . . . .249 Table 230. UART ISP Read Boot Code version number command . . . . . . . . . . . . . . . . . . . . . . . . . . . .249 Table 231. UART ISP Compare command . . . . . . . . . . .249 Table 232. UART ISP ReadUID command . . . . . . . . . . .249 Table 233. UART ISP Return Codes Summary. . . . . . . .250 Table 234. IAP Command Summary . . . . . . . . . . . . . . . .252 Table 235. IAP Prepare sector(s) for write operation command . . . . . . . . . . . . . . . . . . . . . . . . . . . .252 Table 236. IAP Copy RAM to flash command . . . . . . . . .253 Table 237. IAP Erase Sector(s) command . . . . . . . . . . .254 Table 238. IAP Blank check sector(s) command . . . . . . .254 Table 239. IAP Read Part Identification command . . . . .254 Table 240. IAP Read Boot Code version number command . 255 Table 241. IAP Compare command. . . . . . . . . . . . . . . . .255 Table 242. IAP Reinvoke ISP . . . . . . . . . . . . . . . . . . . . .256 Table 243. IAP ReadUID command. . . . . . . . . . . . . . . . .256 A A A A A NXP Semiconductors D D D D D R R R R R D R R FT F D R A FT FT D D R A FT D R A Rev. 1.0 — 7 November 2012 A All information provided in this document is subject to legal disclaimers. R Preliminary user manual D UM10601 A FT FT Fig 47. R A A Fig 45. Fig 46. D R R Fig 44. R A D D Fig 19. Fig 20. Fig 21. Fig 22. Fig 23. Fig 24. Fig 25. Fig 26. Fig 27. Fig 28. Fig 29. Fig 30. Fig 31. Fig 32. Fig 33. Fig 34. Fig 35. Fig 36. Fig 37. Fig 38. Fig 39. Fig 40. Fig 41. Fig 42. Fig 43. D R FT FT A A R R D D D Fig 18. FT FT FT FT Fig 8. Fig 9. Fig 10. Fig 11. Fig 12. Fig 13. Fig 14. Fig 15. Fig 16. Fig 17. LPC800 block diagram . . . . . . . . . . . . . . . . . . . . .6 LPC800 Memory mapping . . . . . . . . . . . . . . . . . . .9 LPC800 clock generation. . . . . . . . . . . . . . . . . . .16 System PLL block diagram . . . . . . . . . . . . . . . . .38 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . .54 Pattern match bit slice . . . . . . . . . . . . . . . . . . . . .85 Example: Connect function U0_RXD and U0_TXD to pins 8 and 14 on the SO20 package . . . . . . .101 SCT block diagram . . . . . . . . . . . . . . . . . . . . . . 113 SCT counter and select logic . . . . . . . . . . . . . . . 114 Match logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 Capture logic . . . . . . . . . . . . . . . . . . . . . . . . . . .132 Event selection . . . . . . . . . . . . . . . . . . . . . . . . .133 Output slice i . . . . . . . . . . . . . . . . . . . . . . . . . . .133 SCT interrupt generation . . . . . . . . . . . . . . . . . .133 MRT block diagram . . . . . . . . . . . . . . . . . . . . . .140 Windowed Watchdog timer block diagram. . . . .148 Early watchdog feed with windowed mode enabled 154 Correct watchdog feed with windowed mode enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154 Watchdog warning interrupt . . . . . . . . . . . . . . . .154 Comparator block diagram. . . . . . . . . . . . . . . . .157 USART clocking. . . . . . . . . . . . . . . . . . . . . . . . .166 USART block diagram . . . . . . . . . . . . . . . . . . . .169 Hardware flow control using RTS and CTS . . . .182 I2C clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . .183 I2C block diagram . . . . . . . . . . . . . . . . . . . . . . .185 SPI clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . .206 SPI block diagram . . . . . . . . . . . . . . . . . . . . . . .209 Basic SPI operating modes . . . . . . . . . . . . . . . .220 Pre_delay and Post_delay . . . . . . . . . . . . . . . . .221 Frame_delay . . . . . . . . . . . . . . . . . . . . . . . . . . .222 Transfer_delay . . . . . . . . . . . . . . . . . . . . . . . . . .223 Examples of data stalls . . . . . . . . . . . . . . . . . . .226 CRC block diagram . . . . . . . . . . . . . . . . . . . . . .228 Boot ROM structure . . . . . . . . . . . . . . . . . . . . . .237 Boot process flowchart . . . . . . . . . . . . . . . . . . .239 IAP parameter passing . . . . . . . . . . . . . . . . . . .252 Power profiles pointer structure . . . . . . . . . . . . .260 LPC800 clock configuration for power API use .260 Power profiles usage . . . . . . . . . . . . . . . . . . . . .264 I2C-bus driver routines pointer structure . . . . . .269 I2C slave mode set-up address packing . . . . . .279 USART driver routines pointer structure . . . . . .284 Connecting the SWD pins to a standard SWD connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292 Pin configuration DIP8 package (LPC810M021FN8) 293 Pin configuration TSSOP16 package . . . . . . . .293 Pin configuration SO20 package (LPC812M101FD20) . . . . . . . . . . . . . . . . . . . . .293 Pin configuration TSSOP20 package . . . . . . . .294 A A A A R R D D D Fig 1. Fig 2. Fig 3. Fig 4. Fig 5. Fig 6. Fig 7. FT FT FT FT FT UM10601 Chapter 27: Supplementary information 27.5 Figures A A A A A NXP Semiconductors © NXP B.V. 2012. All rights reserved. 305 of 313 D D D D D R R R R R A A A A A D R R FT FT FT FT D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D Chapter 1: LPC800 Introductory information A A A A R R D D D Chapter 27: Supplementary information 27.6 Contents FT FT FT UM10601 FT FT NXP Semiconductors Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 6 General description . . . . . . . . . . . . . . . . . . . . . 7 ARM Cortex-M0+ core configuration . . . . . . . . 7 2.2.1 2.2.2 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . 9 Micro Trace Buffer (MTB). . . . . . . . . . . . . . . . . 9 D 1.4 1.5 1.5.1 R A FT D R Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 5 D 1.1 1.2 1.3 A Chapter 2: LPC800 Memory mapping 2.1 2.2 How to read this chapter . . . . . . . . . . . . . . . . . . 8 General description . . . . . . . . . . . . . . . . . . . . . . 8 Chapter 3: LPC800 Nested Vectored Interrupt Controller (NVIC) 3.1 3.2 How to read this chapter . . . . . . . . . . . . . . . . . 10 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.3 3.3.1 General description . . . . . . . . . . . . . . . . . . . . 10 Interrupt sources . . . . . . . . . . . . . . . . . . . . . . 10 Chapter 4: LPC800 System configuration (SYSCON) 4.1 4.2 4.3 4.3.1 4.3.2 4.3.3 4.4 4.5 4.5.1 4.5.2 4.5.3 4.5.4 4.6 4.6.1 4.6.2 4.6.3 4.6.4 4.6.5 4.6.6 4.6.7 4.6.8 4.6.9 4.6.10 4.6.11 4.6.12 4.6.13 4.6.14 4.6.15 4.6.16 How to read this chapter . . . . . . . . . . . . . . . . . 13 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Basic configuration . . . . . . . . . . . . . . . . . . . . . 13 Set up the PLL . . . . . . . . . . . . . . . . . . . . . . . . 13 Configure the main clock and system clock . . 14 Set up the system oscillator using XTALIN and XTALOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 15 General description . . . . . . . . . . . . . . . . . . . . . 15 Clock generation. . . . . . . . . . . . . . . . . . . . . . . 15 Power control of analog components . . . . . . . 16 Configuration of reduced power-modes . . . . . 17 Reset and interrupt control . . . . . . . . . . . . . . . 17 Register description . . . . . . . . . . . . . . . . . . . . 17 System memory remap register . . . . . . . . . . . 19 Peripheral reset control register . . . . . . . . . . . 19 System PLL control register . . . . . . . . . . . . . . 20 System PLL status register. . . . . . . . . . . . . . . 21 System oscillator control register . . . . . . . . . . 21 Watchdog oscillator control register . . . . . . . . 22 System reset status register . . . . . . . . . . . . . . 23 System PLL clock source select register . . . . 23 System PLL clock source update register . . . 24 Main clock source select register . . . . . . . . . . 24 Main clock source update enable register . . . 24 System clock divider register . . . . . . . . . . . . . 25 System clock control register . . . . . . . . . . . . . 25 USART clock divider register . . . . . . . . . . . . . 27 CLKOUT clock source select register. . . . . . . 27 CLKOUT clock source update enable register 27 4.6.17 4.6.18 CLKOUT clock divider register. . . . . . . . . . . . 28 USART fractional generator divider value register 28 4.6.19 USART fractional generator multiplier value register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.6.20 External trace buffer command register . . . . 29 4.6.21 POR captured PIO status register 0 . . . . . . . 30 4.6.22 IOCON glitch filter clock divider registers 6 to 0 . 30 4.6.23 BOD control register . . . . . . . . . . . . . . . . . . . 30 4.6.24 System tick counter calibration register . . . . . 31 4.6.25 IRQ latency register . . . . . . . . . . . . . . . . . . . . 31 4.6.26 NMI source selection register . . . . . . . . . . . . 32 4.6.27 Pin interrupt select registers . . . . . . . . . . . . . 32 4.6.28 Start logic 0 pin wake-up enable register . . . 33 4.6.29 Start logic 1 interrupt wake-up enable register 34 4.6.30 Deep-sleep mode configuration register . . . . 35 4.6.31 Wake-up configuration register . . . . . . . . . . . 35 4.6.32 Power configuration register . . . . . . . . . . . . . 36 4.6.33 Device ID register . . . . . . . . . . . . . . . . . . . . . 37 4.7 Functional description . . . . . . . . . . . . . . . . . . 38 4.7.1 System PLL functional description. . . . . . . . . 38 4.7.1.1 Lock detector . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.7.1.2 Power-down control . . . . . . . . . . . . . . . . . . . . 39 4.7.1.3 Divider ratio programming . . . . . . . . . . . . . . . 39 4.7.1.3.1 Post divider . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.7.1.3.2 Feedback divider . . . . . . . . . . . . . . . . . . . . . . 39 4.7.1.3.3 Changing the divider values. . . . . . . . . . . . . . 39 4.7.1.4 Frequency selection. . . . . . . . . . . . . . . . . . . . 39 4.7.1.4.1 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.7.1.4.2 Power-down mode . . . . . . . . . . . . . . . . . . . . . 40 Chapter 5: LPC800 Reduced power modes and Power Management Unit (PMU) 5.1 5.2 5.3 5.4 How to read this chapter . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Basic configuration . . . . . . . . . . . . . . . . . . . . . Pin description . . . . . . . . . . . . . . . . . . . . . . . . . UM10601 Preliminary user manual 41 41 41 41 5.5 5.5.1 5.6 5.6.1 General description . . . . . . . . . . . . . . . . . . . . Wake-up process . . . . . . . . . . . . . . . . . . . . . . Register description . . . . . . . . . . . . . . . . . . . . Power control register . . . . . . . . . . . . . . . . . . All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 41 42 43 44 © NXP B.V. 2012. All rights reserved. 306 of 313 D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D 53 53 53 54 54 54 54 55 55 55 55 57 57 59 60 6.5.4 6.5.5 6.5.6 6.5.7 6.5.8 6.5.9 6.5.10 6.5.11 6.5.12 6.5.13 6.5.14 6.5.15 6.5.16 6.5.17 6.5.18 PIO0_5 register . . . . . . . . . . . . . . . . . . . . . . . PIO0_4 register . . . . . . . . . . . . . . . . . . . . . . . PIO0_3 register . . . . . . . . . . . . . . . . . . . . . . . PIO0_2 register . . . . . . . . . . . . . . . . . . . . . . . PIO0_11 register . . . . . . . . . . . . . . . . . . . . . . PIO0_10 register . . . . . . . . . . . . . . . . . . . . . . PIO0_16 register . . . . . . . . . . . . . . . . . . . . . . PIO0_15 register . . . . . . . . . . . . . . . . . . . . . . PIO0_1 register . . . . . . . . . . . . . . . . . . . . . . . PIO0_9 register . . . . . . . . . . . . . . . . . . . . . . . PIO0_8 register . . . . . . . . . . . . . . . . . . . . . . . PIO0_7 register . . . . . . . . . . . . . . . . . . . . . . . PIO0_6 register . . . . . . . . . . . . . . . . . . . . . . . PIO0_0 register . . . . . . . . . . . . . . . . . . . . . . . PIO0_14 register . . . . . . . . . . . . . . . . . . . . . . 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 76 76 76 76 77 77 77 78 78 7.6.5 7.6.6 7.6.7 7.6.8 7.6.9 7.7 7.7.1 7.7.2 7.7.3 7.7.4 GPIO port pin registers . . . . . . . . . . . . . . . . . GPIO masked port pin registers. . . . . . . . . . . GPIO port set registers . . . . . . . . . . . . . . . . . GPIO port clear registers . . . . . . . . . . . . . . . . GPIO port toggle registers . . . . . . . . . . . . . . . Functional description . . . . . . . . . . . . . . . . . . Reading pin state . . . . . . . . . . . . . . . . . . . . . . GPIO output . . . . . . . . . . . . . . . . . . . . . . . . . . Masked I/O. . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended practices . . . . . . . . . . . . . . . . 78 79 79 79 80 80 80 80 81 81 D A © NXP B.V. 2012. All rights reserved. 307 of 313 A Rev. 1.0 — 7 November 2012 R All information provided in this document is subject to legal disclaimers. D 8.5.2.1 Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 8.6 Register description . . . . . . . . . . . . . . . . . . . . 86 8.6.1 Pin interrupt mode register. . . . . . . . . . . . . . . 86 8.6.2 Pin interrupt level or rising edge interrupt enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 8.6.3 Pin interrupt level or rising edge interrupt set register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 8.6.4 Pin interrupt level or rising edge interrupt clear register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 FT Preliminary user manual F R UM10601 A D 8.4 8.5 8.5.1 8.5.2 How to read this chapter . . . . . . . . . . . . . . . . . 82 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Basic configuration . . . . . . . . . . . . . . . . . . . . . 82 Configure pins as pin interrupts or as inputs to the pattern match engine . . . . . . . . . . . . . . . . . . . 83 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 83 General description . . . . . . . . . . . . . . . . . . . . . 83 Pin interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . 84 Pattern match engine . . . . . . . . . . . . . . . . . . . 84 FT FT Chapter 8: LPC800 Pin interrupts/pattern match engine 8.1 8.2 8.3 8.3.1 A A How to read this chapter . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Basic configuration . . . . . . . . . . . . . . . . . . . . . Pin description . . . . . . . . . . . . . . . . . . . . . . . . . General description . . . . . . . . . . . . . . . . . . . . . Register description . . . . . . . . . . . . . . . . . . . . GPIO port byte pin registers . . . . . . . . . . . . . . GPIO port word pin registers . . . . . . . . . . . . . GPIO port direction registers . . . . . . . . . . . . . GPIO port mask registers . . . . . . . . . . . . . . . . R R Chapter 7: LPC800 GPIO port 7.1 7.2 7.3 7.4 7.5 7.6 7.6.1 7.6.2 7.6.3 7.6.4 R D D How to read this chapter . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Basic configuration . . . . . . . . . . . . . . . . . . . . . General description . . . . . . . . . . . . . . . . . . . . . Pin configuration . . . . . . . . . . . . . . . . . . . . . . . Pin function. . . . . . . . . . . . . . . . . . . . . . . . . . . Pin mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . Open-drain mode . . . . . . . . . . . . . . . . . . . . . . Analog mode . . . . . . . . . . . . . . . . . . . . . . . . . I2C-bus mode . . . . . . . . . . . . . . . . . . . . . . . . . Programmable glitch filter . . . . . . . . . . . . . . . . Register description . . . . . . . . . . . . . . . . . . . . PIO0_17 register . . . . . . . . . . . . . . . . . . . . . . PIO0_13 register . . . . . . . . . . . . . . . . . . . . . . PIO0_12 register . . . . . . . . . . . . . . . . . . . . . . D FT FT A A R R D D 5.7.7.2 5.7.7.3 Power configuration in Deep-sleep mode . . . 48 Programming Deep-sleep mode . . . . . . . . . . 49 Wake-up from Deep-sleep mode . . . . . . . . . . 49 Power-down mode . . . . . . . . . . . . . . . . . . . . . 49 Power configuration in Power-down mode . . 50 Programming Power-down mode . . . . . . . . . 50 Wake-up from Power-down mode . . . . . . . . . 50 Deep power-down mode . . . . . . . . . . . . . . . . 51 Power configuration in Deep power-down mode . 51 Programming Deep power-down mode . . . . . 51 Wake-up from Deep power-down mode . . . . 51 Chapter 6: LPC800 I/O configuration (IOCON) 6.1 6.2 6.3 6.4 6.4.1 6.4.2 6.4.3 6.4.4 6.4.5 6.4.6 6.4.7 6.5 6.5.1 6.5.2 6.5.3 FT FT FT FT 5.7.5.1 5.7.5.2 5.7.5.3 5.7.6 5.7.6.1 5.7.6.2 5.7.6.3 5.7.7 5.7.7.1 A A A A R R D D D 5.7.3 5.7.3.1 5.7.4 5.7.4.1 5.7.4.2 5.7.4.3 5.7.5 General purpose registers 0 to 3 . . . . . . . . . . 44 Deep power-down control register . . . . . . . . . 45 Functional description . . . . . . . . . . . . . . . . . . 46 Power management . . . . . . . . . . . . . . . . . . . . 46 Reduced power modes and WWDT lock features 47 Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Power configuration in Active mode . . . . . . . . 47 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Power configuration in Sleep mode . . . . . . . . 48 Programming Sleep mode . . . . . . . . . . . . . . . 48 Wake-up from Sleep mode . . . . . . . . . . . . . . . 48 Deep-sleep mode . . . . . . . . . . . . . . . . . . . . . . 48 FT FT FT FT FT UM10601 Chapter 27: Supplementary information 5.6.2 5.6.3 5.7 5.7.1 5.7.2 A A A A A NXP Semiconductors D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D D FT R A FT D R A Preliminary user manual D D UM10601 FT A How to read this chapter . . . . . . . . . . . . . . . . 139 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Basic configuration . . . . . . . . . . . . . . . . . . . . 139 A R Pin assign register 0 Pin assign register 1 Pin assign register 2 Pin assign register 3 Pin assign register 4 Pin assign register 5 Pin assign register 6 Pin assign register 7 Pin assign register 8 Pin enable register 0 .................. .................. .................. .................. .................. .................. .................. .................. .................. .................. 105 105 106 106 106 107 107 108 108 108 10.6.19 SCT capture registers 0 to 4 (REGMODEn bit = 1) 127 10.6.20 SCT match reload registers 0 to 4 (REGMODEn bit = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 10.6.21 SCT capture control registers 0 to 4 (REGMODEn bit = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 10.6.22 SCT event state mask registers 0 to 5 . . . . . 129 10.6.23 SCT event control registers 0 to 5 . . . . . . . . 129 10.6.24 SCT output set registers 0 to 3 . . . . . . . . . . 131 10.6.25 SCT output clear registers 0 to 3 . . . . . . . . . 131 10.7 Functional description . . . . . . . . . . . . . . . . . 132 10.7.1 Match logic. . . . . . . . . . . . . . . . . . . . . . . . . . 132 10.7.2 Capture logic . . . . . . . . . . . . . . . . . . . . . . . . 132 10.7.3 Event selection. . . . . . . . . . . . . . . . . . . . . . . 132 10.7.4 Output generation . . . . . . . . . . . . . . . . . . . . 133 10.7.5 Interrupt generation . . . . . . . . . . . . . . . . . . . 133 10.7.6 Clearing the prescaler . . . . . . . . . . . . . . . . . 134 10.7.7 Match vs. I/O events . . . . . . . . . . . . . . . . . . 134 10.7.8 SCT operation . . . . . . . . . . . . . . . . . . . . . . . 135 10.7.9 Configure the SCT . . . . . . . . . . . . . . . . . . . 135 10.7.9.1 Configure the counter . . . . . . . . . . . . . . . . . 135 10.7.9.2 Configure the match and capture registers . 135 10.7.9.3 Configure events and event responses . . . . 136 10.7.9.4 Configure multiple states . . . . . . . . . . . . . . . 137 10.7.9.5 Miscellaneous options . . . . . . . . . . . . . . . . . 137 10.7.10 Run the SCT . . . . . . . . . . . . . . . . . . . . . . . . 137 10.7.11 Configure the SCT without using states. . . . 138 Chapter 11: LPC800 Multi-Rate Timer (MRT) 11.1 11.2 11.3 R D How to read this chapter . . . . . . . . . . . . . . . . 111 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Basic configuration . . . . . . . . . . . . . . . . . . . . 111 Use the SCT as a simple timer . . . . . . . . . . . 111 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 112 General description . . . . . . . . . . . . . . . . . . . . 112 Register description . . . . . . . . . . . . . . . . . . . 114 SCT configuration register . . . . . . . . . . . . . . 117 SCT control register . . . . . . . . . . . . . . . . . . . 118 SCT limit register . . . . . . . . . . . . . . . . . . . . . 119 SCT halt condition register . . . . . . . . . . . . . . 120 SCT stop condition register . . . . . . . . . . . . . 120 SCT start condition register . . . . . . . . . . . . . 121 SCT counter register . . . . . . . . . . . . . . . . . . 121 SCT state register. . . . . . . . . . . . . . . . . . . . . 122 SCT input register. . . . . . . . . . . . . . . . . . . . . 123 SCT match/capture registers mode register . 123 SCT output register . . . . . . . . . . . . . . . . . . . 124 SCT bidirectional output control register. . . . 124 SCT conflict resolution register. . . . . . . . . . . 125 SCT flag enable register . . . . . . . . . . . . . . . . 126 SCT event flag register . . . . . . . . . . . . . . . . . 126 SCT conflict enable register . . . . . . . . . . . . . 126 SCT conflict flag register . . . . . . . . . . . . . . . 126 SCT match registers 0 to 4 (REGMODEn bit = 0) 127 F FT FT 9.5.1 9.5.2 9.5.3 9.5.4 9.5.5 9.5.6 9.5.7 9.5.8 9.5.9 9.5.10 Chapter 10: LPC800 State Configurable Timer (SCT) 10.1 10.2 10.3 10.3.1 10.4 10.5 10.6 10.6.1 10.6.2 10.6.3 10.6.4 10.6.5 10.6.6 10.6.7 10.6.8 10.6.9 10.6.10 10.6.11 10.6.12 10.6.13 10.6.14 10.6.15 10.6.16 10.6.17 10.6.18 A A A 9.4 9.4.1 9.4.2 9.5 How to read this chapter . . . . . . . . . . . . . . . . 100 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Basic configuration . . . . . . . . . . . . . . . . . . . . 100 Connect an internal signal to a package pin. 101 Enable an analog input or other special function . 101 General description . . . . . . . . . . . . . . . . . . . . 102 Movable functions. . . . . . . . . . . . . . . . . . . . . 102 Switch matrix register interface. . . . . . . . . . . 103 Register description . . . . . . . . . . . . . . . . . . . 104 R R R 8.7 8.7.1 8.7.2 Chapter 9: LPC800 Switch matrix 9.1 9.2 9.3 9.3.1 9.3.2 D D Pattern Match Interrupt Control Register . . . . 90 Pattern Match Interrupt Bit-Slice Source register. 91 Pattern Match Interrupt Bit-Slice Configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Functional description . . . . . . . . . . . . . . . . . . 98 Pin interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 98 Pattern Match engine example . . . . . . . . . . . 99 D 8.6.8 8.6.9 8.6.10 8.6.13 FT FT FT FT 8.6.7 8.6.11 8.6.12 A A A A R R D D D 8.6.6 Pin interrupt active level or falling edge interrupt enable register . . . . . . . . . . . . . . . . . . . . . . . . 88 Pin interrupt active level or falling edge interrupt set register . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Pin interrupt active level or falling edge interrupt clear register . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Pin interrupt rising edge register. . . . . . . . . . . 89 Pin interrupt falling edge register . . . . . . . . . . 90 Pin interrupt status register. . . . . . . . . . . . . . . 90 FT FT FT FT FT UM10601 Chapter 27: Supplementary information 8.6.5 A A A A A NXP Semiconductors 11.4 11.5 11.5.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . 139 General description . . . . . . . . . . . . . . . . . . . 139 Repeat interrupt mode . . . . . . . . . . . . . . . . . 140 All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 308 of 313 D D D D D R R R R R D R R D R R A D D R A 161 161 162 162 163 15.1 How to read this chapter . . . . . . . . . . . . . . . . 164 15.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 15.3 Basic configuration . . . . . . . . . . . . . . . . . . . . 164 15.3.1 Configure the USART clock and baud rate. . 165 15.3.2 Configure the USART for wake-up . . . . . . . 166 15.3.2.1 Wake-up from Sleep mode . . . . . . . . . . . . . . 166 15.3.2.2 Wake-up from Deep-sleep or Power-down mode. 167 15.4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 167 15.5 General description . . . . . . . . . . . . . . . . . . . . 168 15.6 Register description . . . . . . . . . . . . . . . . . . . 170 15.6.1 USART Configuration register . . . . . . . . . . . 171 15.6.2 USART Control register . . . . . . . . . . . . . . . . 172 15.6.3 USART Status register . . . . . . . . . . . . . . . . . 174 15.6.4 USART Interrupt Enable read and set register . . 175 15.6.5 USART Interrupt Enable Clear register . . . . 15.6.6 USART Receiver Data register . . . . . . . . . . 15.6.7 USART Receiver Data with Status register . 15.6.8 USART Transmitter Data Register . . . . . . . 15.6.9 USART Baud Rate Generator register. . . . . 15.6.10 USART Interrupt Status register. . . . . . . . . . 15.7 Functional description . . . . . . . . . . . . . . . . . 15.7.1 Clocking and Baud rates . . . . . . . . . . . . . . . 15.7.1.1 Fractional Rate Generator (FRG) . . . . . . . . 15.7.1.2 Baud Rate Generator (BRG) . . . . . . . . . . . . 15.7.1.3 Baud rate calculations . . . . . . . . . . . . . . . . . 15.7.2 Synchronous mode . . . . . . . . . . . . . . . . . . . 15.7.3 Flow control . . . . . . . . . . . . . . . . . . . . . . . . . 15.7.3.1 Hardware flow control . . . . . . . . . . . . . . . . . 15.7.3.2 Software flow control . . . . . . . . . . . . . . . . . . 176 177 177 178 179 179 180 180 180 181 181 181 181 181 182 Chapter 15: LPC800 USART0/1/2 Chapter 16: LPC800 I2C-bus interface How to read this chapter . . . . . . . . . . . . . . . . 183 UM10601 Preliminary user manual 16.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 309 of 313 A 14.5 General description . . . . . . . . . . . . . . . . . . . 14.5.1 WKT clock sources . . . . . . . . . . . . . . . . . . . 14.6 Register description . . . . . . . . . . . . . . . . . . . 14.6.1 Control register . . . . . . . . . . . . . . . . . . . . . . 14.6.2 Count register . . . . . . . . . . . . . . . . . . . . . . . R 161 161 161 161 Chapter 14: LPC800 Self wake-up timer (WKT) D 157 157 157 158 158 158 160 FT 13.5.1 Reference voltages . . . . . . . . . . . . . . . . . . . 13.5.2 Settling times . . . . . . . . . . . . . . . . . . . . . . . . 13.5.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.5.4 Comparator outputs . . . . . . . . . . . . . . . . . . . 13.6 Register description . . . . . . . . . . . . . . . . . . . 13.6.1 Comparator control register . . . . . . . . . . . . . 13.6.2 Voltage ladder register . . . . . . . . . . . . . . . . . 16.1 F FT FT 155 155 155 155 156 156 Chapter 13: LPC800 Analog comparator How to read this chapter . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Basic configuration . . . . . . . . . . . . . . . . . . . . Pin description . . . . . . . . . . . . . . . . . . . . . . . . A A 149 150 150 152 152 153 153 153 154 14.1 14.2 14.3 14.4 R R 12.5.3.2 Changing the WWDT reload value . . . . . . . 12.6 Register description . . . . . . . . . . . . . . . . . . . 12.6.1 Watchdog mode register . . . . . . . . . . . . . . . 12.6.2 Watchdog Timer Constant register. . . . . . . . 12.6.3 Watchdog Feed register. . . . . . . . . . . . . . . . 12.6.4 Watchdog Timer Value register . . . . . . . . . . 12.6.5 Watchdog Timer Warning Interrupt register . 12.6.6 Watchdog Timer Window register . . . . . . . . 12.7 Functional description . . . . . . . . . . . . . . . . . How to read this chapter . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Basic configuration . . . . . . . . . . . . . . . . . . . . Connect the comparator output to the SCT . Pin description . . . . . . . . . . . . . . . . . . . . . . . . General description . . . . . . . . . . . . . . . . . . . . A D D 146 146 146 146 147 147 148 149 149 13.1 13.2 13.3 13.3.1 13.4 13.5 R FT FT A A R Chapter 12: LPC800 Windowed Watchdog Timer (WWDT) 12.1 How to read this chapter . . . . . . . . . . . . . . . . 12.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3 Basic configuration . . . . . . . . . . . . . . . . . . . . 12.4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 12.5 General description . . . . . . . . . . . . . . . . . . . . 12.5.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . 12.5.2 Clocking and power control . . . . . . . . . . . . . 12.5.3 Using the WWDT lock features. . . . . . . . . . . 12.5.3.1 Disabling the WWDT clock source . . . . . . . . D 143 144 144 145 R D D Control register . . . . . . . . . . . . . . . . . . . . . . Status register . . . . . . . . . . . . . . . . . . . . . . . Idle channel register. . . . . . . . . . . . . . . . . . . Global interrupt flag register. . . . . . . . . . . . . FT FT FT A A R R D D D 11.6.3 11.6.4 11.6.5 11.6.6 FT FT FT FT 141 141 142 143 A A A A R R D D D One-shot interrupt mode. . . . . . . . . . . . . . . . Register description . . . . . . . . . . . . . . . . . . . Time interval register . . . . . . . . . . . . . . . . . . Timer register . . . . . . . . . . . . . . . . . . . . . . . . FT FT FT FT FT UM10601 Chapter 27: Supplementary information 11.5.2 11.6 11.6.1 11.6.2 A A A A A NXP Semiconductors D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D A 234 234 235 Preliminary user manual Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 310 of 313 A 233 234 234 R 19.4.4 Flash signature generation result register . . 19.5 Functional description . . . . . . . . . . . . . . . . . 19.5.1 Flash signature generation . . . . . . . . . . . . . 19.5.1.1 Signature generation address and control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.5.1.2 Signature generation . . . . . . . . . . . . . . . . . . 19.5.1.3 Content verification . . . . . . . . . . . . . . . . . . . D 232 232 232 232 232 233 233 FT 229 229 229 229 231 231 231 231 20.2 D R UM10601 F D 18.7.1 CRC mode register . . . . . . . . . . . . . . . . . . . 18.7.2 CRC seed register . . . . . . . . . . . . . . . . . . . . 18.7.3 CRC checksum register . . . . . . . . . . . . . . . . 18.7.4 CRC data register . . . . . . . . . . . . . . . . . . . . 18.8 Functional description . . . . . . . . . . . . . . . . . 18.8.1 CRC-CCITT set-up . . . . . . . . . . . . . . . . . . . 18.8.2 CRC-16 set-up . . . . . . . . . . . . . . . . . . . . . . . 18.8.3 CRC-32 set-up . . . . . . . . . . . . . . . . . . . . . . . How to read this chapter . . . . . . . . . . . . . . . . 236 FT FT 227 227 227 227 227 228 228 Chapter 20: LPC800 Boot ROM 20.1 A A How to read this chapter . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General description . . . . . . . . . . . . . . . . . . . . Register description . . . . . . . . . . . . . . . . . . . Flash configuration register . . . . . . . . . . . . . Flash signature start address register . . . . . Flash signature stop address register. . . . . . R R 216 217 217 218 218 220 220 221 221 222 223 224 224 224 224 225 Chapter 19: LPC800 Flash controller 19.1 19.2 19.3 19.4 19.4.1 19.4.2 19.4.3 A D D How to read this chapter . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Basic configuration . . . . . . . . . . . . . . . . . . . . Pin description . . . . . . . . . . . . . . . . . . . . . . . . General description . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . Register description . . . . . . . . . . . . . . . . . . . R FT FT A A R 17.6.7 SPI Transmitter Data and Control register . . 17.6.8 SPI Transmitter Data Register . . . . . . . . . . 17.6.9 SPI Transmitter Control register. . . . . . . . . . 17.6.10 SPI Divider register . . . . . . . . . . . . . . . . . . . 17.6.11 SPI Interrupt Status register. . . . . . . . . . . . . 17.7 Functional description . . . . . . . . . . . . . . . . . 17.7.1 Operating modes: clock and phase selection 17.7.2 Frame delays . . . . . . . . . . . . . . . . . . . . . . . . 17.7.2.1 Pre_delay and Post_delay . . . . . . . . . . . . . . 17.7.2.2 Frame_delay . . . . . . . . . . . . . . . . . . . . . . . . 17.7.2.3 Transfer_delay . . . . . . . . . . . . . . . . . . . . . . . 17.7.3 Clocking and data rates . . . . . . . . . . . . . . . . 17.7.3.1 Data rate calculations . . . . . . . . . . . . . . . . . 17.7.4 Slave select . . . . . . . . . . . . . . . . . . . . . . . . . 17.7.5 Data lengths greater than 16 bits . . . . . . . . . 17.7.6 Data stalls . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 18: LPC800 Cyclic Redundancy Check (CRC) engine 18.1 18.2 18.3 18.4 18.5 18.6 18.7 D 199 199 200 201 201 202 203 203 203 203 204 204 205 R D D 16.6.10 Master Data register . . . . . . . . . . . . . . . . . . 16.6.11 Slave Control register . . . . . . . . . . . . . . . . . 16.6.12 Slave Data register . . . . . . . . . . . . . . . . . . . 16.6.13 Slave Address registers . . . . . . . . . . . . . . . . 16.6.14 Slave address Qualifier 0 register . . . . . . . . 16.6.15 Monitor data register . . . . . . . . . . . . . . . . . . 16.7 Functional description . . . . . . . . . . . . . . . . . 16.7.1 Bus rates and timing considerations . . . . . . 16.7.1.1 Rate calculations . . . . . . . . . . . . . . . . . . . . . 16.7.2 Time-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.7.3 Ten-bit addressing . . . . . . . . . . . . . . . . . . . . 16.7.4 Clocking and power considerations . . . . . . . 16.7.5 lnterrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 17: LPC800 SPI0/1 17.1 How to read this chapter . . . . . . . . . . . . . . . . 206 17.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 17.3 Basic configuration . . . . . . . . . . . . . . . . . . . . 206 17.3.1 Configure the SPIs for wake-up . . . . . . . . . . 206 17.3.1.1 Wake-up from Sleep mode . . . . . . . . . . . . . . 207 17.3.1.2 Wake-up from Deep-sleep or Power-down mode. 207 17.4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 207 17.5 General description . . . . . . . . . . . . . . . . . . . . 209 17.6 Register description . . . . . . . . . . . . . . . . . . . 209 17.6.1 SPI Configuration register . . . . . . . . . . . . . . 211 17.6.2 SPI Delay register. . . . . . . . . . . . . . . . . . . . . 212 17.6.3 SPI Status register . . . . . . . . . . . . . . . . . . . . 213 17.6.4 SPI Interrupt Enable read and Set register . 214 17.6.5 SPI Interrupt Enable Clear register. . . . . . . . 215 17.6.6 SPI Receiver Data register . . . . . . . . . . . . . . 215 FT FT FT FT 183 184 184 185 187 189 193 194 195 196 196 197 198 A A A A R R D D D Basic configuration . . . . . . . . . . . . . . . . . . . . Pin description . . . . . . . . . . . . . . . . . . . . . . . . General description . . . . . . . . . . . . . . . . . . . . Register description . . . . . . . . . . . . . . . . . . . I2C Configuration register . . . . . . . . . . . . . . I2C Status register . . . . . . . . . . . . . . . . . . . . Interrupt Enable Set and read register . . . . . Interrupt Enable Clear register . . . . . . . . . . . Time-out value register . . . . . . . . . . . . . . . . . I2C Clock Divider register . . . . . . . . . . . . . . . I2C Interrupt Status register . . . . . . . . . . . . . Master Control register . . . . . . . . . . . . . . . . . Master Time . . . . . . . . . . . . . . . . . . . . . . . . . FT FT FT FT FT UM10601 Chapter 27: Supplementary information 16.3 16.4 16.5 16.6 16.6.1 16.6.2 16.6.3 16.6.4 16.6.5 16.6.6 16.6.7 16.6.8 16.6.9 A A A A A NXP Semiconductors D D D D D R R R R R D R R D R A FT FT FT A A R R R D D R A 22.5.1.5 22.5.1.6 22.5.2 22.5.2.1 22.5.2.2 23.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 © NXP B.V. 2012. All rights reserved. 311 of 313 A 22.5.1.3 22.5.1.4 R 22.5.1.2 Invalid frequency (device maximum clock rate exceeded) . . . . . . . . . . . . . . . . . . . . . . . . . . 265 Invalid frequency selection (system clock divider restrictions) . . . . . . . . . . . . . . . . . . . . . . . . . 266 Exact solution cannot be found (PLL) . . . . . 266 System clock less than or equal to the expected value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 System clock greater than or equal to the expected value. . . . . . . . . . . . . . . . . . . . . . . 266 System clock approximately equal to the expected value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 Power control . . . . . . . . . . . . . . . . . . . . . . . . 267 Invalid frequency (device maximum clock rate exceeded) . . . . . . . . . . . . . . . . . . . . . . . . . . 267 An applicable power setup. . . . . . . . . . . . . . 267 D 22.5.1.1 FT Preliminary user manual F FT FT How to read this chapter . . . . . . . . . . . . . . . . 268 UM10601 A A ReadUID . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 UART ISP Return Codes . . . . . . . . . . . . . . . 250 IAP commands. . . . . . . . . . . . . . . . . . . . . . . 250 Prepare sector(s) for write operation (IAP) . 252 Copy RAM to flash (IAP) . . . . . . . . . . . . . . . 253 Erase Sector(s) (IAP). . . . . . . . . . . . . . . . . . 254 Blank check sector(s) (IAP) . . . . . . . . . . . . . 254 Read Part Identification number (IAP) . . . . . 254 Read Boot code version number (IAP) . . . . 255 Compare <address1> <address2> <no of bytes> (IAP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 21.4.2.8 Reinvoke ISP (IAP) . . . . . . . . . . . . . . . . . . . 256 21.4.2.9 ReadUID (IAP) . . . . . . . . . . . . . . . . . . . . . . . 256 21.4.2.10 Erase page. . . . . . . . . . . . . . . . . . . . . . . . . . 256 21.4.2.11 IAP Status Codes. . . . . . . . . . . . . . . . . . . . . 256 21.5 Functional description . . . . . . . . . . . . . . . . . 257 21.5.1 UART Communication protocol . . . . . . . . . . 257 21.5.1.1 UART ISP command format. . . . . . . . . . . . . 257 21.5.1.2 UART ISP response format . . . . . . . . . . . . . 257 21.5.1.3 UART ISP data format . . . . . . . . . . . . . . . . . 257 21.5.2 Memory and interrupt use for ISP and IAP . 257 21.5.2.1 Interrupts during UART ISP . . . . . . . . . . . . . 257 21.5.2.2 Interrupts during IAP . . . . . . . . . . . . . . . . . . 258 21.5.2.3 RAM used by ISP command handler. . . . . . 258 21.5.2.4 RAM used by IAP command handler. . . . . . 258 21.5.3 Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . 258 21.5.3.1 Comparing flash images . . . . . . . . . . . . . . . 258 21.5.3.2 Serial Wire Debug (SWD) flash programming interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 Chapter 23: LPC800 I2C-bus ROM API 23.1 R R 262 262 263 263 265 265 265 265 265 A D D 259 259 259 260 261 R FT FT A A R 21.4.1.14 21.4.1.15 21.4.2 21.4.2.1 21.4.2.2 21.4.2.3 21.4.2.4 21.4.2.5 21.4.2.6 21.4.2.7 Chapter 22: LPC800 Power profile API ROM driver 22.1 How to read this chapter . . . . . . . . . . . . . . . . 22.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.3 General description . . . . . . . . . . . . . . . . . . . . 22.4 API description . . . . . . . . . . . . . . . . . . . . . . . 22.4.1 set_pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.4.1.1 Param0: system PLL input frequency and Param1: expected system clock . . . . . . . . . . 22.4.1.2 Param2: mode . . . . . . . . . . . . . . . . . . . . . . . 22.4.1.3 Param3: system PLL lock time-out . . . . . . . . 22.4.2 set_power . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.4.2.1 Param0: main clock . . . . . . . . . . . . . . . . . . . 22.4.2.2 Param1: mode . . . . . . . . . . . . . . . . . . . . . . . 22.4.2.3 Param2: system clock . . . . . . . . . . . . . . . . . 22.5 Functional description . . . . . . . . . . . . . . . . . 22.5.1 Clock control . . . . . . . . . . . . . . . . . . . . . . . . . D 238 238 238 239 R D D Boot pins . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory map after any reset . . . . . . . . . . . . Boot process . . . . . . . . . . . . . . . . . . . . . . . . Boot process flowchart. . . . . . . . . . . . . . . . . Chapter 21: LPC800 Flash ISP and IAP programming 21.1 How to read this chapter . . . . . . . . . . . . . . . . 240 21.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 21.3 General description . . . . . . . . . . . . . . . . . . . . 240 21.3.1 Flash configuration . . . . . . . . . . . . . . . . . . . . 240 21.3.2 Flash content protection mechanism . . . . . . 241 21.3.3 Code Read Protection (CRP) . . . . . . . . . . . . 241 21.3.3.1 ISP entry protection . . . . . . . . . . . . . . . . . . . 243 21.4 API description . . . . . . . . . . . . . . . . . . . . . . . 243 21.4.1 UART ISP commands. . . . . . . . . . . . . . . . . . 243 21.4.1.1 Unlock <Unlock code> . . . . . . . . . . . . . . . . . 244 21.4.1.2 Set Baud Rate <Baud Rate> <stop bit> . . . 244 21.4.1.3 Echo <setting> . . . . . . . . . . . . . . . . . . . . . . . 245 21.4.1.4 Write to RAM <start address> <number of bytes> 245 21.4.1.5 Read Memory <address> <number of bytes> . . . 245 21.4.1.6 Prepare sector(s) for write operation <start sector number> <end sector number> . . . . . . . . . . 246 21.4.1.7 Copy RAM to flash <Flash address> <RAM address> <no of bytes> . . . . . . . . . . . . . . . . 246 21.4.1.8 Go <address> <mode> . . . . . . . . . . . . . . . . 247 21.4.1.9 Erase sector(s) <start sector number> <end sector number> . . . . . . . . . . . . . . . . . . . . . . 248 21.4.1.10 Blank check sector(s) <sector number> <end sector number> . . . . . . . . . . . . . . . . . . . . . . 248 21.4.1.11 Read Part Identification number . . . . . . . . . 248 21.4.1.12 Read Boot code version number . . . . . . . . . 249 21.4.1.13 Compare <address1> <address2> <no of bytes> 249 D D D 20.4.1 20.4.2 20.4.3 20.4.4 FT FT FT FT 236 236 237 238 A A A A R R D D D General description . . . . . . . . . . . . . . . . . . . . Boot loader . . . . . . . . . . . . . . . . . . . . . . . . . . ROM-based APIs . . . . . . . . . . . . . . . . . . . . . Functional description . . . . . . . . . . . . . . . . . FT FT FT FT FT UM10601 Chapter 27: Supplementary information 20.3 20.3.1 20.3.2 20.4 A A A A A NXP Semiconductors D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D A 27.3.3 27.4 27.5 27.6 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . UM10601 Preliminary user manual All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 7 November 2012 299 300 305 306 © NXP B.V. 2012. All rights reserved. 312 of 313 A Pin description . . . . . . . . . . . . . . . . . . . . . . . 294 R 26.2 D 291 291 291 292 FT 25.5 Functional description . . . . . . . . . . . . . . . . . 25.5.1 Debug limitations . . . . . . . . . . . . . . . . . . . . . 25.5.2 Debug connections for SWD . . . . . . . . . . . . 25.5.3 Boundary scan . . . . . . . . . . . . . . . . . . . . . . . 298 298 299 299 299 D R Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . Legal information. . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . F D 290 290 290 290 Chapter 27: Supplementary information 27.1 27.2 27.3 27.3.1 27.3.2 FT FT 287 287 287 287 288 288 288 288 289 Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 A A 24.4.6 UART get line. . . . . . . . . . . . . . . . . . . . . . . . 24.4.7 UART put line. . . . . . . . . . . . . . . . . . . . . . . . 24.4.8 UART interrupt service routine. . . . . . . . . . . 24.4.9 Error codes . . . . . . . . . . . . . . . . . . . . . . . . . 24.4.10 UART ROM driver variables. . . . . . . . . . . . . 24.4.10.1 UART_CONFIG structure . . . . . . . . . . . . . . 24.4.10.2 UART_HANDLE_T. . . . . . . . . . . . . . . . . . . . 24.4.10.3 UART_PARAM_T. . . . . . . . . . . . . . . . . . . . . 24.5 Functional description . . . . . . . . . . . . . . . . . Chapter 26: LPC800 Packages and pin description 26.1 R R How to read this chapter . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General description . . . . . . . . . . . . . . . . . . . . Pin description . . . . . . . . . . . . . . . . . . . . . . . . A D D 284 284 284 285 285 286 286 286 286 Chapter 25: LPC800 Debugging 25.1 25.2 25.3 25.4 R FT FT A A R R 275 276 276 276 276 276 277 277 278 278 278 278 278 279 280 281 282 D D D How to read this chapter . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General description . . . . . . . . . . . . . . . . . . . . API description . . . . . . . . . . . . . . . . . . . . . . . UART get memory size. . . . . . . . . . . . . . . . . UART setup . . . . . . . . . . . . . . . . . . . . . . . . . UART init . . . . . . . . . . . . . . . . . . . . . . . . . . . UART get character . . . . . . . . . . . . . . . . . . . UART put character . . . . . . . . . . . . . . . . . . . FT FT FT FT 23.4.17 I2C Get Status . . . . . . . . . . . . . . . . . . . . . . . 23.4.18 I2C time-out value . . . . . . . . . . . . . . . . . . . . 23.4.19 Error codes . . . . . . . . . . . . . . . . . . . . . . . . . 23.4.20 I2C Status code . . . . . . . . . . . . . . . . . . . . . . 23.4.21 I2C ROM driver variables. . . . . . . . . . . . . . . 23.4.21.1 I2C Handle . . . . . . . . . . . . . . . . . . . . . . . . . . 23.4.22 PARAM and RESULT structure . . . . . . . . . . 23.4.23 Error structure . . . . . . . . . . . . . . . . . . . . . . . 23.4.24 I2C Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.4.25 I2C ROM driver pointer . . . . . . . . . . . . . . . . 23.5 Functional description . . . . . . . . . . . . . . . . . 23.5.1 I2C Set-up . . . . . . . . . . . . . . . . . . . . . . . . . . 23.5.2 I2C Master mode set-up . . . . . . . . . . . . . . . 23.5.3 I2C Slave mode set-up . . . . . . . . . . . . . . . . 23.5.4 I2C Master Transmit/Receive. . . . . . . . . . . . 23.5.5 I2C Slave Mode Transmit/Receive. . . . . . . . 23.5.6 I2C time-out feature . . . . . . . . . . . . . . . . . . . Chapter 24: LPC800 USART API ROM driver routines 24.1 24.2 24.3 24.4 24.4.1 24.4.2 24.4.3 24.4.4 24.4.5 A A A A R R D D D 268 269 271 271 271 272 272 272 273 273 273 274 274 274 274 275 275 275 FT FT FT FT FT UM10601 Chapter 27: Supplementary information 23.3 General description . . . . . . . . . . . . . . . . . . . . 23.4 API description . . . . . . . . . . . . . . . . . . . . . . . 23.4.1 ISR handler. . . . . . . . . . . . . . . . . . . . . . . . . . 23.4.2 I2C Master Transmit Polling . . . . . . . . . . . . . 23.4.3 I2C Master Receive Polling . . . . . . . . . . . . . 23.4.4 I2C Master Transmit and Receive Polling . . 23.4.5 I2C Master Transmit Interrupt. . . . . . . . . . . . 23.4.6 I2C Master Receive Interrupt . . . . . . . . . . . . 23.4.7 I2C Master Transmit Receive Interrupt. . . . . 23.4.8 I2C Slave Receive Polling . . . . . . . . . . . . . . 23.4.9 I2C Slave Transmit Polling . . . . . . . . . . . . . . 23.4.10 I2C Slave Receive Interrupt . . . . . . . . . . . . . 23.4.11 I2C Slave Transmit Interrupt. . . . . . . . . . . . . 23.4.12 I2C Set Slave Address . . . . . . . . . . . . . . . . . 23.4.13 I2C Get Memory Size . . . . . . . . . . . . . . . . . . 23.4.14 I2C Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.4.15 I2C Set Bit Rate . . . . . . . . . . . . . . . . . . . . . . 23.4.16 I2C Get Firmware Version . . . . . . . . . . . . . . A A A A A NXP Semiconductors D D D D D R R R R R A A A A A FT FT FT UM10601 FT FT D R R FT FT FT FT Chapter 27: Supplementary information A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D D D R A FT D R A 313 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 7 November 2012 Document identifier: UM10601