BUK9MGP-55PTS Dual TrenchPLUS logic level FET Rev. 01 — 14 May 2009 Product data sheet 1. Product profile 1.1 General description Dual N-channel enhancement mode field-effect power transistor in SO20. Device is manufactured using NXP High-Performance (HPA) TrenchPLUS technology, featuring very low on-state resistance, integrated current sensing transistors and over temperature protection diodes. 1.2 Features and benefits Integrated current sensors Integrated temperature sensors 1.3 Applications Lamp switching Power distribution Motor drive systems Solenoid drivers 1.4 Quick reference data Table 1. Quick reference Symbol Parameter Conditions Min Typ Max Unit Static characteristics, FET1 RDSon drain-source on-state resistance VGS = 5 V; ID = 10 A; Tj = 25 °C; see Figure 23; see Figure 25 - 8.6 10 mΩ ID/Isense ratio of drain current to sense current Tj = 25 °C; VGS = 5 V; see Figure 27 8100 9000 9900 A/A VGS = 0 V; ID = 250 µA; Tj = 25 °C 55 - - V V(BR)DSS drain-source breakdown voltage Static characteristics, FET2 RDSon drain-source on-state resistance VGS = 5 V; ID = 5 A; Tj = 25 °C; see Figure 24; see Figure 26 - 21.3 25 mΩ ID/Isense ratio of drain current to sense current Tj = 25 °C; VGS = 5 V; see Figure 28 5910 6570 7227 A/A VGS = 0 V; ID = 250 µA; Tj = 25 °C 55 - - V V(BR)DSS drain-source breakdown voltage BUK9MGP-55PTS NXP Semiconductors Dual TrenchPLUS logic level FET 2. Pinning information Table 2. Pinning information Pin Symbol Description Simplified outline 1 G1 gate 1 2 IS1 current sense 1 3 D1 drain 1 4 A1 anode 1 5 C1 cathode 1 6 G2 gate 2 7 IS2 current sense 2 8 D2 drain 2 9 A2 anode 2 10 C2 cathode 2 11 D2 drain 2 12 KS2 Kelvin source 2 13 S2 source 2 14 S2 source 2 15 D2 drain 2 16 D1 drain 1 17 KS1 Kelvin source 1 18 S1 source 1 19 S1 source 1 20 D1 drain 1 Graphic symbol 11 20 D1 A1 FET1 D2 A2 FET2 10 1 SOT163-1 (SO20) G1 IS1 S1 KS1 C1 G2 IS2 S2 KS2 C2 003aaa745 3. Ordering information Table 3. Ordering information Type number BUK9MGP-55PTS Package Name Description Version SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 BUK9MGP-55PTS_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 14 May 2009 2 of 20 BUK9MGP-55PTS NXP Semiconductors Dual TrenchPLUS logic level FET 4. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit Limiting values, FET1 VDS drain-source voltage 25 °C < Tj < 150 °C - 55 V VDGR drain-gate voltage RGS = 20 kΩ; 25 °C < Tj < 150 °C - 55 V VGS gate-source voltage -15 15 V ID drain current Tsp = 25 °C; VGS = 5 V; see Figure 3; see Figure 7; [1][2] - 16.9 A Tsp = 100 °C; VGS = 5 V; see Figure 3; - 10.7 A IDM peak drain current Tsp = 25 °C; tp ≤ 10 µs; pulsed; see Figure 7 - 349 A Ptot total power dissipation Tsp = 25 °C; see Figure 1 - 5.2 W Tstg storage temperature -55 150 °C Tj junction temperature -55 150 °C - 100 V [1][2] Visol(FET-TSD) FET to temperature sense diode isolation voltage Limiting values, FET2 VDS drain-source voltage 25 °C < Tj < 150 °C - 55 V VDGR drain-gate voltage RGS = 20 kΩ; 25 °C < Tj < 150 °C - 55 V VGS gate-source voltage -15 15 V ID drain current Tsp = 25 °C; VGS = 5 V; see Figure 4; see Figure 8; [1][2] - 9.16 A Tsp = 100 °C; VGS = 5 V; see Figure 4; - 5.8 A [1][2] IDM peak drain current Tsp = 25 °C; tp ≤ 10 µs; pulsed; see Figure 8 - 148 A Ptot total power dissipation Tsp = 25 °C; see Figure 2 - 3.9 W Tstg storage temperature -55 150 °C Tj junction temperature -55 150 °C - 100 V - 7.3 A - 349 A - 5.5 A - 148 A [3][4] [5] - 929 mJ [3][4] [5] - 360 mJ Visol(FET-TSD) FET to temperature sense diode isolation voltage Source-drain diode, FET1 IS source current Tsp = 25 °C; ISM peak source current tp ≤ 10 µs; pulsed; Tsp = 25 °C [1][2] Source-drain diode, FET2 IS source current Tsp = 25 °C; ISM peak source current tp ≤ 10 µs; pulsed; Tsp = 25 °C [1][2] Avalanche ruggedness, FET1 EDS(AL)S non-repetitive ID = 16.9 A; Vsup ≤ 55 V; VGS = 5 V; Tj(init) = 25 °C; drain-source avalanche unclamped; see Figure 5; energy Avalanche ruggedness, FET2 EDS(AL)S non-repetitive ID = 9.16 A; Vsup ≤ 55 V; VGS = 5 V; Tj(init) = 25 °C; drain-source avalanche unclamped; see Figure 6; energy BUK9MGP-55PTS_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 14 May 2009 3 of 20 BUK9MGP-55PTS NXP Semiconductors Dual TrenchPLUS logic level FET Table 4. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit HBM; C = 100 pF; R = 1.5 kΩ; pins 3, 16 and 20 to pins 1, 2, 17, 18 and 19 shorted - 4 kV HBM; C = 100 pF; R = 1.5 kΩ; all pins - 0.15 kV HBM; C = 100 pF; R = 1.5 kΩ; pins 8, 11 and 15 to pins 6, 7, 12, 13 and 14 shorted - 4 kV HBM; C = 100 pF; R = 1.5 kΩ; all pins - 0.15 kV Electrostatic discharge, FET1 electrostatic discharge voltage VESD Electrostatic discharge, FET2 electrostatic discharge voltage VESD [1] Single device conducting. [2] Current is limited by chip power dissipation rating. [3] Single-pulse avalanche rating limited by maximum junction temperature of 150 °C. [4] Repetitive rating defined in avalanche rating figure. [5] Refer to application note AN10273 for further information. 003aab388 120 Pder (%) Pder (%) 80 80 40 40 0 0 0 Fig 1. 003aab388 120 50 100 150 200 Tsp (°C) Normalized total power dissipation as a function of solder point temperature, FET1 0 Fig 2. 100 150 200 Tsp (°C) Normalized total power dissipation as a function of solder point temperature, FET2 BUK9MGP-55PTS_1 Product data sheet 50 © NXP B.V. 2009. All rights reserved. Rev. 01 — 14 May 2009 4 of 20 BUK9MGP-55PTS NXP Semiconductors Dual TrenchPLUS logic level FET 003aac532 20 003aac533 12 ID (A) 16 ID (A) 8 12 8 4 4 0 0 0 Fig 3. 50 100 150 Tsp (°C) 200 Continuous drain current as a function of solder point temperature, FET1. 003aac527 102 0 Fig 4. 50 100 150 Tsp (°C) Continuous drain current as a function of solder point temperature, FET2. 003aac528 102 IAL (A) IAL (A) 10 10 (1) (1) (2) (2) 1 1 (3) (3) 10-1 10-3 Fig 5. 200 10-2 10-1 1 tAL (ms) 10 Single-pulse and repetitive avalanche rating; avalanche current as a function of avalanche time, FET1 10-1 10-3 Fig 6. 10-1 1 tAL (ms) 10 Single-pulse and repetitive avalanche rating; avalanche current as a function of avalanche time, FET2 BUK9MGP-55PTS_1 Product data sheet 10-2 © NXP B.V. 2009. All rights reserved. Rev. 01 — 14 May 2009 5 of 20 BUK9MGP-55PTS NXP Semiconductors Dual TrenchPLUS logic level FET 003aac362 103 ID (A) 2 10 tp = 10 ms Limit R DS on = VDS / ID 100 ms 1 ms 10 10 ms 100 ms 1 DC 10-1 10-2 10-1 Fig 7. 1 10 VDS (V) 102 Safe operating area; continuous and peak drain currents as a function of drain-source voltage, FET1. 003aac375 103 ID (A) 2 10 Limit R DS on = VDS / ID tp = 10 ms 100 ms 10 1 ms 10 ms 1 100 ms DC 10-1 10-2 10-1 Fig 8. 1 10 VDS (V) 102 Safe operating area; continuous and peak drain currents as a function of drain-source voltage, FET2 BUK9MGP-55PTS_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 14 May 2009 6 of 20 BUK9MGP-55PTS NXP Semiconductors Dual TrenchPLUS logic level FET 5. Thermal characteristics Table 5. Thermal characteristics Symbol Parameter Rth(j-sp) Rth(j-a) Conditions Min Typ Max Unit thermal resistance from FET1 junction to solder point FET2 - - 24 K/W - - 32 K/W thermal resistance from mounted on printed-circuit board; Both junction to ambient channel conducting; zero heat sink area; see Figure 9; see Figure 10 - 73 - K/W mounted on printed-circuit board; Both channel conducting; 200 mm2 copper heat sink area; see Figure 9; see Figure 11 - 60 - K/W mounted on printed-circuit board; Both channel conducting; 400 mm2 copper heat sink area; see Figure 9; see Figure 12 - 51 - K/W mounted on printed-circuit board; One channel conducting; zero heat sink area; see Figure 9; see Figure 10 - 105 - K/W mounted on printed-circuit board; One channel conducting; 200 mm2 copper heat sink area; see Figure 9; see Figure 11 - 90 - K/W mounted on printed-circuit board; One channel conducting; 400 mm2 copper heat sink area; see Figure 9; see Figure 12 - 78 - K/W 003aac472 120 Rth(j-a) (K/W) (1) 80 (2) 001aae478 40 Fig 10. PCB used for thermal tests; zero heat sink area 0 0 Fig 9. 100 200 300 A (mm2) 400 Thermal resistance from junction to ambient as a function of printed-circuit board (PCB) heat sink area BUK9MGP-55PTS_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 14 May 2009 7 of 20 BUK9MGP-55PTS NXP Semiconductors Dual TrenchPLUS logic level FET 001aae479 001aae480 Fig 11. PCB used for thermal tests; heat sink area 200 mm2 Fig 12. PCB used for thermal tests; heat sink area 400 mm2 003aad208 102 Zth(j-mb) (K/W) δ = 0.5 0.2 10 0.1 0.05 0.02 1 10-1 δ= P tp T 10-2 single shot t tp T 10-3 10-6 10-5 10-4 10-3 10-2 10-1 1 10 102 103 4 tp (s) 10 Fig 13. Transient thermal impedance from junction to ambient as a function of pulse duration, FET1 (PCB used for thermal tests; heat sink area 400mm2) 102 Zth(j-mb) (K/W) 003aad209 δ = 0.5 0.2 10 0.1 0.05 0.02 1 δ= P tp T 10-1 t tp T single shot 10-2 10-6 10-5 10-4 10-3 10-2 10-1 1 10 102 103 4 tp (s) 10 Fig 14. Transient thermal impedance from junction to ambient as a function of pulse duration, FET2 (PCB used for thermal tests; heat sink area 400mm2) BUK9MGP-55PTS_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 14 May 2009 8 of 20 BUK9MGP-55PTS NXP Semiconductors Dual TrenchPLUS logic level FET 6. Characteristics Table 6. Symbol Characteristics Parameter Conditions Min Typ Max Unit Static characteristics, FET1 V(BR)DSS VGS(th) IDSS drain-source breakdown voltage ID = 250 µA; VGS = 0 V; Tj = 25 °C 55 - - V ID = 250 µA; VGS = 0 V; Tj = -55 °C 50 - - V gate-source threshold voltage ID = 1 mA; VDS = VGS; Tj = 25 °C; see Figure 21; see Figure 22 1 1.5 2 V ID = 1 mA; VDS = VGS; Tj = -55 °C; see Figure 21; see Figure 22 - - 2.3 V ID = 1 mA; VDS = VGS; Tj = 150 °C; see Figure 21; see Figure 22 0.5 - - V VDS = 40 V; VGS = 0 V; Tj = 25 °C - 0.02 3 µA VDS = 40 V; VGS = 0 V; Tj = 150 °C - - 125 µA drain leakage current IGSS gate leakage current VDS = 0 V; VGS = 15 V; Tj = 25 °C - 2 300 nA RDSon drain-source on-state resistance VGS = 5 V; ID = 10 A; Tj = 25 °C; see Figure 23; see Figure 25 - 8.6 10 mΩ VGS = 5 V; ID = 10 A; Tj = 150 °C; see Figure 25; see Figure 23 - - 18 mΩ VGS = 4.5 V; ID = 10 A; Tj = 25 °C; see Figure 23; see Figure 25 - 9.4 11.1 mΩ VGS = 10 V; ID = 10 A; Tj = 25 °C; see Figure 23; see Figure 25 - 8.1 9 mΩ ID/Isense ratio of drain current to sense current Tj = 25 °C; VGS = 5 V; see Figure 27 8100 9000 9900 A/A SF(TSD) temperature sense diode temperature coefficient IF = 250 µA; 25 °C < Tj < 150 °C; see Figure 29 -5.4 -5.7 -6 mV/K VF(TSD) temperature sense diode forward voltage IF = 250 µA; Tj = 25 °C; see Figure 29 2.855 2.9 2.945 V Static characteristics, FET2 V(BR)DSS drain-source breakdown voltage ID = 250 µA; VGS = 0 V; Tj = 25 °C 55 - - V ID = 250 µA; VGS = 0 V; Tj = -55 °C 50 - - V VGS(th) gate-source threshold voltage ID = 1 mA; VDS = VGS; Tj = 25 °C; see Figure 21; see Figure 22 1 1.5 2 V ID = 1 mA; VDS = VGS; Tj = -55 °C; see Figure 21; see Figure 22 - - 2.3 V ID = 1 mA; VDS = VGS; Tj = 150 °C; see Figure 21; see Figure 22 0.5 - - V - 0.02 3 µA IDSS drain leakage current VDS = 40 V; VGS = 0 V; Tj = 25 °C VDS = 40 V; VGS = 0 V; Tj = 150 °C - - 125 µA IGSS gate leakage current VDS = 0 V; VGS = 15 V; Tj = 25 °C - 2 300 nA BUK9MGP-55PTS_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 14 May 2009 9 of 20 BUK9MGP-55PTS NXP Semiconductors Dual TrenchPLUS logic level FET Table 6. Characteristics …continued Symbol Parameter Conditions Min Typ Max Unit RDSon drain-source on-state resistance VGS = 5 V; ID = 5 A; Tj = 25 °C; see Figure 24; see Figure 26 - 21.3 25 mΩ VGS = 5 V; ID = 5 A; Tj = 150 °C; see Figure 24; see Figure 26 - - 46.8 mΩ VGS = 4.5 V; ID = 5 A; Tj = 25 °C; see Figure 24; see Figure 26 - 23.7 27.9 mΩ VGS = 10 V; ID = 5 A; Tj = 25 °C; see Figure 24; see Figure 26 - 20.3 22.6 mΩ ID/Isense ratio of drain current to sense current Tj = 25 °C; VGS = 5 V; see Figure 28 5910 6570 7227 A/A SF(TSD) temperature sense diode temperature coefficient IF = 250 µA; 25 °C < Tj < 150 °C; see Figure 29 -5.4 -5.7 -6 mV/K VF(TSD) temperature sense diode forward voltage IF = 250 µA; Tj = 25 °C; see Figure 29 2.855 2.9 2.945 V ID = 10 A; VDS = 44 V; VGS = 5 V; see Figure 30 - 54 - nC - 9.4 - nC - 21.5 - nC - 3884 5178 pF - 540 648 pF - 247 338 pF - 41 - ns - 94 - ns - 184 - ns Dynamic characteristics, FET1 QG(tot) total gate charge QGS gate-source charge QGD gate-drain charge Ciss input capacitance Coss output capacitance Crss reverse transfer capacitance td(on) turn-on delay time tr rise time td(off) turn-off delay time tf fall time - 98 - ns LD internal drain inductance From pin to centre of die - 0.85 - nH LS internal source inductance From source lead to source bonding pad - 1.9 - nH ID = 5 A; VDS = 44 V; VGS = 0 V; see Figure 31 - 23 - nC - 3.4 - nC - 9 - nC - 1736 2315 pF - 244 293 pF - 119 163 pF - 29 - ns - 44 - ns VGS = 0 V; VDS = 25 V; f = 1 MHz; Tj = 25 °C; see Figure 32 VDS = 30 V; RL = 3 Ω; VGS = 5 V; RG(ext) = 10 Ω Dynamic characteristics, FET2 QG(tot) total gate charge QGS gate-source charge QGD gate-drain charge Ciss input capacitance Coss output capacitance Crss reverse transfer capacitance td(on) turn-on delay time tr rise time td(off) turn-off delay time - 91 - ns tf fall time - 46 - ns VGS = 0 V; VDS = 25 V; f = 1 MHz; Tj = 25 °C; see Figure 33 VDS = 30 V; RL = 6 Ω; VGS = 5 V; RG(ext) = 10 Ω BUK9MGP-55PTS_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 14 May 2009 10 of 20 BUK9MGP-55PTS NXP Semiconductors Dual TrenchPLUS logic level FET Table 6. Characteristics …continued Symbol Parameter Conditions Min Typ Max Unit LD internal drain inductance From pin to centre of die - 0.85 - nH LS internal source inductance From source lead to source bonding pad - 2 - nH - 0.85 1.2 V - 66.4 - ns - 126 - nC Source-drain diode, FET1 VSD source-drain voltage IS = 10 A; VGS = 0 V; Tj = 25 °C; see Figure 34 trr reverse recovery time Qr recovered charge IS = 5 A; dIS/dt = -100 A/µs; VGS = -10 V; VDS = 30 V; [1] Source-drain diode, FET2 VSD source-drain voltage IS = 5 A; VGS = 0 V; Tj = 25 °C; see Figure 35 - 0.85 1.2 V trr reverse recovery time - 44 - ns Qr recovered charge IS = 5 A; dIS/dt = -100 A/µs; VGS = -10 V; VDS = 30 V - 69 - nC [1] xsa 003aac358 200 ID (A) ID (A) 5 10 10 80 4.5 150 003aac369 100 5 4.5 4 4 60 3.5 3.5 100 3 40 3 50 VGS (V) =2.5 V 20 0 VGS (V) =2.5 V 0 0 2 4 6 8 VDS (V) 10 0 4 6 8 10 VDS (V) Fig 15. Output characteristics: drain current as a function of drain-source voltage; typical values, FET1 Fig 16. Output characteristics: drain current as a function of drain-source voltage; typical values, FET2 BUK9MGP-55PTS_1 Product data sheet 2 © NXP B.V. 2009. All rights reserved. Rev. 01 — 14 May 2009 11 of 20 BUK9MGP-55PTS NXP Semiconductors Dual TrenchPLUS logic level FET 003aac361 30 RDS on (mΩ) 25 003aac372 40 RDS on (mΩ) 20 30 15 10 20 5 0 2 4 6 8 VGS (V) 10 Fig 17. Drain-source on-state resistance as a function of gate-source voltage; typical values, FET1 003aac357 80 gfs (S ) 10 2 6 8 VGS (V) 10 Fig 18. Drain-source on-state resistance as a function of gate-source voltage; typical values, FET2 003aac368 40 gfs (S ) 60 30 40 20 20 10 0 4 0 0 6 12 18 24 I D (A) 30 Fig 19. Forward transconductance as a function of drain current; typical values, FET1 0 10 15 20 25 30 I D (A) Fig 20. Forward transconductance as a function of drain current; typical values, FET2 BUK9MGP-55PTS_1 Product data sheet 5 © NXP B.V. 2009. All rights reserved. Rev. 01 — 14 May 2009 12 of 20 BUK9MGP-55PTS NXP Semiconductors Dual TrenchPLUS logic level FET 003aac894 10−1 003aac895 2.5 ID (A) VGS(th) (V) 10−2 2.0 min typ max 10−3 1.5 10−4 1.0 10−5 0.5 10−6 0 1 2 3 VGS (V) Fig 21. Sub-threshold drain current as a function of gate-source voltage, FET1 and FET2 003aac360 50 RDS on (mΩ) max typ min 0 −60 0 60 120 180 Tj (°C) Fig 22. Gate-source threshold voltage as a function of junction temperature, FET1 and FET2 003aac371 50 RDS on (mΩ) 2.5 3 40 3.5 40 4 4.5 5 3.5 30 2.5 3 4 30 4.5 20 5 20 10 VGS (V) = 10 VGS (V) = 10 0 0 40 80 120 160 I D (A) 200 Fig 23. Drain-source on-state resistance as a function of drain current; typical values, FET1 10 0 40 60 80 I D (A) 100 Fig 24. Drain-source on-state resistance as a function of drain current; typical values, FET2 BUK9MGP-55PTS_1 Product data sheet 20 © NXP B.V. 2009. All rights reserved. Rev. 01 — 14 May 2009 13 of 20 BUK9MGP-55PTS NXP Semiconductors Dual TrenchPLUS logic level FET 001aae823 2.0 001aae823 2.0 a a 1.5 1.5 1.0 1.0 0.5 0.5 0 −60 0 60 120 180 Tj (°C) Fig 25. Normalized drain-source on-state resistance factor as a function of junction temperature, FET1 003aac355 12000 0 −60 0 60 120 180 Tj (°C) Fig 26. Normalized drain-source on-state resistance factor as a function of junction temperature, FET2 003aac367 14000 I D/I sense I D/I sense 12000 11000 10000 10000 8000 9000 6000 8000 4000 2 4 6 8 VGS (V) 10 Fig 27. Ratio of drain current to sense current as a function of gate-source voltage; typical values, FET1 2 6 8 VGS (V) 10 Fig 28. Ratio of drain current to sense current as a function of gate-source voltage; typical values, FET2 BUK9MGP-55PTS_1 Product data sheet 4 © NXP B.V. 2009. All rights reserved. Rev. 01 — 14 May 2009 14 of 20 BUK9MGP-55PTS NXP Semiconductors Dual TrenchPLUS logic level FET 001aae485 3.0 VF(TSD) (V) 2.5 2.0 1.5 0 40 80 120 160 Tj (°C) Fig 29. Temperature sense diode forward voltage as a function of junction temperature; typical values, FET1 and FET2 003aac359 5 003a ac370 5 VGS (V) VGS (V) 4 VDS = 14 V VDS = 14 V 4 VDS = 44 V 3 VDS = 44 V 3 2 2 1 1 0 0 0 20 40 60 QG (nC) 80 Fig 30. Gate-source voltage as a function of turn-on gate charge; typical values, FET1 0 20 QG (nC) 30 Fig 31. Gate-source voltage as a function of turn-on gate charge; typical values, FET2 BUK9MGP-55PTS_1 Product data sheet 10 © NXP B.V. 2009. All rights reserved. Rev. 01 — 14 May 2009 15 of 20 BUK9MGP-55PTS NXP Semiconductors Dual TrenchPLUS logic level FET 003a ac356 104 C (pF) 003a ac366 104 C (pF) Cis s Cis s 103 103 Cos s Cos s Crs s 102 Crs s 102 10 10-1 1 10 VDS (V) 10 10-1 102 Fig 32. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values, FET1 10 VDS (V) 102 Fig 33. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values, FET2 003aac364 60 1 003aac374 50 IS (A) IS (A) 40 40 30 150 °C 150 °C 20 Tj = 25 °C 20 Tj = 25 °C 10 0 0.2 0 0.4 0.6 0.8 1 1.2 VS D (V) Fig 34. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values, FET1 0 1 1.5 VS D (V) 2 Fig 35. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values, FET2 BUK9MGP-55PTS_1 Product data sheet 0.5 © NXP B.V. 2009. All rights reserved. Rev. 01 — 14 May 2009 16 of 20 BUK9MGP-55PTS NXP Semiconductors Dual TrenchPLUS logic level FET 7. Package outline SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c HE y v M A Z 20 11 Q A2 A (A 3) A1 pin 1 index θ Lp L 10 1 e detail X w M bp 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.01 0.019 0.013 0.014 0.009 0.51 0.49 0.30 0.29 0.05 0.419 0.043 0.055 0.394 0.016 inches 0.1 0.012 0.096 0.004 0.089 0.043 0.039 0.01 0.01 Z (1) 0.9 0.4 0.035 0.004 0.016 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT163-1 075E04 MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 36. Package outline SOT163-1 BUK9MGP-55PTS_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 14 May 2009 17 of 20 BUK9MGP-55PTS NXP Semiconductors Dual TrenchPLUS logic level FET 8. Revision history Table 7. Revision history Document ID Release date Data sheet status Change notice Supersedes BUK9MGP-55PTS_1 20090514 Product data sheet - - BUK9MGP-55PTS_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 14 May 2009 18 of 20 BUK9MGP-55PTS NXP Semiconductors Dual TrenchPLUS logic level FET 9. Legal information 9.1 Data sheet status Document status [1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 9.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 9.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. 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Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 9.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. TrenchMOS — is a trademark of NXP B.V. 10. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] BUK9MGP-55PTS_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 14 May 2009 19 of 20 BUK9MGP-55PTS NXP Semiconductors Dual TrenchPLUS logic level FET 11. Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 9.1 9.2 9.3 9.4 10 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General description . . . . . . . . . . . . . . . . . . . . . .1 Features and benefits . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Quick reference data . . . . . . . . . . . . . . . . . . . . .1 Pinning information . . . . . . . . . . . . . . . . . . . . . . .2 Ordering information . . . . . . . . . . . . . . . . . . . . . .2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .3 Thermal characteristics . . . . . . . . . . . . . . . . . . .7 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . .17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . .18 Legal information. . . . . . . . . . . . . . . . . . . . . . . .19 Data sheet status . . . . . . . . . . . . . . . . . . . . . . .19 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Contact information. . . . . . . . . . . . . . . . . . . . . .19 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 14 May 2009 Document identifier: BUK9MGP-55PTS_1