PHILIPS BUK962R2-40C

BUK962R2-40C
N-channel TrenchMOS logic level FET
Rev. 02 — 17 April 2008
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product has been designed and qualified to
the appropriate AEC standard for use in automotive critical applications.
1.2 Features and benefits
„ Low conduction losses due to low
on-state resistance
„ Suitable for logic level gate drive
sources
„ Q101 compliant
„ Suitable for thermally demanding
environments due to 175 °C rating
1.3 Applications
„ 12 V loads
„ General purpose power switching
„ Automotive systems
„ Motors, lamps and solenoids
1.4 Quick reference data
Table 1.
Quick reference
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDS
drain-source voltage
Tj ≥ 25 °C; Tj ≤ 175 °C
-
-
40
V
ID
drain current
VGS = 5 V; Tj = 25 °C;
see Figure 1 and 4
-
-
100
A
Ptot
total power dissipation
Tmb = 25 °C; see Figure 2
-
-
333
W
ID = 100 A; Vsup ≤ 40 V;
RGS = 50 Ω; VGS = 5 V;
Tj(init) = 25 °C; unclamped
-
-
1.2
J
VGS = 5 V; ID = 25 A;
VDS = 32 V; see Figure 14
-
73
-
nC
VGS = 5 V; ID = 25 A;
Tj = 25 °C; see Figure 12, 11
and 13
-
2
2.2
mΩ
[1][2]
Avalanche ruggedness
EDS(AL)S
non-repetitive
drain-source
avalanche energy
Dynamic characteristics
QGD
gate-drain charge
Static characteristics
RDSon
drain-source on-state
resistance
[1]
Continuous current is limited by package.
[2]
Refer to document 9397 750 12572 for further information.
BUK962R2-40C
NXP Semiconductors
N-channel TrenchMOS logic level FET
2. Pinning information
Table 2.
Pinning
Pin
Symbol
Description
1
G
gate
2
D
drain
3
S
source
mb
D
mounting base;
connected to drain
Simplified outline
Graphic symbol
D
mb
G
mbb076
S
2
1
3
SOT404 (D2PAK)
3. Ordering information
Table 3.
Ordering information
Type number
BUK962R2-40C
Package
Name
Description
Version
D2PAK
plastic single-ended surface-mounted package (D2PAK); 3 leads (one lead SOT404
cropped)
4. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
Max
Unit
-
40
V
VDS
drain-source voltage
Tj ≥ 25 °C; Tj ≤ 175 °C
RGS = 20 kΩ
VDGR
drain-gate voltage
VGS
gate-source voltage
ID
drain current
-
40
V
-15
15
V
[1]
-
280
A
VGS = 5 V; Tj = 100 °C; see Figure 1
[2][3]
-
100
A
VGS = 5 V; Tj = 25 °C; see Figure 1 and 4
[2][3]
Tmb = 25 °C; VGS = 5 V; see Figure 1
-
100
A
IDM
peak drain current
Tmb = 25 °C; tp ≤ 10 μs; pulsed; see Figure 4
-
1130
A
Ptot
total power dissipation
Tmb = 25 °C; see Figure 2
-
333
W
Tstg
storage temperature
-55
175
°C
Tj
junction temperature
-55
175
°C
-
1.2
J
-
-
J
Avalanche ruggedness
EDS(AL)S non-repetitive
drain-source avalanche
energy
ID = 100 A; Vsup ≤ 40 V; RGS = 50 Ω;
VGS = 5 V; Tj(init) = 25 °C; unclamped
EDS(AL)R repetitive drain-source
avalanche energy
see Figure 3
[4][5]
[6]
Source-drain diode
IS
source current
Tmb = 25 °C
ISM
peak source current
tp ≤ 10 μs; pulsed; Tmb = 25 °C
[2][3]
BUK962R2-40C_2
Product data sheet
-
100
A
-
1130
A
© NXP B.V. 2008. All rights reserved.
Rev. 02 — 17 April 2008
2 of 13
BUK962R2-40C
NXP Semiconductors
N-channel TrenchMOS logic level FET
[1]
Current is limited by chip power dissipation rating.
[2]
Continuous current is limited by package.
[3]
Refer to document 9397 750 12572 for further information.
[4]
Single-pulse avalanche rating limited by maximum junction temperature of 175 °C.
[5]
Repetitive avalanche rating limited by an average junction temperature of 170 °C.
[6]
Refer to application note AN10273 for further information.
003aac288
300
03na19
120
ID
(A)
Pder
(%)
80
200
100
40
(1)
0
0
0
50
100
150
Tmb (°C)
0
200
50
100
150
200
Tmb (°C)
VGS • 5V
P der =
(1) Capped at 100 A due to package.
Fig 1. Continuous drain current as a function of
mounting base temperature
P tot
P tot (25°C )
× 100 %
Fig 2. Normalized total power dissipation as a
function of mounting base temperature
003aac266
103
IAL
(A)
102
(1)
(2)
10
(3)
1
10-1
10-3
10-2
10-1
1 t (ms) 10
AL
(1) Singleípulse;T j = 25 °C.
(2) Singleípulse;T j = 150 °C.
(3) Repetitive.
Fig 3. Single-pulse and repetitive avalanche rating; avalanche current as a function of avalanche time
BUK962R2-40C_2
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 02 — 17 April 2008
3 of 13
BUK962R2-40C
NXP Semiconductors
N-channel TrenchMOS logic level FET
003aac289
104
ID
(A)
Limit RDSon = VDS / ID
103
tp = 10 μs
100 μs
102
(1)
10
DC
1 ms
10 ms
100 ms
1
10-1
10-1
1
10
102
VDS (V)
Tmb = 25 °C; IDM is single pulse
(1) Capped at 100 A due to package.
Fig 4. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
BUK962R2-40C_2
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 02 — 17 April 2008
4 of 13
BUK962R2-40C
NXP Semiconductors
N-channel TrenchMOS logic level FET
5. Thermal characteristics
Table 5.
Thermal characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Rth(j-a)
thermal resistance
from junction to
ambient
minimum footprint; mounted on a
printed circuit
-
50
-
K/W
Rth(j-mb)
thermal resistance
from junction to
mounting base
see Figure 5
-
-
0.45
K/W
003aab020
1
Zth(j-mb)
(K/W) δ = 0.5
0.2
10−1
0.1
0.05
0.02
10−2
δ=
P
tp
T
single shot
t
tp
T
10−3
10−6
10−5
10−4
10−3
10−2
10−1
tp (s)
1
Fig 5. Transient thermal impedance from junction to mounting base as a function of pulse duration
6. Characteristics
Table 6.
Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
ID = 250 μA; VGS = 0 V;
Tj = 25 °C
40
-
-
V
ID = 250 μA; VGS = 0 V;
Tj = -55 °C
36
-
-
V
1
1.5
2
V
ID = 1 mA; VDS = VGS;
Tj = -55 °C; see Figure 9
-
-
2.3
V
ID = 1 mA; VDS = VGS;
Tj = 175 °C; see Figure 9
0.5
-
-
V
VDS = 40 V; VGS = 0 V;
Tj = 175 °C
-
-
500
μA
VDS = 40 V; VGS = 0 V; Tj = 25 °C
-
0.02
1
μA
Static characteristics
V(BR)DSS
VGS(th)
IDSS
drain-source
breakdown voltage
gate-source threshold ID = 1 mA; VDS = VGS; Tj = 25 °C;
voltage
see Figure 9 and 10
drain leakage current
BUK962R2-40C_2
Product data sheet
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Rev. 02 — 17 April 2008
5 of 13
BUK962R2-40C
NXP Semiconductors
N-channel TrenchMOS logic level FET
Table 6.
Characteristics …continued
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
IGSS
gate leakage current
VDS = 0 V; VGS = 15 V; Tj = 25 °C
-
2
100
nA
VDS = 0 V; VGS = -15 V;
Tj = 25 °C
-
2
100
nA
VGS = 4.5 V; ID = 25 A; Tj = 25 °C
-
-
2.45
mΩ
VGS = 10 V; ID = 25 A; Tj = 25 °C
-
1.6
1.9
mΩ
VGS = 5 V; ID = 25 A; Tj = 175 °C;
see Figure 11
-
-
4.2
mΩ
VGS = 5 V; ID = 25 A; Tj = 25 °C;
see Figure 12, 11 and 13
-
2
2.2
mΩ
IS = 25 A; VGS = 0 V; Tj = 25 °C;
see Figure 16
-
0.85
1.2
V
-
70
-
ns
-
60
-
nC
-
120
-
nC
-
30
-
nC
-
73
-
nC
RDSon
drain-source on-state
resistance
Source-drain diode
VSD
source-drain voltage
trr
reverse recovery time IS = 25 A; dIS/dt = 100 A/μs;
VGS = 0 V; VDS = 30 V
recovered charge
Qr
Dynamic characteristics
QG(tot)
total gate charge
QGS
gate-source charge
QGD
gate-drain charge
Ciss
input capacitance
Coss
output capacitance
Crss
reverse transfer
capacitance
td(on)
turn-on delay time
tr
rise time
td(off)
ID = 25 A; VDS = 32 V; VGS = 5 V;
see Figure 14
VGS = 0 V; VDS = 25 V;
f = 1 MHz; Tj = 25 °C;
see Figure 15
-
12487
16700
pF
-
1323
1600
pF
-
938
1290
pF
-
130
-
ns
-
310
-
ns
turn-off delay time
-
380
-
ns
tf
fall time
-
250
-
ns
LD
internal drain
inductance
from upper edge of drain
mounting base to centre of die
-
2.5
-
nH
LS
internal source
inductance
from source lead to source bond
pad
-
7.5
-
nH
VDS = 30 V; RL = 1.2 Ω;
VGS = 5 V; RG(ext) = 10 Ω
BUK962R2-40C_2
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 02 — 17 April 2008
6 of 13
BUK962R2-40C
NXP Semiconductors
N-channel TrenchMOS logic level FET
003aac256
240
gfs
(S)
003aac253
300
ID
(A)
180
200
120
Tj = 175 °C
100
60
25 °C
0
0
0
20
40
ID (A)
T j = 25 °C;VDS = 25V
2
VGS (V)
4
VDS = 25V
Fig 6. Forward transconductance as a function of
drain current; typical values
003aac252
300
ID
(A)
0
60
VGS (V) = 10
Fig 7. Transfer characteristics: drain current as a
function of gate-source voltage; typical values
03aa33
2.5
VGS(th)
(V)
2
3.8
3.6
200
max
3.2
1.5
typ
1
min
3
100
2.8
0.5
2.6
2.4
0
0
1
2
3
4
VDS (V)
5
T j = 25 °C
0
-60
60
120
Tj (°C)
180
ID = 1 m A;VDS = VGS
Fig 8. Output characteristics: drain current as a
function of drain-source voltage; typical values
Fig 9. Gate-source threshold voltage as a function of
junction temperature
BUK962R2-40C_2
Product data sheet
0
© NXP B.V. 2008. All rights reserved.
Rev. 02 — 17 April 2008
7 of 13
BUK962R2-40C
NXP Semiconductors
N-channel TrenchMOS logic level FET
03aa36
10-1
ID
(A)
03aa27
2
a
10-2
1.5
10-3
min
typ
max
1
10-4
0.5
10-5
10-6
0
1
2
3
VGS (V)
T j = 25 °C;VDS = VGS
a=
Fig 10. Sub-threshold drain current as a function of
gate-source voltage
6
RDSon V (V) = 2.8
GS
(mΩ)
0
-60
003aac287
3
0
60
120
Tj (°C)
180
R DSon
R DSon (25°C )
Fig 11. Normalized drain-source on-state resistance
factor as a function of junction temperature
003aac286
10
RDSon
(mΩ)
3.2
5
8
4
6
3
4
3.6
3.8
10
2
2
0
1
0
50
100
150
200
ID (A)
250
T j = 25 °C
0
10
VGS (V)
15
T j = 25 °C; ID = 25 A
Fig 12. Drain-source on-state resistance as a function
of drain current; typical values
Fig 13. Drain-source on-state resistance as a function
of gate-source voltage; typical values
BUK962R2-40C_2
Product data sheet
5
© NXP B.V. 2008. All rights reserved.
Rev. 02 — 17 April 2008
8 of 13
BUK962R2-40C
NXP Semiconductors
N-channel TrenchMOS logic level FET
003aac254
10
VGS
(V)
VDS = 14 V
8
003aac255
24000
C
(pF)
20000
Ciss
32 V
16000
6
12000
Coss
4
Crss
8000
2
4000
0
0
50
100
150
QG (nC)
0
10-1
200
T j = 25 °C; ID = 25 A
1
10
VDS (V)
102
VGS = 0V ; f = 1 M H z
Fig 14. Gate-source voltage as a function of gate
charge; typical values
Fig 15. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
003aac261
250
IS
(A)
200
150
Tj = 175 °C
100
25 °C
50
0
0
0.5
1
1.5
VSD (V)
2
VGS = 0V
Fig 16. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values
BUK962R2-40C_2
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 02 — 17 April 2008
9 of 13
BUK962R2-40C
NXP Semiconductors
N-channel TrenchMOS logic level FET
7. Package outline
SOT404
Plastic single-ended surface-mounted package (D2PAK); 3 leads (one lead cropped)
A
A1
E
mounting
base
D1
D
HD
2
Lp
1
3
c
b
e
e
Q
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
b
c
D
max.
D1
E
e
Lp
HD
Q
mm
4.50
4.10
1.40
1.27
0.85
0.60
0.64
0.46
11
1.60
1.20
10.30
9.70
2.54
2.90
2.10
15.80
14.80
2.60
2.20
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
05-02-11
06-03-16
SOT404
Fig 17. Package outline SOT404 (D2PAK)
BUK962R2-40C_2
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 02 — 17 April 2008
10 of 13
BUK962R2-40C
NXP Semiconductors
N-channel TrenchMOS logic level FET
8. Revision history
Table 7.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
BUK962R2-40C_2
20080417
Product data sheet
-
BUK962R2-40C_1
-
-
Modifications:
BUK962R2-40C_1
•
Table 6: VDS condition for IDSS corrected.
20080328
product data sheet
BUK962R2-40C_2
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 02 — 17 April 2008
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BUK962R2-40C
NXP Semiconductors
N-channel TrenchMOS logic level FET
9. Legal information
9.1
Data sheet status
Document status[1][2]
Product status[3]
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
Definition
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
9.2
Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
9.3
Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
9.4
Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
TrenchMOS — is a trademark of NXP B.V.
10. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: [email protected]
BUK962R2-40C_2
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 02 — 17 April 2008
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BUK962R2-40C
NXP Semiconductors
N-channel TrenchMOS logic level FET
11. Contents
1
1.1
1.2
1.3
1.4
2
3
4
5
6
7
8
9
9.1
9.2
9.3
9.4
10
11
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General description . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data . . . . . . . . . . . . . . . . . . . . 1
Pinning information . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
Thermal characteristics . . . . . . . . . . . . . . . . . . 5
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 11
Legal information. . . . . . . . . . . . . . . . . . . . . . . 12
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Contact information. . . . . . . . . . . . . . . . . . . . . 12
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 17 April 2008
Document identifier: BUK962R2-40C_2