PLL Frequency Synthesizer ADF4107 Data Sheet FEATURES GENERAL DESCRIPTION 7.0 GHz bandwidth 2.7 V to 3.3 V power supply Separate charge pump supply (VP) allows extended tuning voltage in 3 V systems Programmable dual-modulus prescaler 8/9, 16/17, 32/33, 64/65 Programmable charge pump currents Programmable antibacklash pulse width 3-wire serial interface Analog and digital lock detect Hardware and software power-down mode The ADF4107 frequency synthesizer can be used to implement local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. It consists of a low noise digital PFD (phase frequency detector), a precision charge pump, a programmable reference divider, programmable A and B counters, and a dual-modulus prescaler (P/P + 1). The A (6-bit) and B (13-bit) counters, in conjunction with the dual-modulus prescaler (P/P + 1), implement an N divider (N = BP + A). In addition, the 14-bit reference counter (R counter), allows selectable REFIN frequencies at the PFD input. A complete PLL (phase-locked loop) can be implemented if the synthesizer is used with an external loop filter and VCO (voltage controlled oscillator). Its very high bandwidth means that frequency doublers can be eliminated in many high frequency systems, simplifying system architecture and reducing cost. APPLICATIONS Broadband wireless access Satellite systems Instrumentation Wireless LANs Base stations for wireless radio FUNCTIONAL BLOCK DIAGRAM AVDD DVDD VP RSET CPGND REFERENCE 14-BIT R COUNTER REFIN PHASE FREQUENCY DETECTOR CHARGE PUMP CP 14 R COUNTER LATCH CLK DATA LE 24-BIT INPUT REGISTER SDOUT FUNCTION LATCH 22 FROM FUNCTION LATCH A, B COUNTER LATCH CURRENT SETTING 1 CURRENT SETTING 2 CPI3 CPI2 CPI1 CPI6 CPI5 CPI4 HIGH Z 19 AVDD MUXOUT MUX 13 N = BP + A RFINA RFINB LOCK DETECT 13-BIT B COUNTER SDOUT LOAD PRESCALER P/P + 1 LOAD M3 M2 M1 6-BIT A COUNTER 03338-001 ADF4107 6 CE AGND DGND Figure 1. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. 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Technical Support www.analog.com ADF4107 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Phase Frequency Detector and Charge Pump ..............................9 Applications ....................................................................................... 1 MUXOUT and Lock Detect...................................................... 10 General Description ......................................................................... 1 Input Shift Register .................................................................... 10 Functional Block Diagram .............................................................. 1 Latch Summary........................................................................... 11 Revision History ............................................................................... 2 Reference Counter Latch Map .................................................. 12 Specifications..................................................................................... 3 AB Counter Latch Map ............................................................. 13 Timing Characteristics ................................................................ 4 Function Latch Map ................................................................... 14 Absolute Maximum Ratings ............................................................ 5 Initialization Latch Map ............................................................ 15 ESD Caution .................................................................................. 5 Function Latch ............................................................................ 16 Pin Configurations and Function Descriptions ........................... 6 Initialization Latch ..................................................................... 17 Typical Performance Characteristics ............................................. 7 Device Programming after Initial Power-Up ............................. 17 Functional Description .................................................................... 9 Applications..................................................................................... 18 Reference Input Stage................................................................... 9 Local Oscillator for LMDS Base Station Transmitter ............ 18 RF Input Stage ............................................................................... 9 Interfacing ................................................................................... 19 Prescaler (P/P + 1) ........................................................................ 9 PCB Design Guidelines for Chip Scale Package .................... 19 A and B Counters ......................................................................... 9 Outline Dimensions ....................................................................... 20 R Counter ...................................................................................... 9 Ordering Guide .......................................................................... 20 REVISION HISTORY 3/13—Rev. C to Rev. D Changed RFINA to RFINB Parameter from ±320 mV to ±600 mV, Table 3 ................................................................................................ 5 Updated Outline Dimensions ....................................................... 20 Changes to Ordering Guide .......................................................... 20 11/12—Rev. B to Rev. C Changed EVAL-ADF411xEBZ1 to EV-ADF411XSD1Z ............. 4 Changes to Table 3 ............................................................................ 5 Updated Outline Dimensions ....................................................... 20 Changes to Ordering Guide .......................................................... 20 4/07—Rev. 0 to Rev. A Updated Format .................................................................. Universal Changes to REFIN Characteristics Section ...................................3 Changes to Noise Characteristics Section ......................................4 Changes to Absolute Maximum Ratings Section ..........................5 Changes to Figure 23...................................................................... 12 Changes to Ordering Guide .......................................................... 20 5/03—Revision 0: Initial Version 9/11—Rev. A to Rev. B Changes to Normalized Phase Noise Floor (PNSYNTH) Parameter, Table 1 ................................................................................................ 3 Added Normalized 1/f Noise (PN1_f) Parameter and Endnote 11, Table 1 ................................................................................................ 3 Changed EVAL-ADF4107EB1 to EVAL-ADF411xEBZ1 ............ 4 Changes to Figure 4 and Table 4 ..................................................... 6 Updated Outline Dimensions ....................................................... 20 Changes to Ordering Guide .......................................................... 20 Rev. D | Page 2 of 20 Data Sheet ADF4107 SPECIFICATIONS AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMAX to TMIN, unless otherwise noted. Table 1. Parameter RF CHARACTERISTICS RF Input Frequency (RFIN) 3 RF Input Sensitivity Maximum Allowable Prescaler Output Frequency 4 REFIN CHARACTERISTICS REFIN Input Frequency REFIN Input Sensitivity 5 REFIN Input Capacitance REFIN Input Current PHASE DETECTOR Phase Detector Frequency 7 CHARGE PUMP ICP Sink/Source High Value Low Value Absolute Accuracy RSET Range ICP Three-State Leakage Sink and Source Current Matching ICP vs. VCP ICP vs. Temperature LOGIC INPUTS VIH, Input High Voltage VIL, Input Low Voltage IINH, IINL, Input Current CIN, Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage VOH, Output High Voltage IOH VOL, Output Low Voltage POWER SUPPLIES AVDD DVDD VP IDD 8 (AIDD + DIDD) IP Power-Down Mode 9 (AIDD + DIDD) NOISE CHARACTERISTICS Normalized Phase Noise Floor (PNSYNTH) 10 Normalized 1/f Noise (PN1_f) 11 B Version 1 B Chips 2 (Typ) Unit Test Conditions/Comments 1.0/7.0 –5/+5 300 1.0/7.0 –5/+5 300 GHz min/max dBm min/max MHz max See Figure 18 for input circuit 20/250 0.8/VDD 10 ±100 20/250 0.8/VDD 10 ±100 MHz min/max V p-p min/max pF max µA max For f < 20 MHz, ensure slew rate >50 V/µs Biased at AVDD/2 6 104 104 MHz max ABP = 0,0 (2.9 ns antibacklash pulse width) Programmable; see Figure 25 5 625 2.5 3.0 to 11 1 2 1.5 2 5 625 2.5 3.0 to 11 1 2 1.5 2 mA typ µA typ % typ kΩ typ nA typ % typ % typ % typ With RSET = 5.1 kΩ 1.4 0.6 ±1 10 1.4 0.6 ±1 10 V min V max µA max pF max 1.4 1.4 V min VDD − 0.4 100 0.4 VDD − 0.4 100 0.4 V min µA max V max 2.7/3.3 AVDD AVDD/5.5 17 0.4 10 2.7/3.3 AVDD AVDD/5.5 15 0.4 10 V min/V max V min/V max mA max mA max µA typ AVDD ≤ VP ≤ 5.5 V 15 mA typ TA = 25°C −223 −223 dBc/Hz typ −122 −122 dBc/Hz typ PLL loop BW = 500 kHz, measured at 100 kHz offset 10 kHz offset; normalized to 1 GHz Rev. D | Page 3 of 20 With RSET = 5.1 kΩ See Figure 25 0.5 V ≤ VCP ≤ VP − 0.5 V 0.5 V ≤ VCP ≤ VP − 0.5 V VCP = VP/2 Open-drain output chosen; 1 kΩ pull-up resistor to 1.8 V CMOS output chosen IOL = 500 µA ADF4107 Data Sheet B Version1 B Chips2 (Typ) Unit −93 −76 −83 −93 −76 −83 dBc/Hz typ dBc/Hz typ dBc/Hz typ −90/−92 −90/−92 dBc typ 6400 MHz Output14 −65/−70 −65/−70 dBc typ 6400 MHz Output15 −70/−75 −70/−75 dBc typ Parameter Phase Noise Performance12 900 MHz Output13 6400 MHz Output14 6400 MHz Output15 Spurious Signals 900 MHz Output13 Test Conditions/Comments @ VCO output @ 1 kHz offset and 200 kHz PFD frequency @ 1 kHz offset and 200 kHz PFD frequency @ 1 kHz offset and 1 MHz PFD frequency @ 200 kHz/400 kHz and 200 kHz PFD frequency @ 200 kHz/400 kHz and 200 kHz PFD frequency @ 1 MHz/2 MHz and 1 MHz PFD frequency 1 Operating temperature range (B version) is −40°C to +85°C. The B chip specifications are given as typical values. 3 Use a square wave for lower frequencies, below the minimum stated. 4 This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that is less than this value. 5 AVDD = DVDD = 3 V. 6 AC-coupling ensures AVDD/2 bias. 7 Guaranteed by design. Sample tested to ensure compliance. 8 TA = 25°C; AVDD = DVDD = 3 V; P = 32; RFIN = 7.0 GHz. 9 TA = 25°C; AVDD = DVDD = 3.3 V; R = 16,383; A = 63; B = 891; P = 32; RFIN = 7.0 GHz. 10 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value) and 10 log(FPFD). PNSYNTH = PNTOT – 20 logN −10 logFPFD. 11 The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, fRF, and at a frequency offset, f, is given by PN = PN1_f + 10 log(10 kHz/f) + 20 log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL. 12 The phase noise is measured with the EV-ADF411xSD1Z evaluation board and the HP8562E spectrum analyzer. The spectrum analyzer provides the REFIN for the synthesizer (fREFOUT = 10 MHz @ 0 dBm). 13 fREFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 900 MHz; N = 4500; loop BW = 20 kHz. 14 fREFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 6400 MHz; N = 32,000; loop BW = 20 kHz. 15 fREFIN = 10 MHz; fPFD = 1 MHz; offset frequency = 1 kHz; fRF = 6400 MHz; N = 6400; loop BW = 100 kHz. 2 TIMING CHARACTERISTICS AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMAX to TMIN, unless otherwise noted. 1 Table 2. Limit2 (B Version) 10 10 25 25 10 20 Parameter t1 t2 t3 t4 t5 t6 2 Test Conditions/Comments DATA to CLOCK setup time DATA to CLOCK hold time CLOCK high duration CLOCK low duration CLOCK to LE setup time LE pulse width Guaranteed by design but not production tested. Operating temperature range (B Version) is −40°C to +85°C. t3 t4 CLOCK t1 DATA DB23 (MSB) t2 DB22 DB2 DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1) t6 LE t5 03338-002 1 Unit ns min ns min ns min ns min ns min ns min LE Figure 2. Timing Diagram Rev. D | Page 4 of 20 Data Sheet ADF4107 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter AVDD to GND 1 AVDD to DVDD VP to GND VP to AVDD Digital I/O Voltage to GND Analog I/O Voltage to GND REFIN, RFINA, RFINB to GND RFINA to RFINB Operating Temperature Range Industrial (B Version) Storage Temperature Range Maximum Junction Temperature TSSOP θJA Thermal Impedance LFCSP θJA Thermal Impedance (Paddle Soldered) Reflow Soldering Peak Temperature Time at Peak Temperature Transistor Count CMOS Bipolar 1 Rating −0.3 V to +3.6 V −0.3 V to +0.3 V −0.3 V to +5.8 V −0.3 V to +5.8 V −0.3 V to VDD + 0.3 V −0.3 V to Vp + 0.3 V −0.3 V to VDD + 0.3 V ±600 mV −40°C to +85°C −65°C to +125°C 150°C 112°C/W 30.4°C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. This device is a high performance RF integrated circuit with an ESD rating of <2 kV, and it is ESD sensitive. Proper precautions should be taken for handling and assembly. ESD CAUTION 260°C 40 sec 6425 303 GND = AGND = DGND = 0 V. Rev. D | Page 5 of 20 ADF4107 Data Sheet 20 19 18 17 16 CP RSET VP DVDD DVDD PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VP 16 CP 2 15 DVDD CPGND 3 14 MUXOUT ADF4107 CPGND AGND AGND RFINB RFINA TOP VIEW 13 LE (Not to Scale) 12 DATA RFINB 5 11 CLK AVDD 7 10 CE REFIN 8 9 DGND NOTES: 1. TRANSISTOR COUNT 6425 (CMOS), 303 (BIPOLAR). TOP VIEW (Not to Scale) 15 14 13 12 11 MUXOUT LE DATA CLK CE NOTES 1. TRANSISTOR COUNT 6425 (CMOS), 303 (BIPOLAR). 2. THE EXPOSED PAD MUST BE CONNECTED TO AGND. 03338-003 RFINA 6 ADF4107 AVDD 6 AVDD 7 REFIN 8 DGND 9 DGND 10 AGND 4 1 2 3 4 5 Figure 3. Pin Configuration, TSSOP 03338-004 RSET 1 Figure 4. Pin Configuration, LFCSP Table 4. Pin Function Descriptions Pin No. TSSOP LFCSP 1 19 Mnemonic RSET 2 20 CP 3 4 5 1 2, 3 4 CPGND AGND RFINB 6 7 5 6, 7 RFINA AVDD 8 8 REFIN 9 10 9, 10 11 DGND CE 11 12 CLK 12 13 DATA 13 14 LE 14 15 MUXOUT 15 16, 17 DVDD 16 18 VP EP Description Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. The nominal voltage potential at the RSET pin is 0.66 V. The relationship between ICP and RSET is 25.5 I CP MAX = R SET so, with RSET = 5.1 kΩ, ICP MAX = 5 mA. Charge Pump Output. When enabled, this pin provides ±ICP to the external loop filter, which in turn drives the external VCO. Charge Pump Ground. This is the ground return path for the charge pump. Analog Ground. This is the ground return path of the prescaler. Complementary Input to the RF Prescaler. This point must be decoupled to the ground plane with a small bypass capacitor, typically 100 pF. See Figure 18. Input to the RF Prescaler. This small signal input is ac-coupled to the external VCO. Analog Power Supply. This voltage may range from 2.7 V to 3.3 V. Decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. AVDD must be the same value as DVDD. Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input resistance of 100 kΩ. See Figure 17. This input can be driven from a TTL or CMOS crystal oscillator or it can be ac-coupled. Digital Ground. Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into threestate mode. Taking the pin high powers up the device, depending on the status of the power-down bit, F2. Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input. Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a high impedance CMOS input. Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four latches, the latch being selected using the control bits. This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency to be accessed externally. Digital Power Supply. This may range from 2.7 V to 3.3 V. Decoupling capacitors to the digital ground plane should be placed as close as possible to this pin. DVDD must be the same value as AVDD. Charge Pump Power Supply. This voltage should be greater than or equal to VDD. In systems where VDD is 3 V, it can be set to 5 V and used to drive a VCO with a tuning range of up to 5 V. Exposed Pad. The exposed pad must be connected to AGND. Rev. D | Page 6 of 20 Data Sheet ADF4107 TYPICAL PERFORMANCE CHARACTERISTICS –40 10dB/DIV RL = –40dBc/Hz RMS NOISE = 0.36° –50 PHASE NOISE (dBc/Hz) –60 –70 –80 –90 –100 –110 03338-008 –120 03338-005 –130 –140 100Hz Figure 5. Parameter Data for the RF Input Figure 8. Integrated Phase Noise (900 MHz, 200 kHz, 20 kHz) 0 0 VDD = 3V VP = 3V REF LEVEL = –14.0dBm –10 –5 OUTPUT POWER (dB) –20 –10 –15 –20 TA = +85°C –30 –40 –50 –60 –70 –91.0dBc/Hz TA = –40°C 0 1 2 3 4 5 03338-009 TA = +25°C –30 –90 –100 6 –400kHz –200kHz RF INPUT FREQUENCY (GHz) 900MHz 200kHz 400kHz FREQUENCY Figure 6. Input Sensitivity Figure 9. Reference Spurs (900 MHz, 200 kHz, 20 kHz) 0 0 –20 –30 –40 REF LEVEL = –10dBm VDD = 3V, VP = 5V ICP = 5mA PFD FREQUENCY = 200kHz LOOP BANDWIDTH = 20kHz RES BANDWIDTH = 10Hz VIDEO BANDWIDTH = 10Hz SWEEP = 1.9 SECONDS AVERAGES = 10 –10 –20 OUTPUT POWER (dB) REF LEVEL = –14.3dBm –10 –50 –60 –93.0dBc/Hz –70 –80 –30 –40 –50 –60 –70 03338-007 –80 –90 –100 –2kHz –1kHz 900MHz 1kHz VDD = 3V, VP = 5V ICP = 5mA PFD FREQUENCY = 1MHz LOOP BANDWIDTH = 100kHz RES BANDWIDTH = 10Hz VIDEO BANDWIDTH = 10Hz SWEEP = 1.9 SECONDS AVERAGES = 10 –83.5dBc/Hz 03338-010 OUTPUT POWER (dB) VDD = 3V, VP = 5V ICP = 5mA PFD FREQUENCY = 200kHz LOOP BANDWIDTH = 20kHz RES BANDWIDTH = 1kHz VIDEO BANDWIDTH = 1kHz SWEEP = 2.5 SECONDS AVERAGES = 30 –80 –25 03338-006 RF INPUT POWER (dBm) 1MHz FREQUENCY OFFSET FROM 900MHz CARRIER –90 –100 2kHz –2kHz FREQUENCY –1kHz 6400MHz 1kHz 2kHz FREQUENCY Figure 7. Phase Noise (900 MHz, 200 kHz, 20 kHz) Figure 10. Phase Noise (6.4 GHz, 1 MHz, 100 kHz) Rev. D | Page 7 of 20 ADF4107 Data Sheet –40 –5 10dB/DIV RL = –40dBc/Hz RMS NOISE = 1.8° –70 –80 –90 –100 –110 03338-011 –120 –130 –25 –35 –45 –55 –65 –75 –85 03338-014 PHASE NOISE (dBc/Hz) –60 –140 100Hz VDD = 3V VP = 5V –15 FIRST REFERENCE SPUR (dBc) –50 –95 –105 0 1MHz 1 2 5 –120 0 VDD = 3V, VP = 5V ICP = 5mA PFD FREQUENCY = 1MHz LOOP BANDWIDTH = 100kHz RES BANDWIDTH = 1kHz VIDEO BANDWIDTH = 1kHz SWEEP = 13 SECONDS AVERAGES = 1 –20 –30 –40 VDD = 3V VP = 5V –130 PHASE NOISE (dBc/Hz) REF LEVEL = –10dBm –10 –50 –65.0dBc –66.0dBc –60 –70 –80 –140 –150 –160 03338-012 –170 –90 –100 –2kHz –1kHz 5800MHz 1kHz 03338-015 OUTPUT POWER (dB) 4 Figure 14. Reference Spurs vs. VTUNE (6.4 GHz, 1 MHz, 100 kHz) Figure 11. Integrated Phase Noise (6.4 GHz, 1 MHz, 100 kHz) –180 10k 2kHz 100k 1M 10M 100M PHASE DETECTOR FREQUENCY (Hz) FREQUENCY (MHz) Figure 12. Reference Spurs (6.4 GHz, 1 MHz, 100 kHz) Figure 15. Phase Noise (Referred to CP Output) vs. PFD Frequency –6 –60 VDD = 3V VP = 3V –5 –4 VP = 5V ICP SETTLING = 5mA –3 –70 –2 ICP (mA) PHASE NOISE (dBc/Hz) 3 TUNING VOLTAGE (V) FREQUENCY OFFSET FROM 5800MHz CARRIER –80 –1 0 1 2 3 –90 –20 0 20 40 60 80 03338-016 –100 –40 03338-013 4 5 6 0 100 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 VCP (V) TEMPERATURE (°C) Figure 13. Phase Noise (6.4 GHz, 1 MHz, 100 kHz) vs. Temperature Figure 16. Charge Pump Output Characteristics Rev. D | Page 8 of 20 5.0 Data Sheet ADF4107 FUNCTIONAL DESCRIPTION REFERENCE INPUT STAGE A AND B COUNTERS The reference input stage is shown in Figure 17. SW1 and SW2 are normally closed switches. SW3 is normally open. When power-down is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures that there is no loading of the REFIN pin on power-down. The A and B CMOS counters combine with the dual-modulus prescaler to allow a wide ranging division ratio in the PLL feedback counter. The counters are specified to work when the prescaler output is 300 MHz or less. Thus, with an RF input frequency of 4.0 GHz, a prescaler value of 16/17 is valid but a value of 8/9 is not valid. POWER-DOWN CONTROL Pulse Swallow Function 100kΩ SW2 REFIN TO R COUNTER NC BUFFER NO SW3 fVCO is the output frequency of external voltage controlled oscillator (VCO). P is the preset modulus of dual-modulus prescaler (8/9, 16/17). B is the preset divide ratio of binary 13-bit counter (3 to 8191). A is the preset divide ratio of binary 6-bit swallow counter (0 to 63). fREFIN is the external reference frequency oscillator. RF INPUT STAGE The RF input stage is shown in Figure 18. It is followed by a 2-stage limiting amplifier to generate the CML clock levels needed for the prescaler. 500Ω f REFIN R where: Figure 17. Reference Input Stage BIAS GENERATOR f VCO P B A 03338-017 SW1 The A and B counters, in conjunction with the dual-modulus prescaler, make it possible to generate output frequencies that are spaced only by the reference frequency divided by R. The equation for the VCO frequency is as follows: N = BP + A 1.6V AVDD 13-BIT B COUNTER 500Ω FROM RF INPUT STAGE PRESCALER P/P + 1 RFINA MODULUS CONTROL LOAD LOAD 6-BIT A COUNTER RFINB N DIVIDER Figure 19. A and B Counters 03338-018 AGND TO PFD 03338-019 NC R COUNTER Figure 18. RF Input Stage PRESCALER (P/P + 1) The dual-modulus prescaler (P/P + 1), along with the A and B counters, enables the large division ratio, N, to be realized (N = BP + A). The dual-modulus prescaler, operating at CML levels, takes the clock from the RF input stage and divides it down to a manageable frequency for the CMOS A and CMOS B counters. The prescaler is programmable. It can be set in software to 8/9, 16/17, 32/33, or 64/65. It is based on a synchronous 4/5 core. A minimum divide ratio is possible for fully contiguous output frequencies. This minimum is determined by P, the prescaler value, and is given by: (P2 − P). The 14-bit R counter allows the input reference frequency to be divided down to produce the reference clock to the phase frequency detector (PFD). Division ratios from 1 to 16,383 are allowed. PHASE FREQUENCY DETECTOR AND CHARGE PUMP The phase frequency detector (PFD) takes inputs from the R counter and N counter (N = BP + A) and produces an output proportional to the phase and frequency difference between them. Figure 20 is a simplified schematic. The PFD includes a programmable delay element that controls the width of the antibacklash pulse. This pulse ensures that there is no dead zone in the PFD transfer function and minimizes phase noise and reference spurs. Two bits in the reference counter latch, ABP2 and ABP1, control the width of the pulse. Use of the minimum antibacklash pulse width is not recommended. See Figure 23. Rev. D | Page 9 of 20 ADF4107 Data Sheet DVDD VP CHARGE PUMP HI D1 Q1 UP ANALOG LOCK DETECT U1 R DIVIDER DIGITAL LOCK DETECT CLR1 R COUNTER OUTPUT MUX CONTROL MUXOUT PROGRAMMABLE DELAY N COUNTER OUTPUT U3 CP SDOUT HI ABP1 DGND CLR2 DOWN D2 Q2 03338-021 ABP2 Figure 21. MUXOUT Circuit 03338-020 U2 N DIVIDER CPGND Figure 20. PFD Simplified Schematic and Timing (in Lock) MUXOUT AND LOCK DETECT The output multiplexer on the ADF4107 allows the user to access various internal points on the chip. The state of MUXOUT is controlled by M3, M2, and M1 in the function latch. Figure 25 shows the full truth table. Figure 21 shows the MUXOUT section in block diagram form. Lock Detect MUXOUT can be programmed for two types of lock detect: digital lock detect and analog lock detect. Digital lock detect is active high. When the lock detect precision (LDP) bit in the R counter latch is set to 0, digital lock detect is set high when the phase error on three consecutive phase detector (PD) cycles is less than 15 ns. With LDP set to 1, five consecutive cycles of less than 15 ns are required to set the lock detect. It stays set high until a phase error of greater than 25 ns is detected on any subsequent PD cycle. INPUT SHIFT REGISTER The ADF4107 digital section includes a 24-bit input shift register, a 14-bit R counter, and a 19-bit N counter, comprising a 6-bit A counter and a 13-bit B counter. Data is clocked into the 24-bit shift register on each rising edge of CLK. The data is clocked in MSB first. Data is transferred from the shift register to one of four latches on the rising edge of LE. The destination latch is determined by the state of the two control bits (C2, C1) in the shift register. These are the two LSBs, DB1 and DB0, as shown in the timing diagram of Figure 2. The truth table for these bits is shown in Table 5. Figure 22 shows a summary of how the latches are programmed. Table 5. C2, C1 Truth Table Control Bits C2 C1 0 0 0 1 1 0 1 1 The N-channel open-drain analog lock detect should be operated with an external pull-up resistor of 10 kΩ nominal. When lock has been detected, this output becomes high with narrow, low going pulses. Rev. D | Page 10 of 20 Data Latch R Counter N Counter (A and B) Function Latch (Including Prescaler) Initialization Latch Data Sheet ADF4107 LATCH SUMMARY LOCK DETECT PRECISION REFERENCE COUNTER LATCH RESERVED TEST MODE BITS ANTIBACKLASH WIDTH DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 X 0 0 LDP T2 T1 CONTROL BITS 14-BIT REFERENCE COUNTER ABP2 ABP1 R14 R13 R12 R11 R10 R9 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 R8 R7 R6 R5 R4 R3 R2 R1 C2 (0) C1 (0) RESERVED CP GAIN N COUNTER LATCH 13-BIT B COUNTER DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 X X G1 B13 B12 B11 B10 B9 B8 B7 B6 CONTROL BITS 6-BIT A COUNTER B5 B4 B3 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 B2 B1 A6 A5 A4 A3 A2 A1 C2 (0) C1 (1) CONTROL BITS DB1 DB0 FASTLOCK ENABLE CP THREESTATE PD POLARITY POWERDOWN 1 COUNTER RESET DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 F4 F3 F2 M3 M2 M1 PD1 F1 C2 (1) C1 (0) MUXOUT CONTROL PRESCALER VALUE P2 P1 POWERDOWN 2 FASTLOCK MODE FUNCTION LATCH PD2 CURRENT SETTING 2 CPI6 CPI5 CPI4 CURRENT SETTING 1 CPI3 CPI2 CPI1 TIMER COUNTER CONTROL TC4 TC3 TC2 TC1 F5 MUXOUT CONTROL DB1 DB0 FASTLOCK ENABLE CP THREESTATE PD POLARITY POWERDOWN 1 COUNTER RESET CONTROL BITS DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 F4 F3 F2 M3 M2 M1 PD1 F1 P2 P1 PD2 CURRENT SETTING 2 CPI6 CPI5 CPI4 CURRENT SETTING 1 CPI3 CPI2 TIMER COUNTER CONTROL CPI1 TC4 TC3 TC2 TC1 F5 Figure 22. Latch Summary Rev. D | Page 11 of 20 DB0 C2 (1) C1 (1) 03338-022 PRESCALER VALUE POWERDOWN 2 FASTLOCK MODE INITIALIZATION LATCH ADF4107 Data Sheet LOCK DETECT PRECISION REFERENCE COUNTER LATCH MAP RESERVED TEST MODE BITS ANTIBACKLASH WIDTH DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 X 0 LDP 0 T2 T1 ABP2 ABP1 CONTROL BITS 14-BIT REFERENCE COUNTER R14 R12 R13 R11 R10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 R8 R7 R6 R5 R4 R3 R2 R1 C2 (0) C1 (0) R9 X = DON’T CARE ABP2 0 0 1 1 ABP1 0 1 0 1 R14 R13 R12 .......... R3 R2 R1 DIVIDE RATIO 0 0 0 0 . . . 0 0 0 0 . . . 0 0 0 0 . . . .......... .......... .......... .......... .......... .......... .......... 0 0 0 1 . . . 0 1 1 0 . . . 1 0 1 0 . . . 1 2 3 4 . . . 1 1 1 .......... 1 0 0 16380 1 1 1 .......... 1 0 1 16381 1 1 1 .......... 1 1 0 16382 1 1 1 .......... 1 1 1 16383 ANTIBACKLASH PULSE WIDTH 2.9ns 1.3ns TEST MODE ONLY. DO NOT USE 6.0ns 2.9ns TEST MODE BITS SHOULD BE SET TO 00 FOR NORMAL OPERATION. LDP 0 1 OPERATION THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN 15ns MUST OCCUR BEFORE LOCK DETECT IS SET. FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN 15ns MUST OCCUR BEFORE LOCK DETECT IS SET. 03338-023 BOTH OF THESE BITS MUST BE SET TO 0 FOR NORMAL OPERATION. Figure 23. Reference Counter Latch Map Rev. D | Page 12 of 20 Data Sheet ADF4107 CP GAIN AB COUNTER LATCH MAP RESERVED CONTROL BITS 6-BIT A COUNTER 13-BIT B COUNTER DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 X X G1 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 A6 A5 A4 A3 A2 A1 DB1 DB0 C2 (0) C1 (1) X = DON’T CARE B13 B12 B11 0 0 0 0 . . . 1 1 1 1 0 0 0 0 . . . 1 1 1 1 0 0 0 0 . . . 1 1 1 1 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... A6 A5 .......... A2 A1 A COUNTER DIVIDE RATIO 0 0 0 0 . . . 1 1 1 1 0 0 0 0 . . . 1 1 1 1 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... 0 0 1 1 . . . 0 0 1 1 0 1 0 1 . . . 0 1 0 1 0 1 2 3 . . . 60 61 62 63 B3 B2 B1 B COUNTER DIVIDE RATIO 0 0 0 0 . . . 1 1 1 1 0 0 1 1 . . . 0 0 1 1 0 1 0 1 . . . 0 1 0 1 NOT ALLOWED NOT ALLOWED NOT ALLOWED 3 . . . 8188 8189 8190 8191 F4 (FUNCTION LATCH) FASTLOCK ENABLE CP GAIN OPERATION 0 0 CHARGE PUMP CURRENT SETTING 1 IS PERMANENTLY USED. 0 1 1 0 1 1 CHARGE PUMP CURRENT SETTING 2 IS PERMANENTLY USED. CHARGE PUMP CURRENT SETTING 1 IS USED. CHARGE PUMP CURRENT IS SWITCHED TO SETTING 2. THE TIME SPENT IN SETTING 2 IS DEPENDENT ON WHICH FASTLOCK MODE IS USED. SEE FUNCTION LATCH DESCRIPTION. N = BP + A, P IS PRESCALER VALUE SET IN THE FUNCTION LATCH. B MUST BE GREATER THAN OR EQUAL TO A. FOR CONTINUOUSLY ADJACENT VALUES OF (N × FREF ), AT THE OUTPUT, NMIN IS (P2 – P). 03338-024 THESE BITS ARE NOT USED BY THE DEVICE AND ARE DON'T CARE BITS. Figure 24. AB Counter Latch Map Rev. D | Page 13 of 20 ADF4107 Data Sheet FASTLOCK ENABLE CP THREESTATE PD POLARITY POWERDOWN 1 COUNTER RESET DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 F4 F3 F2 M3 M2 M1 PD1 F1 POWERDOWN 2 FASTLOCK MODE FUNCTION LATCH MAP PRESCALER VALUE P1 PD2 CPI6 CPI5 CPI4 CPI2 CPI3 TIMER COUNTER CONTROL CPI1 TC4 TC3 TC2 TC1 TC4 TC3 TC2 TC1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 3kΩ 1.06 2.12 3.18 4.24 5.30 6.36 7.42 8.50 5.1kΩ 0.625 1.25 1.875 2.5 3.125 3.75 4.375 5.0 CPI6 CPI5 CPI4 CPI3 0 0 0 0 1 1 1 1 CPI2 0 0 1 1 0 0 1 1 CPI1 0 1 0 1 0 1 0 1 PD2 PD1 MODE X X 0 1 X 0 1 1 ASYNCHRONOUS POWER-DOWN NORMAL OPERATION ASYNCHRONOUS POWER-DOWN SYNCHRONOUS POWER-DOWN P1 PRESCALER VALUE 0 1 0 1 8/9 16/17 32/33 64/65 PHASE DETECTOR POLARITY F1 0 1 NEGATIVE POSITIVE 0 1 F3 CHARGE PUMP OUTPUT 0 1 NORMAL THREE-STATE F4 F5 FASTLOCK MODE 0 1 1 X 0 1 FASTLOCK DISABLED FASTLOCK MODE 1 FASTLOCK MODE 2 TIMEOUT (PFD CYCLES) 3 7 11 15 19 23 27 31 35 39 43 47 51 55 59 63 DB1 DB0 C2 (1) C1 (0) COUNTER OPERATION NORMAL R, A, B COUNTERS HELD IN RESET M3 M2 M1 OUTPUT 0 0 0 0 0 1 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 1 0 1 THREE-STATE OUTPUT DIGITAL LOCK DETECT (ACTIVE HIGH) N DIVIDER OUTPUT DVDD R DIVIDER OUTPUT N-CHANNEL OPEN-DRAIN LOCK DETECT SERIAL DATA OUTPUT DGND 11kΩ 0.289 0.580 0.870 1.160 1.450 1.730 2.020 2.320 CE PIN 0 0 1 1 F2 CONTROL BITS ICP (mA) 0 1 1 1 P2 F5 MUXOUT CONTROL 03338-025 P2 CURRENT SETTING 1 CURRENT SETTING 2 Figure 25. Function Latch Map Rev. D | Page 14 of 20 Data Sheet ADF4107 FASTLOCK ENABLE CP THREESTATE PD POLARITY POWERDOWN 1 COUNTER RESET DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 F4 F3 F2 M3 M2 M1 PD1 F1 POWERDOWN 2 FASTLOCK MODE INITIALIZATION LATCH MAP PRESCALER VALUE P1 PD2 CPI6 CPI5 CPI4 CPI3 CPI2 TIMER COUNTER CONTROL CPI1 TC4 TC3 TC2 TC1 TC4 TC3 TC2 TC1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 3kΩ 1.06 2.12 3.18 4.24 5.30 6.36 7.42 8.50 5.1kΩ 0.625 1.25 1.875 2.5 3.125 3.75 4.375 5.0 CPI6 CPI5 CPI4 CPI3 0 0 0 0 1 1 1 1 CPI2 0 0 1 1 0 0 1 1 CPI1 0 1 0 1 0 1 0 1 PD2 PD1 MODE X X 0 1 X 0 1 1 ASYNCHRONOUS POWER-DOWN NORMAL OPERATION ASYNCHRONOUS POWER-DOWN SYNCHRONOUS POWER-DOWN P1 PRESCALER VALUE 0 1 0 1 8/9 16/17 32/33 64/65 PHASE DETECTOR POLARITY F1 0 1 NEGATIVE POSITIVE 0 1 F3 CHARGE PUMP OUTPUT 0 1 NORMAL THREE-STATE F4 F5 FASTLOCK MODE 0 1 1 X 0 1 FASTLOCK DISABLED FASTLOCK MODE 1 FASTLOCK MODE 2 TIMEOUT (PFD CYCLES) 3 7 11 15 19 23 27 31 35 39 43 47 51 55 59 63 DB1 DB0 C2 (1) C1 (1) COUNTER OPERATION NORMAL R, A, B COUNTERS HELD IN RESET M3 M2 M1 OUTPUT 0 0 0 0 0 1 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 1 0 1 THREE-STATE OUTPUT DIGITAL LOCK DETECT (ACTIVE HIGH) N DIVIDER OUTPUT DVDD R DIVIDER OUTPUT N-CHANNEL OPEN-DRAIN LOCK DETECT SERIAL DATA OUTPUT DGND 11kΩ 0.289 0.580 0.870 1.160 1.450 1.730 2.020 2.320 CE PIN 0 0 1 1 F2 CONTROL BITS ICP (mA) 0 1 1 1 P2 F5 MUXOUT CONTROL 03338-026 P2 CURRENT SETTING 1 CURRENT SETTING 2 Figure 26. Initialization Latch Map Rev. D | Page 15 of 20 ADF4107 Data Sheet FUNCTION LATCH Fastlock Mode Bit The on-chip function latch is programmed with C2 and C1 set to 1 and 0, respectively. Figure 25 shows the input data format for programming the function latch. DB10 of the function latch is the fastlock mode bit. When fastlock is enabled, this bit determines which fastlock mode is used. If the fastlock mode bit is 0, then Fastlock Mode 1 is selected; and if the fastlock mode bit is 1, then Fastlock Mode 2 is selected. Counter Reset DB2 (F1) is the counter reset bit. When this bit is 1, the R counter and the AB counters are reset. For normal operation, this bit should be 0. Upon powering up, the F1 bit needs to be disabled (set to 0). Then, the N counter resumes counting in close alignment with the R counter. (The maximum error is one prescaler cycle). Fastlock Mode 1 The charge pump current is switched to the contents of Current Setting 2. The device enters fastlock by having a 1 written to the CP gain bit in the AB counter latch. The device exits fastlock by having a 0 written to the CP gain bit in the AB counter latch. Power-Down Fastlock Mode 2 DB3 (PD1) and DB21 (PD2) provide programmable powerdown modes. They are enabled by the CE pin. The charge pump current is switched to the contents of Current Setting 2. The device enters fastlock by having a 1 written to the CP gain bit in the AB counter latch. The device exits fastlock under the control of the timer counter. After the timeout period determined by the value in TC4 to TC1, the CP gain bit in the AB counter latch is automatically reset to 0 and the device reverts to normal mode instead of fastlock. See Figure 25 for the timeout periods. When the CE pin is low, the device is immediately disabled regardless of the states of PD2 and PD1. In the programmed asynchronous power-down, the device powers down immediately after latching a 1 into the PD1 bit, with the condition that PD2 has been loaded with a 0. In the programmed synchronous power-down, the device power-down is gated by the charge pump to prevent unwanted frequency jumps. Once the power-down is enabled by writing a 1 into PD1 (on condition that a 1 has also been loaded to PD2), then the device goes into power-down on the occurrence of the next charge pump event. When a power-down is activated (either in synchronous or asynchronous mode, including CE pin-activated power-down), the following events occur: • All active dc current paths are removed. • The R, N, and timeout counters are forced to their load state conditions. • The charge pump is forced into three-state mode. • The digital lock detect circuitry is reset. • The RFIN input is debiased. • The reference input buffer circuitry is disabled. • The input register remains active and capable of loading and latching data. MUXOUT Control The on-chip multiplexer is controlled by M3, M2, and M1 on the ADF4107. Figure 25 shows the truth table. Fastlock Enable Bit DB9 of the function latch is the fastlock enable bit. Fastlock is enabled only when this bit is 1. Timer Counter Control The user has the option of programming two charge pump currents. The intent is that Current Setting 1 is used when the RF output is stable and the system is in a static state. Current Setting 2 is meant to be used when the system is dynamic and in a state of change (that is, when a new output frequency is programmed). The normal sequence of events is as follows: The user initially decides what the preferred charge pump currents are going to be. For example, the choice may be 2.5 mA as Current Setting 1 and 5 mA as Current Setting 2. At the same time, it must be decided how long the secondary current is to stay active before reverting to the primary current. This is controlled by the timer counter control bits, DB14 to DB11 (TC4 to TC1), in the function latch. The truth table is given in Figure 25. To program a new output frequency, the user simply programs the AB counter latch with new values for A and B. At the same time, the CP gain bit can be set to 1, which sets the charge pump with the value in CPI6 to CPI4 for a period of time determined by TC4 to TC1. When this time is up, the charge pump current reverts to the value set by CPI3 to CPI1. At the same time, the CP gain bit in the AB counter latch is reset to 0 and is ready for the next time that the user wishes to change the frequency. Note that there is an enable feature on the timer counter. It is enabled when Fastlock Mode 2 is chosen by setting the fastlock mode bit (DB10) in the function latch to 1. Rev. D | Page 16 of 20 Data Sheet ADF4107 Charge Pump Currents 5. Then do an AB load (01 in two LSBs). CPI3, CPI2, and CPI1 program Current Setting 1 for the charge pump. CPI6, CPI5, and CPI4 program Current Setting 2 for the charge pump. The truth table is given in Figure 25. 6. When the initialization latch is loaded, the following occurs: a. b. The function latch contents are loaded. An internal pulse resets the R, AB, and timeout counters to load-state conditions and also three-states the charge pump. Note that the prescaler band gap reference and the oscillator input buffer are unaffected by the internal reset pulse, allowing close phase alignment when counting resumes. Latching the first AB counter data after the initialization word activates the same internal reset pulse. Successive AB loads do not trigger the internal reset pulse unless there is another initialization. Prescaler Value P2 and P1 in the function latch set the prescaler values. The prescaler value should be chosen so that the prescaler output frequency is always less than or equal to 300 MHz. Thus, with an RF frequency of 4 GHz, a prescaler value of 16/17 is valid but a value of 8/9 is not valid. PD Polarity c. This bit sets the phase detector polarity bit. See Figure 25. CP Three-State This bit controls the CP output pin. With the bit set high, the CP output is put into three-state. With the bit set low, the CP output is enabled. INITIALIZATION LATCH The initialization latch is programmed when C2 and C1 are set to 1 and 1. This is essentially the same as the function latch (programmed when C2, C1 = 1, 0). However, when the initialization latch is programmed an additional internal reset pulse is applied to the R and AB counters. This pulse ensures that the AB counter is at load point when the AB counter data is latched and the device will begin counting in close phase alignment. CE Pin Method 1. Apply VDD. 2. Bring CE low to put the device into power-down. This is an asychronous power-down in that it happens immediately. 3. Program the function latch (10). 4. Program the R counter latch (00). 5. Program the AB counter latch (01). 6. Bring CE high to take the device out of power-down. The R and AB counters resume counting in close alignment. Note that after CE goes high, a duration of 1 µs may be required for the prescaler band gap voltage and oscillator input buffer bias to reach steady state. If the latch is programmed for synchronous power-down (CE pin is high; PD1 bit is high; PD2 bit is low), the internal pulse also triggers this power-down. The prescaler reference and the oscillator input buffer are unaffected by the internal reset pulse and so close phase alignment is maintained when counting resumes. CE can be used to power the device up and down in order to check for channel activity. The input register does not need to be reprogrammed each time the device is disabled and enabled as long as it has been programmed at least once after VDD was initially applied. When the first AB counter data is latched after initialization, the internal reset pulse is again activated. However, successive AB counter loads after this will not trigger the internal reset pulse. Counter Reset Method 1. Apply VDD. 2. Do a function latch load (10 in two LSBs). As part of this, load 1 to the F1 bit. This enables the counter reset. 3. Do an R counter load (00 in two LSBs). 4. Do an AB counter load (01 in two LSBs). 5. Do a function latch load (10 in two LSBs). As part of this, load 0 to the F1 bit. This disables the counter reset. DEVICE PROGRAMMING AFTER INITIAL POWER-UP After initially powering up the device, there are three ways to program the device. Initialization Latch Method 1. Apply VDD. 2. Program the initialization latch (11 in two LSBs of input word). Make sure that the F1 bit is programmed to 0. 3. Next, do a function latch load (10 in two LSBs of the control word), making sure that the F1 bit is programmed to a 0. 4. Then do an R load (00 in two LSBs). This sequence provides the same close alignment as the initialization method. It offers direct control over the internal reset. Note that counter reset holds the counters at load point and three-states the charge pump, but does not trigger synchronous power-down. Rev. D | Page 17 of 20 ADF4107 Data Sheet APPLICATIONS Other PLL system specifications are: LOCAL OSCILLATOR FOR LMDS BASE STATION TRANSMITTER KD = 5.0 mA KV = 80 MHz/V Loop bandwidth = 70 kHz FPFD = 1 MHz N = 6300 Extra reference spur attenuation = 10 dB Figure 27 shows the ADF4107 being used with a VCO to produce the LO for an LMDS base station. The reference input signal is applied to the circuit at FREFIN and, in this case, is terminated in 50 Ω. A typical base station system has either a TCXO or an OCXO driving the reference input without any 50 Ω termination. All of these specifications are needed and used to derive the loop filter component values shown in Figure 27. To have a channel spacing of 1 MHz at the output, the 10 MHz reference input must be divided by 10, using the on-chip reference divider of the ADF4107. Figure 27 gives a typical phase noise performance of −83 dBc/Hz at 1 kHz offset from the carrier. Spurs are better than −70 dBc. The loop filter output drives the VCO, which, in turn, is fed back to the RF input of the PLL synthesizer, and drives the RF output terminal. A T-circuit configuration provides 50 Ω matching between the VCO output, the RF output, and the RFIN terminal of the synthesizer. The charge pump output of the ADF4107 (Pin 2) drives the loop filter. In calculating the loop filter component values, a number of items need to be considered. In this example, the loop filter was designed so that the overall phase margin for the system would be 45°. In a PLL system, it is important to know when the system is in lock. In Figure 27, this is accomplished by using the MUXOUT signal from the synthesizer. The MUXOUT pin can be programmed to monitor various internal signals in the synthesizer. One of these is the LD or lock detect signal. VDD VP RFOUT 100pF 7 1000pF 1000pF FREFIN 16 15 VCC 2 7.5kΩ 100pF 51Ω 100pF 14 1.7kΩ AVDD DVDD VP CP 2 8 REFIN 47pF 10 V956ME01 18Ω 18Ω 18Ω ADF4107 CE CLK DATA LE MUXOUT 14 1, 3, 4, 5, 7, 8, 9, 11, 12, 13 LOCK DETECT 100pF RFINA 6 51Ω RFINB 5 DGND 3 4 9 100pF NOTES: 1. DECOUPLING CAPACITORS (0.1µF/10pF) ON AVDD, DVDD, AND VP OF THE ADF4106 AND ON VCC OF THE V956ME03 HAVE BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY. 03338-027 5.1kΩ RSET AGND 1 CPGND SPI®-COMPATIBLE SERIAL BUS 820pF Figure 27. 6.3 GHz Local Oscillator Using the ADF4107 Rev. D | Page 18 of 20 Data Sheet ADF4107 INTERFACING ADSP-2181 Interface The ADF4107 has a simple SPI®-compatible serial interface for writing to the device. CLK, DATA, and LE control the data transfer. When LE (latch enable) goes high, the 24 bits that have been clocked into the input register on each rising edge of CLK are transferred to the appropriate latch. See Figure 2 for the timing diagram and Table 5 for the latch truth table. Figure 29 shows the interface between the ADF4107 and the ADSP21xx digital signal processor. The ADF4107 needs a 24-bit serial word for each latch write. The easiest way to accomplish this using the ADSP-21xx family is to use the autobuffered transmit mode of operation with alternate framing. This provides a means for transmitting an entire block of serial data before an interrupt is generated. Set up the word length for 8 bits and use three memory locations for each 24-bit word. To program each 24-bit latch, store the three 8-bit bytes, enable the autobuffered mode, and then write to the transmit register of the DSP. This last operation initiates the autobuffer transfer. ADuC812 Interface Figure 28 shows the interface between the ADF4107 and the ADuC812 MicroConverter®. Since the ADuC812 is based on an 8051 core, this interface can be used with any 8051-based microcontroller. The MicroConverter is set up for SPI master mode with CPHA = 0. To initiate the operation, the I/O port driving LE is brought low. Each latch of the ADF4107 needs a 24-bit word. This is accomplished by writing three 8-bit bytes from the MicroConverter to the device. When the third byte has been written, the LE input should be brought high to complete the transfer. On first applying power to the ADF4107, it needs four writes (one each to the initialization latch, function latch, R counter latch, and N counter latch) for the output to become active. I/O port lines on the ADuC812 are also used to control powerdown (CE input) and to detect lock (MUXOUT configured as lock detect and polled by the port input). When operating in the mode described, the maximum SCLOCK rate of the ADuC812 is 4 MHz. This means that the maximum rate at which the output frequency can be changed is 166 kHz. MOSI CLK DATA LE ADuC812 I/O PORTS ADF4107 CE MUXOUT (LOCK DETECT) Figure 28. ADuC812 to ADF4107 Interface 03338-028 SCLOCK SCLOCK DT ADSP-21xx TFS CLK DATA LE ADF4107 CE I/O FLAGS MUXOUT (LOCK DETECT) 03338-029 The maximum allowable serial clock rate is 20 MHz. This means that the maximum update rate possible for the device is 833 kHz or one update every 1.2 µs. This is certainly more than adequate for systems that have typical lock times in hundreds of microseconds. Figure 29. ADSP-21xx to ADF4107 Interface PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE The lands on the chip scale package (CP-20-6) are rectangular. The printed circuit board pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. The land should be centered on the pad. This ensures that the solder joint size is maximized. The bottom of the chip scale package has a central thermal pad. The thermal pad on the printed circuit board should be at least as large as this exposed pad. On the printed circuit board, there should be a clearance of at least 0.25 mm between the thermal pad and the inner edges of the pad pattern. This ensures that shorting is avoided. Thermal vias may be used on the printed circuit board thermal pad to improve thermal performance of the package. If vias are used, they should be incorporated in the thermal pad at 1.2 mm pitch grid. The via diameter should be between 0.3 mm and 0.33 mm and the via barrel should be plated with 1 oz. copper to plug the via. The user should connect the printed circuit board thermal pad to AGND. Rev. D | Page 19 of 20 ADF4107 Data Sheet OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.30 0.19 0.65 BSC COPLANARITY 0.10 0.75 0.60 0.45 8° 0° SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 30. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters PIN 1 INDICATOR 0.30 0.25 0.18 0.50 BSC PIN 1 INDICATOR 20 16 15 1 EXPOSED PAD 2.30 2.10 SQ 2.00 11 0.65 0.60 0.55 TOP VIEW 0.80 0.75 0.70 5 10 0.20 MIN BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 6 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-1. ORDERING GUIDE 08-16-2010-B 4.10 4.00 SQ 3.90 Figure 31. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 4 mm × 4 mm Body, Very Very Thin Quad (CP-20-6) Dimensions shown in millimeters Model 1 Temperature Range Package Description Package Option ADF4107BRU ADF4107BRU-REEL ADF4107BRU-REEL7 ADF4107BRUZ ADF4107BRUZ-REEL ADF4107BRUZ-REEL7 ADF4107BCPZ ADF4107BCPZ-REEL ADF4107BCPZ-REEL7 EV-ADF411XSD1Z –40°C to + 85°C –40°C to + 85°C –40°C to + 85°C –40°C to + 85°C –40°C to + 85°C –40°C to + 85°C –40°C to + 85°C –40°C to + 85°C –40°C to + 85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] Evaluation Board RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 CP-20-6 CP-20-6 CP-20-6 1 Z = RoHS Compliant Part. ©2003–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03338-0-3/13(D) Rev. D | Page 20 of 20