Phase Detector/Frequency Synthesizer ADF4002 FEATURES GENERAL DESCRIPTION 400 MHz bandwidth 2.7 V to 3.3 V power supply Separate charge pump supply (VP) allows extended tuning voltage in 3 V systems Programmable charge pump currents 3-wire serial interface Analog and digital lock detect Hardware and software power-down mode 200 MHz phase detector The ADF4002 frequency synthesizer is used to implement local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. It consists of a low-noise digital phase frequency detector (PFD), a precision charge pump, a programmable reference divider, and programmable N divider. The 14-bit reference counter (R counter), allows selectable REFIN frequencies at the PFD input. A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and voltage controlled oscillator (VCO). In addition, by programming R and N to 1, the part can be used as a stand alone PFD and charge pump. APPLICATIONS Clock conditioning Clock generation IF LO generation FUNCTIONAL BLOCK DIAGRAM AVDD DVDD VP RSET CPGND REFERENCE 14-BIT R COUNTER REFIN PHASE FREQUENCY DETECTOR CHARGE PUMP CP 14 R COUNTER LATCH CLK DATA LE 24-BIT INPUT REGISTER 22 LOCK DETECT FUNCTION LATCH CURRENT SETTING 2 CPI3 CPI2 CPI1 CPI6 CPI5 CPI4 HIGH Z N COUNTER LATCH SDOUT CURRENT SETTING 1 AVDD MUXOUT MUX SDOUT RFINA RFINB 13-BIT N COUNTER M3 M2 M1 CE AGND 06052-001 ADF4002 DGND Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. ADF4002 TABLE OF CONTENTS Features .............................................................................................. 1 MUXOUT and Lock Detect.........................................................9 Applications....................................................................................... 1 Input Shift Register .......................................................................9 General Description ......................................................................... 1 Latch Maps and Descriptions ....................................................... 10 Functional Block Diagram .............................................................. 1 Latch Summary........................................................................... 10 Revision History ............................................................................... 2 Reference Counter Latch Map.................................................. 11 Specifications..................................................................................... 3 N Counter Latch Map................................................................ 12 Timing Characteristics ................................................................ 4 Function Latch Map................................................................... 13 Absolute Maximum Ratings............................................................ 5 Initialization Latch Map ............................................................ 14 Thermal Characteristics .............................................................. 5 The Function Latch.................................................................... 15 ESD Caution.................................................................................. 5 The Initialization Latch ............................................................. 16 Pin Configurations and Function Descriptions ........................... 6 Applications..................................................................................... 17 Typical Performance Characteristics ............................................. 7 Very Low Jitter Encode Clock for High Speed Converters... 17 Theory of Operation ........................................................................ 8 PFD............................................................................................... 18 Reference Input Section............................................................... 8 Interfacing ................................................................................... 18 RF Input Stage............................................................................... 8 PCB Design Guidelines for Chip Scale Package .................... 18 N Counter...................................................................................... 8 Outline Dimensions ....................................................................... 20 R Counter ...................................................................................... 8 Ordering Guide .......................................................................... 21 Phase Frequency Detector (PFD) and Charge Pump.............. 8 REVISION HISTORY 4/06—Revision 0: Initial Version Rev. 0 | Page 2 of 24 ADF4002 SPECIFICATIONS AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMAX to TMIN, unless otherwise noted. Table 1. Parameter RF CHARACTERISTICS RF Input Sensitivity RF Input Frequency (RFIN) REFIN CHARACTERISTICS REFIN Input Frequency REFIN Input Sensitivity 2 REFIN Input Capacitance REFIN Input Current PHASE DETECTOR Phase Detector Frequency 4 CHARGE PUMP ICP Sink/Source High Value Low Value Absolute Accuracy RSET Range ICP Three-State Leakage ICP vs. VCP Sink and Source Current Matching ICP vs. Temperature LOGIC INPUTS VIH, Input High Voltage VIL, Input Low Voltage IINH, IINL, Input Current CIN, Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage VOH, Output High Voltage IOH VOL, Output Low Voltage POWER SUPPLIES AVDD DVDD VP IDD 5 (AIDD + DIDD) IP Power-Down Mode NOISE CHARACTERISTICS Normalized Phase Noise Floor 6 Min B Version 1 Typ Max Unit −10 5 0 400 dBm MHz 20 0.8 300 VDD 10 ±100 MHz V p-p pF μA 200 MHz Test Conditions/Comments See Figure 12 for input circuit For RFIN < 5 MHz, ensure slew rate (SR) > 4 V/μs For REFIN < 20 MHz, ensure SR > 50 V/μs Biased at AVDD/2 3 Programmable, see Figure 19 5 625 2.5 3.0 11 1 1.5 2 2 1.4 mA μA % kΩ nA % % % 0.6 ±1 10 V V μA pF 100 0.4 V V μA V 3.3 V 5.5 6.0 0.4 1 V mA mA μA –222 dBc/Hz 1.4 VDD – 0.4 2.7 AVDD AVDD 5.0 1 With RSET = 5.1 kΩ With RSET = 5.1 kΩ See Figure 19 TA = 25°C 0.5 V ≤ VCP ≤ VP – 0.5 V 0.5 V ≤ VCP ≤ VP – 0.5 V VCP = VP/2 Open-drain output chosen, 1 kΩ pull-up resistor to 1.8 V CMOS output chosen IOL = 500 μA AVDD ≤ VP ≤ 5.5 V TA = 25°C AIDD + DIDD Operating temperature range (B version) is –40°C to +85°C. AVDD = DVDD = 3 V. 3 AC coupling ensures AVDD/2 bias. 4 Guaranteed by design. Sample tested to ensure compliance. Use of the PFD at frequencies above 104 MHz requires the minimum antibacklash pulse width enabled. 5 TA = 25°C; AVDD = DVDD = 3 V; RFIN = 350 MHz. The current for any other setup (25°C, 3.0 V) in mA is given by 2.35 + 0.0046 (REFIN) + 0.0062 (RF), RF frequency and REFIN frequency in MHz. 6 The normalized phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value) and 10logFPFD. PNSYNTH = PNTOT – 10logFPFD – 20logN. All phase noise measurements were performed with an Agilent E5500 phase noise test system, using the EVALADF4002EB1 and the HP8644B as the PLL reference. 2 Rev. 0 | Page 3 of 24 ADF4002 TIMING CHARACTERISTICS AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMAX to TMIN, unless otherwise noted. 1 Table 2. Limit (B Version) 2 10 10 25 25 10 20 Parameter t1 t2 t3 t4 t5 t6 1 2 Unit ns min ns min ns min ns min ns min ns min Test Conditions/Comments DATA to CLK setup time DATA to CLK hold time CLK high duration CLK low duration CLK to LE setup time LE pulse width Guaranteed by design, but not production tested. Operating temperature range (B version) is –40°C to +85°C. Timing Diagram t3 t4 CLK t1 DATA DB23 (MSB) t2 DB22 DB2 DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1) t6 LE 06052-022 t5 LE Figure 2. Timing Diagram Rev. 0 | Page 4 of 24 ADF4002 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter AVDD to GND1 AVDD to DVDD VP to GND VP to AVDD Digital I/O Voltage to GND Analog I/O Voltage to GND REFIN, RFINA, RFINB to GND Operating Temperature Range Industrial (B Version) Storage Temperature Range Maximum Junction Temperature Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) Transistor Count CMOS Bipolar 1 Rating –0.3 V to +3.6 V –0.3 V to +0.3 V –0.3 V to +5.8 V –0.3 V to +5.8 V –0.3 V to VDD + 0.3 V –0.3 V to VP + 0.3 V –0.3 V to VDD + 0.3 V –40°C to +85°C –65°C to +125°C 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. This device is a high performance RF integrated circuit with an ESD rating of <2 kV, and it is ESD sensitive. Proper precautions should be taken for handling and assembly. THERMAL CHARACTERISTICS 215°C 220°C 6425 303 Table 4. Thermal Impedance Package Type TSSOP LFCSP_VQ θJA 150.4 122 GND = AGND = DGND = 0 V. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 5 of 24 Unit °C/W °C/W ADF4002 CP 2 CPGND 3 14 ADF4002 VP DVDD MUXOUT CPGND 1 AGND 2 AGND 3 RFINB 4 RFINA 5 LE TOP VIEW RFINB 5 (Not to Scale) 12 DATA 11 CLK AVDD 7 10 CE REFIN 8 9 DGND 06052-002 RFINA 6 PIN 1 INDICATOR ADF4002 TOP VIEW (Not to Scale) 15 MUXOUT 14 LE 13 DATA 12 CLK 11 CE AVDD 6 AVDD 7 REFIN 8 DGND 9 DGND 10 13 AGND 4 06052-003 PIN 1 16 INDICATOR 15 RSET 1 20 CP 19 RSET 18 VP 17 DVDD 16 DVDD PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 4. LFCSP_VQ (Top View) Figure 3. TSSOP (Top View) Table 5. Pin Function Descriptions Pin No. TSSOP LFCSP_VQ 1 19 Mnemonic RSET 2 20 CP 3 4 5 1 2, 3 4 CPGND AGND RFINB 6 7 5 6, 7 RFINA AVDD 8 8 REFIN 9 10 9, 10 11 DGND CE 11 12 CLK 12 13 DATA 13 14 LE 14 15 MUXOUT 15 16, 17 DVDD 16 18 VP Description Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. The nominal voltage potential at the RSET pin is 0.66 V. The relationship between ICP and RSET is 25.5 I CP MAX = R SET Where RSET = 5.1 kΩ and ICP MAX = 5 mA. Charge Pump Output. When enabled, this provides ±ICP to the external loop filter that, in turn, drives the external VCO. Charge Pump Ground. This is the ground return path for the charge pump. Analog Ground. This is the ground return path of the RF input. Complementary Input to the RF Input. This point must be decoupled to the ground plane with a small bypass capacitor, typically 100 pF. See Figure 12. Input to the RF Input. This small signal input is ac-coupled to the external VCO. Analog Power Supply. This can range from 2.7 V to 3.3 V. Decoupling capacitors to the analog ground plane should be placed as close as possible to the AVDD pin. AVDD must be the same value as DVDD. Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input resistance of 100 kΩ. See Figure 11. This input can be driven from a TTL or CMOS crystal oscillator or it can be ac-coupled. Digital Ground. Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-state mode. Taking this pin high powers up the device, depending on the status of the PowerDown Bit F2. Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input. Serial Data Input. The serial data is loaded MSB-first with the two LSBs being the control bits. This input is a high impedance CMOS input. Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four latches; the latch is selected using the control bits. This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency to be accessed externally. Digital Power Supply. This can range from 2.7 V to 3.3 V. Decoupling capacitors to the digital ground plane should be placed as close as possible to this pin. DVDD must be the same value as AVDD. Charge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is 3 V, it can be set to 5.5 V and used to drive a VCO with a tuning range of up to 5 V. Rev. 0 | Page 6 of 24 ADF4002 TYPICAL PERFORMANCE CHARACTERISTICS –70 0 –90 POWER (dBc/Hz) –15 –20 +25°C +85°C –25 –30 –100 –110 –120 –130 –140 –40°C –150 06052-027 –35 0 100 200 300 400 500 06052-032 POWER (dBm) –10 –40 rms NOISE = 0.03 DEGREES –80 –5 –160 1k 600 10k 100k 1M 10M FREQUENCY OFFSET (Hz) FREQUENCY (MHz) Figure 8. Integrated Phase Noise (400 MHz, PFD = 200 MHz, 50 kHz) Figure 5. RF Input Sensitivity –130 0 –135 –140 –40°C PHASE NOISE (dBc/Hz) +25°C –10 +85°C –15 –155 –160 –165 –170 –20 –175 06052-026 –25 –145 0 1 2 3 4 5 6 7 8 9 06052-033 POWER (dBm) –5 –180 100k 10 1M 100M 1G Figure 9. Phase Noise (Referred to CP Output) vs. PFD Frequency Figure 6. RF Input Sensitivity, Low Frequency –70 0 rms NOISE = 0.07 DEGREES –80 10M PFD FREQUENCY (Hz) FREQUENCY (MHz) REF –4dBm SAMP LOG 10dB/ ATTN 10dB 1R MKR1 1.000 MHz –94.5dBc –10 –20 –100 –30 –110 –40 –50 –130 –60 –140 –70 –150 –80 –160 1k 10k 100k 1M –90 10M –94.5dBc 1 06052-030 –120 06052-031 PHASE NOISE (dBc/Hz) –90 –100 FREQUENCY OFFSET (Hz) CENTER 399.995MHz RES BW 20KHz VBW 20KHz SPAN 2.2MHz SWEEP 21ms (601pts) Figure 10. Reference Spurs (400 MHz, 1 MHz, 7 kHz) Figure 7. Integrated Phase Noise (400 MHz, 1 MHz, 50 kHz) Rev. 0 | Page 7 of 24 ADF4002 THEORY OF OPERATION REFERENCE INPUT SECTION The equation for the VCO frequency is The reference input stage is shown in Figure 11. SW1 and SW2 are normally closed switches. SW3 is normally open. When power-down is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures that there is no loading of the REFIN pin on power-down. POWER-DOWN CONTROL f fVCO = N × REFIN R where: fVCO is the output frequency of external voltage controlled oscillator (VCO). N is the preset divide ratio of binary 13-bit counter (1 to 8191). fREFIN is the external reference frequency oscillator. 100kΩ NC FROM N COUNTER LATCH SW2 TO R COUNTER NC BUFFER NO FROM RF INPUT STAGE 06052-013 SW1 SW3 13-BIT N COUNTER TO PFD 06052-021 REFIN Figure 13. N Counter Figure 11. Reference Input Stage R COUNTER RF INPUT STAGE The 14-bit R counter allows the input reference frequency to be divided down to produce the reference clock to the phase frequency detector (PFD). Division ratios from 1 to 16,383 are allowed. The RF input stage is shown in Figure 12. It is followed by a 2-stage limiting amplifier to generate the CML clock levels needed for the N counter. BIAS GENERATOR 500Ω PHASE FREQUENCY DETECTOR (PFD) AND CHARGE PUMP 1.6V AVDD The PFD takes inputs from the R counter and N counter and produces an output proportional to the phase and frequency difference between them. Figure 14 is a simplified schematic. The PFD includes a programmable delay element that controls the width of the antibacklash pulse. This pulse ensures that there is no dead zone in the PFD transfer function, and minimizes phase noise and reference spurs. Two bits in the reference counter latch (ABP2 and ABP1) control the width of the pulse. See Figure 17 for details. The smallest antibacklash pulse width (1.3 ns) should be used if the desired PFD exceeds 104 MHz. 500Ω RFINA AGND 06052-014 RFINB Figure 12. RF Input Stage N COUNTER The N CMOS counter allows a wide ranging division ratio in the PLL feedback counter. Division ratios from 1 to 8191 are allowed. N and R Relationship The N counter makes it possible to generate output frequencies that are spaced only by the reference frequency divided by R. Rev. 0 | Page 8 of 24 ADF4002 VP D1 HI Q1 CHARGE PUMP UP U1 R DIVIDER CLR1 PROGRAMMABLE DELAY ABP2 U3 CP ABP1 CLR2 DOWN D2 Q2 HI 06052-023 U2 N DIVIDER CPGND Digital lock detect is active high. When LDP in the R counter latch is set to 0, digital lock detect is set high when the phase error on three consecutive phase detector (PD) cycles is less than 15 ns. With LDP set to 1, five consecutive cycles of less than 15 ns are required to set the lock detect. It stays set at high until a phase error of greater than 25 ns is detected on any subsequent PD cycle. For PFD frequencies greater than 10 MHz, analog lock detect is more accurate because of the smaller pulse widths. The N-channel, open-drain, analog lock detect should be operated with an external pull-up resistor of 10 kΩ nominal. When lock has been detected this output is high with narrow, low-going pulses. Figure 14. PFD Simplified Schematic and Timing (In Lock) INPUT SHIFT REGISTER MUXOUT AND LOCK DETECT The ADF4002 digital section includes a 24-bit input shift register, a 14-bit R counter, and a 13-bit N counter. Data is clocked into the 24-bit shift register on each rising edge of CLK. The data is clocked in MSB-first. Data is transferred from the shift register to one of four latches on the rising edge of LE. The destination latch is determined by the state of the two control bits (C2, C1) in the shift register. These are the two LSBs, DB1 and DB0, as shown in the timing diagram (see Figure 2). Table 6 provides the truth table for these bits. Figure 16 shows a summary of how the latches are programmed. The output multiplexer on the ADF4002 allows the user to access various internal points on the chip. The state of MUXOUT is controlled by M3, M2, and M1 in the function latch. Figure 19 shows the full truth table. Figure 15 shows the MUXOUT section in block diagram form. DVDD ANALOG LOCK DETECT Table 6. C2, C1 Truth Table DIGITAL LOCK DETECT R COUNTER OUTPUT MUX CONTROL MUXOUT N COUNTER OUTPUT DGND 06052-024 SDOUT Control Bits C2 C1 0 0 0 1 1 0 1 1 Figure 15. MUXOUT Circuit Lock Detect MUXOUT can be programmed for two types of lock detect: digital lock detect and analog lock detect. Rev. 0 | Page 9 of 24 Data Latch R Counter N Counter Function Latch Initialization Latch ADF4002 LATCH MAPS AND DESCRIPTIONS LATCH SUMMARY LOCK DETECT PRECISION REFERENCE COUNTER LATCH RESERVED TEST MODE BITS ANTIBACKLASH WIDTH DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 X 0 0 LDP T2 T1 CONTROL BITS 14-BIT REFERENCE COUNTER ABP2 ABP1 R14 R13 R12 R11 R10 R9 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 R8 R7 R6 R5 R4 R3 R2 R1 C2 (0) C1 (0) RESERVED CP GAIN N COUNTER LATCH 13-BIT N COUNTER DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 G1 B13 B12 B11 B10 B9 B8 B7 B6 CONTROL BITS RESERVED B5 B4 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 B2 B1 X X X X X X C2 (0) C1 (1) MUXOUT CONTROL CONTROL BITS B3 DB1 DB0 FASTLOCK ENABLE CP THREESTATE PD POLARITY POWERDOWN 1 COUNTER RESET DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 F4 F3 F2 M3 M2 M1 PD1 F1 C2 (1) C1 (0) MUXOUT CONTROL RESERVED X X POWERDOWN 2 FASTLOCK MODE FUNCTION LATCH PD2 CURRENT SETTING 2 CPI6 CPI5 CPI4 CURRENT SETTING 1 CPI3 CPI2 CPI1 TIMER COUNTER CONTROL TC4 TC3 TC2 TC1 F5 DB1 DB0 FASTLOCK ENABLE CP THREESTATE PD POLARITY POWERDOWN 1 COUNTER RESET CONTROL BITS DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 F4 F3 F2 M3 M2 M1 PD1 F1 X X PD2 CURRENT SETTING 2 CPI6 CPI5 CPI4 CURRENT SETTING 1 CPI3 CPI2 TIMER COUNTER CONTROL CPI1 TC4 TC3 TC2 TC1 F5 Figure 16. Latch Summary Rev. 0 | Page 10 of 24 DB0 C2 (1) C1 (1) 06052-015 RESERVED POWERDOWN 2 FASTLOCK MODE INITIALIZATION LATCH ADF4002 LOCK DETECT PRECISION REFERENCE COUNTER LATCH MAP RESERVED TEST MODE BITS ANTIBACKLASH WIDTH DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 X 0 0 LDP T2 T1 ABP2 ABP1 CONTROL BITS 14-BIT REFERENCE COUNTER R14 R13 R12 R11 R10 R9 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 R8 R7 R6 R5 R4 R3 R2 R1 C2 (0) C1 (0) X = DON’T CARE ABP2 0 0 1 1 ABP1 0 1 0 1 R14 R13 R12 .......... R3 R2 R1 DIVIDE RATIO 0 0 0 0 . . . 0 0 0 0 . . . 0 0 0 0 . . . .......... .......... .......... .......... .......... .......... .......... 0 0 0 1 . . . 0 1 1 0 . . . 1 0 1 0 . . . 1 2 3 4 . . . 1 1 1 1 1 1 1 1 1 1 1 1 .......... .......... .......... .......... 1 1 1 1 0 0 1 1 0 1 0 1 16380 16381 16382 16383 ANTIBACKLASH PULSEWIDTH 2.9ns 1.3ns 6.0ns 2.9ns TEST MODE BITS SHOULD BE SET TO 00 FOR NORMAL OPERATION. LDP 0 1 OPERATION THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN 15ns MUST OCCUR BEFORE LOCK DETECT IS SET. FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN 15ns MUST OCCUR BEFORE LOCK DETECT IS SET. 06052-025 BOTH OF THESE BITS MUST BE SET TO 0 FOR NORMAL OPERATION. Figure 17. Reference Counter Latch Map Rev. 0 | Page 11 of 24 ADF4002 CP GAIN N COUNTER LATCH MAP RESERVED CONTROL BITS RESERVED 13-BIT N COUNTER DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 X X G1 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 X X X X X X DB1 DB0 C2 (0) C1 (1) X = DON’T CARE N13 N12 N11 0 0 0 0 . . . 1 1 1 1 0 0 0 0 . . . 1 1 1 1 0 0 0 0 . . . 1 1 1 1 F4 (FUNCTION LATCH) CP GAIN FASTLOCK ENABLE .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... N3 N2 N1 N COUNTER DIVIDE RATIO 0 0 0 0 . . . 1 1 1 1 0 0 1 1 . . . 0 0 1 1 0 1 0 1 . . . 0 1 0 1 NOT ALLOWED 1 2 3 . . . 8188 8189 8190 8191 OPERATION 0 0 CHARGE PUMP CURRENT SETTING 1 IS PERMANENTLY USED. 0 1 1 0 1 1 CHARGE PUMP CURRENT SETTING 2 IS PERMANENTLY USED. CHARGE PUMP CURRENT SETTING 1 IS USED. CHARGE PUMP CURRENT IS SWITCHED TO SETTING 2. THE TIME SPENT IN SETTING 2 IS DEPENDENT ON WHICH FASTLOCK MODE IS USED. SEE FUNCTION LATCH DESCRIPTION. 06052-016 THESE BITS ARE NOT USED BY THE DEVICE AND ARE DON'T CARE BITS. THESE BITS ARE NOT USED BY THE DEVICE AND ARE DON'T CARE BITS. Figure 18. N Counter Latch Map Rev. 0 | Page 12 of 24 ADF4002 FASTLOCK ENABLE CP THREESTATE PD POLARITY POWERDOWN 1 COUNTER RESET DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 F4 F3 F2 M3 M2 M1 PD1 F1 RESERVED P2 P1 POWERDOWN 2 FASTLOCK MODE FUNCTION LATCH MAP PD2 CURRENT SETTING 2 CPI6 CPI5 CURRENT SETTING 1 CPI4 CPI3 CPI2 TIMER COUNTER CONTROL CPI1 TC4 TC3 TC2 TC1 TC4 TC3 TC2 TC1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 F5 MUXOUT CONTROL F2 PHASE DETECTOR POLARITY F1 0 1 NEGATIVE POSITIVE 0 1 F3 CHARGE PUMP OUTPUT 0 1 NORMAL THREE-STATE F4 F5 FASTLOCK MODE 0 1 1 X 0 1 FASTLOCK DISABLED FASTLOCK MODE 1 FASTLOCK MODE 2 TIMEOUT (PFD CYCLES) 3 7 11 15 19 23 27 31 35 39 43 47 51 55 59 63 CONTROL BITS DB1 DB0 C2 (1) C1 (0) COUNTER OPERATION NORMAL R, A, B COUNTERS HELD IN RESET M3 M2 M1 OUTPUT 0 0 0 0 0 1 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 1 0 1 THREE-STATE OUTPUT DIGITAL LOCK DETECT (ACTIVE HIGH) N DIVIDER OUTPUT DVDD R DIVIDER OUTPUT N-CHANNEL OPEN-DRAIN LOCK DETECT SERIAL DATA OUTPUT DGND SEE PAGE 16 CPI6 CPI5 CP14 CPI3 0 0 0 0 1 1 1 1 CPI2 0 0 1 1 0 0 1 1 CPI1 0 1 0 1 0 1 0 1 ICP (mA) 3kΩ 1.088 2.176 3.264 4.352 5.440 6.528 7.616 8.704 5.1kΩ 0.625 1.250 1.875 2.500 3.125 3.750 4.375 5.000 CE PIN PD2 PD1 MODE 0 1 1 1 X X 0 1 X 0 1 1 ASYNCHRONOUS POWER-DOWN NORMAL OPERATION ASYNCHRONOUS POWER-DOWN SYNCHRONOUS POWER-DOWN 11kΩ 0.294 0.588 0.882 1.176 1.470 1.764 2.058 2.352 06052-017 THESE BITS ARE NOT USED BY THE DEVICE AND ARE DON'T CARE BITS. Figure 19. Function Latch Map Rev. 0 | Page 13 of 24 ADF4002 FASTLOCK ENABLE CP THREESTATE PD POLARITY POWERDOWN 1 COUNTER RESET DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 F4 F3 F2 M3 M2 M1 PD1 F1 RESERVED P2 P1 POWERDOWN 2 FASTLOCK MODE INITIALIZATION LATCH MAP PD2 CURRENT SETTING 1 CURRENT SETTING 2 CPI6 CPI5 CPI4 CPI3 CPI2 TIMER COUNTER CONTROL CPI1 TC4 TC3 TC2 TC1 TC4 TC3 TC2 TC1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 F5 MUXOUT CONTROL F2 PHASE DETECTOR POLARITY F1 0 1 NEGATIVE POSITIVE 0 1 F3 CHARGE PUMP OUTPUT 0 1 NORMAL THREE-STATE F4 F5 FASTLOCK MODE 0 1 1 X 0 1 FASTLOCK DISABLED FASTLOCK MODE 1 FASTLOCK MODE 2 TIMEOUT (PFD CYCLES) 3 7 11 15 19 23 27 31 35 39 43 47 51 55 59 63 CONTROL BITS DB1 DB0 C2 (1) C1 (1) COUNTER OPERATION NORMAL R, A, B COUNTERS HELD IN RESET M3 M2 M1 OUTPUT 0 0 0 0 0 1 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 1 0 1 THREE-STATE OUTPUT DIGITAL LOCK DETECT (ACTIVE HIGH) N DIVIDER OUTPUT DVDD R DIVIDER OUTPUT N-CHANNEL OPEN-DRAIN LOCK DETECT SERIAL DATA OUTPUT DGND SEE PAGE 16 CPI6 CPI5 CP14 CPI3 0 0 0 0 1 1 1 1 CPI2 0 0 1 1 0 0 1 1 CPI1 0 1 0 1 0 1 0 1 ICP (mA) 3kΩ 1.088 2.176 3.264 4.352 5.440 6.528 7.616 8.704 5.1kΩ 0.625 1.250 1.875 2.500 3.125 3.750 4.375 5.000 CE PIN PD2 PD1 MODE 0 1 1 1 X X 0 1 X 0 1 1 ASYNCHRONOUS POWER-DOWN NORMAL OPERATION ASYNCHRONOUS POWER-DOWN SYNCHRONOUS POWER-DOWN 11kΩ 0.294 0.588 0.882 1.176 1.470 1.764 2.058 2.352 06052-036 THESE BITS ARE NOT USED BY THE DEVICE AND ARE DON'T CARE BITS. Figure 20. Initialization Latch Map Rev. 0 | Page 14 of 24 ADF4002 THE FUNCTION LATCH Fastlock Mode Bit With C2, C1 set to 1, 0, the on-chip function latch is programmed. Figure 19 shows the input data format for programming the function latch. DB10 of the function latch is the fastlock mode bit. When fastlock is enabled, this bit determines the fastlock mode to be used. If the fastlock mode bit is 0, then Fastlock Mode 1 is selected, and if the fastlock mode bit is 1, then Fastlock Mode 2 is selected. Counter Reset DB2 (F1) is the counter reset bit. When this bit is set to 1, the R counter and the N counters are reset. For normal operation, set this bit to 0. Upon powering up, the F1 bit needs to be disabled (set to 0). Then, the N counter resumes counting in close alignment with the R counter (the maximum error is one prescaler cycle). Power-Down Fastlock Mode 1 In this mode, the charge pump current is switched to the contents of Current Setting 2. The device enters fastlock by having a 1 written to the CP gain bit in the N counter latch. The device exits fastlock by having a 0 written to the CP gain bit in the AB counter latch. Fastlock Mode 2 DB3 (PD1) and DB21 (PD2) provide programmable powerdown modes. These bits are enabled by the CE pin. When the CE pin is low, the device is immediately disabled regardless of the states of the PD2, PD1 bits. In the programmed asynchronous power-down, the device powers down immediately after latching a 1 into Bit PD1, with the condition that Bit PD2 has been loaded with a 0. In the programmed synchronous power-down, the device power-down is gated by the charge pump to prevent unwanted frequency jumps. Once the power-down is enabled by writing a 1 into Bit PD1 (on condition that a 1 has also been loaded to Bit PD2), then the device enters power-down on the occurrence of the next charge pump event. When a power-down is activated (either in synchronous or asynchronous mode, including a CE pin activated powerdown), the following events occur: In this mode, the charge pump current is switched to the contents of Current Setting 2. The device enters fastlock by having a 1 written to the CP gain bit in the N counter latch. The device exits fastlock under the control of the timer counter. After the timeout period determined by the value in TC4 to TC1, the CP gain bit in the N counter latch is automatically reset to 0 and the device reverts to normal mode instead of fastlock. See Figure 19 for the timeout periods. Timer Counter Control The user has the option of programming two charge pump currents. The intent is to use the Current Setting 1 when the RF output is stable and the system is in a static state. Current Setting 2 is meant to be used when the system is dynamic and in a state of change, that is, when a new output frequency is programmed. The normal sequence of events is as follows: • All active dc current paths are removed. • The R, N, and timeout counters are forced to their loadstate conditions. • The charge pump is forced into three-state mode. • The digital lock detect circuitry is reset. • The RFIN input is debiased. • The reference input buffer circuitry is disabled. • The input register remains active and capable of loading and latching data. The user initially decides the referred charge pump currents. For example, the choice can be 2.5 mA as Current Setting 1 and 5 mA as Current Setting 2. At the same time, the decision must be made as to how long the secondary current is to stay active before reverting to the primary current. This is controlled by Timer Counter Control Bit DB14 to Timer Counter Control Bit DB11 (TC4 to TC1) in the function latch. See Figure 19 for the truth table. MUXOUT Control The on-chip multiplexer is controlled by M3, M2, and M1 on the ADF4002. Figure 19 shows the truth table. Fastlock Enable Bit DB9 of the function latch is the fastlock enable bit. Only when this is 1 is fastlock enabled. To program a new output frequency, simply program the N counter latch with a new value for N. At the same time, the CP gain bit can be set to 1. This sets the charge pump with the value in CPI6 to CPI4 for a period of time determined by TC4 to TC1. When this time is up, the charge pump current reverts to the value set by CPI3 to CPI1. At the same time, the CP gain bit in the N counter latch is reset to 0 and is ready for the next time that the user wishes to change the frequency. Note that there is an enable feature on the timer counter. It is enabled when Fastlock Mode 2 is chosen by setting the Fastlock Mode Bit DB10 in the function latch to 1. Rev. 0 | Page 15 of 24 ADF4002 Charge Pump Currents • An internal pulse resets the R, N, and timeout counters to load-state conditions and three-states the charge pump. Note that the prescaler band gap reference and the oscillator input buffer are unaffected by the internal reset pulse, allowing close phase alignment when counting resumes. • Latching the first N counter data after the initialization word activates the same internal reset pulse. Successive N loads do not trigger the internal reset pulse unless there is another initialization. CPI3, CPI2, and CPI1 program Current Setting 1 for the charge pump. CPI6, CPI5, and CPI4 program Current Setting 2 for the charge pump. See Figure 19 for the truth table. PD Polarity This bit sets the phase detector polarity bit (see Figure 19). CP Three-State This bit controls the CP output pin. Setting the bit high, puts the CP output into three-state. With the bit set low, the CP output is enabled. CE Pin Method 1. Apply VDD. The initialization latch is programmed when C2, C1 = 1, 1. This is essentially the same as the function latch (programmed when C2, C1 = 1, 0). 2. Bring CE low to put the device into power-down. This is an asynchronous power-down because it happens immediately. However, when the initialization latch is programmed there is an additional internal reset pulse applied to the R and N counters. This pulse ensures that the N counter is at load point when the N counter data is latched and the device begins counting in close phase alignment. 3. Program the function latch (10). 4. Program the R counter latch (00). 5. Program the N counter latch (01). 6. Bring CE high to take the device out of power-down. The R and N counters resume counting in close alignment. Note that after CE goes high, a duration of 1 μs can be required for the prescaler band gap voltage and oscillator input buffer bias to reach steady state. THE INITIALIZATION LATCH If the latch is programmed for synchronous power-down (CE pin is high; PD1 bit is high; and PD2 bit is low), the internal pulse also triggers this power-down. The prescaler reference and the oscillator input buffer are unaffected by the internal reset pulse, thereby maintaining close phase alignment when counting resumes. When the first N counter data is latched after initialization, the internal reset pulse is reactivated. However, successive AB counter loads after this do not trigger the internal reset pulse. Counter Reset Method Device Programming After Initial Power-Up After initially powering up the device, there are three ways to program the device. Initialization Latch Method 1. Apply VDD. 2. Program the initialization latch (11 in two LSBs of input word). Make sure that the F1 bit is programmed to 0. 3. Conduct a function latch load (10 in two LSBs of the control word). Make sure that the F1 bit is programmed to 0. 4. Perform an R load (00 in two LSBs). 5. Perform an N load (01 in two LSBs). When the initialization latch is loaded, the following occurs: • CE can be used to power the device up and down to check for channel activity. The input register does not need to be reprogrammed each time the device is disabled and enabled, as long as it has been programmed at least once after VDD was initially applied. 1. Apply VDD. 2. Do a function latch load (10 in two LSBs). As part of this step, load 1 to the F1 bit. This enables the counter reset. 3. Perform an R counter load (00 in two LSBs). 4. Perform an N counter load (01 in two LSBs). 5. Do a function latch load (10 in two LSBs). As part of this step, load 0 to the F1 bit. This disables the counter reset. This sequence provides the same close alignment as the initialization method. It offers direct control over the internal reset. Note that counter reset holds the counters at load point and three-states the charge pump, but does not trigger synchronous power-down. The function latch contents are loaded. Rev. 0 | Page 16 of 24 ADF4002 APPLICATIONS The design of the loop filter uses the ADIsimPLL (Version 3.0) and is available as a free download from www.analog.com/pll. The rms jitter is measured at <1.2 ps. This level is lower than the maximum allowable 6 ps rms required to ensure the theoretical SNR performance of 59 dB for this converter. VERY LOW JITTER ENCODE CLOCK FOR HIGH SPEED CONVERTERS Figure 21 shows the ADF4002 with a VCXO to provide the encode clock for a high speed analog-to-digital converter (ADC). The converter used in this application is an AD9215-80, a 12-bit converter that accepts up to an 80 MHz encode clock. To realize a stable low jitter clock, use a 77.76 MHz, narrow band VCXO. This example assumes a 19.44 MHz reference clock. The setup shown in Figure 21 using the ADF4002, AD9215, and HSC-ADC-EVALA-SC, allows the user to quickly and effectively determine the suitability of the converter and encode clock. The SPI® interface is used to control the ADF4002, and the USB interface helps control the operation of the AD921580. The controller board sends back FFT information to the PC that, if using an ADC analyzer, provides all conversion results from the ADC. To minimize the phase noise contribution of the ADF4002, the smallest multiplication factor of 4 is used. Thus, the R divider is programmed to 1, and the N divider is programmed to 4. The charge pump output of the ADF4002 (Pin 2) drives the loop filter. The loop filter bandwidth is optimized for the best possible rms jitter, a key factor in the signal-to-noise ratio (SNR) of the ADC. Too narrow a bandwidth allows the VCXO noise to dominate at small offsets from the carrier frequency. Too wide a bandwidth allows the ADF4002 noise to dominate at offsets where the VCXO noise is lower than the ADF4002 noise. Thus, the intersection of the VCXO noise and the ADF4002 inband noise is chosen as the optimum loop filter bandwidth. SPI TCXO: 19.44MHz ADF4002 VCXO: 77.76MHz R=1 PC PD USB N=4 AGILENT: 500kHz, 1.8V p-p AIN HC-ADC-EVALA-SC AD9215-80 Figure 21. ADF4002 as Encode Clock Rev. 0 | Page 17 of 24 06052-034 ENCODE CLOCK ADF4002 PFD As the ADF4002 permits both R and N counters to be programmed to 1, the part can effectively be used as a stand alone PFD and charge pump. This is particularly useful in either a clock cleaning application or a high performance LO. Additionally, the very low normalized phase noise floor (−222 dBc/Hz) enables very low in-band phase noise levels. It is possible to operate the PFD up to a maximum frequency of 200 MHz. In Figure 22, the reference frequency equals the PFD, therefore, R = 1. The charge pump output integrates into a stable control voltage for the VCXO, and the output from the VCXO is divided down to the desired PFD frequency using an external divider. VP On first applying power to the ADF4002, it needs four writes (one each to the initialization latch, function latch, R counter latch, and N counter latch) for the output to become active. I/O port lines on the ADuC812 are also used to control powerdown (CE input) and to detect lock (MUXOUT configured as lock detect and polled by the port input). When operating in the SPI master mode, the maximum SCLOCK rate of the ADuC812 is 4 MHz. This means that the maximum rate at which the output frequency can be changed is 166 kHz. RFOUT SCLOCK 100pF RSET REFIN 1 10kΩ 4 DGND AGND CPGND ADF4002 3 LOOP FILTER RFINA 6 RFINB 5 100pF VCO 100pF 18Ω OR VCXO GND ADF4002 LE I/O PORTS 18Ω VCC Figure 23. ADuC812 to ADF4002 Interface 51Ω GND DECOUPLING CAPACITORS AND INTERFACE SIGNALS HAVE BEEN OMITTED FROM THE DIAGRAM IN THE INTERESTS OF GREATER CLARITY. CE MUXOUT (LOCK DETECT) VCC EXTERNAL PRESCALER 100pF 9 DATA ADuC812 06052-019 VP CE DVDD 8 2 MOSI 18Ω VCC ADSP2181 Interface 06052-035 REFIN 16 15 AVDD 7 CLK Figure 22. ADF4002 as a PFD INTERFACING The ADF4002 has a simple SPI-compatible serial interface for writing to the device. CLK, DATA, and LE control the data transfer. When the latch enable (Pin LE) goes high, the 24 bits that have been clocked into the input register on each rising edge of CLK are transferred to the appropriate latch. For more information, see Figure 2 for the timing diagram and Table 6 for the latch truth table. Figure 24 shows the interface between the ADF4002 and the ADSP21xx digital signal processor. The ADF4002 needs a 24-bit serial word for each latch write. The easiest way to accomplish this using the ADSP21xx family is to use the autobuffered transmit mode of operation with alternate framing. This provides a means for transmitting an entire block of serial data before an interrupt is generated. Set up the word length for 8 bits and use three memory locations for each 24-bit word. To program each 24-bit latch, store the three 8-bit bytes, enable the autobuffered mode, and then write to the transmit register of the DSP. This last operation initiates the autobuffer transfer. SCLK The maximum allowable serial clock rate is 20 MHz. This means that the maximum update rate possible for the device is 833 kHz, or one update every 1.2 μs. This is certainly more than adequate for systems that have typical lock times in hundreds of microseconds. DT DATA ADF4002 ADSP21xx TFS LE CE I/O FLAGS ADuC812 Interface Figure 23 shows the interface between the ADF4002 and the ADuC812 MicroConverter®. Since the ADuC812 is based on an 8051 core, this interface can be used with any 8051-based microcontroller. The MicroConverter is set up for SPI master mode with CPHA = 0. To initiate the operation, the I/O port driving LE is brought low. Each latch of the ADF4002 needs a 24-bit word. This is accomplished by writing three, 8-bit bytes from the MicroConverter to the device. When the third byte CLK MUXOUT (LOCK DETECT) 06052-020 VDD has been written, bring the LE input high to complete the transfer. Figure 24. ADSP-21xx to ADF4002 Interface PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE The lands on the lead frame chip scale package (CP-20-1) are rectangular. The printed circuit board pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. The land should be centered on the pad. This ensures that the solder joint size is maximized. Rev. 0 | Page 18 of 24 ADF4002 The bottom of the lead frame chip scale package has a central thermal pad. The thermal pad on the printed circuit board should be at least as large as this exposed pad. On the printed circuit board, there should be a clearance of at least 0.25 mm between the thermal pad and the inner edges of the pad pattern. This ensures that shorting is avoided. Thermal vias can be used on the printed circuit board thermal pad to improve thermal performance of the package. If vias are used, they should be incorporated in the thermal pad at a 1.2 mm pitch grid. The via diameter should be between 0.3 mm and 0.33 mm and the via barrel should be plated with 1 oz. copper to plug the via. The user should connect the printed circuit board thermal pad to AGND. Rev. 0 | Page 19 of 24 ADF4002 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.30 0.19 0.65 BSC COPLANARITY 0.10 0.20 0.09 0.75 0.60 0.45 8° 0° SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 25. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters 0.60 MAX 4.00 BSC SQ 0.60 MAX PIN 1 INDICATOR TOP VIEW 1.00 0.85 0.80 SEATING PLANE 0.50 BSC 16 15 20 1 11 10 6 2.25 2.10 SQ 1.95 3.75 BCS SQ 0.80 MAX 0.65 TYP 12° MAX PIN 1 INDICATOR 0.20 REF 0.75 0.55 0.35 5 0.25 MIN 0.30 0.23 0.18 0.05 MAX 0.02 NOM COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1 Figure 26. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] (CP-20-1) Dimensions shown in millimeters Rev. 0 | Page 20 of 24 ADF4002 ORDERING GUIDE Model ADF4002BRUZ1 ADF4002BRUZ–RL1 ADF4002BRUZ–RL71 ADF4002BCPZ1 ADF4002BCPZ–RL1 ADF4002BCPZ–RL71 EVAL-ADF4002EB1 EVAL-ADF411XEB1 1 Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Package Description 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 20-Lead LFCSP_VQ 20-Lead LFCSP_VQ 20-Lead LFCSP_VQ Evaluation Board Evaluation Board Z = Pb-free part. Rev. 0 | Page 21 of 24 Package Option RU-16 RU-16 RU-16 CP-20-1 CP-20-1 CP-20-1 ADF4002 NOTES Rev. 0 | Page 22 of 24 ADF4002 NOTES Rev. 0 | Page 23 of 24 ADF4002 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06052-0-4/06(0) Rev. 0 | Page 24 of 24