PHILIPS PNX2000HL

PNX2000
Audio video input processor
Rev. 03 – 23 August 2004
Product data
1. General description
The PNX2000 is a companion IC for use with the Nexperia™ 1 digital video home
entertainment engines such as PNX8526 and PNX8550.
The PNX2000 is always used in combination with the PNX3000.
PNX2000 is intended for mid to high-end analog and hybrid TV sets, performing input
decoding of single stream analog audio and single stream analog video signals. In
addition, the PNX2000 is used for decoding and presentation of all audio output streams
in the system. Figure 1 shows a block diagram of the device.
2. Features
■ Detection of PAL, NTSC or SECAM, and various 1fH and 2fH component video input
sources.
■ Full support for 1fH and 2fH video sources; progressive and interlaced.
■ Decoding for global VBI Standards (WST, WSS, VPS, CC, VITC).
■ ITU-656 output interface.
■ Global multi-standard audio demodulation and decoding.
■ Dolby Pro Logic II™ 2 multi-channel audio decoding and post-processing.
■ Advanced fully programmable audio post-processing functions, including
psychoacoustic spatial algorithms for optimal loudspeaker matching.
3. Applications
■
■
■
■
Analog TV receivers.
Hybrid TV receivers.
DVD recorders.
VCRs.
1.
Nexperia is a trademark of Koninklijke Philips Electronics N.V.
2.
Dolby is a trademark of Dolby Laboratories
PNX2000
Philips Semiconductors
Audio video input processor
4. Ordering information
Table 1:
Ordering information
Type number
Package
name
Description
Version
PNX2000HL
LQFP144
plastic low profile quad flat package; 144 leads; body 20 × 20 × 1.4 mm
SOT486-1
5. Block diagram
DLINK2
DLINK1
DLINK3
video data CVBS, Y/C, YUV
54 MHz clock
27 Msps or 54 Msps
PNX2000
audio data SIF or L/R
I2C-bus
I2D
I2C-BUS
HSYNC
VIDDEC
INT
GTU
HSYNC/
VSYNC
DCU
13.5 MHz or
27 MHz
Xtal
CLOCKS
ITU-656
DEMDEC DSP
6× I2S-bus
outputs
PI-bus
AUDIO DSP
6× I2S-bus
inputs
×4
×6
×2
BCU
mce559
PNX3000
interface
(2 stereo
or 4 mono)
ITU-656
1fH or 2fH
10-bit data
Fig 1. Block diagram
9397 750 13928
Product data
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 03 – 23 August 2004
2 of 31
PNX2000
Philips Semiconductors
Audio video input processor
6. Pinning information
109
144
6.1 Pinning
1
108
PNX2000HL
72
73
37
36
001aaa287
Fig 2. Pin configuration
6.1.1 Pin description
Table 2 describes acronyms used in the pin tables:
Table 2:
Acronym description
Acronym
Description
3V
3.3 V LVCMOS
5VT
5 V tolerant inputs
Z
3-state
TTL
TTL logic
TTL-H
TTL with hysteresis
CMOS
CMOS logic
IA
Input Analog
ID
Input Digital
OD
Output Digital
OA
Output Analog
IOA
I/O Analog
IOD
I/O Digital
GA
Ground Analog
SA
Supply Analog
SD
Supply Digital
OSCIN
Crystal Oscillator Input
OSCOUT
Crystal Oscillator Output
OSCGND
Crystal Oscillator Ground
9397 750 13928
Product data
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 03 – 23 August 2004
3 of 31
PNX2000
Philips Semiconductors
Audio video input processor
Table 3:
Pins in numerical sequence
Pin
Symbol
Type
Description
1
VSSD(I2D)
GD
I2D digital ground
2
DLINK1DP
IA
analog differential data link 1 positive termination
3
DLINK1DN
IA
analog differential data link 1 negative termination
4
DLINK1SP
IA
analog differential strobe link 1 positive termination
5
DLINK1SN
IA
analog differential strobe link 1 negative termination
7
DLINK2DP
IA
analog differential data link 2 positive termination
8
DLINK2DN
IA
analog differential data link 2 negative termination
9
DLINK2SP
IA
analog differential strobe link 2 positive termination
10
DLINK2SN
IA
analog differential strobe link 2 negative termination
12
DLINK3DP
IA
analog differential data link 3 positive termination
13
DLINK3DN
IA
analog differential data link 3 negative termination
14
DLINK3SP
IA
analog differential strobe link 3 positive termination
15
DLINK3SN
IA
analog differential strobe link 3 negative termination
16
VDDD(I2D)
SD
I2D digital 1.8 V supply voltage
17
I2C_ADR
ID
I2C-bus address select (internal pull-down); TTL; 5VT
18
HSYNCFBL1
IA
horizontal sync (external); fastblanking signal from
SCART
19
HSYNCFBL2
IA
horizontal sync (external); fastblanking signal from
SCART
20
HVINFO
OD
horizontal and vertical sync information to PNX3000;
CMOS
21
VSYNC1
ID
vertical sync (external); TTL; 5VT
22
VSYNC2
ID
vertical sync (external); TTL; 5VT
23
VDD3(DTC)
SD
DTC 3.3 V supply voltage
24
VDDD(DTC)
SD
DTC 1.8 V supply voltage
25
VSS(DTC)
GA
DTC analog ground
26
I2C_SCL
IOD
I2C-bus clock; TTL; Z; 5VT
27
I2C_SDA
IOD
I2C-bus data; TTL; Z; 5VT
28
VSSE
-
3.3 V ground
29
VSS
-
1.8 V ground
30
VDDI
-
1.8 V supply voltage
31
MPIFCLK
OD
13.5 MHz or 27 MHz to PNX3000; CMOS
32
VDDE
-
3.3 V supply voltage
33
VDDA(PLL)
-
phase locked loop 1.8 V supply voltage
34
-
n.c.
not connected
35
VDDI
-
1.8 V supply voltage
36
VSS
-
1.8 V ground
37
VDDA(XTAL)
OSCVDD
1.8 V crystal oscillator supply voltage
38
XIN
OSCIN
crystal oscillator input
39
XOUT
OSCOUT
crystal oscillator output
40
XGND
OSCGND
crystal oscillator ground
9397 750 13928
Product data
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 03 – 23 August 2004
4 of 31
PNX2000
Philips Semiconductors
Audio video input processor
Table 3:
Pins in numerical sequence…continued
Pin
Symbol
Type
Description
41
VSSE
-
3.3 V ground
42
VDDI
-
1.8 V supply voltage
43
VSS
-
1.8 V ground
44
VDDM
-
1.8 V supply voltage for KSFRAMs and KROMs
45
RESET_N
IA
external reset input
46
RESET_SEL
ID
selects between using an external reset input or using
internal POR; TTL; 5VT
47
DCLK
OD
reserved; CMOS
48
INTOUT
OD
interrupt line output; Z; 5VT
49
VDDE
-
3.3 V supply voltage
50
LL_CLK
ID
reserved; TTL; 5VT
51
DVO_CLK
OD
digital video output clock; CMOS; Z
52
DVO_VALID
OD
digital video data valid; CMOS; Z
53
VDDI
-
1.8 V supply voltage
54
VSS
-
1.8 V ground
55
DVO_DATA_0
OD
digital video output state 0; CMOS; Z
56
DVO_DATA_1
OD
digital video output state 1; CMOS; Z
57
DVO_DATA_2
OD
digital video output state 2; CMOS; Z
58
DVO_DATA_3
OD
digital video output state 3; CMOS; Z
59
VSSE
-
3.3 V ground
60
DVO_DATA_4
OD
digital video output state 4; CMOS; Z
61
DVO_DATA_5
OD
digital video output state 5; CMOS; Z
62
DVO_DATA_6
OD
digital video output state 6; CMOS; Z
63
DVO_DATA_7
OD
digital video output state 7; CMOS; Z
64
DVO_DATA_8
OD
digital video output state 8; CMOS; Z
65
DVO_DATA_9
OD
digital video output state 9; CMOS; Z
66
VDDE
-
3.3 V supply voltage
67
VDDI
-
1.8 V supply voltage
68
VSS
-
1.8 V ground
69
I2S_OUT_SD3
OD
I2S-bus data-out channel 3; CMOS
70
I2S_OUT_SD3_WS
OD
I2S-bus word select channel 3; CMOS
71
I2S_OUT_SD3_SCK
OD
I2S-bus bit clock channel 3; CMOS
72
VSSE
-
3.3 V ground
73
I2S_OUT_SD6
OD
I2S-bus data out channel 6; CMOS
74
I2S_OUT_SD5
OD
I2S-bus data out channel 5; CMOS
75
I2S_OUT_SD4
OD
I2S-bus data out channel 4; CMOS
76
I2S_OUT_SD2
OD
I2S-bus data out channel 2; CMOS
77
I2S_OUT_SD1
OD
I2S-bus data out channel 1; CMOS
78
I2S_WS_SYS
IOD
I2S-bus system word select; TTL-H; CMOS
79
I2S_SCK_SYS
IOD
I2S-bus system bit clock; TTL-H; CMOS
80
VDDI
-
1.8 V supply voltage
9397 750 13928
Product data
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 03 – 23 August 2004
5 of 31
PNX2000
Philips Semiconductors
Audio video input processor
Table 3:
Pins in numerical sequence…continued
Pin
Symbol
Type
Description
81
VSS
-
1.8 V ground
82
VDDE
-
3.3 V supply voltage
83
I2S_IN_SD6
ID
I2S-bus data in channel 6; TTL; 5VT
84
I2S_IN_SD5
ID
I2S-bus data in channel 5; TTL; 5VT
85
I2S_IN_SD4
ID
I2S-bus data in channel 4; TTL; 5VT
86
I2S_IN_SD3
ID
I2S-bus data in channel 3; TTL; 5VT
87
I2S_IN_SD2
ID
I2S-bus data in channel 2; TTL; 5VT
88
I2S_IN_SD1
ID
I2S-bus data in channel 1; TTL; 5VT
89
ADAC_CLK
OD
Used for 128 fs or 256 fs clock output to external audio
DAC; CMOS.
90
-
n.c.
not connected
91
VDDE
-
3.3 V supply voltage
92
TDI
ID
JTAG test data in; TTL-H; 5VT
93
TDO
OD
JTAG test data out; CMOS
94
TCK
ID
JTAG test clock; TTL-H; 5VT
95
TMS
ID
JTAG test mode select; TTL-H; 5VT
96
TRST_N
ID
JTAG reset (active low); TTL-H; 5VT
97
VDDI
-
1.8 V supply voltage
98
VSS
-
1.8 V ground
99
VSSE
-
3.3 V ground
100
VSS(ADAC)
GD
audio DAC 1.8 V digital ground
101
VDDD(ADAC)
SD
audio DAC 1.8 V digital supply voltage
102
VDDA(ADAC)
SA
audio DAC 3.3 V supply voltage
103
ADAC1_P
SA
Positive analog reference derived via emitter follower
from PNX3000 V_SND pin.
104
ADAC1
OA
analog audio output 1
105
ADAC1_N
GA
Negative analog reference star connected at
PNX3000.
106
ADAC2_N
GA
Negative analog reference star connected at
PNX3000.
107
ADAC2
OA
analog audio output 2
108
ADAC2_P
SA
Positive analog reference derived via emitter follower
from PNX3000 V_SND pin.
109
ADAC3_P
SA
Positive analog reference derived via emitter follower
from PNX3000 V_SND pin.
110
ADAC3
OA
analog audio output 3
111
ADAC3_N
GA
Negative analog reference star connected at
PNX3000.
112
ADAC4_N
GA
Negative analog reference star connected at
PNX3000.
113
ADAC4
OA
analog audio output 4
114
ADAC4_P
SA
Positive analog reference derived via emitter follower
from PNX3000 V_SND pin.
9397 750 13928
Product data
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 03 – 23 August 2004
6 of 31
PNX2000
Philips Semiconductors
Audio video input processor
Table 3:
Pins in numerical sequence…continued
Pin
Symbol
Type
Description
115
ADAC5_P
SA
Positive analog reference derived via emitter follower
from PNX3000 V_SND pin.
116
ADAC5
OA
analog audio output 5
117
ADAC5_N
GA
Negative analog reference star connected at
PNX3000.
118
ADAC6_N
GA
Negative analog reference star connected at
PNX3000.
119
ADAC6
OA
analog audio output 6
120
ADAC6_P
SA
Positive analog reference derived via emitter follower
from PNX3000 V_SND pin.
121
ADAC7_P
SA
Positive analog reference derived via emitter follower
from PNX3000 V_SND pin.
122
ADAC7
OA
analog audio output 7
123
ADAC7_N
GA
Negative analog reference star connected at
PNX3000.
124
ADAC8_N
GA
Negative analog reference star connected at
PNX3000.
125
ADAC8
OA
analog audio output 8
126
ADAC8_P
SA
Positive analog reference derived via emitter follower
from PNX3000 V_SND pin.
127
ADAC9_P
SA
Positive analog reference derived via emitter follower
from PNX3000 V_SND pin.
128
ADAC9
OA
analog audio output 9
129
ADAC9_N
GA
Negative analog reference star connected at
PNX3000.
130
ADAC10_N
GA
Negative analog reference star connected at
PNX3000.
131
ADAC10
OA
analog audio output 10
132
ADAC10_P
SA
Positive analog reference derived via emitter follower
from PNX3000 V_SND pin.
133
ADAC11_P
SA
Positive analog reference derived via emitter follower
from PNX3000 V_SND pin.
134
ADAC11
OA
analog audio output 11
135
ADAC11_N
GA
Negative analog reference star connected at
PNX3000.
136
ADAC12_N
GA
Negative analog reference star connected at
PNX3000.
137
ADAC12
OA
analog audio output 12
138
ADAC12_P
SA
Positive analog reference derived via emitter follower
from PNX3000 V_SND pin.
139
VSS
-
1.8 V ground
140
VDDM
-
1.8 V supply voltage for KSFRAMs and KROMs
141
VDDE
-
3.3 V supply voltage
9397 750 13928
Product data
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 03 – 23 August 2004
7 of 31
PNX2000
Philips Semiconductors
Audio video input processor
Table 3:
Pins in numerical sequence…continued
Pin
Symbol
Type
Description
142
VSSE
-
3.3 V ground
143
VDDE
-
3.3 V supply voltage
144
VSSE
-
3.3 V ground
In the tables that follow, signals of the PNX2000 have been sorted by functional group. For
quick reference Table 4 identifies each functional group and associated table.
Table 4:
Signal groups
Functional group
Table number
I2D-bus
Table 5
AUDIO
Table 6
I2S-bus
Table 7
VIDDEC
Table 8
ITU-656
Table 9
JTAG
Table 10
I2C-bus
Table 11
CLOCK
Table 12
GTU
Table 13
RESET
Table 14
DIGITAL SUPPLY
Table 15
ANALOG SUPPLY
Table 16
Table 5:
I2D pins
Symbol
Pin
Type
Description
DLINK1DP
2
IA
analog differential data link 1 positive termination
DLINK1DN
3
IA
analog differential data link 1 negative termination
DLINK1SP
4
IA
analog differential strobe link 1 positive termination
DLINK1SN
5
IA
analog differential strobe link 1 negative termination
DLINK2DP
7
IA
analog differential data link 2 positive termination
DLINK2DN
8
IA
analog differential data link 2 negative termination
DLINK2SP
9
IA
analog differential strobe link 2 positive termination
DLINK2SN
10
IA
analog differential strobe link 2 negative termination
DLINK3DP
12
IA
analog differential data link 3 positive termination
DLINK3DN
13
IA
analog differential data link 3 negative termination
DLINK3SP
14
IA
analog differential strobe link 3 positive termination
DLINK3SN
15
IA
analog differential strobe link 3 negative termination
Table 6:
Audio pins
Symbol
Pin
Type
Description
ADAC1
104
OA
analog audio output 1
ADAC2
107
OA
analog audio output 2
ADAC3
110
OA
analog audio output 3
ADAC4
113
OA
analog audio output 4
9397 750 13928
Product data
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 03 – 23 August 2004
8 of 31
PNX2000
Philips Semiconductors
Audio video input processor
Table 6:
Audio pins…continued
Symbol
Pin
Type
Description
ADAC5
116
OA
analog audio output 5
ADAC6
119
OA
analog audio output 6
ADAC7
122
OA
analog audio output 7
ADAC8
125
OA
analog audio output 8
ADAC9
128
OA
analog audio output 9
ADAC10
131
OA
analog audio output 10
ADAC11
134
OA
analog audio output 11
ADAC12
137
OA
analog audio output 12
ADAC1_P
103
SA
Positive analog reference derived via emitter follower from
PNX3000 V_SND pin.
ADAC1_N
105
GA
Negative analog reference star connected at PNX3000.
ADAC2_P
108
SA
Positive analog reference derived via emitter follower from
PNX3000 V_SND pin.
ADAC2_N
106
GA
Negative analog reference star connected at PNX3000.
ADAC3_P
109
SA
Positive analog reference derived via emitter follower from
PNX3000 V_SND pin.
ADAC3_N
111
GA
Negative analog reference star connected at PNX3000.
ADAC4_P
114
SA
Positive analog reference derived via emitter follower from
PNX3000 V_SND pin.
ADAC4_N
112
GA
Negative analog reference star connected at PNX3000.
ADAC5_P
115
SA
Positive analog reference derived via emitter follower from
PNX3000 V_SND pin.
ADAC5_N
117
GA
Negative analog reference star connected at PNX3000.
ADAC6_P
120
SA
Positive analog reference derived via emitter follower from
PNX3000 V_SND pin.
ADAC6_N
118
GA
Negative analog reference star connected at PNX3000.
ADAC7_P
121
SA
Positive analog reference derived via emitter follower from
PNX3000 V_SND pin.
ADAC7_N
123
GA
Negative analog reference star connected at PNX3000.
ADAC8_P
126
SA
Positive analog reference derived via emitter follower from
PNX3000 V_SND pin.
ADAC8_N
124
GA
Negative analog reference star connected at PNX3000.
ADAC9_P
127
SA
Positive analog reference derived via emitter follower from
PNX3000 V_SND pin.
ADAC9_N
129
GA
Negative analog reference star connected at PNX3000.
ADAC10_P
132
SA
Positive analog reference derived via emitter follower from
PNX3000 V_SND pin.
ADAC10_N
130
GA
Negative analog reference star connected at PNX3000.
ADAC11_P
133
SA
Positive analog reference derived via emitter follower from
PNX3000 V_SND pin.
ADAC11_N
135
GA
Negative analog reference star connected at PNX3000.
ADAC12_P
138
SA
Positive analog reference derived via emitter follower from
PNX3000 V_SND pin.
ADAC12_N
136
GA
Negative analog reference star connected at PNX3000.
9397 750 13928
Product data
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 03 – 23 August 2004
9 of 31
PNX2000
Philips Semiconductors
Audio video input processor
Table 7:
I2S-bus pins
Symbol
Pin
Type
Description
I2S_IN_SD1
88
ID
I2S-bus data in channel 1; TTL; 5VT
I2S_IN_SD2
87
ID
I2S-bus data in channel 2; TTL; 5VT
I2S_IN_SD3
86
ID
I2S-bus data in channel 3; TTL; 5VT
I2S_IN_SD4
85
ID
I2S-bus data in channel 4; TTL; 5VT
I2S_IN_SD5
84
ID
I2S-bus data in channel 5; TTL; 5VT
I2S_IN_SD6
83
ID
I2S-bus data in channel 6; TTL; 5VT
I2S_OUT_SD1
77
OD
I2S-bus data out channel 1; CMOS
I2S_OUT_SD2
76
OD
I2S-bus data out channel 2; CMOS
I2S_OUT_SD4
75
OD
I2S-bus data out channel 4; CMOS
I2S_OUT_SD5
74
OD
I2S-bus data out channel 5; CMOS
I2S_OUT_SD6
73
OD
I2S-bus data out channel 6; CMOS
I2S_OUT_SD3_SCK
71
OD
I2S-bus bit clock channel 3; CMOS
I2S_OUT_SD3_WS
70
OD
I2S-bus word select channel 3; CMOS
I2S_OUT_SD3
69
OD
I2S-bus data-out channel 3; CMOS
I2S_SCK_SYS
79
IOD
I2S-bus system bit clock; TTL-H; CMOS
I2S_WS_SYS
78
IOD
I2S-bus system word select; TTL-H; CMOS
ADAC_CLK
89
OD
Used for 128 fs or 256 fs clock output to external audio
DAC; CMOS.
Table 8:
VIDDEC pins
Symbol
Pin
Type
HVINFO
20
OD
horizontal and vertical sync information to PNX3000; CMOS
HSYNCFBL1
18
IA
horizontal sync (external); fastblanking signal from SCART
HSYNCFBL2
19
IA
horizontal sync (external); fastblanking signal from SCART
VSYNC1
21
ID
vertical sync (external); TTL; 5VT
VSYNC2
22
ID
vertical sync (external); TTL; 5VT
Description
Table 9:
ITU-656 pins
Symbol
Pin
Type
Description
DVO_DATA_0
55
OD
digital video output state 0; CMOS; Z
DVO_DATA_1
56
OD
digital video output state 1; CMOS; Z
DVO_DATA_2
57
OD
digital video output state 2; CMOS; Z
DVO_DATA_3
58
OD
digital video output state 3; CMOS; Z
DVO_DATA_4
60
OD
digital video output state 4; CMOS; Z
DVO_DATA_5
61
OD
digital video output state 5; CMOS; Z
DVO_DATA_6
62
OD
digital video output state 6; CMOS; Z
DVO_DATA_7
63
OD
digital video output state 7; CMOS; Z
DVO_DATA_8
64
OD
digital video output state 8; CMOS; Z
DVO_DATA_9
65
OD
digital video output state 9; CMOS; Z
9397 750 13928
Product data
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 03 – 23 August 2004
10 of 31
PNX2000
Philips Semiconductors
Audio video input processor
Table 9:
ITU-656 pins…continued
Symbol
Pin
Type
Description
DVO_VALID
52
OD
digital video data valid; CMOS; Z
DVO_CLK
51
OD
digital video output clock; CMOS; Z
LL_CLK
50
ID
reserved; TTL; 5VT [1]
[1]
It is recommended to bias this pad with a 10 kΩ resistor
Table 10:
JTAG pins
Symbol
Pin
Type
Description
TDO
93
OD
JTAG test data out; CMOS
TDI
92
ID
JTAG test data in; TTL-H; 5VT
TCK
94
ID
JTAG test clock; TTL-H; 5VT
TRST_N [1]
96
ID
JTAG reset (active low); TTL-H; 5VT
TMS
95
ID
JTAG test mode select; TTL-H; 5VT
[1]
It is recommended to pull-down TRST_N with a 10 kΩ resistor. This ensures correct reset state of internal
TAP circuitry and correct POR of the device within defined state machine.
Table 11:
I2C-bus pins
Symbol
Pin
Type
Description
I2C_SDA
27
IOD
I2C-bus data; TTL; Z; 5VT
I2C_SCL
26
IOD
I2C-bus clock; TTL; Z; 5VT
I2C_ADR
17
ID
I2C-bus address select (internal pull-down); TTL; 5VT
Table 12:
Clock pins
Symbol
Pin
Type
Description
MPIFCLK
31
OD
13.5 MHz or 27 MHz to PNX3000; CMOS
DCLK
47
OD
reserved; CMOS
XIN
38
OSCIN
crystal oscillator input
XOUT
39
OSCOUT
crystal oscillator output
XGND
40
OSCGND
crystal oscillator ground
Table 13:
GTU pins
Symbol
Pin
Type
Description
INTOUT
48
OD
interrupt line output; Z; 5VT
Table 14:
Reset pins
Symbol
Pin
Type
Description
RESET_N
45
IA
external reset input
RESET_SEL
46
ID
selects between using an external reset input or using
internal POR; TTL; 5VT
HIGH = internal reset
LOW = external reset
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Audio video input processor
Table 15:
Digital supply pins
Symbol
Pin
Type Description
VDDE
32,49,66, 82,91,
-
3.3 V supply voltage
-
3.3 V ground
30,35,53,67, 80,97
-
1.8 V supply voltage
29,36,43, 54,68,81,
98,139
-
1.8 V ground
44,140
-
1.8 V supply voltage for KSFRAMs and KROMs
VSSD(I2D)
1
GD
I2D digital ground
VDDD(I2D)
16
SD
I2D digital 1.8 V supply voltage
VSS(ADAC)
100
GD
audio DAC 1.8 V digital ground
VDDD(ADAC)
101
SD
audio DAC 1.8 V digital supply voltage
VDD3(DTC)
23
SD
DTC 3.3 V supply voltage
VDDD(DTC)
24
SD
DTC 1.8 V supply voltage
141,143
28,41,59, 72,99,
VSSE
142,144
VDDI
[1]
VSS
VDDM
[1]
[1]
VDDI and VDDM can be connected to same 1.8 V supply voltage.
Table 16:
Analog supply pins
Symbol
Pin
Type
Description
VSSA(I2D)
6
GA
I2D analog ground
VDDA(I2D)
11
SA
I2D analog 1.8 V supply voltage
VDDA(PLL)
33
-
phase locked loop 1.8 V supply voltage
VDDA(ADAC)
102
SA
audio DAC 3.3 V supply voltage
VSS(DTC)
25
GA
DTC analog ground
VDDA(XTAL)
37
OSCVDD
1.8 V crystal oscillator supply voltage
7. Functional description
7.1 Overview
Table 17 describes the functions of the hardware blocks (see also PNX2000 Block
Diagram Figure 1).
For more detailed functional description refer to the PNX2000 User Manual.
Table 17:
Block function
Function
Block
Description
High speed data link
I2D
Receives data in three streams from PNX3000.
Video decoder
processor
VIDDEC
Decodes and processes CVBS, YUV or Y/C in YUV
stream.
Serial interface
I2C-bus
To access all the internal registers.
Global Task Unit
GTU
Generates all the internal clocks, reset and power
management.
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Audio video input processor
Table 17:
Block function…continued
Function
Block
Description
TV sound decoder
DEMDEC
DSP
Demodulation, decoding of terrestrial TV audio standards
.
Audio processor
AUDIO DSP
Processing analog and digital audio sources.
Data Capture Unit
DCU
Acquires VBI data (Teletext; CC; VPS) and formats in a
stream.
Formatter unit
ITU-656
Formats YUV, VBI data and CVBS data in ITU-656.
Bus Control Unit
BCU
Bus arbitration among all the internal blocks.
7.2 Interfaces
Table 18:
Interfaces
Interface
Description
I2C-bus
The PNX2000 IC is controlled using an I2C-bus. It performs like an I2C-bus to PI-bus
bridge, i.e. translates I2C-bus slave received commands to PI-bus master commands.
I2 D
Receives data in three streams from PNX3000.
I2S-bus
Serial digital audio interface (6 stereo inputs, 6 stereo outputs) for connection to other
devices that support the I2S-bus standard. Can be used to receive decoded sound
from a multi-channel digital audio decoder, provide additional ADCs and DACs, or loop
audio signals through an external processor or delay line.
ITU-656
Mainly intended to transfer output data stream externally to the PNX8550, but the
output data stream could also be readable by other ITU-656 input devices that
implement data valid signalling.
DACS
Digital-analog converters used to generate analog outputs from Sound Core.
7.3 Features in detail
7.3.1 Video
•
•
•
•
Automatic Gain Control (AGC) to correct amplitude errors at input source.
Synchronization identification (used for channel search).
Sync processing for 1fH and 2fH video input source.
Standard detection of PAL, NTSC or SECAM and various 1fH and 2fH component
video input sources.
1fH video
•
•
•
•
Color decoding (ITU-601) for PAL, NTSC or SECAM input sources.
2D comb filtering.
Support for component video sources with sync on CVBS or green.
Fastblank insertion of RGB signals onto CVBS input.
2fH video
• Support for various progressive and interlaced component video sources.
• Synchronization of video sources with sync on Y or external H/V inputs.
VBI data capture
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Audio video input processor
• Decoding of 525 line standards; WST, WSS, VPS, CC, VITC.
• Decoding of 625 line standards; WST, WSS, CC, VITC.
ITU-656 output interface
• Video and VBI formatting into ITU-style output data stream, compliant to
ITU-656/1364 (exception being the use of a data valid signal).
• Interfacing to PNX8550 IC.
• Support for CVBS/C mode to interface to external picture improvement devices.
7.3.2 Audio
Demodulator and decoder
•
•
•
•
Demodulator and Decoder Easy Programming (DDEP).
Auto Standard Detection (ASD).
Static Standard Selection (SSS).
DQPSK demodulation for different standards, simultaneously with 1-channel FM
demodulation.
• NICAM decoding (B/G, I, D/K and L standard).
• Two-carrier multi-standard FM demodulation (B/G, D/K and M standard).
• Decoding for three analog multi-channel systems (A2, A2+ and A2*) and satellite
sound.
• Adaptive de-emphasis for satellite FM.
• Optional AM demodulation for system L, simultaneously with NICAM.
• Identification A2 systems (B/G, D/K and M standard) with different identification time
constants.
• FM pilot carrier present detector.
• Monitor selection for FM/AM DC values and signals, with peak and quasi peak
detection option.
•
•
•
•
•
•
•
•
BTSC MPX decoding.
SAP decoding.
dbx® 3 TV noise reduction.
Japan (EIAJ) decoding.
FM radio decoding.
Soft muting for DEMDEC outputs DEC, MONO and SAP.
FM over modulation adaptation option to avoid clipping and distortion.
Sample Rate Conversion (SRC) for up to three demodulated terrestrial audio signals.
Allows processing of SCART and demodulated terrestrial signals.
Audio multi-channel decoder
• Dolby Pro Logic II™
3.
dbx is a registered trademark of Carillon Electronics Corp.
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Philips Semiconductors
Audio video input processor
• 6-channel processing for Main Left and Main Right, Subwoofer, Center, Surround Left
and Surround Right.
Volume and tone control
•
•
•
•
•
•
•
•
•
•
•
•
•
Automatic Volume Level (AVL) control.
Smooth volume control.
Master volume control and balance.
Soft mute.
Loudness.
Bass, treble.
Dynamic Bass Enhancement (DBE).
Dynamic ULTRABASS (DUB).
Non-processed subwoofer.
5-band equalizer.
Acoustical compensation.
Programmable beeper.
Noise generation for loudspeaker level trimming.
Reflection and delay
• Dolby Pro Logic II™ delay.
• Pseudo hall/matrix function.
Psychoacoustic spatial algorithms, downmix and split
•
•
•
•
•
•
Incredible Mono.
Incredible Stereo.
Virtual Dolby Surround™.
Virtual Dolby Digital™.
Bass Redirection according to Dolby™ specifications.
BBE® Sound Processing 4
Interfaces and switching
•
•
•
•
•
•
•
•
4.
Digital audio input interface (stereo I2S-bus input interface).
Digital audio output interface (stereo I2S-bus output interface).
Digital crossbar switch for all digital signal sources and destinations.
Output crossbar for exchange of channel processing functionality.
Voice recognition output interface (stereo I2S-bus output interface).
Audio monitoring for level detection.
Eight audio DACs for 6-channel loudspeaker outputs and stereo headphones output.
Four audio DACs for stereo SCART output and stereo LINE output.
BBE is a registered trademark of BBE Sound Inc. See Section 18.
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Audio video input processor
• Serial data link interfacing for analog multi-purpose interface PNX3000.
8. Television application
Figure 3 shows an overview of the top level hardware architecture of a TV application,
using the PNX3000 and PNX2000 as an analog front-end and the PNX8550 as the main
processor. This system is aimed at the hybrid (analog or digital) TV market.
The main SOC in the system, PNX8550, performs key features for high quality television
like video quality enhancement, motion compensation and picture-in-picture processing.
PNX2000 together with PNX3000 are used to perform the input decoding of a single
stream of analog audio and a single stream of analog video (1fH or 2fH) broadcast signals.
PNX2000 performs the following main functions:
•
•
•
•
•
•
Color decoding into ITU-601 compatible format (1fH or 2fH).
A digital interface to external 3D comb filter.
VBI data capture (Teletext, WSS, CC).
ITU-656 formatting for communication to PNX8550.
Audio demodulation and decoding.
Audio processing and D-A conversion.
The audio data is transferred between PNX2000 and PNX8550 using I2S-bus. PNX2000
and PNX3000 are controlled from PNX8550 via the I2C-bus.
CVBS
TUNERS
UV1316
UV13361
SCART
I2D
VIF
21
L/R
audio
20
19
20
17
18
15
14 16
13
12 14
11
10 12
21
18
19
16
17
15
13
CVBS Y/C
RGB 2
audio I2S-bus
2
PNX2000 audio I S-bus PNX8550
PNX3000
10
6
8
9
(2×)
DEFL.
CONT.
audio I2S-bus
(3×)
CVBS 1
32-bit
DDR
16 Mb
8-bit or 16-bit
FLASH
ROM
18 Mb
7
4
6
2
4
5
DISPLAY
PROCESSOR
RGB
AMPLIFIER
L/R audio 2
11
8
RGB
10 bits (3×)
YUV (656)
SIF
L/R audio 1
3
2
1
status
LEVEL ADJUSTMENT
REMOTE CONTROL
AUDIO
AMPLIFIER
STANDBY
MICROCONTROLLER
mce558
LOCAL KEYPAD
Fig 3. TV application
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Audio video input processor
9. Limiting values
Permanent damage may occur if absolute maximum ratings are exceeded. Prolonged
operation at maximum rating may significantly reduce the reliability of the product.
Table 19: Absolute maximum ratings
Ratings are valid only within operating temperature range unless otherwise specified. All voltages are with respect to VSS
unless otherwise stated.
Symbol
Parameter
Min
Max
Unit
VDD(core)
supply voltage
−0.5
+2.5
V
VDD(I/O)
supply voltage
−0.5
+4.6
V
−0.5
VDD(I/O) + 0.5
V
DC input voltage
VI
( [1] [2]
and
[3])
( [2]
and [3])
VI
DC input voltage 5V tolerant I/O pins
Ilatchup
latch-up current ( [4])
Vesd
electrostatic discharge voltage HBM ( [5] and
Vesd
electrostatic discharge voltage MM
Tstg
storage temperature
[1]
Not to exceed 4.6 V.
[2]
Including voltage on outputs in 3-state mode.
( [6]
[7])
and [7])
−0.5
+6
V
100
-
mA
-
±2
kV
-
±200
V
−40
+125
°C
[3]
Only valid when the VDD(I/O) supply voltage is present.
[4]
Valid for : −(0.5 × VDD) < V < +(1.5 × VDD); Tj < 125 °C.
[5]
Human Body Model, Ileak < 1 mA.
[6]
Machine Model 0.5 mH, Ileak < 1 mA.
[7]
This product includes circuits specifically designed for the protection of its internal devices from the damaging effects of excessive static
charge. However, it is suggested that conventional precautions be taken to avoid applying voltages greater than the rated maximum.
10. Characteristics
10.1 Static characteristics
Table 20: Static characteristics: power supply pins
Tamb = 0 °C to +70 °C to commercial unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1.8V Power Supply Pins: VDDI, VDDM, VDDD(I2D), VDDA(I2D), VDDA(PLL), VDDA(XTAL), VDDD(ADAC), VDDD(DTC)
VDD(core)
supply voltage, 1.8 V supplies
-
1.65
1.8
1.95
V
IDD(core)
supply current, 1.8 V supplies
VDD(core) = 1.8 V
-
250
-
mA
3.3V Power Supply Pins: VDDE, VDD3(DTC), VDDA(ADAC)
VDD(3V3)
supply voltage, 3.3 V supplies
-
3.0
3.3
3.6
V
IDD(3V3)
supply current, 3.3 V supplies
VDD(core) = 3.3 V
-
50
-
mA
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Audio video input processor
Table 21: Static characteristics: digital pins
Tamb = 0 °C to +70 °C to commercial unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Vi = 0
-
-
1
µA
I2S inputs: I2S_IN_SD1-6, I2C Address: I2C_ADR
IIL
LOW-level input current
VI
input voltage
-
0
-
5.5
V
VIH
HIGH-level input voltage
-
2.0
-
-
V
VIL
LOW-level input voltage
-
-
-
0.8
V
IPD
pull-down current
Vi = VDD(I/O)
20
50
75
µA
External Sync: VSYNC1, VSYNC2, Reset: RESET_SEL, ITU-656: LL_CLK
IIL
LOW-level input current
Vi = 0
-
-
1
µA
IIH
HIGH-level input current
Vi = VDD(I/O)
-
-
1
µA
VI
input voltage
-
0
-
5.5
V
VIH
HIGH-level input voltage
-
2.0
-
-
V
VIL
LOW-level input voltage
-
-
-
0.8
V
Vi = VDD(I/O)
-
-
1
µA
Jtag inputs: TDI, TCK, TRST_N, TMS
IIH
HIGH-level input current
VI
input voltage
-
0
-
5.5
V
VIH
HIGH-level input voltage
-
2.0
-
-
V
VIL
LOW-level input voltage
-
-
-
0.8
V
Vhys
hysteresis voltage
-
-
0.3
-
V
IPU
pull-up current
Vi = 0
−25
−50
−65
µA
VDD(I/O) < Vi < 5 V
0
0
0
µA
-
5
-
pF
I2C Pins: I2C_SDA, I2C_SCL
CI
input capacitance
-
ILI
input leakage current [1]
VDD(3V3) = 3.3 V; Tamb = 25 °C
1.37
1.85
2.45
µA
IIN(MAX)
max. input current [2]
at 5 V
8.20
10.7
12.45
µA
VI
input voltage
-
0
-
5
V
VIL
LOW-level input voltage
-
-
-
0.8
V
VIH
HIGH-level input voltage
-
2.0
-
-
V
VOL
LOW-level output voltage
-
-
-
0.4
V
IOL
LOW-level output current
VOL=0.4V
-
8.45
-
mA
ITU-656 Outputs: DVO_DATA_0-9, DVO_VALID, DVO_CLK
Ioz
3-state output leakage
VO = 0
VO = VDD(I/O)
-
-
1
µA
VI
input voltage
-
0
-
5.5
V
VOH
HIGH-level output voltage
IOH = −4 mA
2.4
-
-
V
VOL
LOW-level output voltage
IOL = 4 mA
-
-
0.4
V
IOH
HIGH-level output current
VOH = 2.4
−4
-
-
mA
IOL
LOW-level output current
VOL = 0.4 V
4
-
-
mA
IOH
HIGH-level short circuit current
VOH = 0
-
-
−45
mA
IOL
LOW-level short circuit current
VOL = VDD(I/O)
-
-
50
mA
I2S I/O: I2S_SCK_SYS, I2S_WS_SYS
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Audio video input processor
Table 21: Static characteristics: digital pins…continued
Tamb = 0 °C to +70 °C to commercial unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
IIL
LOW-level input current
Vi = 0
-
-
1
µA
IIH
HIGH-level input current
Vi = VDD(I/O)
-
-
1
µA
VI
input voltage
-
0
-
VDD(I/O)
V
VIH
HIGH-level input voltage
-
2.0
-
-
V
VIL
LOW-level input voltage
-
-
-
0.8
V
Vhys
hysteresis voltage
-
-
0.4
-
V
Ioz
3-state output leakage
VO = 0
VO = VDD(I/O)
-
-
1
µA
VOH
HIGH-level output voltage
IOH = −8 mA
2.4
-
-
V
VOL
LOW-level output voltage
IOL = 8 mA
-
-
0.4
V
IOH
HIGH-level output current
VOH = 2.4
−8
-
-
mA
IOL
LOW-level output current
VOL = 0.4 V
8
-
-
mA
IOH
HIGH-level short circuit current
VOH = 0
-
-
−95
mA
IOL
LOW-level short circuit current
VOL = VDD(I/O)
-
-
95
mA
-
V
I2S Outputs: I2S_OUT_SD1-6, JTAG Output: TDO, PNX3000 Clock: MPIFCLK, Sync Output: HVINFO
VOH
HIGH-level output voltage
IOH = −4 mA
2.4
-
VOL
LOW-level output voltage
IOL = 4 mA
-
-
0.4
V
IOH
HIGH-level output current
VOH = 2.4
−4
-
-
mA
IOL
LOW-level output current
VOL = 0.4V
4
-
-
mA
IOH
HIGH-level short circuit current
VOH = 0
-
-
−45
mA
IOL
LOW-level short circuit current
VOL = VDD(I/O)
-
-
50
mA
I2S Output: I2S_OUT_SD3_SCK, I2S_OUT_SD3_WS, ADAC_CLK, Clock Output: DCLK
VOH
HIGH-level output voltage
IOH = −8 mA
2.4
-
-
V
VOL
LOW-level output voltage
IOL = 8 mA
-
-
0.4
V
IOH
HIGH-level output current
VOH = 2.4
−8
-
-
mA
IOL
LOW-level output current
VOL = 0.4 V
8
-
-
mA
IOH
HIGH-level short circuit current
VOH = 0
-
-
−95
mA
IOL
LOW-level short circuit current
VOL = VDD(I/O)
-
-
95
mA
Interrupt: INTOUT
Ioz
3-state output leakage
VO = 0
VO = VDD(I/O)
-
-
1
µA
VI
input voltage
-
0
-
5.5
V
VOL
LOW-level output voltage
IOL = 8 mA
-
-
0.4
V
IOL
LOW-level output current
VOL = 0.4 V
8
-
-
mA
IOL
LOW-level short circuit current
VOL = VDD(I/O)
-
-
140
mA
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Philips Semiconductors
Audio video input processor
Table 22: Static characteristics: analog pins
Tamb = 0 °C to +70 °C to commercial unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
External Sync: HSYNCFBL1, HSYNCFBL2
VIT
input threshold
dtc_lowth = 0
-
1.65
-
V
VIT
input threshold
dtc_lowth = 1
-
0.65
-
V
Reset: RESET_N
Vtrip_high
high trip level
RESET_SEL = 0
1.0
1.2
1.4
V
Vtrip_low
low trip level
RESET_SEL = 0
0.95
1.1
1.3
V
I2D
Inputs: DLINK1-3DP, DLINK1-3DN,DLINK1-3SP, DLINK1-3SN
Vsens
input sensitivity
-
-
6
-
mV
Zdiff
differential line load impedance
across input diff pair
-
100
-
Ω
VDATA(pos)
data pos. range
-
0
-
300
mV
VDATA(neg)
data neg. range
-
0
-
300
mV
VSTROBE(pos)
strobe pos. range
-
0
-
300
mV
VSTROBE(neg)
strobe neg. range
-
0
-
300
mV
Audio DACs: ADAC1-12P, ADAC1-12N
VREFP
positive reference voltage
-
3.0
3.3
3.6
V
VREFN
negative reference voltage
-
-
0
-
V
IREFP
positive reference current
-
-
820
-
µA
Audio DACs: ADAC1-12
VOUT(rms)
output voltage (rms); single-ended, digital
i/p level = 0 dBFS
-
-
1.17
-
V
ROUT
output resistance
-
0.7
1.0
1.3
kΩ
RL
load resistance
-
10
-
-
kΩ
10.2 Dynamic characteristics
Table 23:
Dynamic characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fclk
clock frequency
-
-
400
-
kHz
tr
rise time
1.5 kΩ ext. pull-up; 160 pF load
-
550
-
ns
tf
fall time
1.5 kΩ ext. pull-up; 160 pF load
130
162
245
ns
I2C
Viddec: HVINFO (slew rate limited)
tthl
output transition time (H to L)
30 pF load
-
10
13.8
ns
ttlh
output transition time (L to H)
30 pF load
-
10
13.8
ns
data setup at Rx
40 pF load
-
-
7.3
ns
ITU-656
tsu(DATA)
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Audio video input processor
Table 23:
Dynamic characteristics…continued
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
th(DATA)
data hold at Rx
40 pF load
-
-
4.9
ns
fs
audio sample frequency
-
32
48
48
kHz
fSCK
SCK frequency
I2S-bus master mode
-
64fs
-
-
fSCK
SCK frequency
I2S-bus slave mode
32fs
64fs
256fs
-
DFSCK
SCK duty factor
I2S-bus master mode
40
50
60
%
DFSCK
SCK duty factor
I2S-bus slave mode
35
-
65
%
tRSCK
SCK rise / fall time
I2S-bus master mode; Cload = 30 pF
-
-
5
ns
tRSCK
SCK rise / fall time
I2S-bus slave mode; fSCK = 3.072 MHz -
-
50
ns
td
delay time: SCK to WS and SD
outputs [2]
TSCK = 1/fSCK
0.3
0.5
0.7
TSCK
th
hold time: SCK to WS and SD inputs -
0
-
-
ns
ts
setup time: WS and SD inputs to
SCK
TSCK = 1/fSCK
0.2
-
-
TSCK
fclock(WORD) word clock frequency
-
-
13.5
-
MHz
WL
word length
-
-
44
-
bit
DR
data rate
-
-
594
-
Mbit/s
fclock(BIT)
bit clock freq.
-
-
297
-
MHz
I2S
I2D
JTAG Clock Reset
tlow
Time RESET_N should be below
Vtrip_high before internal reset = 1.
RESET_SEL = 0
-
-
11
µs
thigh
Time RESET_N should be above
Vtrip_high before internal reset = 0
(after tpulse).
RESET_SEL = 0
-
-
2
µs
tpulse
Time before PNX2000 internal reset
= 0 [3].
RESET_SEL = 0
200
-
-
ns
[1]
Allowed SCK/WS ratios are 32, 48, 64, 128 and 256 SCK periods per WS period.
[2]
All timings relative to the rising edge of SCK.
[3]
See Section 10.4 for waveforms.
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Audio video input processor
10.3 Audio DAC characteristics
Table 24: Dynamic characteristics: Audio DAC
Tamb = 0 °C to +70 °C for commercial unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Audio DAC Outputs: ADAC1-12
fs
audio sample frequency
-
32
48 [1]
48
kHz
S/N
Signal to Noise Ratio, CCIR-2 k
weighted
outputs muted; reference f = 2 kHz,
0 dBFS
-
94
-
dB
f =1 kHz; 0 dBFS; 22 kHz
measurement bandwidth
-
−77
-
dB
(THD+N)/S Total Harmonic Distortion + Noise to
Signal ratio
fres
frequency response
+/-1 dB
<10
-
22.5
kHz
αct
crosstalk between adjacent DACs
f = 1 kHz; 0 dBFS
-
−90
-
dB
[1]
Allowed audio sample frequencies are 32 kHz, 44.1 kHz and 48 kHz. Default fS in I2S-bus master mode is 48 kHz.
The audio DACs are based on a switched-resistor architecture which acts as a controlled
voltage divider between the positive and negative references ADACn_P and ADACn_N.
Therefore all noise on the reference pins will spread directly to the associated output pin
ADACn. Consequently it is important to provide adequate filtering of the reference voltage
to allow optimum signal-to-noise performance. Also, the voltage difference between
ADACn_P and SDAC_3V3 should be kept to a minimum as any difference will degrade
distortion performance.
The DACs have an internal resolution of 4 bits, running at a clock frequency of 128 fS,
using a noise shaper circuit to shift the quantization noise to out-of-band frequencies. To
prevent HF overloading of the circuit that is driven by the DAC outputs, a 3.3 nF capacitor
should be used to filter off the HF signal content. Together with the DAC’s nominal output
impedance of 1 kΩ, a first order roll-off at approximately 50 kHz will result. One capacitor
is required for each DAC output, connected between ADACn and the corresponding
ADACn_N.
10.4 Timing
10.4.1 Clock
Crystal specification
The crystal oscillator can be used with an external crystal, or in bypass mode with external
clock signal, see Figure 4.
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Audio video input processor
VDDA
VSSA
pd
VDDA
xtm
XO
VSSA
pd
xtm
XO
clkout
clkout
on-chip
osc_in
osc_out
osc_in
osc_out
n.c.
off-chip
clock
(a)
(b)
Cx1
Cx2
mce560
Fig 4. Application diagram: (a) slave/test mode, (b) oscillation mode
The supported crystal/external clock frequencies are 27 MHz and 13.5 MHz. The crystal
oscillator is followed by a selectable divide-by-two frequency divider giving three available
clock frequencies, as shown in Table 25.
Table 25:
Primary clock settings
Clock/Crystal Input
Divider setting
Clock frequency
27 MHz
x/1
27 MHz
27 MHz
x/2
13.5 MHz
13.5 MHz
x/1
13.5 MHz
13.5 MHz
x/2
6.75 MHz
The crystal specification is:
•
•
•
•
•
Package: surface mount.
Accuracy: (±50 ppm).
Temperature: (±50 ppm).
Operating temperature range: −20 to +70 oC.
Load capacitance: 30 pF.
Table 26:
Crystal parameters
Oscillator
Crystal load
Max.crystal series
External load
frequency (fc)
capacitance (CL)
resistance (RS)
capacitors (Cx1; Cx2)
10 pF
< 600 Ω
2 x 18 pF
20 pF
< 255 Ω
2 x 38 pF
30 pF
< 140 Ω
2 x 58 pF
10 pF
< 130 Ω
2 x 18 pF
20 pF
< 50 Ω
38 pF; 18 pF
30 pF
n.a.
n.a.
13.5 MHz
27 MHz
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Audio video input processor
10.4.2 Reset
long external reset
produces internal reset
short spike
ignored
RESET_N
tpulse
tlow
internal
reset
thigh
mce561
RESET_N pin and internal reset timing
Fig 5. PNX2000 reset
10.4.3 ITU-656
DVO_CLK
DVO_DATA[9:0]
DVO_VALID
tsu(DATA)
th(DATA)
mce562
Fig 6. Timing ITU interface
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Audio video input processor
11. Glossary
AGC................. Automatic Gain Control
SSOP...............Shrink Small Outline Package
ASD ................. Auto Standard Detection
SOC .................System On Chip
AVL.................. Auto Volume Level
VBI...................Vertical Blanking Interval
BCU................. Bus Control Unit
VIDDEC ...........Video front-end Decoder
BTSC............... Broadcast TV System Committee
VITC.................Vertical Interval Time Code
DBE ................. Dynamic Base Enhancement
VPS..................Video Program System
DCU................. Data Capture Unit
WSS.................Wide Screen Signaling
DDEP .............. Demodulator and Decoder Easy
Programming
WST.................World System Teletext
DEMDEC ......... Demodulator Decoder
DQPSK............ Differential Quadrature Phase Shift Keying
DSP ................. Digital Signal Processor
DUB................. Dynamic UltraBass
DVD ................. Digital Video Disc
EIAJ ................ Electronic Industries Association of Japan
GTU ................. Global Task Unit
HBM ................ Human Body Model
LQFP ............... Low profile Quad Flat Package
MM .................. Machine Model
MPX................. Multiplexer
NICAM............. Near Instantaneous Compounded Audio
Multiplex
NTSC............... National TV Systems Committee
PAL.................. Phase Alternate Line
SAP ................. Secondary Audio Program
SCART ............ Syndicate for Constructors of Apparatus for
Radio and Television
SECAM ........... Sequential Color and Memory
SMD ................ Surface Mount Device
SRC ................. Sample Rate Conversion
SSS ................. Static Standard Selection
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Audio video input processor
12. Package outline
LQFP144: plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm
SOT486-1
c
y
X
A
73
72
108
109
ZE
e
E HE
A A2
(A 3)
A1
θ
wM
Lp
bp
L
pin 1 index
detail X
37
144
1
36
v M A
ZD
wM
bp
e
D
B
HD
v M B
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
mm
1.6
0.15
0.05
1.45
1.35
0.25
0.27
0.17
0.20
0.09
20.1
19.9
20.1
19.9
0.5
HD
HE
22.15 22.15
21.85 21.85
L
Lp
v
w
y
1
0.75
0.45
0.2
0.08
0.08
Z D(1) Z E(1)
1.4
1.1
1.4
1.1
θ
o
7
o
0
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT486-1
136E23
MS-026
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
00-03-14
03-02-20
Fig 7. LQFP package outline
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13. Soldering
13.1 Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account of
soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages
(document order number 9398 652 90011).
There is no soldering method that is ideal for all IC packages. Wave soldering can still be
used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these
situations reflow soldering is recommended. In these situations reflow soldering is
recommended.
13.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and
binding agent) to be applied to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement. Driven by legislation and
environmental forces the worldwide use of lead-free solder pastes is increasing.
Several methods exist for reflowing; for example, convection or convection/infrared
heating in a conveyor type oven. Throughput times (preheating, soldering and cooling)
vary between 100 and 200 seconds depending on heating method.
Typical reflow peak temperatures range from 215 to 270 °C depending on solder paste
material. The top-surface temperature of the packages should preferably be kept:
• below 220 °C (SnPb process) or below 245 °C (Pb-free process)
— for all BGA and SSOP-T packages
— for packages with a thickness ≥ 2.5 mm
— for packages with a thickness < 2.5 mm and a volume ≥ 350 mm3 so called
thick/large packages.
• below 235 °C (SnPb process) or below 260 °C (Pb-free process) for packages with a
thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages.
Moisture sensitivity precautions, as indicated on packing, must be respected at all times.
13.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices
(SMDs) or printed-circuit boards with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering method was specifically
developed.
If wave soldering is used the following conditions must be observed for optimal results:
• Use a double-wave soldering method comprising a turbulent wave with high upward
pressure followed by a smooth laminar wave.
• For packages with leads on two sides and a pitch (e):
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Audio video input processor
— larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be
parallel to the transport direction of the printed-circuit board;
— smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the
transport direction of the printed-circuit board.
The footprint must incorporate solder thieves at the downstream end.
• For packages with leads on four sides, the footprint must be placed at a 45° angle to
the transport direction of the printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
During placement and before soldering, the package must be fixed with a droplet of
adhesive. The adhesive can be applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the adhesive is cured.
Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 °C or
265 °C, depending on solder material applied, SnPb or Pb-free respectively.
A mildly-activated flux will eliminate the need for removal of corrosive residues in most
applications.
13.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage
(24 V or less) soldering iron applied to the flat part of the lead. Contact time must be
limited to 10 seconds at up to 300 °C.
When using a dedicated tool, all other leads can be soldered in one operation within
2 to 5 seconds between 270 and 320 °C.
13.5 Package related soldering information
Table 27:
Suitability of surface mount IC packages for wave and reflow soldering methods
Package [1]
Soldering method
Reflow [2]
Wave
BGA, LBGA, LFBGA, SQFP, SSOP-T [3], TFBGA, not suitable
VFBGA
suitable
DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, not suitable [4]
HTQFP, HTSSOP, HVQFN, HVSON, SMS
suitable
PLCC [5], SO, SOJ
suitable
suitable
LQFP, QFP, TQFP
not recommended [5] [6]
suitable
SSOP, TSSOP, VSO, VSSOP
not
PMFP [8]
not suitable
suitable
not suitable
[1]
For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026);
order a copy from your Philips Semiconductors sales office.
[2]
All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the
maximum temperature (with respect to time) and body size of the package, there is a risk that internal or
external package cracks may occur due to vaporization of the moisture in them (the so called popcorn
effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit
Packages; Section: Packing Methods.
9397 750 13928
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recommended [7]
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Audio video input processor
[3]
These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no
account be processed through more than one soldering cycle or subjected to infrared reflow soldering with
peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow oven. The package
body peak temperature must be kept as low as possible.
[4]
These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the
solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink
on the top side, the solder might be deposited on the heatsink surface.
[5]
If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave
direction. The package footprint must incorporate solder thieves downstream and at the side corners.
[6]
Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
[7]
Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
[8]
Hot bar or manual soldering is suitable for PMFP packages.
14. Revision history
Table 28:
Revision history
Rev Date
CPCN
Description
03
20040823
Minor revision (9397 750 13928)
02
20040712
Upgraded to Product data (9397 750 13591). Table 3 and Table 4 added.
01
20040504
Preliminary data (9397 750 12066)
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Audio video input processor
15. Data sheet status
Level
Data sheet
status [1]
Product
status [2] [3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips Semiconductors
reserves the right to change the specification in any manner without notice.
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published at a later
date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the
design and supply the best possible product.
III
Product data
This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make
changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be
communicated via a Customer Product/Process Change Notification (CPCN).
Production
[1]
Consult the most recently issued data sheet before initiating or completing a design.
[2]
The product status of the device(s) described in this data sheet may have changed
since this data sheet was published. The latest information is available on the
Internet at URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status
determines the data sheet status
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
18. Licenses
16. Definitions
Purchase of Philips I2C components
Purchase of Philips I2C components conveys a license
under the Philips’ I2C patent to use the components in the
I2C system provided the system conforms to the I2C
specification defined by Philips. This specification can be
ordered using the code 9398 393 40011.
Short-form specification – The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition – Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information – Applications that are described herein for any of
these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
Dolby Laboratories
‘Dolby’ and ‘Pro Logic’ are trademarks of Dolby Laboratories, San
Francisco, USA. Products are available to licensees of Dolby Laboratories
Licensing Corp., 100 Potrero Avenue, San Francisco, CA, 94103, USA. Tel:
1-415-558-0200, Fax: 1-415-863-1373.
Supply of this implementation of Dolby Technology does not convey a
license, nor imply a right under any patent to use this implementation in any
final product. A license for such use is required from Dolby Laboratories.
BBE Sound
17. Disclaimers
BBE is a registered trademark of BBE Sound Inc., 5381 Production Drive,
Huntington Beach, CA, 92649, USA. The use of BBE needs licensing from
BBE Sound Inc. Tel: 1-714-897-6766, Fax: 1-714-895-6728.
Life support – These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
dbx - TV noise reduction
Right to make changes – Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
A Set-Maker License is required for use of this product under one (or more)
of the following patents: US4,539,526; 5,796,842; 6,118,879 and U.S.
Patent Application 09/638245 . For further information contact THAT
Corporation, 45 Sumner Street, Milford, Massachusetts 01757-1656, USA.
Tel: 1-508-478-9200, FAX: 1-508-478-0990
19. Trademarks
Nexperia – is a trademark of Koninklijke Philips Electronics N.V.
Dolby Pro Logic,Virtual Dolby Digital and Virtual Dolby Surround – are
trademarks of Dolby Laboratories |nc.
BBE – is a registered trademark of BBE Sound Inc.
dbx – is a registered trademark of Carillon Electronics Corp.
20. Contact information
For additional information, please visit http://www.semiconductors.philips.com
For sales office addresses, send an email to: [email protected]
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Audio video input processor
21. Contents
1
2
3
4
5
6
6.1
6.1.1
7
7.1
7.2
7.3
7.3.1
7.3.2
8
9
10
10.1
10.2
10.3
10.4
10.4.1
10.4.2
10.4.3
11
12
13
13.1
13.2
13.3
13.4
13.5
14
15
16
17
18
19
20
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . 12
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Features in detail . . . . . . . . . . . . . . . . . . . . . . 13
Video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Audio. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Television application . . . . . . . . . . . . . . . . . . . 16
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 17
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 17
Static characteristics. . . . . . . . . . . . . . . . . . . . 17
Dynamic characteristics . . . . . . . . . . . . . . . . . 20
Audio DAC characteristics . . . . . . . . . . . . . . . 22
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
ITU-656. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 26
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Introduction to soldering surface mount
packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 27
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 27
Manual soldering . . . . . . . . . . . . . . . . . . . . . . 28
Package related soldering information . . . . . . 28
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 29
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 30
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Contact information . . . . . . . . . . . . . . . . . . . . 30
© Koninklijke Philips Electronics N.V. 2004
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner. The information presented in this document does
not form part of any quotation or contract, is believed to be accurate and reliable and may
be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under
patent- or other industrial or intellectual property rights.
Date of release: 23 August 2004
Document order number: 9397 750 13928
Published in Netherlands