ATMEL AT49BV640S

Features
• Single Voltage Operation Read/Write: 2.65V - 3.6V
• Access Time – 70 ns
• Sector Erase Architecture
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•
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•
•
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– One Hundred Twenty-seven 32K Word (64K Bytes) Main Sectors with
Individual Write Lockout
– Eight 4K Word (8K Bytes) Sectors with Individual Write Lockout
Fast Word Program Time – 10 µs
Typical Sector Erase Time: 32K Word Sectors – 700 ms; 4K Word Sectors – 100 ms
Suspend/Resume Feature for Erase and Program
– Supports Reading and Programming Data from Any Sector by Suspending
Erase of a Different Sector
– Supports Reading Any Word by Suspending Programming of Any Other Word
Low-power Operation
– 10 mA Active
– 15 µA Standby
VPP Pin for Write Protection and Accelerated Program Operation
RESET Input for Device Initialization
Softlock Sector Protection
Secure Lock and Freeze Feature
Top or Bottom Boot Block Configuration Available
128-bit Protection Register
Minimum 100,000 Erase Cycles
Common Flash Interface (CFI)
CBGA Green (Pb/Halide-free/RoHS Compliant) Packaging
64-megabit
(4M x 16)
Secure
3-volt Only
Memory
AT49BV640S
AT49BV640ST
1. Description
The AT49BV640S(T) is a 2.7-volt 32-megabit Flash memory organized as 4,194,304
words of 16 bits each. The memory is divided into 135 sectors for erase operations.
The device is offered in a 64-ball CBGA package. The device has CE and OE control
signals to avoid any bus contention. This device can be read or reprogrammed using
a single power supply, making it ideally suited for in-system programming.
The device powers on in the read mode. Command sequences are used to place
the device in other operation modes such as program and erase. The device has
the capability to protect the data in any sector (see “Softlock Sector Protection” on
page 6).
To increase the flexibility of the device, it contains an Erase Suspend and Program
Suspend feature. This feature will put the erase or program on hold for any amount of
time and let the user read data from or program data to any of the remaining sectors
within the memory.
The VPP pin provides data protection. When the VPP input is below 0.4V, the program
and erase functions are inhibited. When VPP is at 1.65V or above, normal program
and erase operations can be performed. With VPP at 10.0V, the program (Dual-word
Program command) operation is accelerated.
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ATMEL CONFIDENTIAL:
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2. Pin Configurations
2.1
Pin Name
Pin Function
A0 - A21
Addresses
CE
Chip Enable
OE
Output Enable
WE
Write Enable
RESET
Reset
VPP
Write Protection and Power Supply for Accelerated Program Operations
I/O0 - I/O15
Data Inputs/Outputs
NC
No Connect
VCCQ
Output Power Supply
64-ball CBGA Top View
1
2
3
4
5
6
7
8
A0
A5
A7
VPP
A12
VCC
A17
A21
A1
VSS
A8
CE
A13
NC
A18
NC
A2
A6
A9
A11
A14
NC
A19
A20
A3
A4
A10 RESET NC
NC
A15
A16
I/O8
I/O1
I/O9
I/O4
NC
I/O15
NC
NC
I/O0 I/010 I/O11 I/O12
NC
NC
OE
NC
NC
I/O2 VCCQ I/O5
I/O6 I/O14 WE
NC
NC
VCC VSS I/O13 VSS
A
B
C
D
E
I/O3
F
G
H
2
I/O7
NC
AT49BV640S(T)
3583AX–FLASH–12/8/05
AT49BV640S(T)
3. Block Diagram
I/O0 - I/O15
INPUT
BUFFER
INPUT
BUFFER
IDENTIFIER
REGISTER
STATUS
REGISTER
DATA
REGISTER
A0 - A21
OUTPUT
MULTIPLEXER
OUTPUT
BUFFER
CE
WE
OE
RESET
COMMAND
REGISTER
ADDRESS
LATCH
DATA
COMPARATOR
Y-DECODER
Y-GATING
WRITE STATE
MACHINE
PROGRAM/ERASE
VOLTAGE SWITCH
VPP
VCC
GND
X-DECODER
MAIN
MEMORY
4. Device Operation
4.1
Command Sequences
When the device is first powered on, it will be in the read mode. Command sequences are used
to place the device in other operating modes such as program and erase. The command
sequences are written by applying a low pulse on the WE input with CE low and OE high or by
applying a low-going pulse on the CE input with WE low and OE high. The address is latched on
the first rising edge of the WE or CE. Valid data is latched on the rising edge of the WE or the CE
pulse, whichever occurs first. The addresses used in the command sequences are not affected
by entering the command sequences.
4.2
Read
The AT49BV640S(T) is accessed like an EPROM. When CE and OE are low and WE is high,
the data stored at the memory location determined by the address pins are asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dual-line
control gives designers flexibility in preventing bus contention.
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4.3
Reset
A RESET input pin is provided to ease some system applications. When RESET is at a logic
high level, the device is in its standard operating mode. A low level on the RESET pin halts the
present device operation and puts the outputs of the device in a high-impedance state. When a
high level is reasserted on the RESET pin, the device returns to read mode.
4.4
Erase
Before a word can be reprogrammed it must be erased. The erased state of the memory bits is a
logical “1”. The individual sectors can be erased by using the Sector Erase command.
4.4.1
Sector Erase
The device is organized into 135 sectors (SA0 - SA134) that can be individually erased. The
Sector Erase command is a two-bus cycle operation. The sector address and the D0H Data
Input command are latched on the rising edge of WE. The sector erase starts after the rising
edge of WE of the second cycle provided the given sector has not been protected. The erase
operation is internally controlled; it will automatically time to completion. The maximum time to
erase a sector is tSEC. An attempt to erase a sector that has been protected will result in the
operation terminating immediately.
4.5
Word Programming
Once a memory sector is erased, it is programmed (to a logical “0”) on a word-by-word basis.
Programming is accomplished via the Internal Device command register and is a two-bus cycle
operation. The device will automatically generate the required internal program pulses.
Any commands except Read Status Register, Program Suspend and Program Resume written
to the chip during the embedded programming cycle will be ignored. If a hardware reset happens during programming, the data at the location being programmed will be corrupted. Please
note that a data “0” cannot be programmed back to a “1”; only erase operations can convert “0”s
to “1”s. Programming is completed after the specified tBP cycle time. If the program status bit is a
“1”, the device was not able to verify that the program operation was performed successfully.
The status register indicates the programming status. While the program sequence executes,
status bit I/O7 is “0”.
4.6
VPP Pin
The circuitry of the AT49BV640S(T) is designed so that the device cannot be programmed or
erased if the VPP voltage is less that 0.4V. When VPP is at 1.65V or above, normal program and
erase operations can be performed. The VPP pin cannot be left floating.
4
AT49BV640S(T)
3583AX–FLASH–12/8/05
AT49BV640S(T)
4.7
Read Status Register
The status register indicates the status of device operations and the success/failure of that operation. The Read Status Register command causes subsequent reads to output data from the
status register until another command is issued. To return to reading from the memory, issue a
Read command.
The status register bits are output on I/O7 - I/O0. The upper byte, I/O15 - I/O8, outputs 00H
when a Read Status Register command is issued.
The contents of the status register [SR7:SR0] are latched on the falling edge of OE or CE
(whichever occurs last), which prevents possible bus errors that might occur if status register
contents change while being read. CE or OE must be toggled with each subsequent status read,
or the status register will not indicate completion of a Program or Erase operation.
When the Write State Machine (WSM) is active, SR7 will indicate the status of the WSM; the
remaining bits in the status register indicate whether the WSM was successful in performing the
preferred operation (see Table 4-1).
Table 4-1.
Status Register Bit Definition
WSMS
ESS
ES
PRS
VPPS
PSS
SLS
R
7
6
5
4
3
2
1
0
Notes
SR7 WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
Check Write State Machine bit first to determine Word Program
or Sector Erase completion, before checking program or erase
status bits.
SR6 = ERASE SUSPEND STATUS (ESS)
1 = Erase Suspended
0 = Erase In Progress/Completed
When Erase Suspend is issued, WSM halts execution and sets
both WSMS and ESS bits to “1” – ESS bit remains set to “1” until
an Erase Resume command is issued.
SR5 = ERASE STATUS (ES)
1 = Error in Sector Erase
0 = Successful Sector Erase
When this bit is set to “1”, WSM has applied the max number of
erase pulses to the sector and is still unable to verify successful
sector erasure.
SR4 = PROGRAM STATUS (PRS)
1 = Error in Programming
0 = Successful Programming
When this bit is set to “1”, WSM has attempted but failed to
program a word
SR3 = VPP STATUS (VPPS)
1 = VPP Low Detect, Operation Abort
0 = VPP OK
The VPP status bit does not provide continuous indication of VPP
level. The WSM interrogates VPP level only after the Program or
Erase command sequences have been entered and informs the
system if VPP has not been switched on. The VPP is also checked
before the operation is verified by the WSM.
SR2 = PROGRAM SUSPEND STATUS (PSS)
1 = Program Suspended
0 = Program in Progress/Completed
When Program Suspend is issued, WSM halts execution and
sets both WSMS and PSS bits to “1”. PSS bit remains set to “1”
until a Program Resume command is issued.
SR1 = SECTOR LOCK STATUS (SLS)
1 = Prog/Erase attempted on a locked sector; Operation aborted.
0 = No operation to locked sectors
If a Program or Erase operation is attempted to one of the locked
sectors, this bit is set by the WSM. The operation specified is
aborted and the device is returned to read status mode.
SR0 = Reserved for Future Enhancements (R)
This bit is reserved for future use and should be masked out
when polling the status register.
Note:
1. A Command Sequence Error is indicated when SR1, SR3, SR4 and SR5 are set.
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4.8
Clear Status Register
The WSM can set status register bits 1 through 7 and can clear bits 2, 6 and 7; but, the WSM
cannot clear status register bits 1, 3, 4 or 5. Because bits 1, 3, 4 and 5 indicate various error conditions, these bits can be cleared only through the Clear Status Register command. By allowing
the system software to control the resetting of these bits, several operations may be performed
(such as cumulatively programming several addresses or erasing multiple sectors in sequence)
before reading the status register to determine if an error occurred during those operations. The
status register should be cleared before beginning another operation. The Read command must
be issued before data can be read from the memory array. The status register can also be
cleared by resetting the device.
4.9
Softlock Sector Protection
The AT49BV640S(T) offers the Softlock Sector Protection mode. Once this mode is enabled,
the contents of the selected sector is read-only and cannot be erased or programmed. At powerup and reset, all sectors have their Softlock protection mode enabled.
4.9.1
Unlock
The Softlock protection mode can be disabled by issuing a two-bus cycle Unlock command to
the selected sector. Once a sector is unlocked, its contents can be erased or programmed. To
enable the Softlock protection mode, a two-bus cycle Softlock command must be issued to the
selected sector.
4.9.2
Sector Protection Detection
A software method is available to determine if the Softlock Sector Protection feature is enabled.
When the device is in the software product identification mode a read from I/O0 at address location 00002H within a sector will show if the sector is unlocked or softlocked.
Table 4-2.
I/O0
6
Softlock Sector Protection Status
Sector Protection Status
0
Sector Not Locked
1
Softlock Enabled
AT49BV640S(T)
3583AX–FLASH–12/8/05
AT49BV640S(T)
4.10
Secure Lock
In some applications, in addition to the standard softlock sector protection mechanism, a
requirement exists to allow for the permanent and irreversible locking of selected regions in the
memory. The AT49BV640S(T) allows the user to permanently lock thirty-eight regions, and once
activated these secure regions cannot be altered or erased through Software or Hardware at
any time. Once activated, no facility exists to over-ride the secure lock mechanism. The size and
the location of the secure regions is determined by the Top or Bottom Boot Block designation.
The location of the secure regions is shown on pages 17 - 20.
The secure regions can be locked in any sequence and at any time during normal device operation. Read operations can still be performed on any region that has the secure lock feature
enabled. Full read/write operations and standard sector operations including standard Sector
locking can be performed on all regions that are not secure locked.
To secure lock a region, a two-bus cycle command must be used as shown in the “Command
Definition Table”. The data programmed during the second bus cycle in bits D15 - D0 determines whether a corresponding region is secure locked or not. If data bit DX is “0”, the
corresponding region, SCRX, shown below will be secure locked. If data bit DX is “1”, the corresponding region shown below will not be secure locked.
Table 4-3.
Secure Lock Table
DIN1, data programmed
during 2nd bus cycle of
Lock SCR7 - SCR0
Command
DIN2, data programmed
during 2nd bus cycle of
Lock SCR23 - SCR8
Command
DIN3, data programmed
during 3rd bus cycle of
Lock SCR37 - SCR24
Command
Note:
D15
D14
D13
D12
D11
X
X
X
X
X
D10
D9
D8
D7
D6
D5
D4
D3
D2
D0
Protection
Freeze
SCR7 SCR6 SCR5 SCR4 SCR3 SCR2 SCR1 SCR0 Register –
Bit
Block B(1)
SCR23 SCR22 SCR21 SCR20 SCR19 SCR18 SCR17 SCR16 SCR15 SCR14 SCR13 SCR12 SCR11 SCR10
X
D1
SCR37 SCR36 SCR35 SCR34 SCR33 SCR32 SCR31 SCR30 SCR29 SCR28 SCR27 SCR26 SCR25
X
SCR9
SCR8
SCR24
X
1. Protection Register – Block B refers to the user-programmable region of the 128-bit protection register. For details, see
section “128-bit Protection Register” on page 8.
To determine whether a secure region is locked or not, the status of SCR command is given,
and data bits D15 - D0 are read. If the data bit is “0”, the corresponding region is secure locked,
if the data bit is “1”, the corresponding region can be programmed.
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4.11
Erase Suspend/Erase Resume
The Erase Suspend command allows the system to interrupt a sector erase operation and then
program or read data from a different sector within the memory. After the Erase Suspend command is given, the device requires a maximum time of 15 µs to suspend the erase operation.
After the erase operation has been suspended, the system can then read data or program data
to any other sector within the device. An address is not required during the Erase Suspend command. During a sector erase suspend, another sector cannot be erased. To resume the sector
erase operation, the system must write the Erase Resume command. The Erase Resume
command is a one-bus cycle command. The only valid commands while erase is suspended are
Read Status Register, Product ID Entry, CFI Query, Program, Program Resume, Erase
Resume, Sector Softlock and Sector Unlock.
4.12
Program Suspend/Program Resume
The Program Suspend command allows the system to interrupt a programming operation and
then read data from a different word within the memory. After the Program Suspend command is
given, the device requires a maximum of 10 µs to suspend the programming operation. After the
programming operation has been suspended, the system can then read from any other word
within the device. An address is not required during the program suspend operation. To resume
the programming operation, the system must write the Program Resume command. The
program suspend and resume are one-bus cycle commands. The command sequence for the
erase suspend and program suspend are the same, and the command sequence for the erase
resume and program resume are the same. Read, Read Status Register, Product ID Entry, Program Resume are valid commands during a Program Suspend.
4.13
Product Identification
The product identification mode identifies the device and manufacturer as Atmel. It may be
accessed by a software operation. For details, see “Operating Modes” on page 21.
4.14
128-bit Protection Register
The AT49BV640S(T) contains a 128-bit register that can be used for security purposes in system design. The protection register is divided into two 64-bit blocks. The two blocks are
designated as block A and block B. The data in block A is non-changeable and is programmed
at the factory with a unique number. The data in block B is programmed by the user and can be
locked out such that data in the sector cannot be reprogrammed. To program block B in the protection register, the two-bus cycle Program Protection Register command must be used as
shown in the “Command Definition Table” on page 15. To lock out block B, the two-bus cycle
Lock Protection Register command must be used as shown in the “Command Definition Table”.
Data bit D1 must be zero during the second bus cycle. To determine whether block B is locked
out, use the status of block B protection command. If data bit D1 is zero, block B is locked. If
data bit D1 is one, block B can be reprogrammed. Please see the “Protection Register Addressing Table” on page 16 for the address locations in the protection register. To read the protection
register, the Product ID Entry command is given followed by a normal read operation from an
address within the protection register. After determining whether block B is protected or not, or
reading the protection register, the Read command must be given to return to the read mode.
8
AT49BV640S(T)
3583AX–FLASH–12/8/05
AT49BV640S(T)
4.15
Freeze Feature
The AT49BV640S(T) device contains a freeze feature that will freeze the lock status of the
secure regions and the lock status of protection register B. The freeze feature prevents any further locking of the secure regions and also prevents any change to the lock status of protection
register B. If the user requires certain regions to be locked, then these regions must be programmed and locked prior to activation of the freeze command. It is important to note that
enabling the freeze feature is irreversible.
To enable the freeze feature, during the second bus cycle of the Lock Protection Register
(Block B), Lock SCR7-SCR0 command, bit D10 must be a “0”, and bits D9 - D1 must be all “1s”.
This bit sequence is used to prevent inadvertent activation of the freeze feature. Although
enabling the freeze feature requires D9 - D1 to be all “1s”, the lock status of the secure regions
and protection register B will not change to the unlocked state by enabling the freeze feature.
4.16
Common Flash Interface (CFI)
CFI is a published, standardized data structure that may be read from a flash device. CFI allows
system software to query the installed device to determine the configurations, various electrical
and timing parameters, and functions supported by the device. CFI is used to allow the system
to learn how to interface to the flash device most optimally. The two primary benefits of using
CFI are ease of upgrading and second source availability. The command to enter the CFI Query
mode is a one-bus cycle command which requires writing data 98h to any address. The CFI
Query command can be written when the device is ready to read data or can also be written
when the part is in the product ID mode. Once in the CFI Query mode, the system can read CFI
data at the addresses given in “Common Flash Interface Definition Table” on page 26. To return
to the read mode, the read command should be issued.
4.17
Hardware Data Protection
Hardware features protect against inadvertent programs to the AT49BV640S(T) in the following
ways: (a) VCC sense: if VCC is below 1.8V (typical), the device is reset and the program and
erase functions are inhibited. (b) Program inhibit: holding any one of OE low, CE high or WE
high inhibits program cycles. (c) Program inhibit: VPP is less than VILPP.
4.18
Input Levels
While operating with a 2.65V to 3.6V power supply, the address inputs and control inputs (OE,
CE and WE) may be driven from 0 to 5.5V without adversely affecting the operation of the
device. The I/O lines can be driven from 0 to VCCQ + 0.6V.
4.19
Output Levels
For the AT49BV640S(T), output high levels are equal to VCCQ - 0.1V (not VCC). For 2.65V to
3.6V output levels, VCCQ must be tied to VCC.
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4.20
Word Program Flowchart
4.21
Word Program Procedure
Bus
Operation
Start
Write 40,
Any Address
Command
Program
Setup
Write
Data
Data = Data to program
Addr = Location to program
Read
None
Status register data: Toggle CE
or
OE to update status register
Idle
None
Check SR7
1 = WSM Ready
0 = WSM Busy
(Confirm)
Program
Suspend
Loop
Read-Status
Register
No
0
SR7 =
Suspend?
Ye s
1
Full Status
Check
(If Desired)
Data = 40
Addr = Any Address
Write
(Setup)
Write Data,
Word Address
Comments
Repeat for subsequent Word Program operations.
Full status register check can be done after each program, or
after a sequence of program operations.
Write FF after the last operation to set to the Read state.
Program
Complete
4.22
Full Status Check Flowchart
Read Status
Register
SR3 =
1
VP P Range
Error
4.23
Full Status Check Procedure
Bus
Operation
Command
Idle
None
Check SR3:
1 = VPP Error
Idle
None
Check SR4:
1 = Data Program Error
Idle
None
Check SR1:
1 = Sector locked; operation
aborted
0
SR4 =
1
Program
Error
0
SR1 =
1
Device
Protect Error
0
Comments
SR3 MUST be cleared before the Write State Machine allows
further program attempts.
If an error is detected, clear the status register before
continuing operations – only the Clear Status Register
command clears the status register error bits.
Program
Successful
10
AT49BV640S(T)
3583AX–FLASH–12/8/05
AT49BV640S(T)
4.24
Program Suspend/Resume Flowchart
4.25
Program Suspend/Resume Procedure
Bus
Operation
Start
Command
Comments
Write B0
Any Address
(Program Suspend)
Write
Program
Suspend
Data = B0
Addr = Any address
Write 70
Any Address
(Read Status)
Write
Read
Status
Data = 70
Addr = Any address
Read
None
Status register data: Toggle CE
or
OE to update status register
Addr = Any address
Idle
None
Check SR7
1 = WSM Ready
0 = WSM Busy
Idle
None
Check SR2
1 = Program suspended
0 = Program completed
Write
Read Array
Read
None
Write
Program
Resume
Read Status
Register
SR7 =
0
1
SR2 =
0
Program
Completed
1
Write FF
(Read Array)
Read
Data
Done
Reading
Write FF
No
Read
Data
Ye s
Write D0
Any Address
(Read
Array)
Data = FF
Addr = Any address
Read data from any word in the
memory
Data = D0
Addr = Any address
(Program Resume)
Program
Resumed
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4.26
Sector Erase Flowchart
4.27
Sector Erase Procedure
Bus
Operation
Start
Write 20,
Any Address
(Sector Erase)
Write D0,
(Erase Confirm)
Sector Address
Suspend
Erase
Loop
Read Status
Register
Command
Write
Sector
Erase
Setup
Write
Erase
Confirm
Data = D0
Addr = Sector to be erased (SA)
Read
None
Status register data: Toggle CE
or
OE to update status register data
Idle
None
Check SR7
1 = WSMS Ready
0 = WSMS Busy
No
Suspend
Erase
0
SR7 =
Full Erase
Status Check
(If Desired)
Repeat for subsequent sector erasures.
Full status register check can be done after each sector erase,
or after a sequence of sector erasures.
Write FF after the last operation to enter read mode.
Sector Erase
Complete
Full Erase Status Check Flowchart
SR3 =
4.29
Full Erase Status Check Procedure
Bus
Operation
Command
VP P Range
Error
Idle
None
Check SR3:
1 = VPP Range Error
Command
Sequence Error
Idle
None
Check SR4, SR5:
Both 1 = Command Sequence
Error
1
Sector Erase
Error
Idle
None
Check SR5:
1 = Sector Erase Error
1
Sector Locked
Error
Idle
None
Check SR1:
1 = Attempted erase of locked
sector; erase aborted.
Read Status
Register
1
0
SR4, SR5 =
1,1
0
SR5 =
0
SR1 =
0
Sector Erase
Successful
12
Data = 20
Addr = Any Address
Ye s
1
4.28
Comments
Comments
SR1, SR3 must be cleared before the Write State Machine
allows further erase attempts.
Only the Clear Status Register command clears SR1, SR3,
SR4, SR5.
If an error is detected, clear the status register before
attempting an erase retry or other error recovery.
AT49BV640S(T)
3583AX–FLASH–12/8/05
AT49BV640S(T)
4.30
Erase Suspend/Resume Flowchart
4.31
Erase Suspend/Resume Procedure
Bus
Operation
Start
Command
Write B0,
Any Address
(Erase Suspend)
Write
Erase
Suspend
Data = B0
Addr = Any address
Write 70,
Any Address
(Read-Status)
Write
Read
Status
Data = 70
Addr = Any address
Read
None
Status register data: Toggle CE
or
OE to update status register
Addr = Any address
Idle
None
Check SR7
1 = WSM Ready
0 = WSM Busy
Idle
None
Check SR6
1 = Erase suspended
0 = Erase completed
Write
Read or
Program
Read or
Write
None
Write
Program
Resume
Read-Status
Register
SR7 =
0
1
SR6 =
0
Erase
Completed
1
Write FF
(Read Array)
Comments
ReadData
Done
Reading
0
Data = FF or 40
Addr = Any address
Read or program data from/to
sector other than the one being
erased
1
(Erase Resume)
3583AX–FLASH–12/8/05
Write D0,
Any Address
Write FF
Erase
Resumed
Read Array
Data
(Read-Array)
Data = D0
Addr = Any address
ATMEL CONFIDENTIAL:
13
Under Non-Disclosure Agreement (NDA)
ATMEL CONFIDENTIAL:
Under Non-Disclosure Agreement (NDA)
4.32
Protection Register Programming
Flowchart
Write C0,
Any Address
Write PR
Address Data
SR7 =
Program
PR Setup
Data = C0
Addr = Any Address
(Confirm Data)
Write
Protection
Program
Data = Data to Program
Addr = Location to Program
Read
None
Status register data: Toggle CE
or
OE to update status register data
Idle
None
Check SR7
1 = WSMS Ready
0 = WSMS Busy
0
Full-Status
Check
(If Desired)
Program Protection Register operation addresses must be
within the protection register address space. Addresses
outside this space will return an error.
Repeat for subsequent programming operations.
Full status register check can be done after each program, or
after a sequence of program operations.
Write FF after the last operation to return to the Read mode.
Program
Complete
Full Status Check Flowchart
Read Status
Register Data
VP P Range Error
0
SR1, SR4 =
0, 1
1, 1
Register Locked;
Program Aborted
0
Program
Successful
14
4.35
Full Status Check Procedure
Bus
Operation
Command
Idle
None
Check SR1, SR3, SR4:
0,1,1 = VPP Range Error
Idle
None
Check SR1, SR3, SR4:
0,0,1 = Programming Error
Idle
None
Check SR1, SR3, SR4:
1, 0,1 = Sector locked; operation
aborted
Program Error
0
SR1, SR4 =
Comments
Write
1
1, 1
Command
(Program-Setup)
Read-Status
Register
SR3, SR4 =
Protection Register Programming
Procedure
Bus
Operation
Start
4.34
4.33
Comments
SR3 must be cleared before the Write State Machine allows
further program attempts.
Only the Clear Status Register command clears SR1, SR3,
SR4.
If an error is detected, clear the status register before
attempting a program retry or other error recovery.
AT49BV640S(T)
3583AX–FLASH–12/8/05
AT49BV640S(T)
5. Command Definition Table
1st Bus Cycle
Bus
Cycles
Addr
Data
Read
1
XX
FF
Sector Erase
2
XX
2
Command Sequence
2nd Bus Cycle
Addr
Data
20
SA(2)
D0
XX
40/10
Addr
DIN
3
XX
E0
Addr0
DIN0
Erase/Program Suspend
1
XX
B0
Erase/Program Resume
1
XX
D0
1
XX
90
Sector Softlock
2
XX
60
SA(2)
01
Sector Unlock
2
XX
60
SA(2)
D0
Read Status Register
2
XX
70
XX
DOUT(5)
Clear Status Register
1
XX
50
Program Protection Register (Block B)
2
XX
C0
Addr(6)
DIN
Lock Protection Register (Block B), Lock
SCR7 - SCR0
2
XX
C0
80
DIN1(7)
Lock SCR23 - SCR8
2
XX
C0
79
DIN2(8)
Lock SCR37 - SCR24
2
XX
C0
78
DIN3(9)
Status of Protection Register (Block B),
SCR7 - SCR0
2
XX
90
80
DOUT1(10)
Status of SCR23 - SCR8
2
XX
90
79
DOUT2(11)
Status of SCR37 - SCR24
2
XX
90
78
DOUT3(12)
CFI Query
1
XX
98
Word Program
Dual Word Program
Product ID Entry
Notes:
(3)
(4)
3rd Bus Cycle
Addr
Data
Addr1
DIN1
1. The DATA FORMAT shown for each bus cycle is as follows; I/O7 - I/O0 (Hex). I/O15 - I/O8 are don’t care. The ADDRESS FORMAT
shown for each bus cycle is as follows: A7 - A0 (Hex). Address A21 through A8 are don’t care.
2. SA = sector address. Any word address within a sector can be used to designate the sector address (see pages 17 - 20 for details).
3. This fast programming option enables the user to program two words in parallel only when VPP = 9.5V. The addresses, Addr0 and
Addr1, of the two words, DIN0 and DIN1, must only differ in address A0. This command should be used during manufacturing purposes only.
4. During the second bus cycle, the manufacturer code is read from address 000000H, the device code is read from address
000001H, and the data in the protection register is read from addresses 000081H - 000088H.
5. The status register bits are output on I/O7 - I/O0.
6. Any address within the user programmable protection register region. Address locations are shown on the “Protection Register
Addressing Table” on page 16.
7. DIN1 represents 16 bits of data. If D1 is a “0”, Protection Register (Block B) will be locked. If D9 - D2 is a “0”, the corresponding
region, SCR7 - SCR0, will be secure locked. If D10 is a “0” and bits D9 - D1 are all “1”, the Freeze feature will be enabled. See
Table 4-3 on page 7.
8. DIN2 represents 16 bits of data. If D15 - D0 is a “0”, the corresponding region, SCR23 - SCR8 will be secure locked.
See Table 4-3 on page 7.
9. DIN3 represents 16 bits of data. If D14 - D1 is a “0”, the corresponding region SCR37 - SCR24 will be secure locked.
See Table 4-3 on page 7.
10. If data bit D1 is “0”, block B is locked. If data bit D1 is “1”, block B can be reprogrammed. If data bit DX (X = 9 - 2) is “0”, SCR (X - 2)
is locked. If data bit DX is a “1”, SCR (X - 2) can be reprogrammed. If bit D10 is a “0”, the freeze feature is enabled.
11. If data bit DX (X = 15 - 0) is “0”, SCR (X + 8) is locked. If data bit DX is a “1”, SCR (X + 8) can be reprogrammed.
12. If data bit DX (X = 14 - 1) is “0”, SCR (X + 23) is locked. If data bit DX is a “1” SCR (X + 23) can be reprogrammed.
3583AX–FLASH–12/8/05
ATMEL CONFIDENTIAL:
15
Under Non-Disclosure Agreement (NDA)
ATMEL CONFIDENTIAL:
Under Non-Disclosure Agreement (NDA)
6. Absolute Maximum Ratings*
*NOTICE:
Temperature under Bias ................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages Except VPP
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground ...........................-0.6V to VCCQ + 0.6V
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
VPP Input Voltage
with Respect to Ground .....................................-0.6V to 10.0V
7. Protection Register Addressing Table
Address
Use
Block
A8
A7
A6
A5
A4
A3
A2
A1
A0
81
Factory
A
0
1
0
0
0
0
0
0
1
82
Factory
A
0
1
0
0
0
0
0
1
0
83
Factory
A
0
1
0
0
0
0
0
1
1
84
Factory
A
0
1
0
0
0
0
1
0
0
85
User
B
0
1
0
0
0
0
1
0
1
86
User
B
0
1
0
0
0
0
1
1
0
87
User
B
0
1
0
0
0
0
1
1
1
88
User
B
0
1
0
0
0
1
0
0
0
Note:
16
All address lines not specified in the above table must be “0” when accessing the protection register, i.e., A21 - A8 = 0.
AT49BV640S(T)
3583AX–FLASH–12/8/05
AT49BV640S(T)
8. Memory Organization –
AT49BV640S (Continued)
8. Memory Organization –
AT49BV640S
Secure
Region
(SCR)
x16
Secure
Region
(SCR)
x16
Sector
Size
(Words)
Address Range
(A21 - A0)
SA35
32K
E0000 - E7FFF
SA36
32K
E8000 - EFFFF
SA37
32K
F0000 - F7FFF
SA38
32K
F8000 - FFFFF
SA39
32K
100000 - 107FFF
SA40
32K
108000 - 10FFFF
SA41
32K
110000 - 117FFF
SA42
32K
118000 - 11FFFF
SA43
32K
120000 - 127FFF
SA44
32K
128000 - 12FFFF
SA45
32K
130000 - 137FFF
SA46
32K
138000 - 13FFFF
SA47
32K
140000 - 147FFF
SA48
32K
148000 - 14FFFF
Sector
Size
(Words)
Address Range
(A21 - A0)
SA0
4K
00000 - 00FFF
SA1
4K
01000 - 01FFF
SA2
4K
02000 - 02FFF
SA3
4K
03000 - 03FFF
SA4
4K
04000 - 04FFF
SA5
4K
05000 - 05FFF
SA6
4K
06000 - 06FFF
SA7
4K
07000 - 07FFF
1
SA8
32K
08000 - 0FFFF
2
SA9
32K
10000 - 17FFF
3
SA10
32K
18000 - 1FFFF
4
SA11
32K
20000 - 27FFF
5
SA12
32K
28000 - 2FFFF
6
SA13
32K
30000 - 37FFF
7
SA14
32K
38000 - 3FFFF
SA49
32K
150000 - 157FFF
SA15
32K
40000 - 47FFF
SA50
32K
158000 - 15FFFF
SA16
32K
48000 - 4FFFF
SA51
32K
160000 - 167FFF
SA17
32K
50000 - 57FFF
SA52
32K
168000 - 16FFFF
SA18
32K
58000 - 5FFFF
SA53
32K
170000 - 177FFF
SA19
32K
60000 - 67FFF
SA54
32K
178000 - 17FFFF
SA20
32K
68000 - 6FFFF
SA55
32K
180000 - 187FFF
SA21
32K
70000 - 77FFF
SA56
32K
188000 - 18FFFF
SA22
32K
78000 - 7FFFF
SA57
32K
190000 - 197FFF
SA23
32K
80000 - 87FFF
SA58
32K
198000 - 19FFFF
SA24
32K
88000 - 8FFFF
SA59
32K
1A0000 - 1A7FFF
SA25
32K
90000 - 97FFF
SA60
32K
1A8000 - 1AFFFF
SA26
32K
98000 - 9FFFF
SA61
32K
1B0000 - 1B7FFF
SA27
32K
A0000 - A7FFF
SA62
32K
1B8000 - 1BFFFF
SA28
32K
A8000 - AFFFF
SA63
32K
1C0000 - 1C7FFF
SA29
32K
B0000 - B7FFF
SA64
32K
1C8000 - 1CFFFF
SA30
32K
B8000 - BFFFF
SA65
32K
1D0000 - 1D7FFF
SA31
32K
C0000 - C7FFF
SA66
32K
1D8000 - 1DFFFF
SA32
32K
C8000 - CFFFF
SA67
32K
1E0000 - 1E7FFF
SA33
32K
D0000 - D7FFF
SA68
32K
1E8000 - 1EFFFF
SA34
32K
D8000 - DFFFF
SA69
32K
1F0000 - 1F7FFF
SA70
32K
1F8000 - 1FFFFF
13
0
14
15
16
8
17
9
18
10
19
11
20
12
3583AX–FLASH–12/8/05
21
ATMEL CONFIDENTIAL:
17
Under Non-Disclosure Agreement (NDA)
ATMEL CONFIDENTIAL:
Under Non-Disclosure Agreement (NDA)
8. Memory Organization –
AT49BV640S (Continued)
Secure
Region
(SCR)
8. Memory Organization –
AT49BV640S (Continued)
x16
Sector
Size
(Words)
Address Range
(A21 - A0)
SA71
32K
200000 - 207FFF
SA72
32K
208000 - 20FFFF
22
x16
Sector
Size
(Words)
Address Range
(A21 - A0)
SA103
32K
300000 - 307FFF
SA104
32K
308000 - 30FFFF
30
SA73
32K
210000 - 217FFF
SA105
32K
310000 - 317FFF
SA74
32K
218000 - 21FFFF
SA106
32K
318000 - 31FFFF
SA75
32K
220000 - 227FFF
SA107
32K
320000 - 327FFF
SA76
32K
228000 - 22FFFF
SA108
32K
328000 - 32FFFF
23
31
SA77
32K
230000 - 237FFF
SA109
32K
330000 - 337FFF
SA78
32K
238000 - 23FFFF
SA110
32K
338000 - 33FFFF
SA79
32K
240000 - 247FFF
SA111
32K
340000 - 347FFF
SA80
32K
248000 - 24FFFF
SA112
32K
348000 - 34FFFF
24
32
SA81
32K
250000 - 257FFF
SA113
32K
350000 - 357FFF
SA82
32K
258000 - 25FFFF
SA114
32K
358000 - 35FFFF
SA83
32K
260000 - 267FFF
SA115
32K
360000 - 367FFF
SA84
32K
268000 - 26FFFF
SA116
32K
368000 - 36FFFF
25
33
SA85
32K
270000 - 277FFF
SA117
32K
370000 - 377FFF
SA86
32K
278000 - 27FFFF
SA118
32K
378000 - 37FFFF
SA87
32K
280000 - 287FFF
SA119
32K
380000 - 387FFF
SA88
32K
288000 - 28FFFF
SA120
32K
388000 - 38FFFF
26
34
SA89
32K
290000 - 297FFF
SA121
32K
390000 - 397FFF
SA90
32K
298000 - 29FFFF
SA122
32K
398000 - 39FFFF
SA91
32K
2A0000 - 2A7FFF
SA123
32K
3A0000 - 3A7FFF
SA92
32K
2A8000 - 2AFFFF
SA124
32K
3A8000 - 3AFFFF
27
35
SA93
32K
2B0000 - 2B7FFF
SA125
32K
3B0000 - 3B7FFF
SA94
32K
2B8000 - 2BFFFF
SA126
32K
3B8000 - 3BFFFF
SA95
32K
2C0000 - 2C7FFF
SA127
32K
3C0000 - 3C7FFF
SA96
32K
2C8000 - 2CFFFF
SA128
32K
3C8000 - 3CFFFF
28
36
SA97
32K
2D0000 - 2D7FFF
SA129
32K
3D0000 - 3D7FFF
SA98
32K
2D8000 - 2DFFFF
SA130
32K
3D8000 - 3DFFFF
SA99
32K
2E0000 - 2E7FFF
SA131
32K
3E0000 - 3E7FFF
SA100
32K
2E8000 - 2EFFFF
SA132
32K
3E8000 - 3EFFFF
29
18
Secure
Region
(SCR)
37
SA101
32K
2F0000 - 2F7FFF
SA133
32K
3F0000 - 3F7FFF
SA102
32K
2F8000 - 2FFFFF
SA134
32K
3F8000 - 3FFFFF
AT49BV640S(T)
3583AX–FLASH–12/8/05
AT49BV640S(T)
9. Memory Organization –
AT49BV640ST (Continued)
9. Memory Organization –
AT49BV640ST
Secure
Region
(SCR)
x16
Sector
Size
(Words)
Address Range
(A21 - A0)
SA0
32K
00000 - 07FFF
SA1
32K
08000 - 0FFFF
SA2
32K
10000 - 17FFF
SA3
32K
18000 - 1FFFF
37
Secure
Region
(SCR)
x16
Sector
Size
(Words)
Address Range
(A21 - A0)
SA36
32K
120000 - 127FFF
SA37
32K
128000 - 12FFFF
SA38
32K
130000 - 137FFF
SA39
32K
138000 - 13FFFF
SA40
32K
140000 - 147FFF
SA41
32K
148000 - 14FFFF
SA42
32K
150000 - 157FFF
SA43
32K
158000 - 15FFFF
SA44
32K
160000 - 167FFF
SA45
32K
168000 - 16FFFF
28
SA4
32K
20000 - 27FFF
SA5
32K
28000 - 2FFFF
SA6
32K
30000 - 37FFF
SA7
32K
38000 - 3FFFF
SA8
32K
40000 - 47FFF
SA9
32K
48000 - 4FFFF
SA10
32K
50000 - 57FFF
SA11
32K
58000 - 5FFFF
SA12
32K
60000 - 67FFF
SA13
32K
68000 - 6FFFF
SA14
32K
70000 - 77FFF
SA15
32K
78000 - 7FFFF
SA52
32K
1A0000 - 1A7FFF
SA16
32K
80000 - 87FFF
SA53
32K
1A8000 - 1AFFFF
SA17
32K
88000 - 8FFFF
SA54
32K
1B0000 - 1B7FFF
SA18
32K
90000 - 97FFF
SA55
32K
1B8000 - 1BFFFF
SA19
32K
98000 - 9FFFF
SA56
32K
1C0000 - 1C7FFF
SA20
32K
A0000 - A7FFF
SA57
32K
1C8000 - 1CFFFF
SA21
32K
A8000 - AFFFF
SA58
32K
1D0000 - 1D7FFF
SA22
32K
B0000 - B7FFF
SA59
32K
1D8000 - 1DFFFF
SA60
32K
1E0000 - 1E7FFF
SA61
32K
1E8000 - 1EFFFF
SA62
32K
1F0000 - 1F7FFF
SA63
32K
1F8000 - 1FFFFF
SA64
32K
200000 - 207FFF
SA65
32K
208000 - 20FFFF
27
36
26
35
SA24
32K
C0000 - C7FFF
SA25
32K
C8000 - CFFFF
SA26
32K
D0000 - D7FFF
SA27
32K
D8000 - DFFFF
SA28
32K
E0000 - E7FFF
SA29
32K
E8000 - EFFFF
F0000 - F7FFF
SA31
32K
F8000 - FFFFF
SA32
32K
100000 - 107FFF
SA33
32K
108000 - 10FFFF
SA34
32K
110000 - 117FFF
SA35
32K
118000 - 11FFFF
29
3583AX–FLASH–12/8/05
32K
180000 - 187FFF
SA49
32K
188000 - 18FFFF
SA50
32K
190000 - 197FFF
SA51
32K
198000 - 19FFFF
21
30
32K
SA48
22
31
SA30
178000 - 17FFFF
23
32
B8000 - BFFFF
170000 - 177FFF
32K
24
33
32K
32K
SA47
25
34
SA23
SA46
SA66
32K
210000 - 217FFF
SA67
32K
218000 - 21FFFF
SA68
32K
220000 - 227FFF
SA69
32K
228000 - 22FFFF
SA70
32K
230000 - 237FFF
SA71
32K
238000 - 23FFFF
20
ATMEL CONFIDENTIAL:
19
Under Non-Disclosure Agreement (NDA)
ATMEL CONFIDENTIAL:
Under Non-Disclosure Agreement (NDA)
9. Memory Organization –
AT49BV640ST (Continued)
Secure
Region
(SCR)
x16
Sector
Size
(Words)
Address Range
(A21 - A0)
SA72
32K
240000 - 247FFF
SA73
32K
248000 - 24FFFF
19
9. Memory Organization –
AT49BV640ST (Continued)
Secure
Region
(SCR)
x16
Sector
Size
(Words)
Address Range
(A21 - A0)
SA104
32K
340000 - 347FFF
SA105
32K
348000 - 34FFFF
11
SA74
32K
250000 - 257FFF
SA106
32K
350000 - 357FFF
SA75
32K
258000 - 25FFFF
SA107
32K
358000 - 35FFFF
SA76
32K
260000 - 267FFF
SA108
32K
360000 - 367FFF
SA77
32K
268000 - 26FFFF
SA109
32K
368000 - 36FFFF
18
10
SA78
32K
270000 - 277FFF
SA110
32K
370000 - 377FFF
SA79
32K
278000 - 27FFFF
SA111
32K
378000 - 37FFFF
SA80
32K
280000 - 287FFF
SA112
32K
380000 - 387FFF
SA81
32K
288000 - 28FFFF
SA113
32K
388000 - 38FFFF
17
9
SA82
32K
290000 - 297FFF
SA114
32K
390000 - 397FFF
SA83
32K
298000 -29FFFF
SA115
32K
398000 - 39FFFF
SA84
32K
2A0000 - 2A7FFF
SA116
32K
3A0000 - 3A7FFF
SA85
32K
2A8000 - 2AFFFF
SA117
32K
3A8000 - 3AFFFF
16
8
SA86
32K
2B0000 - 2B7FFF
SA118
32K
3B0000 - 3B7FFF
SA87
32K
2B8000 - 2BFFFF
SA119
32K
3B8000 - 3BFFFF
SA88
32K
2C0000 - 2C7FFF
7
SA120
32K
3C0000 - 3C7FFF
SA89
32K
2C8000 - 2CFFFF
6
SA121
32K
3C8000 - 3CFFFF
SA90
32K
2D0000 - 2D7FFF
5
SA122
32K
3D0000 - 3D7FFF
SA91
32K
2D8000 - 2DFFFF
4
SA123
32K
3D8000 - 3DFFFF
SA92
32K
2E0000 - 2E7FFF
3
SA124
32K
3E0000 - 3E7FFF
SA93
32K
2E8000 - 2EFFFF
2
SA125
32K
3E8000 - 3EFFFF
SA94
32K
2F0000 - 2F7FFF
1
SA126
32K
3F0000 - 3F7FFF
SA95
32K
2F8000 - 2FFFFF
SA127
4K
3F8000 - 3F8FFF
SA96
32K
300000 - 307FFF
SA128
4K
3F9000 - 3F9FFF
SA97
32K
308000 - 30FFFF
SA129
4K
3FA000 - 3FAFFF
SA98
32K
310000 - 317FFF
SA130
4K
3FB000 - 3FBFFF
15
14
13
0
SA99
32K
318000 - 31FFFF
SA131
4K
3FC000 - 3FCFFF
SA100
32K
320000 - 327FFF
SA132
4K
3FD000 - 3FDFFF
SA101
32K
328000 - 32FFFF
SA133
4K
3FE000 - 3FEFFF
SA102
32K
330000 - 337FFF
SA134
4K
3FF000 - 3FFFFF
SA103
32K
338000 - 33FFFF
12
20
AT49BV640S(T)
3583AX–FLASH–12/8/05
AT49BV640S(T)
10. DC and AC Operating Range
AT49BV640S(T)-70
Operating Temperature (Case)
Industrial
-40°C - 85°C
VCC Power Supply
2.65V - 3.6V
11. Operating Modes
Mode
CE
Read
OE
VIL
(3)
VIL
WE
VPP(1)
Ai
I/O
VIH
X(2)
Ai
DOUT
Ai
DIN
X
High Z
RESET
VIH
Program/Erase
VIL
VIH
VIL
VIH
VIHPP(4)
Standby/Program
Inhibit
VIH
X(2)
X
VIH
X
X
X
VIH
VIH
X
X
VIL
X
VIH
X
X
X
X
X
VILPP(5)
Output Disable
X
VIH
X
VIH
X
Reset
X
X
X
VIL
X
Program Inhibit
Product Identification
Software
Notes:
VIH
High Z
X
High Z
A0 = VIL, A1 - A21 = VIL
Manufacturer Code(6)
A0 = VIH, A1 - A21 = VIL
Device Code(6)
1. The VPP pin can be tied to VCC. For faster program operation, VPP can be set to 9.5V ± 0.5V.
2. X can be VIL or VIH.
3. Refer to AC programming waveforms on page 25.
4. VIHPP (min) = 1.65V.
5. VILPP (max) = 0.4V.
6. Manufacturer Code: 001FH; Device Code: 02DEH – AT49BV640S; 02DBH – AT49BV640ST
12. DC Characteristics
Symbol
Parameter
Condition
ILI
Input Load Current
ILO
Max
Units
VIN = 0V to VCC
2
µA
Output Leakage Current
VI/O = 0V to VCC
2
µA
ISB
VCC Standby Current CMOS
CE = VCCQ - 0.3V to VCC
15
25
µA
ICC(1)
VCC Active Read Current
f = 5 MHz; IOUT = 0 mA
10
15
mA
ICC1
VCC Programming Current
25
mA
IPP1
VPP Input Load Current
10
µA
VIL
Input Low Voltage
0.6
V
VIH
Input High Voltage
VOL
Output Low Voltage
IOL = 2.1 mA
VOH
Output High Voltage
IOH = -100 µA
Note:
Min
Typ
VCCQ - 0.6
V
0.45
VCCQ - 0.1
V
V
1. In the erase mode, ICC is 25 mA.
3583AX–FLASH–12/8/05
ATMEL CONFIDENTIAL:
21
Under Non-Disclosure Agreement (NDA)
ATMEL CONFIDENTIAL:
Under Non-Disclosure Agreement (NDA)
13. Input Test Waveforms and Measurement Level
2.0V
AC
DRIVING
LEVELS
1.5V
AC
MEASUREMENT
LEVEL
0.6V
tR, tF < 5 ns
14. Output Test Load
VCCQ
1.8K
OUTPUT
PIN
1.3K
30 pF
15. Pin Capacitance
f = 1 MHz, T = 25°C(1)
CIN
COUT
Note:
22
Typ
Max
Units
Conditions
4
6
pF
VIN = 0V
8
12
pF
VOUT = 0V
1. This parameter is characterized and is not 100% tested.
AT49BV640S(T)
3583AX–FLASH–12/8/05
AT49BV640S(T)
16. AC Read Characteristics
AT49BV640S(T)-70
Symbol
Parameter
tRC
Read Cycle Time
tACC
Access, Address to Data Valid
70
ns
tCE(1)
Access, CE to Data Valid
70
ns
tOE(2)
OE to Data Valid
20
ns
CE, OE High to Data Float
25
ns
tDF
(3)(4)
Min
Max
70
tOH
Output Hold from OE, CE or Address, whichever Occurs First
tRO
RESET to Output Delay
Units
ns
0
ns
100
ns
17. Asynchronous Read Cycle Waveform(1)(2)(3)(4)
tRC
ADDRESS VALID
A0 - A21
CE
tCE
tOE
OE
tDF
tOH
tACC
tRO
RESET
I/O0 - I/O15
Notes:
HIGH Z
OUTPUT
VALID
1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC.
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC.
3. tDF is specified from OE or CE, whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
3583AX–FLASH–12/8/05
ATMEL CONFIDENTIAL:
23
Under Non-Disclosure Agreement (NDA)
ATMEL CONFIDENTIAL:
Under Non-Disclosure Agreement (NDA)
18. AC Word Load Characteristics
Symbol
Parameter
Min
Max
Units
tAS, tOES
Address, OE Setup Time
20
ns
tAH
Address Hold Time
0
ns
tCS
Chip Select Setup Time
0
ns
tCH
Chip Select Hold Time
0
ns
tWP
Write Pulse Width (WE or CE)
25
ns
tWPH
Write Pulse Width High
15
ns
tDS
Data Setup Time
25
ns
tDH, tOEH
Data, OE Hold Time
0
ns
19. AC Word Load Waveforms
19.1
WE Controlled
19.2
CE Controlled
24
AT49BV640S(T)
3583AX–FLASH–12/8/05
AT49BV640S(T)
20. Program Cycle Characteristics
Symbol
Parameter
tBP
Min
Typ
Max
Units
Word Programming Time
10
120
µs
tBPD
Word Programming Time in Dual Programming Mode
5
60
µs
tAS
Address Setup Time
20
ns
tAH
Address Hold Time
0
ns
tDS
Data Setup Time
25
ns
tDH
Data Hold Time
0
ns
tWP
Write Pulse Width
25
ns
tWPH
Write Pulse Width High
15
ns
tWC
Write Cycle Time
70
ns
tRP
Reset Pulse Width
500
ns
tSEC1
Sector Erase Cycle Time (4K Word Sectors)
0.1
2.0
seconds
tSEC2
Sector Erase Cycle Time (32K Word Sectors)
0.5
6.0
seconds
tES
Erase Suspend Time
15
µs
tPS
Program Suspend Time
10
µs
tERES
Delay between Erase Resume and Erase Suspend
500
µs
21. Program Cycle Waveforms
PROGRAM CYCLE
OE
(2)
CE
tBP
tWP
WE
tWPH
tDH
tAS
A0 - A21
XX
tAH
(1)
ADDRESS
tWC
I/O0 - I/O15
tDS
INPUT DATA
Note 3
22. Sector Erase Cycle Waveforms
OE
(2)
CE
tWP
tWPH
WE
tDH
tAS
A0 - A21
XX
tAH
(1)
Note 4
tWC
I/O0 - I/O15
tDS
20
WORD 0
Notes:
tSEC1/2
D0
WORD 1
1. Any address can be used to load data.
2. OE must be high only when WE and CE are both low.
3. The data can be 40H or 10H.
4. The address depends on what sector is to be erased.
3583AX–FLASH–12/8/05
ATMEL CONFIDENTIAL:
25
Under Non-Disclosure Agreement (NDA)
ATMEL CONFIDENTIAL:
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23. Common Flash Interface Definition Table
26
Address
AT49BV640ST
AT49BV640S
Comments
10h
0051h
0051h
“Q”
11h
0052h
0052h
“R”
12h
0059h
0059h
“Y”
13h
0003h
0003h
14h
0000h
0000h
15h
0041h
0041h
16h
0000h
0000h
17h
0000h
0000h
18h
0000h
0000h
19h
0000h
0000h
1Ah
0000h
0000h
1Bh
0027h
0027h
VCC min write/erase
1Ch
0036h
0036h
VCC max write/erase
1Dh
0090h
0090h
VPP min voltage
1Eh
00A0h
00A0h
VPP max voltage
1Fh
0004h
0004h
Typ word write – 10 µs
20h
0002h
0002h
Typ dual word program time – 5 µs
21h
0009h
0009h
Typ sector erase – 700 ms
22h
0000h
0000h
Typ chip erase – N/A
23h
0004h
0004h
Max word write/typ time
24h
0004h
0004h
Max dual word program time/typical time
25h
0003h
0003h
Max sector erase/typ sector erase
26h
0000h
0000h
Max chip erase/ typ chip erase – N/A
27h
0017h
0017h
Device size
28h
0001h
0001h
x16 device
29h
0000h
0000h
x16 device
2Ah
0002h
0002h
Maximum number of bytes in multiple byte write = 4
2Bh
0000h
0000h
Maximum number of bytes in multiple byte write = 4
2Ch
0002h
0002h
2 regions, x = 2
2Dh
007Eh
0007h
64K bytes, Y = 126 (Top); 8K bytes, Y = 7 (Bottom)
2Eh
0000h
0000h
64K bytes, Y = 126 (Top); 8K bytes, Y = 7 (Bottom)
2Fh
0000h
0020h
64K bytes, Z = 256 (Top); 8K bytes, Z = 32 (Bottom)
30h
0001h
0000h
64K bytes, Z = 256 (Top); 8K bytes, Z = 32 (Bottom)
31h
0007h
007Eh
8K bytes, Y = 7 (Top); 64K bytes, Y = 126 (Bottom)
32h
0000h
0000h
8K bytes, Y = 7 (Top); 64K bytes, Y = 126 (Bottom)
33h
0020h
0000h
8K bytes, Z = 32 (Top);64K bytes, Z = 256 (Bottom)
34h
0000h
0001h
8K bytes, Z = 32 (Top);64K bytes, Z = 256 (Bottom)
AT49BV640S(T)
3583AX–FLASH–12/8/05
AT49BV640S(T)
23. Common Flash Interface Definition Table (Continued)
Address
AT49BV640ST
AT49BV640S
Comments
VENDOR SPECIFIC EXTENDED QUERY
41h
0050h
0050h
“P”
42h
0052h
0052h
“R”
43h
0049h
0049h
“I”
44h
0031h
0031h
Major version number, ASCII
45h
0030h
0030h
Minor version number, ASCII
46h
0086h
0086h
Bit 0 – chip erase supported, 0 – no, 1 – yes
Bit 1 – erase suspend supported, 0 – no, 1 – yes
Bit 2 – program suspend supported, 0 – no, 1 – yes
Bit 3 – simultaneous operations supported, 0 – no, 1 – yes
Bit 4 – burst mode read supported, 0 – no, 1 – yes
Bit 5 – page mode read supported, 0 – no, 1 – yes
Bit 6 – queued erase supported, 0 – no, 1 – yes
Bit 7 – protection bits supported, 0 – no, 1 – yes
47h
0000h
0001h
Bit 0 – top (“0”) or bottom (“1”) boot block device
Undefined bits are “0”
0000h
Bit 0 – 4 word linear burst with wrap around, 0 – no, 1 – yes
Bit 1 – 8 word linear burst with wrap around, 0 – no, 1 – yes
Bit 2 – 16 word linear burst with wrap around, 0 – no, 1 – yes
Bit 3 – continuous burst, 0 – no, 1 – yes
Undefined bits are “0”
48h
0000h
49h
0000h
0000h
Bit 0 – 4 word page, 0 – no, 1 – yes
Bit 1 – 8 word page, 0 – no, 1 – yes
Undefined bits are “0”
4Ah
0080h
0080h
Location of protection register lock byte, the section’s first byte
4Bh
0003h
0003h
# of bytes in the factory prog section of prot register – 2*n
4Ch
0003h
0003h
# of bytes in the user prog section of prot register – 2*n
3583AX–FLASH–12/8/05
ATMEL CONFIDENTIAL:
27
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ATMEL CONFIDENTIAL:
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24. Ordering Information
24.1
Green Package (Pb/Halide-free/RoHS Compliant)
ICC (mA)
tACC
(ns)
Active
Standby
70
10
0.025
Ordering Code
Package
Operation Range
64C1
Industrial
(-40° to 85° C)
AT49BV640S-70CU
AT49BV640ST-70CU
Package Type
64C1
28
64-ball, Plastic Chip-size Ball Grid Array Package (CBGA)
AT49BV640S(T)
3583AX–FLASH–12/8/05
AT49BV640S(T)
25. Packaging Information
25.1
64C1 – CBGA
0.12 C
D
C Seating Plane
E
Side View
A1
Top View
A
D1
1.0 mm Ref
8
7
6
5
4
3
2
1
A
B
C
D
E1
COMMON DIMENSIONS
(Unit of Measure = mm)
E
F
e
G
SYMBOL
MIN
NOM
MAX
H
A
–
–
1.00
A1
0.23
–
–
D
8.90
9.00
9.10
1.50 mm Ref
Øb
e
D1
Bottom View
E
E1
NOTE
7.0 TYP
9.90
10.00
10.10
7.0 TYP
e
1.0 TYP
Øb
0.35 TYP
1/25/05
R
2325 Orchard Parkway
San Jose, CA 95131
3583AX–FLASH–12/8/05
TITLE
64C1, 64-ball (8 x 8 Array), 9 x 10 x 1.0 mm Body, 1.0 mm Ball Pitch
Chip-scale Ball Grid Array Package (CBGA)
DRAWING NO.
64C1
REV.
B
ATMEL CONFIDENTIAL:
29
Under Non-Disclosure Agreement (NDA)
ATMEL CONFIDENTIAL:
Under Non-Disclosure Agreement (NDA)
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3583AX–FLASH–12/8/05