CY3210-29x66 EvalPod Schematic.pdf

5
4
3
2
1
VCC
Be aware when
measuring current that
this resistor may need
to be removed.
R1
D1
VCC
VCC
C1
C2
C3
C4
C5
3528
0603
0.1 uFd
0603
0.1 uFd
0603
0.1 uFd
0603
0.1 uFd
+
10 uFd 16v
0603
1K
U1
OCD_DE
OCD_DE
OCD_DO
12
13
OCDE
OCDO
OCD_HCLK
OCD_CCLK
60
61
HCLK
CCLK
0603
OCD_RESET
56.2
C6
R3
1K
NO LOAD
62
XRES
P0_0
P0_1
P0_2
P0_3
P0_4
P0_5
P0_6
P0_7
74
3
77
99
79
97
81
95
P0_0/AI
P0_1/AI
P0_2/AIO
P0_3/AIO
P0_4/AIO
P0_5/AIO
P0_6/AI
P0_7/AI
P1_0
P1_1
P1_2
P1_3
P1_4
P1_5
P1_6
P1_7
44
30
45
29
46
28
47
24
P1_0/XTALOUT
P1_1/XTALIN
P1_2
P1_3
P1_4/EXTCLK
P1_5/SDA
P1_6
P1_7/SCL
P2_0
P2_1
P2_2
P2_3
P2_4
P2_5
P2_6
P2_7
68
7
69
6
70
5
72
4
P2_0/AI
P2_1/AI
P2_2/AI
P2_3/AI
P2_4/AGND
P2_5
P2_6/VREF
P2_7
P3_0
P3_1
P3_2
P3_3
P3_4
P3_5
P3_6
P3_7
56
19
57
18
58
17
59
16
P3_0
P3_1
P3_2
P3_3
P3_4
P3_5
P3_6
P3_7
TV1
TV2
TV4
TV6
TV8
TV10
TV12
TV14
TV16
TV18
TV20
1
2
25
26
27
31
33
35
48
49
50
P0_[0:7]
0603
0603
VCC
R4
P1_[0:7]
OCD_DO
R5
1K
NO LOAD
U2
0603
0603
VCC
C8
C
R6
OCD_CCLK
0603
56.2
C9
NO LOAD
XRES
24
4
25
3
26
2
27
1
P0_0
P0_1
P0_2
P0_3
P0_4
P0_5
P0_6
P0_7
SMP
9
SMP
0603
14
OCD_RESET
P3
8
7
6
5
4
3
2
1
C11
330 pFd
20
8
21
7
22
6
23
5
P2_0
P2_1
P2_2
P2_3
P2_4
P2_5
P2_6
P2_7
P2_[0:7]
28 DIP Socket
R8
1K
63
11
64
10
66
9
67
8
P4_0
P4_1
P4_2
P4_3
P4_4
P4_5
P4_6
P4_7
P5_0
P5_1
P5_2
P5_3
P5_4
P5_5
P5_6
P5_7
52
23
53
22
54
21
55
20
P5_0
P5_1
P5_2
P5_3
P5_4
P5_5
P5_6
P5_7
P6_0
P6_1
P6_2
P6_3
P6_4
P6_5
P6_6
P6_7
86
87
88
89
90
91
92
93
P6_0
P6_1
P6_2
P6_3
P6_4
P6_5
P6_6
P6_7
P7_0
P7_1
P7_2
P7_3
P7_4
P7_5
P7_6
P7_7
43
42
41
40
39
38
37
36
P7_0
P7_1
P7_2
P7_3
P7_4
P7_5
P7_6
P7_7
SMP
14
SMP
RECEPTACLE 20x1
C
P2
P3_6
P3_4
P3_2
P3_0
P4_6
P4_4
P4_2
P4_0
P5_6
P5_4
P5_2
P5_0
P6_6
P6_4
P6_2
P6_0
P7_6
P7_4
P7_2
P7_0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
RECEPTACLE 20x1
B
0603
0603
P1_0
P1_1
P1_2
P1_3
P1_4
P1_5
P1_6
P1_7
R9
OCD_HCLK
0603
B
P2_0
P2_1
P2_2
P2_3
P2_4
P2_5
P2_6
P2_7
15
13
16
12
17
11
18
10
P4_0
P4_1
P4_2
P4_3
P4_4
P4_5
P4_6
P4_7
D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
C12
56.2
R10
1K
RJ45 Right Angle
NO LOAD
0603
0603
NC12
NC13
NC14
NC15
NC16
NC17
NC18
NC19
NC20
NC21
NC22
TV3
TV5
TV7
TV9
TV11
TV13
TV15
TV17
TV19
TV21
TV22
GND1
GND2
GND3
GND4
GND5
NOTE: RJ45 pinout assumes a
straight-through connector
will be used.
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
51
71
73
75
76
78
80
94
96
98
100
CY8C29000 TQFP100
VCC
15
34
65
84
85
C10
0.1 uFd
R7
1K
0603
0603
19
P0_0
P0_1
P0_2
P0_3
P0_4
P0_5
P0_6
P0_7
P1_0
P1_1
P1_2
P1_3
P1_4
P1_5
P1_6
P1_7
GND2
VCC
28
0603
56.2
P3_7
P3_5
P3_3
P3_1
P4_7
P4_5
P4_3
P4_1
P5_7
P5_5
P5_3
P5_1
P6_7
P6_5
P6_3
P6_1
P7_7
P7_5
P7_3
P7_1
VDD1
VDD2
VDD3
LED Green
R2
P1
32
82
83
1206
D
C13
0603
A
TP1
TP2
TP-43R TP-43R
0.1 uFd
J1
PCB:
PCA:
VCC
PDCR-9311 REV*A
121R-31100 REV*B
A
CYPRESS SEMICONDUCTOR © 2005
1
2
3
4
5
OCD_RESET
P1_1
P1_0
Title
CY8C29000 28 PDIP Module
TP3
TP-43R
HDR 1x5
Programming header
Size
B
Test points
Date:
5
4
3
2
Document Number
REF-13446
Monday, May 22, 2006
Rev
*A
Sheet
1
1
of
1