L9949 DOOR ACTUATOR DRIVER ■ ONE FULL BRIDGE FOR 6A LOAD (ron = 150mΩ) ■ THREE HALF BRIDGES FOR 1.6A LOAD (ron = 800mΩ) ■ ONE HIGHSIDE DRIVER FOR 6A LOAD (ron = 100mΩ) ■ VERY LOW CURRENT CONSUMPTION IN STANDBY MODE (IS < 6µA, typ. Tj ≤ 85°C) ■ SERIAL PERIPHERAL INTERFACE (SPI) TO MICROCONTROLLER ■ ALL OUTPUTS SHORT CIRCUIT PROTECTED ■ CURRENT MONITOR OUTPUT FOR FULL BRIDGE AND HIGHSIDE DRIVER ■ ALL OUTPUTS OVER TEMPERATURE PROTECTED ■ OPEN LOAD DIAGNOSTIC FOR ALL OUTPUTS ■ OVERLOAD DIAGNOSTIC FOR ALL OUTPUTS MULTIPOWER BCD60III TECHNOLOGY PowerSO20 ORDERING NUMBER: L9949 FULL BRIDGE FOR DOOR LATCH OR MIRROR RETRACT, HALF BRIDGES FOR MIRROR AXIS CONTROL AND HIGH-SIDE DRIVER FOR MIRROR DEFROSTER DESCRIPTION APPLICATIONS ■ FOR AUTOMOTIVE APPLICATIONS, E.G. The L9949 is a microprocessor controlled power interface for automotive applications. It is realized in multipower BCD60III technology. Up to three DC mo- BLOCK DIAGRAM VS (battery) MUX VCC CM OUT1 M e.g. for mirror retract or door latch Full bridge OUT2 µC SPI DO CLK CSN Driver Interface & Diagnostic DI OUT3 M OUT4 M Half bridge e.g. for mirror axis control Half bridge OUT5 OUT6 e.g. for mirror defroster Highside driver Ground September 2002 1/20 L9949 DESCRIPTION (continued) tors and one grounded resistive load can be driven with its three half bridges, one full bridge and one highside driver power outputs. The integrated standard serial peripheral interface (SPI) controls all operation modes (forward, reverse, brake and high impedance). All diagnostic informations are available via the SPI. Dual Power Supply: VS and VCC The power supply voltage VS supplies the full bridge, the half bridges and the highside driver. An internal charge-pump are used to drive the highside switches. The logic supply voltage VCC (stabilized 5V) is used for the logic part and the SPI of the device. Due to the independent logic supply voltage the control and status information will not be lost, if there are temporary spikes or glitches on the power supply voltage. In case of poweron (VCC increases from undervoltage to VVCC OFF = 4.2V) the circuit is initialized by an internally generated power-on-reset (POR). If the voltage VCC decreases under the minimum threshold (VVCC ON = 3.4V), the outputs are switched to tristate (high impedance) and the status registers are cleared. Standby-Mode The standby mode of the L9949 is activated by setting the bits 12 and 13 of the Input Data Register to zero. All latched data will be cleared and the inputs and outputs are switched to high impedance. In the standby mode the current at VS (VCC) is less than typ. 6µA (40µA) for CSN = high (DO in tristate). By switching the VCC voltage a very low quiescent current can be achieved. If one of the bits 12 and 13 are set to high, the device will be switched to active mode. Inductive Loads Each half bridge is built by internally connected highside and a lowside power DMOS transistor. Due to the builtin reverse diodes of the output transistors inductive loads can be driven at the outputs OUT1 to OUT5 without external free-wheeling diodes. The highside driver OUT6 is intended to drive resistive loads only hence only a limited energie (E<1mJ ) can be dissipated by the internal ESD-diode in freewheeling condition. For inductive loads (L>100µH) an external free-wheeling diode connected to GND and OUT6 is needed. Diagnostic Functions All diagnostic functions (over/open load, power supply over-/undervoltage, temperature warning and thermal shutdown) are internally filtered and the condition has to be valid for at least 10µs (0.5ms, respectively) before the corresponding status bit in the status registers will be set. The filters are used to improve the noise immunity of the device. The open load and temperature warning function are intended for information purpose and will not change the state of the output drivers. In contrast, the overload and thermal shutdown condition will disable the corresponding driver (overload) or all drivers (thermal shutdown), respectively. The microcontroller has to clear the status bits to reactivate the corresponding drivers. This is to avoid an uncontrolled switching behaviour of the device which may result in a heavy noise on the GND and VS lines in case of an fault condition (e.g. short to GND or VS). Overvoltage and Undervoltage Detection If the power supply voltage VS rises above the overvoltage threshold VSOV OFF (max. 22V), the outputs OUT1 to OUT6 are switched to high impedance state to protect the load. If the supply voltage recovers to normal operating voltage, the device will return to the programmed state (lockout bit 14 = 0). When the voltage VS drops below the undervoltage threshold VSUV OFF (min. 6V), the output stages are switched to high impedance to avoid the operation of the power devices without sufficient gate driving voltage (increased power dissipation). If the supply voltage VS and the internal charge-pump recovers to normal operating voltage the system returns to the programmed state (lockout bit 14 = 0). If the lockout bit 14 is set, the automatic turn-on of the drivers is deactivated. The microcontroller needs to clear the status bits to reactivate the drivers. 2/20 L9949 Temperature Warning and Thermal Shutdown When the junction temperature rises above Tj TW a temperature warning flag is set and is available via the SPI. If the junction temperature increases above the second threshold Tj SD, the thermal shutdown bit will be set and the power DMOS transistors of the output stages are switched off to protect the device. In order to reactivate the output stages the junction temperature must decrease below Tj SD - Tj SD HYS and the thermal shutdown bit has to be cleared by the microcontroller. Open Load Detection The open load detection monitors the voltage drop of current sense resistors in each highside and lowside driver of the output stage. The output signal of an open load comparator has to be valid for at least 0.5 ms (tdOL) to set the open load bit (bit 1-11) in the status register 1. Over Load Detection In the case of an overcurrent condition an overcurrent flag (bit 1-11) is set in the status register 0 in the same way as open load detection. If the overcurrent signal is valid for at least tISC = 10µs, the overcurrent flag is set and the corresponding driver is switched off to reduce the power dissipation and to protect the integrated circuit. The microcontroller has to clear the status bits to reactivate the corresponding driver. Current monitor The current monitor output sources a current image at the current monitor output which has a fixed ratio (1/ 10000) of the instantaneous current of the selected highside driver. The bits 12 and 13 of the Input Data register controls which of the outputs OUT1, OUT2 and OUT6 will be multiplexed to the current monitor output. The current monitor output allows a more precise analyse of the actual state of the load rather than the detection of an open- or overload condition. For example this can be used to detect the motor state (free-running, loaded or blocked) or the temperature of the heating element. Figure 1. Pin Connection (Top view) GND 1 20 GND OUT3 2 19 OUT6 OUT4 3 18 VS OUT5 4 17 DO VS 5 16 CM CLK 6 15 VCC DI 7 14 CSN VS 8 13 VS OUT1 9 12 OUT2 10 11 GND GND D99AT455Amod 3/20 L9949 PIN FUNCTION N° Pin 1, 10, 11, 20 GND 5, 8, 13, 18 VS 15 VCC Logic supply voltage: For this input a ceramic capacitors as close as possible to GND are recommended. 14 CSN Chip Select Not input: This input is low active and requires CMOS logic levels. The serial data transfer between L9949 and micro controller is enabled by pulling the input CSN to low level. If an input voltage of more than 9.6V above VCC is applied to CSN pin the L9949 will be switched into a test mode. 6 CLK Serial clock input: This input controls the internal shift register of the SPI and requires CMOS logic levels. 7 Data In 17 Description Ground: Reference potential Important: For the capability of driving the full current at the outputs all pins of GND must be externally connected ! Power supply voltage (battery): For this input a ceramic capacitor as close as possible to GND is recommended. Important: For the capability of driving the full current at the outputs all pins of VS must be externally connected ! Serial data input: The input requires CMOS logic levels and receives serial data from the microcontroller. The data is an 16bit control word and the least significant bit (LSB, bit 0) is transferred first. Data Out Serial data output: The diagnosis data is available via the SPI and this tristate-output. The output will remain in tristate, if the chip is not selected by the input CSN (CSN = high) 16 CM 9 OUT1 Halfbridge-output 1: The output is built by a highside and a lowside switch, which are internally connected. The output stage of both switches is a power DMOS transistor. Each driver has an internal parasitic reverse diode (bulk-drain-diode, highside driver from OUT1 to VS, lowside driver from GND to OUT1). This output is overcurrent and open load protected. 12 OUT2 Halfbridge-output 2: 2 OUT3 Halfbridge-output 3: The output is built by a highside and a lowside switch, which are internally connected. The output stage of both switches is a power DMOS transistor. Each driver has an internal parasitic reverse diode (bulk-drain-diode, highside driver from OUT3 to VS, lowside driver from GND to OUT3). This output is overcurrent and open load protected. 3 OUT4 Halfbridge-output 4: → see OUT3 (pin 2) 4 OUT5 Halfbridge-output 5: → see OUT3 (pin 2) 19 OUT6 Highside-driver-output 6: The output is built by a highside switch and can be used only for a resistive load, because the internal reverse diode from GND to OUT6 is missing. This highside switch is a power DMOS transistor with an internal parasitic reverse diode from OUT6 to VS (bulk-drain-diode). The output is overcurrent and open load protected. 4/20 Current monitor output: Depending on the multiplexer bits 12 and 13 of the Input Data register this output sources an image of the instant current through the corresponding highside driver with a ratio of 1/10000 → see OUT1 (pin 9) L9949 ABSOLUTE MAXIMUM RATINGS Symbol Parameter VS Value Unit -0.3...28 V 40 V -0.3 to 6 V digital input / output voltage -0.3 to VCC + 0.3 V current monitor output -0.3 to VCC + 0.3 V ±10 A ±5 A DC supply voltage single pulse tmax < 400 ms VCC stabilized supply voltage, logic supply VDI VDO VCLK , VCSN VCM IOUT1,OUT2, output current OUT6 IOUT3,OUT5 output current Note: All maximum ratings are absolute ratings. Leaving the limitation of anyone of these values may cause an irreversible damage of the integrated circuit! ESD PROTECTION Parameter Value All pins ±2(1) kV output pins: OUT1 – OUT6 ±4(2) kV Value Unit -40 to 150 °C (1) (2) HBM according to MIL 883C, Methode 3015.7 or EIA/JESD22-A114-A HBM with all unzapped pins grounded THERMAL DATA Symbol Parameter Operating junction temperature: Tj Operating Junction Temperature Temperature warning and thermal shutdown: Symbol TjTW ON Parameter Temperature Warning Threshold Junction Temperature TjTW OFF Temperature Warning Threshold Junction Temperature Min. Tj increasing Tj decreasing Max. Unit 150 °C 120 TjTW HYS Temperature Warning Hysteresis °C 10 TjSD ON Thermal Shutdown Threshold Junction Temperature Tj increasing TjSD OFF Thermal Shutdown Threshold Junction Temperature Tj decreasing TjSD HYS Thermal Shutdown Hysteresis Typ. K 180 150 °C °C 10 K 5/20 L9949 Figure 2. Thermal Data of Package PowerSO20 Z th(j-a) Zth (˚C/W) 10 diss. area dimensions 1x1 sq. mm 2x2 sq. mm 3x3 sq. mm silicon diss. area 1 0.1 4x4 sq. mm 5x5 sq. mm 0.001 0.01 0.1 die size 6x6 sq. mm mounted on standard board Tamb = 20˚C still air dissipated power 1 W - single pulse diss. area located in a corner 1 Time (s) 10 100 1000 ELECTRICAL CHARACTERISTCS VS = 8 to 16 V, VCC = 4.5 to 5.5 V, Tj = -40 to 150 °C, unless otherwise specified. The voltages are refered to GND and currents are assumed positive, when the current flows into the pin. Symbol Parameter Test Condition Min. Typ. Max. Unit 28 V Supply VS Operating Supply Voltage Range 7 IS DC Supply Current active mode, VS = 16 V, VCC = 5.3 V, OUT1 - OUT6 floating 7 20 mA Quiescent Supply Current standby mode, VS = 16 V, VCC = 0 V, 6 12 µA Tj < 85 °C(1) OUT1 - OUT6 floating ICC DC Supply Current active mode, CSN = VCC, VS = 16 V; VCC = 5.3 V 1 2 mA Quiescent Supply Current standby mode, CSN = VCC, VS = 16V, VCC = 5.3V, 40 75 µA 50 90 µA Tj < 85 °C(1) OUT1 - OUT6 floating IS + ICC 6/20 Sum Supply Quiescent Current standby mode, CSN = VCC, VS = 16 V, VCC = 5.3 V, Tj < 85 °C OUT1 - OUT6 floating L9949 ELECTRICAL CHARACTERISTCS (continued) VS = 8 to 16 V, VCC = 4.5 to 5.5 V, Tj = -40 to 150 °C, unless otherwise specified. The voltages are refered to GND and currents are assumed positive, when the current flows into the pin. Symbol Parameter Test Condition Min. Typ. Max. Unit 7.6 V (1) Parameter is measured at -40°C and 25°C. Value for 85°C is guaranteed by design Over- and undervoltage detection VSUV ON VS UV-Threshold Voltage VS increasing VSUV OFF VS UV-Threshold Voltage VS decreasing VSUV hyst VS UV-hysteresis VSUV ON – VSUV OFF VSOV OFF VS OV-threshold voltage VS increasing VSOV ON VS OV-threshold voltage VS decreasing VS OV-hysteresis VSOV OFF – VSOV ON VSOV 6 V 0.6 V 22 18 V V 1 V hyst VVCC OFF Power-on-reset Threshold VCC increasing VVCC ON Power-on-reset Threshold VCC decreasing VVCC Power-on-reset Hysteresis VVCC OFF – VVCC ON 3.4 4.2 V 4 V 0.3 V hyst Current Monitor Output VCM Functional Voltage Range VCC = 5 V ICM,r Current Monitor Output Ratio: ICM / IOUT1,2,6 0 V ≤ VCM ≤ 4 V Current Monitor Accuracy 0V ≤ VCM ≤ 4V, ICM =50µA, 600 µA (FS=full scale=600µA) ICM acc 0 4 - 1 ---------------10000 4% + 1%FS V 8% + 2%FS Outputs: OUT1 - OUT6 RON OUT1 On-resistance to Supply or GND RON OUT2 On-resistance to Supply or GND VS = 13.5 V, Tj = 25 °C, IOUT1 = ± 3.0 A 150 mΩ VS = 13.5 V, Tj = 125 °C, IOUT1 = ± 3.0 A 225 mΩ VS = 8.0 V, Tj = 25 °C, IOUT1 = ± 3.0 A 180 mΩ VS = 13.5 V, Tj = 25 °C, IOUT2 = ± 3.0 A 150 mΩ VS = 13.5 V, Tj = 125 °C, IOUT2 = ± 3.0 A 225 mΩ VS = 8.0 V, Tj = 25 °C, IOUT2 = ± 3.0 A 180 mΩ 7/20 L9949 ELECTRICAL CHARACTERISTCS (continued) VS = 8 to 16 V, VCC = 4.5 to 5.5 V, Tj = -40 to 150 °C, unless otherwise specified. The voltages are refered to GND and currents are assumed positive, when the current flows into the pin. Symbol Parameter RON OUT3 On-resistance to Supply or GND RON OUT4 On-resistance to Supply or GND RON OUT5 On-resistance to Supply or GND RON OUT6 On-resistance to Supply Test Condition Min. Typ. Max. Unit VS = 13.5 V, Tj = 25 °C, IOUT3 = ± 0.8 A 800 mΩ VS = 13.5 V, Tj = 125 °C, IOUT3 = ± 0.8 A 1250 mΩ VS = 8.0 V, Tj = 25 °C, IOUT3 = ± 0.8 A 980 mΩ VS = 13.5 V, Tj = 25 °C, IOUT4 = ± 0.8 A 800 mΩ VS = 13.5 V, Tj = 125 °C, IOUT4 = ± 0.8 A 1250 mΩ VS = 8.0 V, Tj = 25 °C, IOUT4 = ± 0.8 A 980 mΩ VS = 13.5 V, Tj = 25 °C, IOUT5 = ± 0.8 A 800 mΩ VS = 13.5 V, Tj = 125 °C, IOUT5 = ± 0.8 A 1250 mΩ VS = 8.0 V, Tj = 25 °C, IOUT5 = ± 0.8 A 980 mΩ VS = 13.5 V, Tj = 25 °C, IOUT6 = - 2.5 A 100 mΩ VS = 13.5 V, Tj = 125 °C, IOUT6 = - 2.5 A 150 mΩ VS = 8.0 V, Tj = 25 °C, IOUT6 = - 2.5 A 120 mΩ |IOUT1| Output Current Limitation to Supply or GND sink and source, current ramp 6 10 A |IOUT2| Output Current Limitation to Supply or GND sink and source, current ramp 6 10 A |IOUT3| Output Current Limitation to Supply or GND sink and source, current ramp 1.6 2.5 A |IOUT4| Output Current Limitation to Supply or GND sink and source, current ramp 1.6 2.5 A |IOUT5| output current limitation to Supply or GND sink and source, current ramp 1.6 2.5 A |IOUT6| Output Current Limitation to GND source, current ramp 6.3 11 A source, switching into resistive load, go-nogo test 5.1 11 A |IOUT6/res| Output Current Limitation to GND switching into resistive load For details of the on-resistance (Ron over temperature) see the figures „Typical ron characteristics“ for the differential output stages (FIGURE 3, FIGURE 4, FIGURE 5) 8/20 L9949 Figure 3. TYPICAL RON CHARACTERISTICS OUT1,2 160 140 Ron [mOhm] 120 100 HS 13.5V HS 8V LS 13.5 LS 8V 80 60 40 20 0 -40 -20 0 20 40 60 80 100 120 TEMP [C] Figure 4. TYPICAL RON CHARACTERISTICS OUT3,4,5 1100 1000 900 Ron [mOhm] 800 700 600 HS 13.5V HS 8V LS 13.5 LS 8V 500 400 300 200 100 0 -40 -20 0 20 40 60 80 100 120 TEMP [C] 9/20 L9949 Figure 5. TYPICAL RON CHARACTERISTICS OUT6 110 100 90 Ron [mOhm] 80 70 60 HS 13.5V 50 HS 8V 40 30 20 10 0 -40 -20 0 20 40 60 80 100 120 TEMP [C] ELECTRICAL CHARACTERISTCS VS = 8 to 16 V, VCC = 4.5 to 5.5 V, Tj = -40 to 150 °C, unless otherwise specified. The voltages are refered to GND and currents are assumed positive, when the current flows into the pin. Symbol Parameter Test Condition Min. Typ. Max. Unit OUTPUTS: OUT1 - OUT6 td ON H Output Delay Time, Highside Driver On VS = 13,5 V corresponding low side driver is not active 20 40 80 µs td OFF H Output Delay Time, Highside Driver Off VS = 13,5 V 80 150 300 µs td ON L Output Delay Time, Lowside Driver On VS = 13,5 V corresponding highside driver is not active 20 40 80 µs td OFF L Output Delay Time, Lowside Driver Off VS = 13.5 V 80 150 300 µs tD HL Dead Time, Source to Sink td ON L (HS was on) - td OFF H 5 200 µs tD LH Dead Time, Sink to Source td ON H (LS was on) - td OFF L 5 200 µs IQLH Leakage Current Highside Drivers of OUT1-6 VOUT1-6 = 0 V, standby mode 0 2 5 µA -40 -15 0 µA 0 7 20 µA -40 -15 0 µA VOUT1-6 = 0 V, active mode IQLL Leakage Current Lowside Drivers of OUT1-5 VOUT1-5 = VS, standby mode VOUT1-5 = VS, active mode 10/20 L9949 ELECTRICAL CHARACTERISTCS (continued) VS = 8 to 16 V, VCC = 4.5 to 5.5 V, Tj = -40 to 150 °C, unless otherwise specified. The voltages are refered to GND and currents are assumed positive, when the current flows into the pin. Symbol Parameter Test Condition Min. Typ. Max. Unit OUTPUTS: OUT1 - OUT6 IOLD12 Open Load Detection Current of OUT1 and OUT2 80 160 320 mA IOLD345 Open load detection current of OUT3, OUT4 and OUT5 20 40 60 mA IOLD6 open load detection current of OUT6 60 160 320 mA tdOL minimum duration of open load condition to set the status bit 500 3000 µs tISC minimum duration of overcurrent condition to switch off the driver 10 100 µs dVOUT12/dt slew rate of OUT1 and OUT2 VS = 13.5 V, for highside driver: Iload = -3A, for lowside driver: Iload = 3A 0.1 0.2 0.4 V/µs dVOUT345/dt slew rate of OUT3, OUT4 and OUT5 VS = 13.5 V, for highside driver: Iload = -0.8A, for lowside driver: Iload = 0.8A 0.09 0.2 0.4 V/µs dVOUT6/dt slew rate of OUT6 VS = 13.5 V, Iload = -2.5A 0.1 0.2 0.4 V/µs Figure 6. Application Circuit Diagram VBAT *see comment below 5V STXXX VCC VS CM OUT1 M OUT2 L9949 OUT3 CSN OUT4 CLK M M OUT5 DI OUT6 DO GND *see comment below VCC CM0 CM1 VCC VS CM SS1 CSN SCK CLK M OUT2 L9949 OUT3 SS0 µC OUT1 OUT4 M M OUT5 MOSI DI MISO DO OUT6 GND *in case of an unexpected freewheeling condition (e.g. POR, TSD or OV event) capacitor value must be high enough to limit maximum Vs voltage of L9949 appl_n_wmf below absolute maximum ratings. 11/20 L9949 Figure 7. Functional Block Diagram CLK (pin 6) DO (pin 17) VS (pin8) CSN (pin 14) DI (pin 7) HS HS VS (pin5) OUT5 (pin4) Chargepump A-driver LS SPI LS A-driver HS OUT1 (pin9) VS (pin5) OUT4 (pin3) LS VS (pin8) Driver Interface Diagnostic Power-On-Reset HS B-driver LS VS (pin5) OUT3 (pin2) LS B-driver VS (pin13) HS Voltage and Current Reference HS A-driver LS VS (pin18) HS A-driver ESD Temperature Protection A-driver OUT2 (pin12) OUT6 (pin19) VS (pin18) VS (pin13) Current Monitor HS B-driver VCC HS B-driver LS ESD B-driver GND (pins 1,10,11,20) VCC (pin 15) CM (pin 16) VS (pins 5,8,13,18) FUNCTIONAL DESCRIPTION OF THE SPI Serial Peripheral Interface (SPI) This device uses a standard SPI to communicate with a microcontroller. The SPI can be driven by a microcontroller with its SPI peripheral running in either of the two following modes: CPOL = CPHA = 0 or CPOL = CPHA = 1. For these two modes, input data is sampled by the low to high transition of the clock CLK, and output data is changed from the high to low transition of CLK. The difference of these two modes is the standby polarity of the CLK. For CPOL = 0 the CLK remains low and for CPOL = 1 the CLK remains high. This device is not limited to microcontrollers with a build-in SPI. Only three CMOS-compatible output pins and one input pin will be needed to communicate with the device. A fault condition can be detected by setting CSN to low. If CSN = 0, the DO-pin will reflect the status bit 0 (fault condition) of the device which is a logical-or of all bits in the status registers 0 and 1. The microcontroller can poll the status of the device without the need of a full SPI-communication cycle. Note: In contrast to the SPI-standard the least significant bit (LSB) will be transfered first (see. FIGURE 8). Chip Select not (CSN) The input pin is used to select the serial interface of this device. When CSN is high, the output pin (DO) will be in high impedance state. A low signal will activate the output driver and a serial communication can be started. Serial Data In (DI) The input pin is used to transfer data serial into the device. The data applied to the DI will be sampled at the 12/20 L9949 rising edge of the CLK signal and shifted into an internal 16 bit shift register. At the rising edge of the CSN signal the contents of the shift register will be transfered to Data Input Register (see FIGURE 8). The SPI uses an internal 16 bit counter which will be reset at the rising edge of the CSN signal. Only the first 16 bits of the data input DI will be relevant. If more than 16 bits are transfered the trailing bits will be ignored. Serial Data Out (DO) The output driver is activated by a logical low level at the CSN input and will go from high impedance to a low or high level depending on the status bit 0 (fault condition). The first rising edge of the CLK input after a high to low transition of the CSN pin will transfer the content of the selected status register into the data out shift register. Each subsequent falling edge of the CLK will shift the next bit out. Serial Clock (CLK) The CLK input is used to synchronize the input and output serial bit streams. The data input (DI) is sampled at the rising edge of the CLK and the data output (DO) will change with the falling edge of the CLK signal (see FIGURE 8). Input Data Register After the rising edge of CSN the contents of the input shift register will be written to the input data register. Depending on bit 0 the contents of the selected status register will be transfered to DO during the current communication cycle. Bit 1-11 controls the behaviour of the corresponding driver. If bit 12 and bit 13 are zero, the device will go into the standby-mode. If at least one of both bits are one these bits will be used to control the current monitor multiplexer. Bit 14 selects the VS lockout mode. If this bit is set, an over- or undervoltage condition at the power supply VS will disable all driver stages until the status bit will be cleared by the microcontroller. Bit 15 is used to reset all status bits in both status registers. The bits in the status registers will be cleared after the current communication cycle (rising edge of CSN). Status Register This devices uses two status registers to store and to monitor the state of the device. Bit 0 is used as a fault bit and is a logical-NOR combination of all other bits in both status registers. The state of this bit can be polled by the microcontroller without the need of a full SPI-communication cycle (see FIGURE 13). If one of the overcurrent bits is set, the corresponding driver will be disabled. The microcontroller has to clear the overcurrent bit to enable the driver. If the thermal shutdown bit is set, all drivers will go into a high impedance state. Again the microcontroller has to clear the bit to enable the drivers. The behaviour of the device in case of an over- or undervoltage condition will depend on the VS lockout bit (bit 14) in the input data register. If bit 14 is cleared, the device will reactivate the drivers if the power supply VS returns to normal operating range. In this case no interaction from the microcontroller is needed. Test Mode Due to the current limitations of a single bond wire the output stages OUT1, 2 and 6 need two bond wires in parallel. For the full output current driving capability it is necessary to check that both bond wires are connected correctly to the lead frame. Therefore the drivers and DMOS-transistors of the outputs OUT1, 2 and 6 are splitted into two independet stages, one for each bond wire (see FIGURE 6.4). In normal operating mode the splitted outputs are connected in parallel. In the test mode bit 5 and 6 of the input data register select the A-driver, bit 7 and 8 the B-driver. If all four bits (5 - 8) are switched to high level, no driver will be activated. For all combinations beside both high of bit 5 and 6 or bit 7 and 8 the output stages OUT3 and OUT4 are controlled like in normal operating mode. In any case the output stages are protected against shoot through current. Furthermore the inputs CLK and DI are connected by an OR to the output DO for testing the threshold voltages and the hysteresis. The input CLK can be tested by clamping the input DI to low level and vice versa. 13/20 L9949 SPI Interface – Input Data and Status Register Input Data Register BIT Status Register Function BIT Function Register 0 Register 1 15 High level reset all bits in selected status register 15 always H always H 14 VS under- / overvoltage lockout bit 14 VS overvoltage not used – set to L 13 Control bits for standby mode and Current monitor multiplexer 13 VS undervoltage chargepump off 12 bit13 bit12 function 12 Temperature shutdown Temperature warning 0 0 standby mode 11 0 1 OUT1 OUT6 – HS driver overcurrent OUT6 – HS driver open load 1 0 OUT2 10 1 1 OUT6 OUT5 – HS driver overcurrent OUT5 – HS driver open load 11 OUT6 – HS driver on/off (1) 9 OUT5 – LS driver overcurrent OUT5 – LS driver open load 10 OUT5 – HS driver on/off (1) 8 OUT4 – HS driver overcurrent OUT4 – HS driver open load 9 OUT5 – LS driver on/off (1) 7 OUT4 – LS driver overcurrent OUT4 – LS driver open load 8 OUT4 – HS driver on/off 5(1) 6 OUT3 – HS driver overcurrent OUT3 – HS driver open load 5 OUT3 – LS driver overcurrent OUT3 – LS driver open load 4 OUT2 – HS driver overcurrent OUT2 – HS driver open load 3 OUT2 – LS driver overcurrent OUT2 – LS driver open load 7 6 5 OUT4 – LS driver on/off 5(1) OUT3 – HS driver on/off 5(1) OUT3 – LS driver on/off 5(1) test mode bit 8 bit 7 1 1 B-driver is active test mode bit 6 bit 5 1 1 A-driver is active 4 OUT2 – HS driver on/off 51 2 OUT1 – HS driver overcurrent OUT1 – HS driver open load 3 OUT2 – LS driver on/off 1 1 OUT1 – LS driver overcurrent OUT1 – LS driver open load 2 OUT1 – HS driver on/off 1 0 no fault condition (2) 1 OUT1 – LS driver on/off 1 0 Status register select bit H = on; L = off; HS = highside; LS = lowside L: status register 0; H: status register 1 (1) (2) 14/20 If the bits of HS- and LS-driver of the same output stage are high, the internal logic prevents that both drivers of this output stage can be switched on simultaneously in order to avoid a high internal current from V S to GND. A logical NOR-combination of all bits 1 to 14 in both status registers. This bit can be polled by the micro-controller without the need of the full SPI communication (see Figure 13). A broken VCC-connection of the L9949 can be detected by the microcontroller, bec ause all 15 bits low or high is not a valid frame. L9949 SPI INTERFACE ELECTRICAL CHARACTERISTCS VS = 8 to 16 V, VCC = 4.5 to 5.5 V, Tj = -40 to 150 °C, unless otherwise specified. The voltages are refered to GND and currents are assumed positive, when the current flows into the pin. Symbol Parameter Test Condition Min. Typ. Max. Unit Switching from standby to active mode. Time until output drivers are enabled after CSN going to high. 200 µs 1.5 V Delay time from standby to active mode tset Delay Time Inputs: CSN, CLK and DI VINL Input Low Level VCC = 5 V VINH Input High Level VCC = 5 V 3.5 V VINHyst Input Hystersis VCC = 5 V 0.5 V ICSNin Pull Up Current at input CSN VCSN = 3.5 V -50 -25 -10 µA ICLK in Pull Down Current at input CLK VCLK = 1.5 V 10 25 50 µA IDI in Pull Down Current at input DI VDI = 1.5 V 10 25 50 µA Cin(1) Input Capacitance at input CSN or CLK 0 V < VCC < 5.5 V 10 15 pF DI timing (see Fig. 9 )(2) tCLK Clock Period VCC = 5 V 1000 ns tCLKH Clock High Time VCC = 5 V 400 ns tCLKL Clock Low Time VCC = 5 V 400 ns tset CSN CSN setup time, CSN low before rising edge of CLK VCC = 5 V 400 ns tset CLK CLK setup time, CLK high before rising edge of CSN VCC = 5 V 400 ns tset DI DI setup time VCC = 5 V 200 ns thold DI DI hold time VCC = 5 V 200 ns tr-in Rise Time of Input Signal DI, CLK, CSN VCC = 5 V 100 ns tf-in Fall Time of Input Signal DI, CLK, CSN VCC = 5 V 100 ns VDOL Output Low Level VCC = 5 V, ID = -4 mA 0.4 V VDOH Output High Level VCC = 5 V, ID = -4 mA VCC -1.3 VCC = 5 V, ID = -200 µA; Tj = 25°C VCC -0.8 DO 0.2 VCC -1.0 V V 15/20 L9949 SPI INTERFACE ELECTRICAL CHARACTERISTCS (continued) VS = 8 to 16 V, VCC = 4.5 to 5.5 V, Tj = -40 to 150 °C, unless otherwise specified. The voltages are refered to GND and currents are assumed positive, when the current flows into the pin. Symbol Parameter Test Condition Min. Typ. Max. Unit 10 µA IDOLK Tristate Leakage Current VCSN = VCC, 0 V < VDO < VCC -10 CDO Tristate Input Capacitance VCSN = VCC, 0 V < VCC < 5.5 V 10 15 pF DO timing (see Figg. 10 & 11) tr DO DO Rise Time CL = 100 pF, Iload = -1mA 50 100 ns tf DO Data Out Fall Time CL = 100 pF, Iload = 1mA 50 100 ns ten DO tri L DO Enable Time from tristate to low level CL = 100 pF, Iload = 1mA pull-up load to VCC 80 250 ns ten DO L tri DO Disable Time from low level totristate CL = 100 pF, Iload = 4mA pull-up load to VCC 200 400 ns ten DO tri H DO Enable Time from tristate to high level CL = 100 pF, Iload = -1mA pull-down load to GND 80 250 ns DO Disable Time from high level totristate CL = 100 pF, Iload = -4mA ppull-down load to GND 200 400 ns DO Delay Time VDO < 0.3 VCC, VDO > 0.7 VCC, CL = 100 pF 50 250 ns ten DO H tri td DO (1) (2) Value of input capacity is not measured in production test. Parameter guarenteed by design. DI timing parameters tested in production by a passed/failed test: Tj=-40°C/+25°C: SPI communication @2MHz Tj=+125°C: SPI communication @1.25MHz Figure 8. SPI-Interface - Transfer Timing Diagram CSN high to low: DO enabled CSN time CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 time DI: data will be accepted on the rising edge of CLK signal actual data DI 0 1 2 3 4 5 6 7 8 new data l 9 10 11 12 13 14 15 0 1 time DO: data will change on the falling edge of CLK signal status information DO 0 1 2 3 fault bit e.g.OUT1 4 5 6 7 8 9 10 11 12 13 14 15 0 time CSN low to high: actual data is transfered to output power switches old data 1 actual data time 16/20 L9949 Figure 9. SPI-interface - Input Timing 0.8 V CC CSN 0.2 V CC tset CSN tset CLK tCLKH 0.8 V CC CLK 0.2 V CC tset DI thold DI Valid DI tCLKL 0.8 V CC Valid 0.2 V CC Figure 10. Data Out Valid Data Delay Time and Valid Time tf in tr in 0.8 V CC 0.5 V CC 0.2 V CC CLK tr DO DO (low to high) 0.7 V CC 0.3 V CC td DO tf DO 0.7 V CC DO (high to low) 0.3 V CC Figure 11. SPI-Interface - Data Out Enable and Disable Time tf in t r in 0.8 V CC 50% 0.2 V CC CSN DO pull-up load to VCC CL =100pF 50% ten DO tri L t dis DO L tri DO pull-down load to GND CL =100pF 50% ten DO tri H t dis DO H tri 17/20 L9949 Figure 12. SPI-Interface - Driver Turn On/Off Timing CSN low to high: data fro m shi ft register is transferred to output power switches t t r in f in 80% 50% 20% CSN td OFF output current of a driver ON state OFF state 80% 50% 20% t OFF t dON t output current of a driver ON OFF state 80% ON state 50% 20% Figure 13. SPI-Interface - Timing of Status Bit 0 (Fault Condition) CSN high to low and CLK stays low: status information of data bit 0 (fault condition) is transfered to Data Out CSN time CLK time DI time Data In: data is not accepted DO 0time Data Out: status information of data bit 0 (fault condition) will stay as long as CSN is low 18/20 L9949 DIM. mm MIN. TYP. A a1 inch MAX. MIN. TYP. 3.6 0.1 0.142 0.3 a2 0.004 0.012 3.3 0.130 a3 0 0.1 0.000 0.004 b 0.4 0.53 0.016 0.021 0.013 c 0.23 0.32 0.009 D (1) 15.8 16 0.622 0.630 D1 9.4 9.8 0.370 0.386 E 13.9 14.5 0.547 0.570 e 1.27 e3 11.43 E1 (1) 10.9 0.450 0.429 0.437 2.9 0.114 E3 5.8 6.2 0.228 0.244 G 0 0.1 0.000 0.004 H 15.5 15.9 0.610 h L 0.626 1.1 0.8 JEDEC MO-166 0.043 1.1 0.031 N 8˚ (typ.) S 8˚ (max.) T Weight: 1.9gr 0.050 11.1 E2 OUTLINE AND MECHANICAL DATA MAX. 10 0.043 0.394 PowerSO20 (1) “D and E1” do not include mold flash or protusions. - Mold flash or protusions shall not exceed 0.15mm (0.006”) - Critical dimensions: “E”, “G” and “a3”. N R N a2 b A e DETAIL A c a1 DETAIL B E e3 H DETAIL A lead D slug a3 DETAIL B 20 11 0.35 Gage Plane -C- S SEATING PLANE L G E2 E1 BOTTOM VIEW C (COPLANARITY) T E3 1 h x 45 10 PSO20MEC D1 0056635 19/20 L9949 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. 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