ATMEL AT90SC9608RT

Features
General
• High-performance, Low-power secureAVR™ RISC Architecture
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– 135 Powerful Instructions (Most Executed in a Single Clock Cycle)
Low Power Idle and Power-down Modes
Bond Pad Locations Conforming to ISO 7816-2
ESD Protection to ± 6000V
Operating Ranges: 1.62 to 5.5V
Compliant with GSM, 3GPP and EMV 2000 Specifications; PC Industry Compatible
Available in Wafers, Modules, and Industry-standard Packages
Memory
• 96K Bytes of ROM Program Memory plus 32K Bytes of ROM with specific access
• 8K Bytes of EEPROM, Including 128 OTP Bytes and 384-byte Bit-addressable Area
– 1 to 64-byte Program / Erase
– 2 ms Program / 2 ms Erase
– Typically More than 500,000 Write/Erase Cycles at a Temperature of 25oC
– 10 Years Data Retention
• 4K Bytes of RAM
Peripherals
• One ISO 7816 Controller
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Secure
Microcontroller
for Smart Cards
AT90SC
9608RT
Summary
– Up to 625 kbps at 5 MHz
– Compliant with T=0 and T=1 Protocols
One I/O Port
Programmable Internal Oscillator (up to 20 MHz for Internal CPU Clock)
Two 16-bit Timers
Random Number Generator (RNG)
2-level, 7-vector Interrupt Controller
Hardware DES and Triple DES DPA Resistant
Checksum Accelerator
CRC 16 & 32 Engine (Compliant with ISO/IEC 3309)
Security
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Dedicated Hardware for Protection Against SPA/DPA Attacks
Advanced Protection Against Physical Attack, Including Active Shield
Environmental Protection Systems
Voltage Monitor
Frequency Monitor
Temperature Monitor
Light Protection
Secure Memory Management/Access Protection (Supervisor Mode)
Certification
• EAL4+
• VISA
• CAST
6554AS–SPD–15May07
Note: This is a summary document. A complete document will be
available under NDA. For more information, please contact your
local Atmel sales office.
Development Tools
• Voyager Emulation Platform (ATV4) to Support Software Development
• IAR Embedded Workbench® V3.20 Debugger or Atmel’s AVR Studio® Version 4.07 or Above
• Software Libraries and Application Notes
Description
The AT90SC9608RT is a low-power, high-performance, 8/16-bit microcontroller with ROM program memory and EEPROM
data memory, based on the secureAVR RISC architecture. By executing powerful instructions in a single clock cycle, the
AT90SC9608RT achieves throughputs close to 1 MIPS per MHz. Its Harvard architecture includes 32 general purpose
working registers directly connected to the ALU, allowing two independent registers to be accessed in one single instruction executed in one clock cycle.
The AT90SC9608RT uses the secureAVR that allows the linear addressing of up to 8M bytes of code and up to 16M bytes
of data as well as a number of new functional and security features.
The AT90SC9608RT includes 8K bytes of Atmel’s high density, non volatile memory.
Additional security features include power and frequency protection logic, logical scrambling on program data and
addresses, Power Analysis countermeasures and memory accesses controlled by a supervisor mode.
Figure 1 shows the AT90SC9608RT secureAVR RISC Architecture.
Figure 1. AT90SC9608RT secureAVR RISC Architecture
Data Bus
8-bit
OTP
Access
Control
RNG
EEPROM
User Memory
PC
16
Instruction
Register
Interrupt
Unit
X
Access
Control
Y
Z
8
8
16
Instruction
Decoder
16
Control
Lines
ALU
GND
VCC
RAM
Data Memory
General
Purpose
Registers
Program
Memory
CLK
Secure
Control
ISO 7816
Controller
ISO 7816
I/O Port 0
IN/OUT0
Timer
Reset
Circuit
8
RST
DES
Status
Register
DPA Counter
measures
CRC and
Checksum
Accelerator
2
AT90SC9608RT
6554AS–SPD–15May07
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