Features • Write Protect Pin for Hardware Data Protection – Utilizes Different Array Protection Compared to the AT24C02B • Low-voltage and Standard-voltage Operation – 1.8 (VCC = 1.8V to 5.5V) Internally Organized 256 x 8 (2K) Two-wire Serial Interface Schmitt Trigger, Filtered Inputs for Noise Suppression Bidirectional Data Transfer Protocol 1 MHz (5V) and 400 kHz (1.8V, 2.5V, 2.7V) Clock Rate 8-byte Page Partial Page Writes Allowed Self-timed Write Cycle (5 ms Max) High Reliability – Endurance: One Million Write Cycles – Data Retention: 100 Years • 8-lead PDIP, 8-lead JEDEC SOIC and 8-lead TSSOP Packages • Die Sales: Wafer Form, Waffle Pack, and Bumped Wafers • • • • • • • • • Two-wire Serial EEPROM 2K (256 x 8) AT24HC02B Description The AT24HC02B provides 2048 bits of serial electrically erasable and programmable read-only memory (EEPROM) organized as 256 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and lowvoltage operation are essential. The AT24HC02B is available in space-saving 8-lead PDIP, 8-lead JEDEC SOIC and 8-lead TSSOP packages and is accessed via a two-wire serial interface. In addition, the entire family is available in 1.8V (1.8V to 5.5V) version. Table 1. Pin Configuration Pin Name Function A0–A2 Address Inputs SDA Serial Data SCL Serial Clock Input WP Write Protect NC No-connect 8-lead TSSOP A0 A1 A2 GND 1 2 3 4 8 7 6 5 VCC WP SCL SDA 8-lead PDIP A0 A1 A2 GND 1 2 3 4 8 7 6 5 VCC WP SCL SDA 8-lead SOIC A0 A1 A2 GND 1 2 3 4 8 7 6 5 VCC WP SCL SDA Rev. 5134A–SEEPR–9/05 1 Absolute Maximum Ratings* *NOTICE: Operating Temperature........................................−40°C to +85°C Storage Temperature .........................................−65°C to +150°C Voltage on Any Pin with Respect to Ground ........................................ −1.0V to +7.0V Maximum Operating Voltage .......................................... 6.25V Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Output Current........................................................ 5.0 mA Figure 1. Block Diagram START STOP LOGIC Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open collector devices. DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address inputs that must be hardwired for the AT24HC02B. As many as eight 2K devices may be addressed on a single bus system. (Device addressing is discussed in detail under Device Addressing, page 8). 2 AT24HC02B 5134A–SEEPR–9/05 AT24HC02B WRITE PROTECT (WP): The AT24HC02B has a WP pin that provides hardware data protection. The WP pin allows normal read/write operations when connected to ground (GND). When the WP pin is connected to VCC, the write protection feature is enabled and operates as shown. Table 2. Write Protect Part of the Array Protected WP Pin Status Memory Organization 24HC02B At VCC Upper Half (1K) Array At GND Normal Read/Write Operations AT24HC02B, 2K SERIAL EEPROM: The 2K is internally organized with 32 pages of 8 bytes each. Random word addressing requires an 8-bit data word address. Table 3. Pin Capacitance(1) Applicable over recommended operating range from TAI = 25°C, f = 1.0 MHz, VCC = +1.8V Symbol Test Condition CI/O CIN Note: Max Units Conditions Input/Output Capacitance (SDA) 8 pF VI/O = 0V Input Capacitance (A0, A1, A2, SCL) 6 pF VIN = 0V 1. This parameter is characterized and is not 100% tested. 3 5134A–SEEPR–9/05 Table 4. DC Characteristics Applicable over recommended operating range from: TAI = −40°C to +85°C, VCC = +1.8V to +5.5V (unless otherwise noted) Symbol Parameter VCC1 Supply Voltage VCC2 Max Units 1.8 5.5 V Supply Voltage 2.5 5.5 V VCC3 Supply Voltage 2.7 5.5 V VCC4 Supply Voltage 4.5 5.5 V ICC Supply Current VCC = 5.0V READ at 100 kHz 0.4 1.0 mA ICC Supply Current VCC = 5.0V WRITE at 100 kHz 2.0 3.0 mA ISB1 Standby Current VCC = 1.8V VIN = VCC or VSS 0.6 3.0 µA ISB2 Standby Current VCC = 2.5V VIN = VCC or VSS 1.4 4.0 µA ISB3 Standby Current VCC = 2.7V VIN = VCC or VSS 1.6 4.0 µA ISB4 Standby Current VCC = 5.0V VIN = VCC or VSS 8.0 18.0 µA ILI Input Leakage Current VIN = VCC or VSS 0.10 3.0 µA ILO Output Leakage Current VOUT = VCC or VSS 0.05 3.0 µA −0.6 VCC x 0.3 V VCC x 0.7 VCC + 0.5 V VIL Input Low Level Test Condition (1) (1) Min Typ VIH Input High Level VOL2 Output Low Level VCC = 3.0V IOL = 2.1 mA 0.4 V VOL1 Output Low Level VCC = 1.8V IOL = 0.15 mA 0.2 V Note: 4 1. VIL min and VIH max are reference only and are not tested. AT24HC02B 5134A–SEEPR–9/05 AT24HC02B Table 5. AC Characteristics Applicable over recommended operating range from TAI = –40°C to +85°C, VCC = +1.8V to +5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted) 1.8, 2.5, 2.7 Symbol Parameter fSCL Clock Frequency, SCL tLOW Clock Pulse Width Low 1.2 0.4 µs tHIGH Clock Pulse Width High 0.6 0.4 µs tI Noise Suppression Time tAA Clock Low to Data Out Valid 0.1 tBUF Time the bus must be free before a new transmission can start 1.2 0.5 µs tHD.STA Start Hold Time 0.6 0.25 µs tSU.STA Start Setup Time 0.6 0.25 µs tHD.DAT Data In Hold Time 0 0 µs tSU.DAT Data In Setup Time 100 100 ns tR Min Inputs Rise Time Max 5.0-volt Min 400 50 (1) (1) 0.9 0.05 Max Units 1000 kHz 40 ns 0.55 µs 0.3 0.3 µs 300 100 ns tF Inputs Fall Time tSU.STO Stop Setup Time 0.6 .25 µs tDH Data Out Hold Time 50 50 ns Write Cycle Time tWR (1) Endurance Note: 5.0V, 25°C, Byte Mode 5 1M 5 ms Write Cycles 1. This parameter is ensured by characterization only. 5 5134A–SEEPR–9/05 Device Operation CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (see Figure 2). Data changes during SCL high periods will indicate a start or stop condition as defined below. Figure 2. Data Validity START CONDITION: A high-to-low transition of SDA with SCL high is a start condition that must precede any other command (see Figure 3). Figure 3. Start and Stop Definition STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (see Figure 3). ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. . The EEPROM sends a “0” to acknowledge that it has received each word. This happens during the ninth clock cycle. STANDBY MODE: The AT24HC02B features a low-power standby mode that is enabled: (a) upon power-up and (b) after the receipt of the Stop bit and the completion of any internal operations. MEMORY RESET: After an interruption in protocol, power loss or system reset, any two-wire part can be reset by following these steps: 6 AT24HC02B 5134A–SEEPR–9/05 AT24HC02B 1. Clock up to 9 cycles 2. Look for SDA high in each cycle while SCL is high 3. Create a start condition as SDA is high. Figure 4. Bus Timing Figure 5. Write Cycle Timing SCL SDA 8th BIT ACK WORDn (1) twr STOP CONDITION Notes: START CONDITION 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. 7 5134A–SEEPR–9/05 Figure 6. Output Acknowledge Device Addressing The 2K EEPROM device requires an 8-bit device address word following a start condition to enable the chip for a read or write operation, as shown in Figure 7. Figure 7. Device Address 2K 1 MSB 0 1 0 A2 A1 A0 R/W LSB The device address word consists of a mandatory “1”, “0” sequence for the first four most significant bits as shown. This is common to all the EEPROM devices. The next three bits are the A2, A1 and A0 device address bits for the 2K EEPROM. These three bits must compare to their corresponding hardwired input pins. The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high, and a write operation is initiated if this bit is low. Upon a compare of the device address, the EEPROM will output a “0”. If a compare is not made, the chip will return to a standby state. Write Operations 8 BYTE WRITE: A write operation requires an 8-bit data word address following the device address word and acknowledgement. Upon receipt of this address, the EEPROM will again respond with a “0” and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a “0” and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time, the EEPROM enters an internally-timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle, and the EEPROM will not respond until the write is complete, see Figure 8 on page 9. AT24HC02B 5134A–SEEPR–9/05 AT24HC02B Figure 8. Byte Write S T A R T DEVICE ADDRESS W R I T E WORD ADDRESS S T O P DATA SDA LINE M S B L R A M S / C S BW K B L A S C B K A C K PAGE WRITE: The 2K EEPROM is capable of an 8-byte page write. A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to seven (2K) more data words. The EEPROM will respond with a “0” after each data word received. The microcontroller must terminate the page write sequence with a stop condition, see Figure 9. Figure 9. Page Write S T A R T DEVICE ADDRESS W R I T E WORD ADDRESS (n) DATA (n) DATA (n + 1) S T O P DATA (n + x) SDA LINE M S B L R A S / C BW K A C K A C K A C K A C K The data word address lower three (2K) bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than eight (2K) data words are transmitted to the EEPROM, the data word address will “roll over” and previous data will be overwritten. ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a “0” allowing the read or write sequence to continue. 9 5134A–SEEPR–9/05 Read Operations Read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to “1”. There are three read operations: current address read, random address read and sequential read. CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address “roll over” during read is from the last byte of the last memory page to the first byte of the first page. The address “roll over” during write is from the last byte of the current page to the first byte of the same page. Once the device address with the read/write select bit set to “1” is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input “0” but does generate a following stop condition, see Figure 10. Figure 10. Current Address Read S T A R T R E A D DEVICE ADDRESS S T O P SDA LINE L R A S / C BW K M S B N O DATA A C K RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a “0” but does generate a following stop condition, see Figure 11. Figure 11. Random Read S T A R T DEVICE ADDRESS W R I T E S T A R T WORD ADDRESS n S T O P R E A D DEVICE ADDRESS SDA LINE M S B L R A M S / C S BW K B L A S C B K M S B L S B A C K DATA n N O A C K DUMMY WRITE SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will “roll over” and the sequen- 10 AT24HC02B 5134A–SEEPR–9/05 AT24HC02B tial read will continue. The sequential read operation is terminated when the microcontroller does not respond with a “0” but does generate a following stop condition, see Figure 12. Figure 12. Sequential Read 11 5134A–SEEPR–9/05 AT24HC02B Ordering Information(1) Ordering Code Package Operation Range 8P3 8S1 8A2 Lead-free/Halogen-free/ Industrial Temperature (−40°C to 85°C) Die Sale Industrial Temperature (−40°C to 85°C) (2) AT24HC02B-10PU-1.8 AT24HC02BN-10SU-1.8(2) AT24HC02B-10TU-1.8(2) AT24HC02B-W1.8-11(3) Notes: 1. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics table. 2. “U” designates Green Package + RoHS compliant 3. Available in waffle pack and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please contact Serial EEPROM Marketing. Package Type 8P3 8-pin, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8A2 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) Options −1.8 12 Low Voltage (1.8V to 5.5V) AT24HC02B 5134A–SEEPR–9/05 AT24HC02B Packaging Information 8P3 – PDIP E 1 E1 N Top View c eA End View COMMON DIMENSIONS (Unit of Measure = inches) D e D1 A2 A SYMBOL A b2 b3 b 4 PLCS Side View L NOM MAX NOTE – – 0.210 2 A2 0.115 0.130 0.195 b 0.014 0.018 0.022 5 b2 0.045 0.060 0.070 6 b3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 D 0.355 0.365 0.400 3 D1 0.005 – – 3 E 0.300 0.310 0.325 4 E1 0.240 0.250 0.280 3 e 0.100 BSC eA L Notes: MIN 0.300 BSC 0.115 0.130 4 0.150 2 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA, for additional information. 2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3. 3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch. 4. E and eA measured with the leads constrained to be perpendicular to datum. 5. Pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm). 01/09/02 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) DRAWING NO. REV. 8P3 B 13 5134A–SEEPR–9/05 8S1 – JEDEC SOIC C 1 E E1 L N ∅ Top View End View e B COMMON DIMENSIONS (Unit of Measure = mm) A A1 D Side View SYMBOL MIN NOM MAX A 1.35 – 1.75 A1 0.10 – 0.25 b 0.31 – 0.51 C 0.17 – 0.25 D 4.80 – 5.00 E1 3.81 – 3.99 E 5.79 – 6.20 e NOTE 1.27 BSC L 0.40 – 1.27 ∅ 0° – 8° Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. 10/7/03 R 14 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) DRAWING NO. 8S1 REV. B AT24HC02B 5134A–SEEPR–9/05 AT24HC02B 8A2 – TSSOP 3 2 1 Pin 1 indicator this corner E1 E L1 N L Top View End View COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A b D MIN NOM MAX NOTE 2.90 3.00 3.10 2, 5 3, 5 E e D A2 6.40 BSC E1 4.30 4.40 4.50 A – – 1.20 A2 0.80 1.00 1.05 b 0.19 – 0.30 e Side View L 0.65 BSC 0.45 L1 Notes: 4 0.60 0.75 1.00 REF 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07 mm. 5. Dimension D and E1 to be determined at Datum Plane H. 5/30/02 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 8A2, 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) DRAWING NO. 8A2 REV. B 15 5134A–SEEPR–9/05 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards 1150 East Cheyenne Mtn. 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