Features • • • • • • • • Low Voltage and Standard Voltage Operation: 2.7 (VCC = 2.7V to 5.5V) Internally Organized 128 x 8 Two-wire Serial Interface Bidirectional Data Transfer Protocol 1 MHz Compatibility 4-Byte Page Write Mode Self-Timed Write Cycle (5 ms max) High Reliability – Endurance: 1 Million Write Cycles – Data Retention: 100 Years • Automotive Grade and Lead-Free/Halogen-Free Devices Available • 8-lead JEDEC SOIC and 8-lead TSSOP Packages Description The AT24C11 provides 1024 bits of serial electrically erasable and programmable read only memory (EEPROM) organized as 128 words of 8 bits each. The device is optimized for use in many automotive applications where low power and low voltage operation are essential. The AT24C11 is available in space saving 8-lead JEDEC SOIC and 8-lead TSSOP packages and is accessed via a Two-wire serial interface. In addition, the entire family is available in 2.7V (2.7V to 5.5V). Table 1. Pin Configuration Pin Name Function NC No Connect SDA Serial Data SCL Serial Clock Input TEST Test Input (GND or VCC) 8-lead TSSOP NC NC NC GND 1 2 3 4 8 7 6 5 Two-wire Automotive Temperature Serial EEPROM 1K (128 x 8) AT24C11 8-lead SOIC VCC TEST SCL SDA NC NC NC GND 1 2 3 4 8 7 6 5 VCC TEST SCL SDA Rev. 5093D–SEEPR–2/07 1 Absolute Maximum Ratings* Operating Temperature..................................–55°C to +125°C Storage Temperature .....................................–65°C to +150°C Voltage on Any Pin with Respect to Ground .................................... –1.0V to +7.0V Maximum Operating Voltage .......................................... 6.25V DC Output Current........................................................ 5.0 mA *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Figure 1. Block Diagram 2 AT24C11 5093D–SEEPR–2/07 AT24C11 Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open collector devices. Memory Organization AT24C11, 1K SERIAL EEPROM: Internally organized with 32 pages of 4 bytes each. The 1K requires a 7-bit data word address for random word addressing. Table 2. Pin Capacitance Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +2.7V to +5.5V Symbol Test Condition Max Units Condition CI/O Input/Output Capacitance (SDA) 8 pF VI/O = 0V CIN Input Capacitance (A0, A1, A2, SCL) 6 pF VIN = 0V Table 3. DC Characteristics Applicable over recommended operating range from: TAE = –40°C to +125°C, VCC = +2.7V to +5.5V (unless otherwise noted) Symbol Parameter Max Units VCC1 Supply Voltage 2.7 5.5 V VCC2 Supply Voltage 4.5 5.5 V ICC Supply Current VCC = 5.0V READ at 100 kHz 0.4 1.0 mA ICC Supply Current VCC = 5.0V WRITE at 100 kHz 2.0 3.0 mA ISB1 Standby Current VCC = 1.8V VIN = VCC or VSS 0.6 3.0 µA ISB2 Standby Current VCC = 2.5V VIN = VCC or VSS 1.4 4.0 µA ISB3 Standby Current VCC = 2.7V VIN = VCC or VSS 1.6 4.0 µA ISB4 Standby Current VCC = 5.0V VIN = VCC or VSS 8.0 18.0 µA ILI Input Leakage Current VIN = VCC or VSS 0.10 3.0 µA ILO Output Leakage Current VOUT = VCC or VSS 0.05 3.0 µA –0.6 VCC × 0.3 V VCC × 0.7 VCC + 0.5 V VIL Test Condition (1) Input Low Level (1) Min Typ VIH Input High Level VOL2 Output Low Level VCC = 3.0V IOL = 2.1 mA 0.4 V VOL1 Output Low Level VCC = 1.8V IOL = 0.15 mA 0.2 V Note: 1. VIL min and VIH max are reference only and are not tested. 3 5093D–SEEPR–2/07 Table 4. AC Characteristics Applicable over recommended operating range from TA = –40°C to +125°C, VCC = +2.7V to +5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted) 2.7V, 5.0V Symbol Parameter fSCL Clock Frequency, SCL tLOW Clock Pulse Width Low 0.4 µs tHIGH Clock Pulse Width High 0.4 µs tAA Clock Low to Data Out Valid 0.05 tBUF Time the bus must be free before a new transmission can start(1) 0.5 µs tHD.STA Start Hold Time 0.25 µs tSU.STA Start Set-up Time 0.6 µs tHD.DAT Data In Hold Time 0 µs tSU.DAT Data In Set-up Time 100 ns tR Inputs Rise Time(1) 0.3 µs tF Inputs Fall Time(1) 100 ns tSU.STO Stop Set-up Time tDH Data Out Hold Time tWR Write Cycle Time Endurance(1) 5.0V, 25°C, Page Mode Note: 4 Min Max Units 1000 kHz 0.55 µs 0.25 µs 50 ns 5 1M ms Write Cycles 1. This parameter is ensured by characterization only. AT24C11 5093D–SEEPR–2/07 AT24C11 Device Operation CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (see Figure 4 on page 6). Data changes during SCL high periods will indicate a start or stop condition as defined below. START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (see Figure 5 on page 7). STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition which terminates all communications. After a read sequence, the stop command will place the EEPROM in a standby power mode (see Figure 5 on page 7). ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. Any device on the system bus receiving data (when communicating with the EEPROM) must pull the SDA bus low to acknowledge that it has successfully received each word. This must happen during the ninth clock cycle after each word received and after all other system devices have freed the SDA bus. The EEPROM will likewise acknowledge by pulling SDA low after receiving each address or data word (see Figure 6 on page 7). STANDBY MODE: The AT24C11 features a low power standby mode which is enabled: (a) upon power-up and (b) after the receipt of the STOP bit and the completion of any internal operations. MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2wire part can be reset by following these steps: (a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then (c) create a start condition as SDA is high. 5 5093D–SEEPR–2/07 Figure 2. Bus Timing SCL: Serial Clock, SDA: Serial Data I/O Figure 3. Write Cycle Timing SCL: Serial Clock, SDA: Serial Data I/O SCL SDA 8th BIT ACK WORDn twr STOP CONDITION Note: (1) START CONDITION 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. Figure 4. Data Validity 6 AT24C11 5093D–SEEPR–2/07 AT24C11 Figure 5. Start and Stop Definition Figure 6. Output Acknowledge 7 5093D–SEEPR–2/07 Write Operations BYTE WRITE: Following a start condition, a write operation requires a 7-bit data word address and a low write bit. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8bit data word, the EEPROM will output a zero and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally-timed write cycle to the nonvolatile memory. All inputs are disabled during this write cycle, tWR, and the EEPROM will not respond until the write is complete (see refer to Figure 7 on page 9). PAGE WRITE: The AT24C11 is capable of a 4-byte page write. A page write is initiated the same as a byte write but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to three more data words. The EEPROM will respond with a zero after each data word received. The microcontroller must terminate the page write sequence with a stop condition (see Figure 8 on page 9). The data word address lower 2 bits are internally incremented following the receipt of each data word. The higher five data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than four data words are transmitted to the EEPROM, the data word address will “roll over” and previous data will be overwritten. Access to 1 additional page is available upon request. ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a zero allowing the read or write sequence to continue. Read Operations Read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. There are two read operations: byte read and sequential read. BYTE READ: A byte read is initiated with a start condition followed by a 7-bit data word address and a high read bit. The AT24C11 will respond with an acknowledge and then serially output 8 data bits. The microcontroller does not respond with a zero but does generate a following stop condition (see Figure 9 on page 9). SEQUENTIAL READ: Sequential reads are initiated the same as a byte read. After the microcontroller receives an 8-bit data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will “roll over” and the sequential read will continue. The sequential read operation is terminated when the microcontroller does not respond with an input zero but does generate a following stop condition (see Figure 10 on page 9). 8 AT24C11 5093D–SEEPR–2/07 AT24C11 Figure 7. Byte Write Figure 8. Page Write Figure 9. Byte Read Figure 10. Sequential Read 9 5093D–SEEPR–2/07 AT24C11 Ordering Information Ordering Code Package AT24C11N-10SQ-2.7 AT24C11-10TQ-2.7 8S1 8A2 Operation Range Lead-free/Halogen-free/ Automotive Temperature (–40°C to 85°C) Package Type 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) Options –2.7 10 Low-Voltage (2.7V to 5.5V) AT24C11 5093D–SEEPR–2/07 AT24C11 8S1 – JEDEC SOIC C 1 E E1 L N ∅ Top View End View e B COMMON DIMENSIONS (Unit of Measure = mm) A A1 D Side View SYMBOL MIN NOM MAX A 1.35 – 1.75 A1 0.10 – 0.25 b 0.31 – 0.51 C 0.17 – 0.25 D 4.80 – 5.00 E1 3.81 – 3.99 E 5.79 – 6.20 e NOTE 1.27 BSC L 0.40 – 1.27 ∅ 0˚ – 8˚ Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. 10/7/03 R 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) DRAWING NO. 8S1 REV. B 11 5093D–SEEPR–2/07 8A2 – TSSOP 3 2 1 Pin 1 indicator this corner E1 E L1 N L Top View End View COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A b D MIN NOM MAX NOTE 2.90 3.00 3.10 2, 5 4.40 4.50 3, 5 E E1 e D A2 6.40 BSC 4.30 A – – 1.20 A2 0.80 1.00 1.05 b 0.19 – 0.30 e Side View L 0.65 BSC 0.45 L1 Notes: 0.60 0.75 1.00 REF 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07 mm. 5. Dimension D and E1 to be determined at Datum Plane H. 5/30/02 R 12 4 2325 Orchard Parkway San Jose, CA 95131 TITLE 8A2, 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) DRAWING NO. 8A2 REV. B AT24C11 5093D–SEEPR–2/07 AT24C11 Revision History Doc. Rev. Date Comments 5093D 1/2007 Removed PDIP package offering Removed PB parts 5093C 9/2006 Revision history implemented; Removed ‘Preliminary’ status from datasheet. 13 5093D–SEEPR–2/07 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards Zone Industrielle 13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00 Fax: (33) 4-42-53-60-01 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. 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