VIA Technologies Incorporated VT1616 6-Channel AC97 Codec with S/PDIF Features • • • • • • • • • • • • • • • Description AC’97 2.2 compliant codec VIA Technologies’ VT1616TM 20-bit ¦∆ audio codec conforms to the AC’97 2.2 and S/PDIF 20-bit, stereo ADC and 6-channel stereo DACs Output specifications. The VT1616 integrates 1 Hz resolution VSR on all channels Sample Rate Converters on all channels and can be Integrated IEC958 line driver for S/PDIF output adjusted in 1Hz increments. There is a provision in S/PDIF compressed digital or LPCM audio out hardware for down-mixing the 6 channels into Hardware downmix option to 2 channels stereo when only two end points are available. The ADC DC removal for removing recording white noise analog mixer circuitry integrates a stereo enhancement to provide a pleasing 3D surround 4-bit 3D stereo expansion for simulated surround sound effect for stereo media. This codec is 4 stereo, 2 mono analog line-level inputs designed with aggressive power management to Second line-level output with volume control achieve low power consumption. When used with a 3.3V analog supply, power consumption is further External Audio Amplifier Control reduced. The primary applications for this part are Low Power consumption mode desktop and portable personal computers Exceeds Microsoft® WHQL logo requirements multimedia subsystems. However, it is suitable for 3.3V digital, 3.3 or 5V analog power supply any system requiring 6-channel audio output for home theater systems at competitive prices. 48-pin LQFP small footprint package CENTER + LFE PCM OUT SRC DAC REAR SURROUND PCM OUT SRC DAC PC_BEEP PHONE VOL MUTE VOL MUTE VOL MUTE LFE/CENTER M U X Σ FRONT PCM OUT SRC VOL MUTE LINE VOL MUTE CD VOL MUTE VIDEO VOL MUTE AUX VOL MUTE VOL MUTE MIC1 MIC2 SYNC BIT_CLK SDATA_OUT SDATA_IN RESET# XTL_IN XTL_OUT M U X VOL DAC Σ Σ 3D M U X VOLUME /MUTE LNL/SR_OUT MASTER VOLUME LINE_OUT MONO VOLUME MONO_OUT Σ +20dB M U X AC’97 Digital Interface OSC MASTER INPUT VOLUME ADC SRC PCM IN S/PDIF_OUT Figure 1. Functional Block Diagram Revision 1.5, October 11, 2002 1 Data Sheet VT1616 6-Channel AC97 Codec with S/PDIF © VIA Technologies, Inc., 2000, 2001, 2002. All Rights Reserved. VIA TECHNOLOGIES PRODUCTS ARE NOT AUTHORIZED FOR, AND SHOULD NOT BE USED WITHIN, LIFE SUPPORT SYSTEMS OR NUCLEAR FACILTY APPLICATIONS WITHOUT THE SPECIFIC WRITTEN CONSENT OF VIA TECNOLOGIES, Inc. Life support systems are those intended to support or sustain life, and show failure to perform when used as directed can reasonably expect to result in personal injury or death. Nuclear facilities are those involved in the production, handling, use, storage, disposal, or any other activity involving fissionable materials or their waste products. The VIA Technologies logo is a trademark of VIA Technologies, Inc. All other trademarks referenced in this document are owned by their respective companies. VIA Technologies, Inc. believes the information contained herein to be correct at the time of the publication. The information is provided “AS IS” without warranty of any kind (expressed or implied). No responsibility is assumed by VIA Technologies, Inc. for the use of this information, nor infringements of patents or other rights of third parties. VIA Technologies, Inc. reserves the right to make changes at any time, without prior notice, to improve and supply the best possible product and is not responsible and does not assume any liability for misapplication or use outside the limits specified in this document. VIA Technologies provides no warranty for the use of its products and assumes no liability for errors contained in this document. Contact Information US Office 940 Mission Court Fremont, CA 94539 USA Tel: (510) 687-4600 Fax: (510) 687-4654 Web: www.viatech.com Revision 1.5, October 11, 2002 Taiwan Office 8th Floor, No. 533 Chung-Cheng Road, Hsien-Tien Taipei, Taiwan ROC Tel: 886 (2) 2218-5452 Fax: 886 (2) 2218-5453 Web: www.via.com.tw 2 Data Sheet SPDIF_OUT EAPD ID1 ID0 LFE_OUT CENTER_OUT AGND2 LNL/SR_OUT_R NC LNL/SR_OUT_L AVCC2 MONO_OUT 48 47 46 45 44 43 42 41 40 39 38 37 VT1616 6-Channel AC97 Codec with S/PDIF DVCC1 1 36 LINE_OUT_R XTL_IN 2 35 LINE_OUT_L XTL_OUT 3 34 NC DGND1 4 33 NC SDATA_OUT 5 32 CAP2 BIT_CLK 6 31 NC DGND2 7 30 AFLT2 SDATA_IN 8 29 AFLT1 DVCC2 9 28 VREF_OUT SYNC 10 27 VREF RESET# 11 26 AGND1 PC_BEEP 12 25 AVCC1 21 22 23 24 MIC1 MIC2 LINE_IN_L LINE_IN_R 18 CD_L 20 17 VIDEO_R CD_R 16 VIDEO_L 19 15 AUX_R CD_GND 14 AUX_L PHONE 13 VT1616 Figure 2. Pin Diagram - 48-Pin LQFP Revision 1.5, October 11, 2002 3 Data Sheet VT1616 6-Channel AC97 Codec with S/PDIF Table 1. Pin Description Pin # Symbol Type 1 DVCC1 P Digital Supply Voltage, 3.3V only 2 XTL_IN I 24.576 MHz Crystal or clock input 3 XTL_OUT O 24.576 MHz Crystal 4 DGND1 P Digital Ground 5 SDATA_OUT I AC’97 Serial Data Input Stream 6 BIT_CLK I/O 12.288 MHz Serial Data Clock 7 DGND2 P Digital Ground 8 SDATA_IN O AC’97 Serial Data Output Stream 9 DVCC2 P Digital Supply Voltage, 3.3V only 10 SYNC I 48 KHz Fixed Rate Sync Pulse 11 RESET# I AC’97 Master Reset 12 PC_BEEP I PC Speaker Beep Pass Through 13 PHONE I Telephony Subsystem Speakerphone 14 AUX_L I Auxiliary Audio Left Channel 15 AUX_R I Auxiliary Audio Right Channel 16 VIDEO_L I Video Audio Left Channel 17 VIDEO_R I Video Audio Right Channel 18 CD_L I CD Audio Left Channel 19 CD_GND I CD Audio Analog Ground 20 CD_R I CD Audio Right Channel 21 MIC1 I Desktop Microphone 22 MIC2 I Second Microphone 23 LINE_IN_L I Line In Left Channel 24 LINE_IN_R I Line In Right Channel 25 AVCC1 P Analog Supply Voltage, 5V or 3.3V 26 AGND1 P Analog Ground 27 VREF I Reference Voltage 28 VREF_OUT O Reference Voltage Output 29 AFLT1 O Left Channel Anti-Aliasing Filter Capacitor 30 AFLT2 O Right Channel Anti-Aliasing Filter Capacitor 31 NC – No Connect 32 CAP2 – ADC Reference Voltage Capacitor 33 NC – No Connect 34 NC – No Connect 35 LINE_OUT_L O Line Out Left Channel 36 LINE_OUT_R O Line Out Right Channel Revision 1.5, October 11, 2002 Description 4 Data Sheet VT1616 6-Channel AC97 Codec with S/PDIF Table 1. Pin Description (continued...) Pin # Symbol Type Description 37 MONO_OUT O Mono Output 38 AVCC2 P Analog Supply Voltage, 5V or 3.3V 39 LNL/SR_OUT_L O Alternate Left Line Level out or Rear Channel Left 40 NC – No Connect 41 LNL/SR_OUT_R O Alternate Right Line Level out or Rear Channel Right 42 AGND2 P Analog Ground 43 CENTER_OUT O Center Channel Output 44 LFE_OUT O Low Frequency Effects Output 45 ID0 I Multiple Codec Select (Internal pull-up). Please see Table 5. 46 ID1 I Multiple Codec Select (Internal pull-up). Please see Table 5. 47 EAPD O External Power Amplifier Power Down 48 SPDIF_OUT I/O PCM/Non-Audio Sony/Philips Digital I/F Output (Internal pull-up). If left floating, S/PDIF not implemented reported on 2Ah, bit 2 = “0” Note: The VT1616 supports +5V or +3.3V analog power supply. For best analog performance use a 5V analog supply. For maximum power savings use 3.3V for both analog and digital sections. You must use 3.3V as the digital supply. The digital I/Os are NOT 5V tolerant. Revision 1.5, October 11, 2002 5 Data Sheet VT1616 6-Channel AC97 Codec with S/PDIF 1 9 DVCC1 2 24.576MHz 22pF 3 DVCC2 25 Regulated power supply recommended for best analog performance 10µF 0.1µF 10µF 0.1µF 0.1µF 10µF 0.1µF 5V AVCC 10µF 3.3V DVCC 38 AVCC1 AVCC2 XTL_IN ID1 XTL_OUT ID0 46 Master Codec Select 45 22pF 1kΩ 1µF LINE_OUT_L 35 1µF 1nF 23 LINE INPUTS LINE LEVEL OUTPUTS 1µF 1kΩ 1µF 24 LINE_IN_R LINE_OUT_R 36 1µF 1nF 18 1kΩ 1µF 19 MONO_OUT CD_GND 37 MONO OUTPUT 1µF 1nF 20 16 LNL/SR_OUT_L VIDEO_L LNL/SR_OUT_R 39 41 Repeat circuits as above for the 4 surround channels 1µF 17 VT1616 VIDEO_R 1µF 14 AUXILIARY INPUTS CENTER_OUT AUX_L LFE_OUT 43 44 1µF 15 AUX_R EAPD 1µF 21 MIC1 IN MIC1 SPDIF_OUT MIC2 VREFOUT 1µF 22 MIC2 IN 1µF 13 PHONE VREF PHONE 47 28 27 32 SDATA_OUT SDATA_IN RESET# 0.1µF 10 6 5 8 11 SYNC AFLT2 BIT_CLK 10µF 30 270pF NPO SDATA_OUT SDATA_IN RESET# AFLT1 DC‘97 10µF CAP2 AVCC SYNC RCA coaxial S/PDIF PC_BEEP 2.7nF BIT_CLK 110Ω 0.1µF 12 4.7kΩ 220Ω 48 0.1µF 47kΩ PC BEEP 3.3V DVCC 47kΩ CD_R 1µF VIDEO INPUTS 47kΩ CD_L 1µF CD INPUTS 47kΩ LINE_IN_L DGND1 DGND2 4 7 AGND1 AGND2 26 42 29 270pF NPO Single point connection Board Analog Ground Board Digital Ground Figure 3. Typical Connection Diagram Revision 1.5, October 11, 2002 6 Data Sheet VT1616 6-Channel AC97 Codec with S/PDIF Register Map Index Register Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 – SE4 SE3 SE2 SE1 SE0 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 00h Reset 02h Stereo Output Volume Mute – – ML4 ML3 ML2 ML1 ML0 – – – MR4 MR3 MR2 MR1 MR0 04h Alt. Line Output Vol. Mute – – ML4 ML3 ML2 ML1 ML0 – – – MR4 MR3 MR2 MR1 MR0 06h Mono Output Volume Mute – – – – – – – – – – MM4 MM3 MM2 MM1 MM0 0Ah PC Beep Volume Mute – – – – – – – – – – PV3 PV2 PV1 PV0 0Ch Phone Volume Mute – – – – – – – – – – GN4 GN3 GN2 GN1 GN0 0Eh Mic In Volume Mute – – – – – – – – 20dB – GN4 GN3 GN2 GN1 GN0 10h Line In Volume Mute – – GL4 GL3 GL2 GL1 GL0 – – – GR4 GR3 GR2 GR1 GR0 12h CD In Volume Mute – – GL4 GL3 GL2 GL1 GL0 – – – GR4 GR3 GR2 GR1 GR0 14h Video In Volume Mute – – GL4 GL3 GL2 GL1 GL0 – – – GR4 GR3 GR2 GR1 GR0 16h Aux In Volume Mute – – GL4 GL3 GL2 GL1 GL0 – – – GR4 GR3 GR2 GR1 GR0 18h PCM Out volume Mute – – GL4 GL3 GL2 GL1 GL0 – – – GR4 GR3 GR2 GR1 GR0 1Ah Record Select – – – – – SL2 SL1 SL0 – – – – – SR2 SR1 SR0 1Ch Record Gain Mute – – – GL3 GL2 GL1 GL0 – – – – GR3 GR2 GR1 GR0 20h General Purpose – – 3D – – – MIX MS LPBK – – – – – – – 22h 3D Control – – – – – – – – – – – – DP3 DP2 DP1 DP0 26h Power Down & Status PR5 PR4 PR3 PR2 PR1 PR0 – – – – REF ANL DAC ADC 28h Extended Audio ID – – – LDAC SDAC CDAC – – – SPDIF – VRA 2Ah Ext. Audio Stat/Control – LDAC SDAC CDAC SSA1 SSA0 – SPDIF – VRA 2Ch PCM Front DAC Rate SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 2Eh Surround DAC Rate SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 30h PCM LFE DAC Rate SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 32h PCM LR ADC Rate SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 36h LFE/Center Volume Mute – – LFE4 LFE3 LFE2 LFE1 LFE0 Mute – – CNT4 CNT3 CNT2 CNT1 CNT0 38h Surround Volume Mute – – LSR4 LSR3 LSR2 LSR1 LSR0 Mute – – RSR4 RSR3 RSR2 RSR1 RSR0 3Ah S/PDIF Control V – ... ... ... ... EAPD PR6 ID1 ID0 – – – – PRK PRJ SSR1 SSR0 ... ... PRI SPCV – L CC6 CC5 CC4 CC3 CC2 CC1 CC0 PRE COPY /PCM PRO ... ... ... ... ... ... ... ... ... ... ... ... 5Ah Test Control Register LVL Res. Res. LCTF STF BPDC DC Res. Res. Res. Res. Res. IB1 IB0 Res. Res. 5Ch Special Control Reg. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LBE ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 7Ah Vendor Reserved – – – – – – – – – – – – – – – – 7Ch Vendor ID1 F7 F6 F5 F4 F3 F2 F1 F0 S7 S6 S5 S4 S3 S2 S1 S0 7Eh Vendor ID2 T7 T6 T5 T4 T3 T2 T1 T0 ... REV7 REV6 REV5 REV4 REV3 REV2 REV1 REV0 In compliance with the AC ‘97 rev. 2.2 specification, all reserved or non-implemented register bits, non-implemented addresses, odd register addresses return 0 when read. Vendor specific registers 5Ah - 7Ah are reserved for special functions, testing and similar operations. Revision 1.5, October 11, 2002 7 Data Sheet VT1616 6-Channel AC97 Codec with S/PDIF Register Descriptions Reset Register (Index 00h) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default – SE4 SE3 SE2 SE1 SE0 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 6D50h The Reset register is used to configure the hardware to a known state or to read the ID code of the part. A code was assigned to VIA Technologies (27 = 11011h) for 3D Stereo Enhancement reflected in SE[4:0]. ID8 and ID6 are set to 1b to report that the ADC and DAC are 20-bit resolution respectively. The VT1616 supports an alternate line level out with independent volume control as reflected by ID4=1b. However, since pins 39 and 41 are shared with the Surround DAC outputs, register 5Ah, bit 15, LVL has to be set to “1”. Writing data to this register will set all the mixer registers to their default values. For description of the bits set to 0b, refer to AC’97 Rev. 2.2 spec. Stereo Output Control Register (Index 02h) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default Mute – – ML4 ML3 ML2 ML1 ML0 – – – MR4 MR3 MR2 MR1 MR0 8000h Mute Stereo Output Mute Control “1” : “0” : ML[4:0] Mute enabled Mute disabled Master Output (Left Channel) Volume Control These five bits select the level of attenuation applied to the Left channel of the Stereo Output signal. The level of attenuation is programmable from 0dB to -46.5dB in 1.5dB increments, providing a total of 32 programmable levels. Please refer to Table 2 on page 10 for details. MR[4:0] Master Output (Right Channel) Volume Control These five bits select the level of attenuation applied to the Right channel of the Stereo Output signal. The level of attenuation is programmable from 0dB to -46.5dB in 1.5dB increments, providing a total of 32 programmable levels. Please refer to Table 2 on page 10 for details. Revision 1.5, October 11, 2002 8 Data Sheet VT1616 6-Channel AC97 Codec with S/PDIF Alternate Line Output Control Register (Index 04h) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default Mute – – ML4 ML3 ML2 ML1 ML0 – – – MR4 MR3 MR2 MR1 MR0 8000h Note: Pins 39 and 41 are shared with the Surround DAC outputs. LVL, register 5Ah, bit 15, has to be set to “1” Mute Stereo Output Mute Control “1” : “0” : ML[4:0] Mute enabled Mute disabled Alternate Line Output (Left Channel) Volume Control These six bits select the level of attenuation applied to the Left channel of the Stereo Output signal. The level of attenuation is programmable from 0dB to -46.5dB in 1.5dB increments, providing a total of 32 programmable levels. Please refer to Table 2 on page 10 for details. MR[4:0] Alternate Line Output (Right Channel) Volume Control These five bits select the level of attenuation applied to the Right channel of the Stereo Output signal. The level of attenuation is programmable from 0dB to -46.5dB in 1.5dB increments, providing a total of 32 programmable levels. Please refer to Table 2 on page 10 for details. Revision 1.5, October 11, 2002 9 Data Sheet VT1616 6-Channel AC97 Codec with S/PDIF Mono Output Control Register (Index 06h) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 Mute – – – – – – – – – – Mute D4 D3 D2 D1 D0 MM4 MM3 MM2 MM1 MM0 Default 8000h Mono Output Mute Control “1” : “0” : MM[4:0] Mute enabled Mute disabled Mono Output Volume Control These five bits select the level of attenuation applied to the Mono Output signal. The level of attenuation is programmable from 0dB to -46.5dB in 1.5dB increments, providing a total of 32 programmable levels. Please refer to Table 2 on page 10 for details. Table 2. Stereo and Mono Output Attenuation M4 M3 M2 M1 M0 Level (dB) 0 0 0 0 0 0 0.0 1 0 0 0 0 1 -1.5 2 0 0 0 1 0 -3.0 3 0 0 0 1 1 -4.5 4 0 0 1 0 0 -6.0 5 0 0 1 0 1 -7.5 .. .. .. .. .. .. .. .. .. .. .. .. .. .. 28 1 1 1 0 0 -42.0 29 1 1 1 0 1 -43.5 30 1 1 1 1 0 -45.0 31 1 1 1 1 1 -46.5 PC Beep Input Volume Control Register (Index 0Ah) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default Mute – – – – – – – – – – PV3 PV2 PV1 PV0 – 8000h Mute PC Beep Input Mute Control “1” : “0” : PV[3:0] Mute enabled Mute disabled PC Beep Input Volume Control These four bits select the level of attenuation applied to the PC beep input signal. The level of attenuation is programmable from 0dB to -45dB in 3dB increments, providing a total of 16 programmable levels. The beep gain is set at 0dB when PV[3:0] = 0h. Even though the default of the input volume control is mute, as long as RESET# is active, PC Beep will be passively routed to the line outputs. Revision 1.5, October 11, 2002 10 Data Sheet VT1616 6-Channel AC97 Codec with S/PDIF Phone Input Volume Control Register (Index 0Ch) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default Mute – – – – – – – – – – GN4 GN3 GN2 GN1 GN0 8008h Mute Phone Input Mute Control “1” : “0” : GN[4:0] Mute enabled Mute disabled Phone Input Volume Control These five bits select the gain applied to the Phone Input signal. The gain is programmable from 34.5dB to 12dB in 1.5dB increments, providing a total of 32 programmable levels. Please refer to Table 3 on page 14 for details. Mic Input Volume Control Register (Index 0Eh) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default Mute – – – – – – – – 20dB – GN4 GN3 GN2 GN1 GN0 8008h Mute Mic Input Mute Control “1” : “0” : 20dB Mic Boost Control “1” : “0” : GN[4:0] Mute enabled Mute disabled Fixed 20dB gain enabled Fixed 20dB gain disabled Mic Input Volume Control These five bits select the gain applied to the Mic Input signal. The gain is programmable from 34.5dB to 12dB in 1.5dB increments, providing a total of 32 programmable levels. Please refer to Table 3 on page 14 for details. Revision 1.5, October 11, 2002 11 Data Sheet VT1616 6-Channel AC97 Codec with S/PDIF Line Input Control Register (Index 10h) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default Mute – – GL4 GL3 GL2 GL1 GL0 – – – GR4 GR3 GR2 GR1 GR0 8808h Mute Line Input Mute Control “1” : “0” : GL[4:0] Mute enabled Mute disabled Left Channel Gain Control These five bits select the gain applied to the LEFT channel of the Line Input signal. The gain is programmable from -34.5dB to 12dB in 1.5dB increments, providing a total of 32 programmable levels. Please refer to Table 3 on page 14 for details. GR[4:0] Right Channel Gain Control These five bits select the gain applied to the RIGHT channel of the Line Input signal. The gain is programmable from -34.5dB to 12dB in 1.5dB increments, providing a total of 32 programmable levels. Please refer to Table 3 on page 14 for details. CD Input Control Register (Index 12h) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default Mute – – GL4 GL3 GL2 GL1 GL0 – – – GR4 GR3 GR2 GR1 GR0 8808h Mute CD Input Mute Control “1” : “0” : GL[4:0] Mute enabled Mute disabled Left Channel Gain Control These five bits select the gain applied to the Left channel of the CD Input signal. The gain is programmable from -34.5dB to 12dB in 1.5dB increments, providing a total of 32 programmable levels. Please refer to Table 3 on page 14 for details. GR[4:0] Right Channel Gain Control These five bits select the gain applied to the Right channel of the CD Input signal. The gain is programmable from -34.5dB to 12dB in 1.5dB increments, providing a total of 32 programmable levels. Please refer to Table 3 on page 14 for details. Revision 1.5, October 11, 2002 12 Data Sheet VT1616 6-Channel AC97 Codec with S/PDIF Video Input Control Register (Index 14h) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default Mute – – GL4 GL3 GL2 GL1 GL0 – – – GR4 GR3 GR2 GR1 GR0 8808h Mute Video Input Mute Control “1” : GL[4:0] Mute enabled “0”:Mute disabled Left Channel Gain Control These five bits select the gain applied to the Left channel of the Video Input signal. The gain is programmable from -34.5dB to 12dB in 1.5dB increments, providing a total of 32 programmable levels. Please refer to Table 3 on page 14 for details. GR[4:0] Right Channel Gain Control These five bits select the gain applied to the Right channel of the Video Input signal. The gain is programmable from -34.5dB to 12dB in 1.5dB increments, providing a total of 32 programmable levels. Please refer to Table 3 on page 14 for details. Auxiliary Input Control Register (Index 16h) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default Mute – – GL4 GL3 GL2 GL1 GL0 – – – GR4 GR3 GR2 GR1 GR0 8808h Mute Auxiliary Input Mute Control “1” : GL[4:0] Mute enabled “0”:Mute disabled Left Channel Gain Control These five bits select the gain applied to the Left channel of the Auxiliary Input signal. The gain is programmable from -34.5dB to 12dB in 1.5dB increments, providing a total of 32 programmable levels. Please refer to Table 3 on page 14 for details. GR[4:0] Right Channel Gain Control These five bits select the gain applied to the Right channel of the Auxiliary Input signal. The gain is programmable from -34.5dB to 12dB in 1.5dB increments, providing a total of 32 programmable levels. Please refer to Table 3 on page 14 for details. Revision 1.5, October 11, 2002 13 Data Sheet VT1616 6-Channel AC97 Codec with S/PDIF PCM Output Control Register (Index 18h) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default Mute – – GL4 GL3 GL2 GL1 GL0 – – – GR4 GR3 GR2 GR1 GR0 8808h Mute PCM Output Mute Control “1” : “0” : GL[4:0] Mute enabled Mute disabled Left Channel Gain Control These five bits select the gain applied to the LEFT channel of the PCM Output signal. The gain is programmable from -34.5dB to 12dB in 1.5dB increments, providing a total of 32 programmable levels. Please refer to Table 3 on page 14 for details. GR[4:0] Right Channel Gain Control These five bits select the gain applied to the RIGHT channel of the PCM Output signal. The gain is programmable from -34.5dB to 12dB in 1.5dB increments, providing a total of 32 programmable levels. Please refer to Table 3 (below) on page 14 for details. Table 3. Programmable Mixer Input Gain Levels 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Revision 1.5, October 11, 2002 G4 G3 G2 G1 G0 Level (dB) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 12.0 10.5 9.0 7.5 6.0 4.5 3.0 1.5 0.0 -1.5 -3.0 -4.5 -6.0 -7.5 -9.0 -10.5 -12.0 -13.5 -15.0 -16.5 -18.0 -19.5 -21.0 -22.5 -24.0 -25.5 -27.0 -28.5 -30.0 -31.5 -33.0 -34.5 14 Data Sheet VT1616 6-Channel AC97 Codec with S/PDIF Record Select Register (Index 1Ah) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default – – – – – SL2 SL1 SL0 – – – – – SR2 SR1 SR0 0000h SL[2:0] Record Source Select (Left Channel) These bits determine the record source for the left channel. SR[2:0] SL2 SL1 SL0 Left Record Source 0 0 0 Mic 0 0 1 CD (L) 0 1 0 Video In (L) 0 1 1 Aux In (L) 1 0 0 Line In (L) 1 0 1 Stereo Mix (L) 1 1 0 Mono Mix 1 1 1 Phone Record Source Select (Right Channel) These bits determine the record source for the right channel. SR2 SR1 SR0 Right Record Source 0 0 0 Mic 0 0 1 CD (R) 0 1 0 Video In (R) 0 1 1 Aux In (R) 1 0 0 Line In (R) 1 0 1 Stereo Mix (R) 1 1 0 Mono Mix 1 1 1 Phone Revision 1.5, October 11, 2002 15 Data Sheet VT1616 6-Channel AC97 Codec with S/PDIF Record Gain Control Register (Index 1Ch) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default Mute – – – GL3 GL2 GL1 GL0 – – – – GR3 GR2 GR1 GR0 8000h Mute Record Mute Control “1” : “0” : GL[3:0] Mute enabled Mute disabled Record Gain Control (Left Channel) These four bits select the gain applied to the LEFT channel recording source. The gain is programmable from 0dB to 22.5dB in 1.5dB increments, providing a total of 16 programmable levels. The gain is set at 0dB when GL[3:0] = 0h. GR[3:0] Record Gain Control (Right Channel) These four bits select the gain applied to the RIGHT channel recording source. The gain is programmable from 0dB to 22.5dB in 1.5dB increments, providing a total of 16 programmable levels. The gain is set at 0dB when GR[3:0] = 0h. General Purpose Register (Index 20h) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default – – 3D – – – MIX MS LPBK – – – – – – – 0000h 3D 3D Stereo Enhancement “1” : “0” : MIX Mono Output Mode “1” : “0” : MS Mic Output Mono mix output Microphone Select “1” : “0” : LPBK Enable 3D Disable 3D Microphone 2 Microphone 1 Loopback Mode For this bit to be valid, 5C_0 must be set to “1”. See description of LBE on page 26. “1” : DAC/ADC Loopback enabled “0” : DAC/ADC Loopback disabled Revision 1.5, October 11, 2002 16 Data Sheet VT1616 6-Channel AC97 Codec with S/PDIF 3D Control Register (Index 22h) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default – – – – – – – – – – – – DP3 DP2 DP1 DP0 0000h DP[3:0] 3D Depth Control These four bits control the linear depth control of the 3D stereo enhancement built into the codec. The gain is programmable from 0% to 100% in 6.67% increments, providing a total of 16 programmable levels. The default value corresponds to no stereo enhancement. Table 4. 3D Depth Control DP3 DP2 DP1 DP0 Level (%) 0 0 0 0 0 0.0 1 0 0 0 1 6.67 2 0 0 1 0 13.33 3 0 0 1 1 20 4 0 1 0 0 26.67 5 0 1 0 1 33.33 .. .. .. .. .. .. .. .. .. .. .. .. 12 1 1 0 0 80 13 1 1 0 1 86.67 14 1 1 1 0 93.33 15 1 1 1 1 100 Revision 1.5, October 11, 2002 17 Data Sheet VT1616 6-Channel AC97 Codec with S/PDIF Power Down and Status Register (Index 26h) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default EAPD PR6 PR5 PR4 PR3 PR2 PR1 PR0 – – – – REF ANL DAC ADC 0000h EAPD Enable Amplifier Power Down “1” : Powerdown External Power Amplifier “0” : External Power Amplifier active The signal polarity at pin 47, EAPD is identical to bit description. PR[6:0] Power Down Mode Bits These read/write bits are used to control the power down states of the VT1616. Each power down function bit is enabled by setting the respective bit high. Particularly, PR5 has no effect unless PR0, PR1 and PR4 are all set to “1”. This implies that the codec can be woken up by a warm reset, because warm reset clears PR4, which in turn disables the function of PR5. The register bit, however will not be cleared by a warm reset. The power down modes controlled by each bit is described in the table below: Bit Function PR0 ADC and Mux Powerdown PR1 DAC Powerdown PR2 Mixer Powerdown (VREF on) PR3 Mixer Powerdown (VREF off) PR4 AC Link Powerdown (BIT_CLK off) PR5 Internal Clock Disabled PR6 Alternate Line Out Powerdown REF,ANL,ADC,DACStatus (READ Only) bits These bits are used to monitor the readiness of some sections of the VT1616. Reading a “1” from any of these bits would be an indication of a “ready” state. Bit Status Bit REF VREF at nominal level ANL Mixer, Mux and Volume Controls ready DAC DAC ready to accept data ADC ADC ready to transmit data Revision 1.5, October 11, 2002 18 Data Sheet VT1616 6-Channel AC97 Codec with S/PDIF Extended Audio ID Register (Index 28h) D15 D14 D13 D12 D11 D10 ID1 ID0 – – – – D9 D8 D7 D6 AMAP LDAC SDAC CDAC D5 D4 D3 D2 D1 D0 Default – – – SPDIF – VRA 01Exh The Extended Audio ID is a read only register that indicates the capabilities of the VT1616. ID[1:0] (See Table below) One primary and an additional codec may be supported as an option. Since the VT1616 codec has all six outputs implemented, the ID pin setting affects only the BIT_CLK direction and the register decoding. BIT_CLK output the power-up default. Setting the codec besides default changes BIT_CLK to input mode. As indicated by D9, AMAP=0, there is no need to change slot mappings. Table 5. Multiple Codec Mode Status Bits Note: AMAP ID0 Codec Mode 0 0 Primary Codec (default) 0 1 Secondary Codec 1 0 Invalid 1 1 Invalid The state of the ID pins is reported in reverse polarity on register 28h, bits D15 and D14. If you use this table to configure the codec via pins 45 and 46, use the inverse values. Please, refer to Figure 4 on page 27. BIT_CLK is an output for the primary codec and an input pin for the controller and secondary codecs. ID[1:0] pins with internal pull-up resistors defaults codec as primary codec. Slot/DAC mapping based on Codec ID “0” : xDAC ID1 Feature not applicable since all possible channels are available on VT1616. Multi-channel Output Capabilities “1”: LDAC, SDAC, CDAC report to the querying host that the codec has all six outputs implemented. SPDIF Sony/Philips Digital Audio Interface “1” : “0” : VRA Feature implemented in compliance to “S/PDIF Output for AC ‘97, Rev 1.0” Indicates that SPDIF_OUT pin 48 is left floating or pulled-high. It reflects the lack of external S/PDIF application circuitry. Variable Sampling Rate PCM Audio “1” : Revision 1.5, October 11, 2002 Feature implemented in compliance to AC ‘97 2.2 Appendix A 19 Data Sheet VT1616 6-Channel AC97 Codec with S/PDIF Extended Audio Status/Control Register (Index 2Ah) D15 D14 D13 D12 D11 D10 D9 – – PRK PRJ PRI SPCV – PRx D8 D7 D6 D5 D4 LDAC SDAC CDAC SSA1 SSA0 D3 D2 D1 D0 Default – SPDIF – VRA 3800h Multi-channel Output Control All three bits, PRK, PRJ, PRI behave similarly. When set to “0”, the respective DAC(s) is (are) turned on. PRK is for LFE, PRJ for Surround (Rear pair), PRI for Center channel. SPCV S/PDIF Configuration Valid (Read Only) “0” : S/PDIF configuration (SSA, SSR, DAC rate, DRS) invalid (not supported) “1” : S/PDIF configuration (SSA, SSR, DAC rate, DRS) valid (supported) xDAC Multi-channel Output Status (Read Only) These read only bits, LDAC, SDAC, CDAC behave similarly. When they report “1”, the respective DAC(s), LFE, Surround and Center is (are) ready. SSA[1:0] S/PDIF Slot Assignment These bits determine the S/PDIF data source from AC-link slot selection when SPDIF_OUT, pin 48 is low during reset (pulled low by external application circuit). If the S/PDIF application circuit is not implemented, these bits will return only 0. The default state reflects the pervasive design feature of common AC’97 digital controllers supporting slots 3 & 4. Slots 10 & 11 are expected to be used in the future to support concurrent 6 channels analog and 2 channel digital audio (compressed or LPCM). SPDIF SSA1 SSA0 S/PDIF Source Data 0 0 AC-link slots 3 & 4 (front stereo pair, power-up default) 0 1 AC-link slots 7 & 8 (surround pair) 1 0 AC-link slots 6 & 9 (LFE & Center pair) 1 1 AC-link slots 10 &11 Sony/Philips Digital Audio Interface Enable/Disable “1” : “0” : VRA Set this bit to turn on the S/PDIF transmitter. The S/PDIF transmitter is off by default. Variable Sampling Rate Mode control “1” : “0” : Revision 1.5, October 11, 2002 Enable VSR Fixed 48 KHz sampling rate 20 Data Sheet VT1616 6-Channel AC97 Codec with S/PDIF PCM Front and Center DAC Sample Rate Register (Index 2Ch) D15 D14 D13 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h SR[15:0] D12 D11 Main stereo + Center or all DAC Sample Rate (in Hz) 16-bit unsigned value representing the sample rate in 1Hz resolution. The default value is 48 KHz (48000 = BB80h). This register controls all six DAC output rate providing a sample accurate synchronization among the channels. Registers 2Eh and 30h are read/writable but have no control over the Surround and LFE channels. They reflect 2Ch when read back. PCM Surround DAC Sample Rate Register (Index 2Eh) D15 D14 D13 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h SR[15:0] D12 D11 Surround DAC Sample Rate (in Hz) 16-bit unsigned alias value of 2Ch representing the sample rate in 1Hz resolution. The default value is 48 KHz (48000 = BB80h). This register has no physical control over the Surround pair DACs sampling rate. PCM LFE DAC Sample Rate Register (Index 30h) D15 D14 D13 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h SR[15:0] D12 D11 LFE DAC Sample Rate (in Hz) 16-bit unsigned alias value of 2Ch representing the sample rate in 1Hz resolution. The default value is 48 KHz (48000 = BB80h). This register has no physical control over the LFE DAC’s sampling rate. PCM ADC Sample Rate Register (Index 32h) D15 D14 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h SR[15:0] D13 D12 D11 ADC Sample Rate (in Hz) 16-bit unsigned value representing the sample rate in 1Hz resolution. The default value is 48 KHz (48000 = BB80h). Revision 1.5, October 11, 2002 21 Data Sheet VT1616 6-Channel AC97 Codec with S/PDIF LFE and Center Channels Output Volume Control Register (Index 36h) D15 D14 D13 Mute – – Mute D12 D11 D9 D8 D7 D6 D5 – – LFE4 LFE3 LFE2 LFE1 LFE0 Mute D4 D3 D2 D1 D0 CNT4 CNT3 CNT2 CNT1 CNT0 Default 8080h Individual Output Mute Control “1” : “0” : LFE[4:0] D10 Mute enabled Mute disabled LFE Output Volume Control These five bits select the level of attenuation applied to the Low Frequency Effect channel. The level of attenuation is programmable from 0dB to -46.5dB in 1.5dB increments, providing a total of 32 programmable levels. Please refer to Table 2 on page 10 for details. CNT[4:0] Center Channel Output Volume Control These five bits select the level of attenuation applied to the Center channel. The level of attenuation is programmable from 0dB to -46.5dB in 1.5dB increments, providing a total of 32 programmable levels. Please refer to Table 2 on page 10 for details. Revision 1.5, October 11, 2002 22 Data Sheet VT1616 6-Channel AC97 Codec with S/PDIF Surround Channels Output Volume Control Register (Index 38h) D15 D14 D13 Mute – – D12 D11 D10 D9 D8 D7 LSR4 LSR3 LSR2 LSR1 LSR0 Mute D6 D5 – – D4 D3 D2 D1 D0 RSR4 RSR3 RSR2 RSR1 RSR0 Default 8080h Note: Pins 39 and 41 are shared with the Alternate Line Level Out, main stereo DAC outputs. LVL, register 5Ah, bit 15, has to be set to “0” for this register to be effective on the same volume control block. Mute Individual Output Mute Control “1” : “0” : LSR[4:0] Mute enabled Mute disabled Left Surround (Rear) Channel Output Volume Control These five bits select the level of attenuation applied to the Left Surround channel. The level of attenuation is programmable from 0dB to -46.5dB in 1.5dB increments, providing a total of 32 programmable levels. Please refer to Table 2 on page 10 for details. RSR[4:0] Right Surround (Rear) Channel Output Volume Control These five bits select the level of attenuation applied to the Right Surround channel. The level of attenuation is programmable from 0dB to -46.5dB in 1.5dB increments, providing a total of 32 programmable levels. Please refer to Table 2 on page 10 for details. Revision 1.5, October 11, 2002 23 Data Sheet VT1616 6-Channel AC97 Codec with S/PDIF S/PDIF Control Register (Index 3Ah) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 V – SSR1 SSR0 L CC6 CC5 CC4 CC3 CC2 CC1 CC0 PRE D2 D1 COPY /PCM D0 Default PRO x000h This read/write register controls the S/PDIF functionality when SPDIF bit at 28h_2 reports S/PDIF is implemented. It will return 0000h when SPDIF_OUT, pin 48 left floating or pulled high. If S/PDIF is implemented for the final product, it will read 2000h at power-up. The register manages the bit fields propagated as channel status (or subframe in the V case). With the exception of V, this register should only be written when the S/PDIF transmitter is disabled (SPDIF bit at 2Ah_2 is “0”). This ensures that control and status information start up correctly at the beginning of S/PDIF transmission. V Validity This bit affects the “Validity flag”, bit 28 transmitted in each subframe and enables the S/PDIF transmitter to maintain connection during error or mute conditions. “0” : If a valid Left/Right pair was received via AC-link and transmitted through S/PDIF, the Validity bit should be reset to “0” “1” : Tags both samples as invalid by setting bit 28, “Validity flag” to “1” SSR[1:0] S/PDIF Sample Rate These bits declare the available S/PDIF transmitter clock rate (64*fs). L SSR1 SSR0 S/PDIF Sample Rate 0 0 Not Available 0 1 Reserved 1 0 48 KHz (default) 1 1 Not Available Generation Level Programmed according to IEC standards. CC[6:0] Category Code Programmed according to IEC standards. PRE Preemphasis “1” : Indicates filter preemphasis is 50/15µs. “0” : Default is no Preemphasis. COPY Copyright “1” : Indicates copyright is asserted. “0” : Copyright is not asserted (default). /PCM Non-Audio Samples “1” : Set this bit for transmitting non-PCM audio samples such as AC-3. “0” : Indicates samples are linear PCM suitable for direct conversion to audio playback. . PRO Professional “1” : Set Professional mode. Set this bit in conjunction with /PCM bit (above) for AC-3. “0” : Indicates Consumer mode (default). Revision 1.5, October 11, 2002 24 Data Sheet VT1616 6-Channel AC97 Codec with S/PDIF Vendor Reserved Register (Index 5Ah) D15 D14 D13 D12 LVL Res. Res. LCTF Res. D11 D10 STF BPDC D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default DC Res. Res. Res. Res. Res. IB1 IB0 Res. Res. 8200h Test Mode Bits These read/write bits are used for testing the digital modes of the audio codec. Do not access them during Normal operation. LVL Alternate Line Level Out to Surround Out The VT1616 powers up with pins 39 and 41 assigned to the Front channel DACs as described in the AC97 Revision 2.2 specification. When this bit is to “0”, the output pins get assigned to the Rear stereo DAC pair with an independent volume control. LCTF Downmix LFE and Center DAC outputs to the Front channels The VT1616 is capable of downmixing the LFE and the Center channel outputs to the Line_Out pins using internal hardware. Without processing overhead, it is possible to listen to all the channels without loss of audio cues. The relative SPL (Sound Pressure Level) for these channels are retained as meant by the digital audio content mastering engineer. This is ideal for 4-channel applications. STF Downmix Surround DAC outputs to the Front channels The VT1616 is capable of downmixing the Rear channel outputs to the Line_Out pins using internal hardware besides the LFE and the Center. This is useful when multichannel material needs to be played back on a stereo end point like headphones. Without processing overhead, it is possible to listen to all the channels without loss of audio cues. The relative SPL (Sound Pressure Level) for these channels are retained as meant by the digital audio content mastering engineer. This is ideal for 2-channel applications when LCTF and STF are both activated at the same time. BPDC ADC DC-offset Removal Control The default setting of “0” ensures that the circuit is disabled at power up. When set to “1”, the DCoffset cancellation circuit will be enabled. This helps to maximize recording quality by removing white noise. DC DC-offset Removal Capability This read only bit indicates that the codec incorporates DC-offset removal hardware. IB[1:0] Analog Current Setting Bits Normally these bits should be left at default when analog operating at 5V supply. The four possible settings adjust the power consumption of the analog section. The power-up default 00b sets the codec for the best overall analog performance at 5V. At 3.3V analog supply, 10b should be set for the lowest power instead of default 00b. This mode is desirable for system designs with limited power budget such as battery operated portable devices. Setting to 11b puts the codec to its best AA mixer performance overall. Revision 1.5, October 11, 2002 IB1 IB0 Analog Current Setting 0 0 Normal (1X) 0 1 Reduced (4/5X) 1 0 Power Miser (2/3X) 1 1 Enhanced (4/3X) 25 Data Sheet VT1616 6-Channel AC97 Codec with S/PDIF Vendor Reserved Register (Index 5Ch) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LBE 0000h LBE Loopback Test Mode Engage When set to “1”, it will allow the functionality of 20h_7, Loopback test mode. Res. Test Mode Bits These read/write bits are used for testing the digital modes of the audio codec. Do not access them during Normal operation. Vendor Identification Register (Index 7Ch) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default F7 F6 F5 F4 F3 F2 F1 F0 S7 S6 S5 S4 S3 S2 S1 S0 4943h The upper and lower byte of this register (index 7Ch), in conjunction with the upper byte of index register 7Eh, make up the vendor identification code for the VT1616. The Vendor ID Code (in ASCII format) is equal to “ICE”, where: F[7:0] Upper Byte (Index 7Ch) D[15:8] = I S[7:0] Lower Byte (Index 7Ch) D[7:0] = C T[15:8] Upper Byte (Index 7Eh) D[15:8] = E Revision Identification Register (Index 7Eh) D15 D14 D13 D12 D11 D10 D9 D8 T7 T6 T5 T4 T3 T2 T1 T0 D7 D6 D5 D4 D3 D2 D1 D0 REV7 REV6 REV5 REV4 REV3 REV2 REV1 REV0 Default 4551h The upper byte of this register is used in conjunction with index register 7Ch to make up the Vendor ID code for the VT1616. The lower byte identifies VT1616 and its revision code. T[15:8] See description in Vendor Identification Register. REV[7:0] Revision ID “51”: VT1616 identification and revision number Note: As a reference, other valid Rev IDs associated with VIA AC’97 products are: “01h” for the VT1611 (ICE1230), “11h” for the VT1611A (ICE1232), and “14h” for the ICE1232A (this part has no corresponding VIA part number). Revision 1.5, October 11, 2002 26 Data Sheet VT1616 6-Channel AC97 Codec with S/PDIF Multiple Codec Example The primary codec provides the master BIT_CLK. The secondary codec, if any, and the controller, will use this clock to work in synchronous mode. Note that the ID[1:0] pins are internally pulled up; therefore, it is necessary to pull the ID[1:0] pins low to set the codec as secondary. Notice that the state of the ID[1:0] pins are reflected in reverse polarity as shown on Table 5 on page 19. See Reg. 28h for more details. DC ‘97 AC ‘97 ~ Primary SYNC BIT_CLK SDATA_OUT RESET# SDATA_IN0 SDATA_IN1 SYNC BIT_CLK SDATA_OUT RESET# SDATA_IN ID1 ID0 1 1 AC ‘97 ~ Secondary SYNC BIT_CLK SDATA_OUT RESET# SDATA_IN ID1 ID0 1 0 Figure 4. Multiple Codec Example Revision 1.5, October 11, 2002 27 Data Sheet VT1616 6-Channel AC97 Codec with S/PDIF Power Management The VT1616 may be placed in several power down states using the power down control bits located in index register 26h. Table 6 lists the power down states accessible through this register. Table 6. Power Down Mode Bits Note: Bit Function PR0 ADC and Mux Powerdown PR1 DAC Powerdown PR2 Mixer Powerdown (VREF on) PR3 Mixer Powerdown (VREF off) PR4 AC Link Powerdown (BIT_CLK off) PR5 Internal Clock Disabled PR6 Alternate Line Out Powerdown Registers maintain values in sleep mode (PR4 write) and wake up with a warm reset (register values) or a cold reset (default values). Power Down and Status register (index 26h) read action verifies stability before power down write action occurs. PR0=1 PR1=1 ADC’s OFF PR0 Normal PR0=0 & ADC=1 PR2=1 Analog OFF PR2 / PR3 DAC’s OFF PR1 PR1=0 & DAC=1 PR4=1 PR2=0 & ANL=1 Digital I/F OFF PR4 Shut Off Warm Reset Default Ready=1 Cold Reset Note: In this example, the Analog Mixer has been disabled, but VREF is still on. Figure 5. AC’97 Power Down / Power Up Procedure Complete power down of the AC’97 device is achieved by sequential writes to the Power Down and Status Control Register (Index 26h) as follows: Normal Operations: ADC’s and Input Mux: DAC’s: Analog Mixer: VREF_OUT: AC-link: Internal Clocks: Alt. Line Out: Revision 1.5, October 11, 2002 PR[6:0] = 00h PR0 = 1 (write) PR1 = 1 (write) PR2 = 1 (write) PR3 = 1 (write) PR4 = 1 (write) PR5 = 1 (write) PR6 = 1 (write) 28 Data Sheet VT1616 6-Channel AC97 Codec with S/PDIF Power Management (continued...) Cold Reset PR0=1 PR1=1 ADC’s OFF PR0 Normal PR0=0 & ADC=1 PR5=1 PR4=1 DAC’s OFF PR1 PR1=0 & DAC=1 Digital I/F OFF PR4 Shut Off Oscillator Off Warm Reset Cold Reset Note: To wake up the codec, a warm reset can be used; PR4 is reset to zero upon either reset. PR5 can only be cleared by a cold reset. Figure 6. AC’97 Power Down Procedure with Analog Section Still Active Test Mode Operation ATE Test Mode: (PCB in-circuit Testing of the VT1616) ATE Test mode is entered when the SDATA_OUT signal is sampled at the rising edge of the RESET# signal. In this mode, the SDATA_IN and BIT_CLK pins are placed in a high impedance (Hi-Z) state as shown on Table 14 on page 39. This mode of operation doesn’t occur under normal operating conditions. Vendor Test Mode: Vendor Test mode is entered when the SYNC signal is sampled during the rising edge of the RESET# signal as shown on Table 15 on page 39. This mode of operation doesn’t occur under normal operating conditions. Revision 1.5, October 11, 2002 29 Data Sheet VT1616 6-Channel AC97 Codec with S/PDIF Absolute Maximum Ratings Table 7. Limits (AGND = DGND = 0V) Symbol Parameter Min Typ Max Unit – Digital Power Supplies (DVCC) -0.3 4.0 V – Analog Power Supplies (AVCC) -0.3 6.0 V – Input Current per Pin -10 10 mA – Output Current per Pin -15 15 mA – Digital Input Voltage -0.3 DVCC+0.3 V – Analog Input Voltage -0.3 AVCC+0.3 V – Total Power Dissipation – Ambient Temperature -55 110 °C – Storage Temperature -65 150 °C Caution: 270 mW Exceeding any of these limits can cause permanent failure of the device and will void any claims against product quality. Recommended Operating Conditions Table 8. Limits (AGND = DGND = 0V) Symbol Parameter Min Typ Max Unit – Digital Power Supplies (DVCC) 3.135 3.3 3.465 V – Analog Power Supplies (AVCC), preferred 4.75 5 5.25 V – Analog Power Supplies (AVCC), for low power apps 3.135 3.3 3.465 V – Operating Ambient Temperature 70 °C Revision 1.5, October 11, 2002 0 30 Data Sheet VT1616 6-Channel AC97 Codec with S/PDIF Performance Specifications Table 9. Analog Performance Characteristics (+5V Power) TA=25°C, AVCC = 5V ± 5%, DVCC = 3.3V ± 5%; AGND = DGND =0V; 10kΩ / 50pF Load; FS = 48 KHz, 0dB = 1VRMS; BW: 20Hz ~ 20 KHz, 0dB Attentuation, IB[1:0]=00 (power up default), as targeted for a 2-layers VT5542 ACR card Symbol Parameter Min Full Scale Input Voltage: Line Inputs 1.0 Unit VRMS 1.0 VRMS Mic Inputs (20dB = 1) 0.1 VRMS Line Outputs 1.0 VRMS Mono Output 1.0 VRMS CD to LINE_OUT 96 dB Other to LINE_OUT 96 dB Analog S/N: Analog Frequency Response 20 Digital S/N: DACs 85 ADC 75 20,000 88 Hz dB 91 dB LINE_IN to LINE_OUT -94 -74 dB (DA) DAC to LINE_OUT -82 -74 dB 19,200 Hz D/A and A/D Frequency Response: DACs 20 ADC 20 19,200 Hz Transition Band: DACs 19,200 28,800 Hz ADC 19,200 28,800 Hz Stop Band: DACs 28,800 infinity Hz ADC 28,800 infinity Hz Stop Band Rejection: DACs 75 dB ADC 75 dB Out-of-Band Rejection -40 Group Delay dB 1 Power Supply Rejection Ratio (1 KHz) -40 Input Channel Crosstalk -100 Attenuation, Gain Step Size ms dB -70 Spurious Tone Reduction dB dB 1.5 dB 45 kΩ Input Capacitance 15 pF VREFOUT 2.4 V Input Impedance Note: Max Mic Inputs (20dB = 0) Full Scale Output Voltage: Total Harmonic Distortion: Typ 10 VIL = 0.8V, VIH = 2.4V Analog Frequency Response has ±1dB limits SNR (measured as THD+N) of rms output level with 1 KHz full-scale input to rms output level with all zeros into digital input Measured “A wtd” over a 20Hz ~ 20 KHz bandwidth (AES17-1991 Idle Channel Noise or EIAJ CP-307 SNR) THD: 0dB gain, 20 KHz BW, Fs = 48 KHz, -3dB “large” signal A/D and D/A Frequency Response has ±0.25dB limits Stop Band Rejection determines filter requirements Out-of-Band rejection determines audible noise Integrated Out-of-band noise generated by DAC during normal PCM audio playback over: BW = 28.8 KHz~100 KHz, with respect to 1 VRMS DAC output Revision 1.5, October 11, 2002 31 Data Sheet VT1616 6-Channel AC97 Codec with S/PDIF Performance Specifications (continued...) Table 10. Analog Performance Characteristics (+3.3V Power) TA=25°C, AVCC = DVCC = 3.3V ± 5%; AGND = DGND =0V; 10kΩ / 50pF Load; FS = 48 KHz, 0dB = 0.70VRMS; BW: 20Hz ~ 20 KHz, 0dB Attentuation, IB[1:0]=10 (set by software), as targeted for a 2-layers VT5542 ACR card Symbol Parameter Min Full Scale Input Voltage: Typ Unit Line Inputs 0.7 VRMS Mic Inputs (20dB = 0) 0.7 VRMS Mic Inputs (20dB = 1) 0.07 VRMS Line Outputs 0.70 VRMS Mono Output 0.07 VRMS 92 dB Full Scale Output Voltage: Analog S/N: CD to LINE_OUT Other to LINE_OUT Analog Frequency Response Digital S/N: Total Harmonic Distortion: D/A and A/D Frequency Response: 92 20 dB 20,000 Hz DACs 85 dB ADC 88 dB Line Outputs -70 dB DACs 20 19,200 Hz ADC 20 19,200 Hz Transition Band: DACs 19,200 28,800 Hz ADCs 19,200 28,800 Hz Stop Band: DACs 28,800 infinity Hz ADC 28,800 infinity Hz DACs TBD ADC TBD Stop Band Rejection: Out-of-Band Rejection dB dB -40 Group Delay dB 1 Power Supply Rejection Ration (1 KHz) -40 Input Channel Crosstalk ms dB -70 dB Spurious Tone Reduction -100 dB Attenuation, Gain Step Size 1.5 dB 50 kΩ Input Capacitance 15 pF VREFOUT 1.5 V Input Impedance Note: Max 10 VIL = 0.8V, VIH = 2.4V Analog Frequency Response has ±1dB limits SNR (measured as THD+N) of rms output level with 1 KHz full-scale input to rms output level with all zeros into digital input Measured “A wtd” over a 20Hz ~ 20 KHz bandwidth (AES17-1991 Idle Channel Noise or EIAJ CP-307 SNR) THD: 0dB gain, 20 KHz BW, Fs = 48 KHz, -3dB “large” signal A/D and D/A Frequency Response has ±0.25dB limits Stop Band Rejection determines filter requirements Out-of-Band rejection determines audible noise Integrated Out-of-band noise generated by DAC during normal PCM audio playback over: BW = 28.8 KHz~100 KHz, with respect to 0.70 VRMS DAC output Revision 1.5, October 11, 2002 32 Data Sheet VT1616 6-Channel AC97 Codec with S/PDIF Performance Specifications (continued...) Table 11. Miscellaneous Analog Performance Characteristics (TA=25°C, AVCC = 5.0V ± 5%, DVCC = 3.3V ± 5%; AGND = DGND =0V; 10kΩ / 50pF Load); FS = 48 KHz, 0dB = 1VRMS; BW: 20Hz ~ 20 KHz, 0dB Attentuation) Symbol Parameter Min Typ Max Unit Mixer Gain Range Span: LINE_IN, AUX, VIDEO, MIC1, MIC2, PHONE, PC_BEEP 46.5 dB LINE_OUT, MONO_OUT 46.5 dB Mixer Step Size: All Volume Controls except PC_BEEP PC_BEEP Mixer Mute Level Mixer Gain: Interchannel Gain Mismatch Gain Drift ADC and Analog Inputs (Rs=50Ω) DAC and Analog Outputs: 1.5 dB 3.0 dB 110 dB -0.5 0.5 100 Resolution Gain Error ±2 Offset Error 10 Input Impedance 50 Resolution 80 Interchannel Gain Mismatch 0.1 Gain Error Gain Drift Revision 1.5, October 11, 2002 33 ppm/°C 18 bits ±5 % mV kΩ 18 Interchannel Isolation bits dB 0.2 ±5 60 dB dB % ppm/°C Data Sheet VT1616 6-Channel AC97 Codec with S/PDIF Electrical Specifications Table 12. DC Characteristics (TA=25°C, AVCC = 5.0V ± 5%, DVCC = 3.3V ± 5%; AGND = DGND =0V; 50pF Load) Symbol Parameter Min Typ -0.3 Max Unit Vcc+0.3 V 0.3 x Vcc V VIN Input Voltage Range VIL Input Low Voltage VIH Input High Voltage VOL Output Low Voltage VOH Output High Voltage 2.4 – Input Leakage Current (AC-Link) -10 10 µA – Output Leakage Current (AC-Link and Hi-Z) -10 10 µA – Output Buffer Drive Current 0.7 x Vcc V 0.4 V V TBD mA Table 13. Power Consumption (+5V Power) (TA=25°C, AVCC = 5.0V ± 5% DVCC = 3.3V ± 5%; AGND = DGND =0V; 50pF Load) Symbol Parameter Min Typ Max Unit IVCC Digital Supply Current: Power Up (default) 27 mA IVCC All active (2Ah = 0004h) 38 mA IVCC S/PDIF on (2Ah = 3804h) 33 mA IVCC All DACs off (PR1, 26h = 0200h, 2Ah = 3800h) 14 mA IVCC PR4 (26h =1F00h, 2Ah = 3800h) 0.5 mA IVCC Power Down (PR6, RESET# = 0) 0.08 mA IAVCC Analog Supply Current: Power Up (default) 42 mA IAVCC All active (2A = 0004h) 52 mA IAVCC PR0 (26h = 0100h, i.e. ADC off) 42 mA IAVCC All DACs off (PR1, 26h = 0200h, 2Ah = 3800h) 37 mA IAVCC PR2 (26h = 0700h) 16 mA IAVCC Power Down (PR3, 26h = 0F00h, 2Ah = 3800h) 3 mA Table 14. Power Consumption (+3.3V Power) (TA=25°C, AVCC = DVCC = 3.3V ± 5%; AGND = DGND =0V; 50pF Load) Symbol Parameter Min Typ Max Unit IVCC Digital Supply Current: Power Up TBD mA IVCC Digital Supply Current: Power Down TBD mA IAVCC Analog Supply Current: Power Up default TBD mA IAVCC Analog Supply Current: Power Up, IB[1:0]=11 TBD mA IAVCC Analog Supply Current: Power Down, IB[1:0]=xx TBD mA Revision 1.5, October 11, 2002 34 Data Sheet VT1616 6-Channel AC97 Codec with S/PDIF AC Timing Characteristics (Test Conditions: TA=25°C, AVCC = 5.0V ± 5%, DVCC = 3.3V ± 5%; AGND = DGND =0V; 50pF Load) Table 15. Cold Reset Symbol Parameter Min TRST_LOW RESET# Active Low Pulse Width TRST2CLK RESET# Inactive to BIT_CLK Startup Delay TRST_LOW Typ Max Unit 1 µs 162.8 ns TRST2CLK RESET# BIT_CLK Figure 7. Cold Reset Timing Table 16. Warm Reset Symbol Parameter Min TSYNC_HIGH Sync Active High Pulse Width TSYNC2CLK SYNC Inactive to BIT_CLK Startup Delay Typ 1.3 162.8 TSYNC_HIGH Max Unit µs ns TSYNC2CLK SYNC BIT_CLK Figure 8. Warm Reset Timing Revision 1.5, October 11, 2002 35 Data Sheet VT1616 6-Channel AC97 Codec with S/PDIF Table 17. BIT_CLK Timing Symbol Parameter Min Typ BIT_CLK Frequency TCLK_PERIOD Max 12.288 BIT_CLK Period MHz 81.4 BIT_CLK Output Jitter Unit ns 750 ps TCLK_HIGH BIT_CLK Pulse Width (high) 32.56 40.7 48.84 ns TCLK_LOW BIT_CLK Pulse Width (low) 32.56 40.7 48.84 ns 60 % Max Unit TCLK_DC BIT_CLK Duty Cycle 40 TCLK_HIGH TCLK_LOW BIT_CLK TCLK_PERIOD Figure 9. BIT_CLK Timing Table 18. SYNC Timing Symbol Parameter Min SYNC Frequency TSYNC_PERIOD SYNC Period Typ 48 KHz 20.8 µs TSYNC_HIGH SYNC Pulse Width (high) 1.3 µs TSYNC_LOW SYNC Pulse Width (low) 19.5 µs TSYNC_HIGH = 16 TCLK_PERIOD TSYNC_LOW= 240 TCLK_PERIOD SYNC TSYNC_PERIOD Figure 10. SYNC Timing Revision 1.5, October 11, 2002 36 Data Sheet VT1616 6-Channel AC97 Codec with S/PDIF Table 19. Setup and Hold Timing Symbol Parameter Min Typ Max Unit TSETUP1 SDATA_OUT Setup to falling edge of BIT_CLK 15 ns THOLD1 SDATA_OUT Hold from falling edge of BIT_CLK 5 ns TSETUP2 SYNC Setup to rising edge of BIT_CLK 15 ns THOLD2 SYNC Hold to rising edge of BIT_CLK 5 ns Note: SDATA_IN setup and hold calculations determined by AC’97 controller propagation delay. TSETUP1 THOLD1 BIT_CLK SDATA_IN SDATA_OUT SYNC TSETUP2 THOLD2 Figure 11. Setup and Hold Timing Table 20. Rise and Fall Timing Symbol Parameter Min Typ Max Unit TRISE BIT_CLK rise time 2 6 ns TFALL BIT_CLK fall time 2 6 ns TRISE SYNC rise time 2 6 ns TFALL SYNC fall time 2 6 ns TRISE SDATA_IN rise time 2 6 ns TFALL SDATA_OUT fall time 2 6 ns TRISE SDATA_OUT rise time 2 6 ns TFALL SDATA_OUT fall time 2 6 ns BIT_CLK, SYNC SDATA_IN, SDATA_OUT TRISE TFALL Figure 12. Rise Time and Fall Timing Revision 1.5, October 11, 2002 37 Data Sheet VT1616 6-Channel AC97 Codec with S/PDIF Table 21. AC Link Low Power Mode Symbol TS2_PDOWN Note: Parameter Min Typ End of Slot 2 to BIT_CLK / SDATA_IN low Max Unit 1 µs BIT_CLK not to scale. SYNC Slot 1 Slot 2 BIT_CLK TS2_PDOWN SDATA_OUT SDATA_IN Figure 13. AC Link Power Mode Timing Revision 1.5, October 11, 2002 38 Data Sheet VT1616 6-Channel AC97 Codec with S/PDIF Table 22. ATE Test Mode Timing Symbol Parameter Min TSETUP2RST SDATA_OUT setup to RESET# rising edge TOFF Typ Max Unit 15 ns RESET# rising edge to Hi-Z state 25 ns TSETUP2RST RESET# SDATA_OUT SDATA_IN, BIT_CLK Hi-Z TOFF Figure 14. ATE Test Mode Timing Table 23. Vendor Test Mode Timing Symbol Parameter Min TSETUP2RST SYNC setup to RESET# rising edge TOFF Typ Max Unit 15 RESET# rising edge to Hi-Z state ns 25 ns TSETUP2RST RESET# SYNC BIT_CLK Hi-Z TOFF Figure 15. Vendor Test Mode Timing Revision 1.5, October 11, 2002 39 Data Sheet VT1616 6-Channel AC97 Codec with S/PDIF Package Dimensions A B Pin 1 Identifier Part Number Date Code and Chip Version D VT1616 YYMMVV LLLLLLLLL C Lot Code C M J E I K F H G Mechanical Dimensions Symbol A B C D E 8.6 6.9 8.6 6.9 0° F G H I J K 0.13 0.05 – 0.3 0.100 0.28 0.15 1.7 0.7 0.175 48-pin (7x7) LQFP minimum 0.5 maximum 9.4 7.1 9.4 7.1 10° Dimensions above are in millimeters, unless otherwise stated Revision 1.5, October 11, 2002 40 Data Sheet