SAMSUNG KB8825

Final version ( 99.4.30 )
1.1GHZ DUAL PLL
KB8825
INTRODUCTION
16−TSSOP−0044
The KB8825 is a high performance dual frequency synthesizer with
two integrated high frequency pre-scalers for RF operation up to 1.1
GHz.
The KB8825 is composed of modulus pre-scalers providing 64 and
66, no dead-zone PFD, selectable charge pump current, selectable
power down mode circuits, lock detector output, and loop filter’s time
constant switch.
It is fabricated using the ASP5HB Bi-CMOS process and is available
16-TSSOP with surface mount plastic packaging. Serial data is transferred into the KB8825 via three-wire interface (CK, DATA, EN).
FEATURES
•
Two systems for receiver and transmitter
•
Very low operating current consumption: Icc = Typ. 5.5mA @ 3.0V
•
Low operating power supply voltage : 2.2 ~ 5.5V ( 200MHz ~ 550MHz Operating )
2.7 ~ 3.6V ( 550MHz ~ 1.1GHz Operating )
•
Modulus pre-scaler: 64 / 66
•
No dead-zone PFD
•
Colpitt type local oscillation
•
Selectable charge pump current
•
Selectable power down mode
•
TSSOP 16-pin package (0.65 mm pitch)
ORDERING INFORMATION
Device
Package
Operating Temperature
+KB8825
16−TSSOP−0044
−30 °C to + 85 °C
+: New product
APPLICATIONS
•
Cordless telephone systems
•
Portable wireless communications (PCS)
•
Wireless Local Area Networks (WLANs)
•
Other wireless communication systems
1
Final version ( 99.4.30 )
KB8825
1.1GHZ DUAL PLL
BLOCK DIAGRAM
Fin1 1
VCC
1/2
Prescaler
1
32, 33
Prescaler
1
32, 33
Buffer
Buffer
2
CP1 3
GND 4
LD
5
CK
6
DATA 7
EN
Pre_Amp
Charge
Pump
1/2
2
Channel 1
Programable
Divider
Channel 2
Programable
Divider
Lock
Detector
6
Control
Circuit
17
12
Reference
Divider
Charge
Pump
14 CP2
Phase
Detector
13 GND
Switch
12
Local
OSC
11 OSCI
Buffer
PIN CONFIGURATION
Fin1
1
16
VCC
2
15
VCC
CP1
3
14
CP2
GND
4
13
GND
LD
5
12
SW
CK
6
11
OSCI
DATA
7
10
OSCO
EN
8
9
BO
16TSSOP
2
SW
10 OSCO
1/2
8
KB8825
16 Fin2
15 VCC
2
Phase
Detector
Pre_Amp
Fin2
9
BO
Final version ( 99.4.30 )
1.1GHZ DUAL PLL
KB8825
PIN DESCRIPTION
Pin No.
Symbol
I/O
Description
1
Fin1
I
Input terminal of channel 1 RF signal.
2, 15
Vcc
−
Power supply voltage input. PIN2 and PIN15 are connected together.
3
CP1
O
Output terminal of channel 1 charge pump. Charge pump is constant current output
circuit, and output current is selected by input serial data.
4, 13
GND
−
Terminal of GND. PIN4 and PIN13 are connected in common.
5
LD
O
Output terminal of lock detection. It is the open drain output.
6
CK
I
Input terminal of clock.
7
DATA
I
Input terminal of data.
8
EN
I
Input terminal of enable signal.
9
BO
O
Output terminal of buffer amplifier. The signal of local oscillation is output through the
buffer amplifier.
10
OSCO
O
Output terminal of local oscillation signal.
11
OSCI
I
Input terminal of local oscillation signal. In case of external input, connecting it to this
terminal.
12
SW
O
Switchover terminal for the time constant of loop filter. It is an open drain output. If
you don’t switch the time constant of loop filter, general output is available.
14
CP2
0
Output terminal of channel 2 charge pump. Charge pump is a constant current output
circuit, and the output current is selected by input serial data.
16
Fin2
I
Input terminal of channel 2 RF signal.
ABSOLUTE MAXIMUM RATINGS
Characteristic
Symbol
Value
Unit
Power Supply Voltage
Vcc
6
V
Power Dissipation
PD
600
mW
Operating temperature
TOPR
−30 ~ + 85
°C
Storage temperature
TSTG
−55~ +150
°C
Take care ! ESD sensitive device
3
Final version ( 99.4.30 )
KB8825
1.1GHZ DUAL PLL
ELECTRICAL CHARACTERISTICS
(Ta = 25°C, VCC = 3V, unless otherwise specified)
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Fin1=Fin2= 200MHz ~ 550MHz
2.2
3.0
5.5
V
Fin1=Fin2= 550MHz ~ 1.1GHz
2.7
3.0
3.6
V
3.5
5.5
7.5
mA
−
0
10
µA
200
−
1100
MHz
Vcc=2.2V
− 15
−
0
Vcc=3.0V
− 15
−
0
Vcc=5.5V
− 10
−
0
Vcc=2.2V
−15
−
0
Vcc=3.0V
−15
−
0
Vcc=5.5V
− 10
−
0
Vcc=2.7V
− 10
−
0
Vcc=3.0V
− 10
−
0
Vcc=3.6V
− 10
−
0
5
-
25
Vcc=2.2V
− 10
0
5
Vcc=3.0V
− 10
0
5
Vcc=5.5V
0
-
5
Vcc=2.2V
− 10
0
5
Vcc=3.0V
− 10
0
5
Vcc=5.5V
−5
0
5
Operating Power supply
voltage
VCC
Operating current
consumption
ICC
Fin1=Fin2=1.1GHz/ -5dBm input
Standby current
ISB
Standby mode
Fin operating frequency
Fin
Fin1 = Fin2 = − 5dBm
Fin1 = Fin2
= 200MHz
Fin input sensitivity
Fin
Fin1 = Fin2
= 550MHz
Fin1 = Fin2
= 1.1GHz
OSCI operating frequency
Fosc
VFin = 0dBm, sinewave
fosc = 10MHz
OSCI input voltage
Vosc
fosc = 20MHz
dBm
MHz
dBm
Serial data input high
voltage (CK, DATA, EN)
VIH
VCC = 2.2 to 5.5V
VCC −
0.4
−
−
V
Serial data input low voltage
(CK, DATA, EN)
VIL
VCC = 2.2 to 5.5V
−
−
0.4
V
ICP1
CP1 = 0, CP2 = 0
VCP = 1.5 V
–
± 100
−
µA
ICP2
CP1 = 0, CP2 = 1
VCP = 1.5V
–
± 200
−
µA
ICP3
CP1 = 1, CP2 = 0
VCP = 1.5V
−
± 400
−
µA
ICP4
CP1 = 1, CP2 = 1
VCP = 1.5V
−
± 800
−
µA
ICPL
Standby mode, Vcp = 1.5V
−1
−
+1
µA
Charge pump output
current
Charge pump leakage
4
Final version ( 99.4.30 )
1.1GHZ DUAL PLL
KB8825
FUNCTIONAL DESCRIPTIONS
SERIAL DATA INPUT AND TIMING
CK (Pin6), DATA (Pin7), EN (Pin8) terminals in KB8825 are used for MICOM (MPU) serial data interface (MSB: 1st
input data; LSB: Last input data). Serial data controls the programmable reference divider, programmable divider
(CH1), programmable divider (CH2), and control latch separately by means of group code. Binary serial data is
entered via the DATA pin.
One bit of data is shifted into the internal shift register on the rising edge of the clock. When EN pin is high, stored
data is latched. The three terminals, CK, DATA, and EN, contain Schmitt trigger circuits to keep the data from
errors caused by noise, etc.
< Notice >
1. When power supply of KB8825 is disconnected, CLK, DATA, EN port from MCU should be pulled low.
2. When power goes up first, R counter data should be entered earlier than N1 and N2 counter data.
3. When power goes up first, control data should be entered earlier than N1 and N2 counter data.
≥ 1us
CK
DATA
MSB
N1 (R1)
≥ 0.2us
≥
0.2us
≥
≥0.2us
N2 (R2)
LSB
N3 (R3)
N16 (R11)
N17 (R12)
GC2
GC1
≥0.1us
≥ 0.1us
MSB
EN
≥ 0.2us
≥ 0.2us
Figure 1.
NOTE: Start data input with MSB first
SERIAL DATA GROUP AND GROUP CODE
The IC can be controlled through 4 kinds of group selection. Each group is identified by selective a 2-bit group code
given below.
Serial Bits
Group Location
GC1 (LSB)
GC2 (LSB-1)
0
0
Control Latch
0
1
Ch 1 N Latch
1
0
Ch 2 N Latch
1
1
OSC R Latch
5
Final version ( 99.4.30 )
KB8825
1.1GHZ DUAL PLL
CONTROL LATCH
The control register executes the following functions:
•
Mode selection (H: test mode, L: normal mode)
•
Charge pump’s polarity and output current selection for each channel.
•
Output state selection for Lock Detector.
•
Standby control of each channel and reference divider.
•
ON / OFF control in filter switch.
MSB
T
CH1
CP
CP1
CH2
CP2
SB1
CP1
LSB
CP2
SB2
SBR
LD1
LD2
SW
GC2
"0"
GC1
"0"
Group Code
Figure 2.
Bit
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Name
T
CP
CP1
CP2
SB1
CP1
CP2
Description
test mode
charge
pump out
polarity
channel 1
charge
pump
output
current
channel 1
charge
pump
output
current
channel 1
standby
channel 2
charge
pump
output
current
channel 2
charge
pump
output
current
Bit
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Name
SB2
SBR
LD1
LD2
SW
GC2
GC1
Description
channel 2
standby
reference
divider
standby
lock
detector
control 1
lock
detector
control 2
filter switch
group code
“0”
group code
“0”
6
Final version ( 99.4.30 )
1.1GHZ DUAL PLL
KB8825
CHARGE PUMP OUTPUT POLARITY (CP)
In normal operation, the CP should be “0”. In reverse operation, the CP should be
“1”.
Depending upon VCO characteristics, CP should be set accordingly;
When VCO characteristics are like (1), CP should be set low
When VCO characteristics are like (2), CP should be set high.
VCO Characteristics
(1)
VCO
Output
Frequency
(2)
VCO Input Voltage
CHARGE PUMP OUTPUT CURRENT (CP1, CP2)
The KB8825 includes a constant current output type charge pump circuit.
Output current is varied according to control bit “CP1” and “CP2”.
In order to get high speed lock-up, select the best charge pump output current.
Control Bit
CP1
CP2
Charge Pump
Output Current
0
0
±100 µA
0
1
±200 µA
1
0
±400 µA
1
1
±800 µA
7
Final version ( 99.4.30 )
KB8825
1.1GHZ DUAL PLL
TEST MODE AND LOCK DETECTOR OUTPUT (T, LD1, LD2)
When T is normal “0”, LD (Pin5)state is varied by controlling “SB1”, “SB2”, “LD1” and “LD2”.
When T is high “1”, LD (Pin5) state is changed to be useful for test
T
SB1
SB2
0
0
1
0
0
1
1
1
0
1
0
8
1
LD1
LD2
LD Output State
0
0
low
0
1
channel2
1
0
channel1
1
1
channel1. AND. channel2
0
0
low
0
1
high
1
0
channel1
1
1
channel1
0
0
low
0
1
channel2
1
0
high
1
1
channel2
0
0
low
0
1
high
1
0
high
1
1
high
0
0
low
0
1
pres2
1
0
fpll2
1
1
fref
0
0
div4
0
1
pres1
1
0
fpll1
1
1
fosc/2
1
1
×
×
low
0
0
×
×
low
Final version ( 99.4.30 )
1.1GHZ DUAL PLL
KB8825
LOCK DETECTOR OUTPUT
When the phase comparator detects a phase difference, LD (Pin5) outputs “L”.
When the phase comparator locks, LD outputs “H”. On standby, it outputs “H”.
When T is less than 2/fosc (T<2 /fosc ) for more than three cycles of reference divider output as in the figure below,
the lock detector outputs “H”.
A
B
Reference
Divider output
Channel
Divider output
T
Charge pump
output
T<2/fosc
Lock detector
output
Figure 3. Lock Detector Output
fosc: OSCI operating frequency (LOCAL OSC).
T: time difference of the pulse between reference divider output and channel divider output.
A =
B =
Number of divisions by reference divider
fosc
2
fosc
(s)
(s)
PROGRAMMABLE STANDBY MODE (SB1, SB2, SBR)
Standby mode can be controlled by 3-control bits such as SB1, SB2 and SBR. SB1 and SB2 can control standby
mode of channel 1 and channel2. The “SBR” bit can do ON / OFF control of reference divider.
Control Bit
Standby Mode State
SB1
SB2
SBR
CH1
CH2
REF
Mode Status
0
0
×
ON
ON
ON
Inter locking Mode
0
1
×
ON
OFF
ON
CH1 Locking Mode
1
0
×
OFF
ON
ON
CH2 Locking Mode
1
1
0
OFF
OFF
ON
REF On Mode
1
1
1
OFF
OFF
OFF
Standby Mode
9
Final version ( 99.4.30 )
KB8825
1.1GHZ DUAL PLL
FILTER SWITCH CONTROL (SW)
The operation mode of the SW terminal is set by bit “SW”.
SW control is useful for switching the time canstant of the loop filter.
Output type of this terminal is an open drain output. High lock mode or normal lock mode can be used, taking
advantage of filter switch control (SW) with the charge pump output current.
When fast lock function can’t be used, normal lock mode is available.
Control Bits
Operation Mode
SW
CP1
CP2
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
(SW and LPF example) The third order LPF
Normal Lock Mode
CP1
R
R
SW
R
High Lock Mode
GND
CRYSTAL OSCILLATOR CIRCUIT (OSCI, OSCO) AND BUFFER OUT (BO)
External capacitors C1, C2, C3, and C4 are required to set the proper crystal’s load capacitance and oscillation
frequency as shown in figure 4. The value of the capacitors is dependent on the crystal chosen.
The BO (Pin9) outputs local oscillation signal with buffer amplifier.
This terminal (Pin9) can be applied to the 2nd mixer input
C4
1000pF
OSCI
OSCI
C1
C2
OSCO
OSCO
1000pF
1000pF
BO
2'nd MIX
or OPEN
BO
Figure 4.
10
Reference Oscillator
C3
C2
2'nd MIX
or OPEN
Final version ( 99.4.30 )
1.1GHZ DUAL PLL
KB8825
PROGRAMMABLE REFERENCE COUNTER
This block generates the reference frequency for the PLL.
The reference divider is composed of 12-bit reference divider and a half fixed divider
Sending certain data to the reference divider allows the setting of any of 6 to 8190 divisions (multiple of two).
MSB
R1
LSB
R2
R3
R4
R5
R6
R7
R8
R9
R10 R11 R12
Division Ratio of the R counter, R
GC2
"1"
GC1
"1"
Group Code
R = R1 × 20 + R2 × 21 + … + R12 × 211
Division ratio: 2 × R = 2 × (3~4095) = 6 ~ 8190
Data is shifted in MSB first.
Division
Ratio
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
3
0
0
0
0
0
0
0
0
0
0
1
1
4
0
0
0
0
0
0
0
0
0
1
0
0
•
•
•
•
•
•
•
•
•
•
•
•
•
4095
1
1
1
1
1
1
1
1
1
1
1
1
Example) A 21.25MHz X-tal oscillator is connected, and divided into 25kHz steps.
(Reference frequency is 12.5kHz)
21.25 MHz ÷ 12.5 kHz = 1700
1700 = 2 × R
R = (850)10 = (1101010010)2
MSB
0
LSB
1
0
0
1
0
1
0
1
1
0
0
1
1
11
Final version ( 99.4.30 )
KB8825
1.1GHZ DUAL PLL
CHANNEL 1, CHANNEL 2 PROGRAMMABLE N COUNTER
These programmable dividers are composed of a 5-bit swallow counter (5-bit programmable divider),
12-bit programmable main counter, and two-modulus prescalers providing 64 and 66 divisions.
Sending certain data to the swallow counter and the 12-bit programmable main counter allows the setting of any of
2048 to 262142 divisions (multiple of two).
The 12-bit programmable divider and swallow counter are set by each channel;
each channel is identified by a group code.
MSB
N1
Swallow counter
N2
N3
N4
LSB
main counter
N5
N6
N7
N8
N9
N10
N11
N12
N13
N14
N15
N16
N17
Division Ratio of the N Counter, N
N18
N19
Group Code
CH1 = "10"
CH2 = "01"
Figure 5.
5-BIT SWALLOW COUNTER DIVISION RATIO (A COUNTER)
A = N1 × 20 + N2 × 21 … N5 × 24
Division ratio: 0 to 31, B ≥ A
Division Ratio
(A)
N5
N4
N3
N2
N1
0
0
0
0
0
0
1
0
0
0
0
1
•
•
•
•
•
•
31
1
1
1
1
1
12-BIT MAIN COUNTER DIVISION RATIO (B COUNTER)
B = N6 × 20 + N7 × 21 + N7 × 22 … N17× 211
Division ratio: 3 to 4095
Data is shifted in MSB first
Division
Ratio (B)
N17
N16
N15
N14
N13
N12
N11
N10
N9
N8
N7
N6
3
0
0
0
0
0
0
0
0
0
0
1
1
4
0
0
0
0
0
0
0
0
0
0
0
0
•
•
•
•
•
•
•
•
•
•
•
•
•
4095
1
1
1
1
1
1
1
1
1
1
1
1
12
Final version ( 99.4.30 )
1.1GHZ DUAL PLL
KB8825
Channel1 and 2 Programmable Counter Division Ratio, N
N = 2 × (32 × B + A), B ≥ A
Division ratio: 192 ~ 262142
Example) A Signal of 453 MHz is entered into Fin1, and divided into 25 kHz steps.
(Reference frequency is 12.5 kHz)
453 MHz ÷ 12.5 kHz = 36240
36240 = 2 × (32 × B + A)
∴ B = (1132)10 = (10001101100)2, A = (16)10 = (10000)2
MSB
LSB
0
0
0
0
1
0
0
1
1
0
1
1
0
0
0
1
0
1
0
Example) A Signal of 462.9 MHz is entered into Fin2, and divided into 25 kHz step.
(Reference frequency is 12.5 kHz)
462.9 MHz ÷ 12.5 kHz = 37032
37032 = 2 × (32 × B + A)
∴ B = (1157)10 = (10010000101)2, A = (8)10 = (01000)2
MSB
0
LSB
0
0
1
0
1
0
1
0
0
0
0
1
0
0
1
0
0
1
PHASE DETECTOR AND CHARGE PUMP CHARACTERISTICS
Phase difference detection Range: -2 π ~ +2 π
When SW = Low
fr
fp
LD
CPO
fr > fp
fr = fp
fr < fp
fr < fp
fr < fp
Figure 6.
13
Final version ( 99.4.30 )
KB8825
1.1GHZ DUAL PLL
APPLICATION CIRCUIT ( HANDSET )
RX_VCC
RX_VCC
2 3
2
3
9
1
10
1
RSSI
1
IIFLT2
7
2
IFLT3
5
IFLT4
4
6
OSC
DECPL
8
1
2
2
1
100p
1
1
1
1
1
2
R18
2
2
2
1K
2
2
2
1
1
R212
OSCI
7
1
2
R31R30R29
1K 1K 1K
1
3
1
1
1
2
L10
C4228
TP6
2
1
2
Q10
3p
CP2
R40
1
5.6K
23
2
2
R36
1
2
1
R35
2
1
2
1
1SV239
10N
1
2
1
C55
1
2
220N
2
1
R37
2
1
560
2
1
R38
C57
15K
1N
C54
10N
1
C56
C60
2p
R34
30K
D2
2
2p
1
2
0.5X1.0X1.5t
7.5K
1
10K
2
1p
1
220
10K
L9
1
C63
2
R41
C59
1
1
2
R39
3p
2
2
3p
2
1
2p
C58
1
1p
C62
1
C65
2
2
1
C61
1
Q9
C4228
2
1
1
220N
2
C67
2
2
C53
C52
100p
2
RX_VCC
2
1
3
1
100p
1
100
1
1
R32
2
2
1
2
2
2
8
1
2
2
1
47p
EN
DATA
5
2
1
1
1
1
2
BO
4
RX_VCC
TX_VCC
18K
C68
OSCO
3
6
GND
2
LD
CP1
1
CLK
VCC
2
51
L11 R43
C70
9
S/W
FIN1
1
TX VCO
220N
5.6K
10
11
1
1
1
R33
1
15p
C64
100N
R44
12
2
2
2
2
GND
1
1
2
KB8825
RX_VCO
TX_VCC
1
1N
100
L6
220
CP2
1 2
R19
C36
220N
0.5X1.0X1.5t
C66
VCC
2
FIN2
1
1
1
2
2
2p
R421
C34
2
51K
C41
220N
13
8.2N
14
R20
16
8.2N
15
C38 C37
1SV239
2
47p
2
2.2K
2
D1
1 2
10K
1
10K
2
1
2
1p
1
1
C71
2
2
2
2
1
C44
3p
2p
R23
R25
R22
1
C40
1
3p
2p
C35
1
C39
1
1
1
1
N.A
2
1
14
3
1
IFLT1
3
100N1.5N
1
1
3
C43
2
C73
39p
2~6p
Y1
C69
Q11 2
C32 C31
C33
C27C26
1
2
2
1
TX_VCO1
1
C4228
470
10.63MHz
C42
2
220
L12
RFIN+
VCC
2
1
1
2
2
2
925~927MHz
100N
1
2
1
1
2
Q7
C4228
2p
C72
R16
1
1
15p 3p
TX_VCC
220
1
100N
5.6K
C45
1N
2
C29
4.7N 10K
1
C30 R17
CP1
R24
L7
2
L13
R45
RSSI AF_OUT
C25
TP5
23
Q8
1
2
RX VCO
RX_VCC
C4228
C51C48
C74
11
13
RFIN-
2
1
220N
2
C46
100N
1
1
1
2
6p
2
560p
18K
2
1
15N
1
4
RX_VCO
12
14
TMC
GND
DEMO
1
C28
1
2
6
1
1
TP41
2
2
AFO
AFLT2
AFLT1
2
R272
C47
C49
1
100
KA8532
2
1
2
1
4p
U1
2
2
1
L8 R26
1
Q5
1
2
1
2
2
2
F2
SF X033H
1
2 5
3
Q6
KSC1623Y
2
R15
Q4
680
3.9nH
2
1
RSSI
KSC1623Y
RX_VCC
220
R28
7p
6.8K
100N
3
2
1
1
6p
C50
1
6.8N
TP3
1
R131 2
2
2
2
N.A
560
15
1
1
2
902~905MHz
C75
16
1
2
10N
2
C1510.7MHz
R7
10N
C1
4.7K
1
C16
1
KSC2223Y
C12
10K
F1
2
1
6p
C14
1N
2
2
2
1
2
8.2nH
22K
1
2
2p
L15 L14
5p
1
6p
C10 R6
10N
R9
150p
3
4
SGM2016M
1
C7
L1
C76
6p
C4228
C5
1
2
2
Q2
1
1
C4228
2
1
1
5p
Q3
2
3
2
C13
2
2
2 1
3
Q1
1
2
2
2
2
L3
1
47K
220N 3.3uH
100K
C24
1
2
1
1
R1
L4
C9
R4
1
C11 L5
1
2
C4
4.7K
2
10N
L2
R2
1
2
2
1
10N
ANT1
C8
1
C3
2
1
1
1
220
1
1
2
1
2
1
2
R3
2
C18
220N220
2.7K
R11
C23
6.8K
2.2K
R12
2
R10
C6 R5
220N
1
IF
1
1
10N 330
R14
1
1
1
1
TP2
C22
220p
1
TP11 1
AF_OUT
1
2
C17R8
C2
2
2
100p 1.2N
1
C20 C21
2
2
C19
1.5N
CNT1
11
RX VCC
9 AF_OUT
7 GND GND
5 RSSI LDT
TX
VCC
CLK
3
DATA
1 AF IN
GND EN
12
10
8
6
4
2
Final version ( 99.4.30 )
1.1GHZ DUAL PLL
KB8825
APPLICATION CIRCUIT ( BASESET )
RX_VCC
RX_VCC
2 3
2
3
1
1
3
9
10
11
1
RSSI
1
IIFLT2
IFLT1
2
7
IFLT3
IFLT4
5
6
4
DECPL
VCC
OSC
8
1
2
2
1
C32 C31
100p
1
39p
1
1
C33
1~10p
1
1
C27C26
100N1.5N
2
R18
2
2
2
2
1
1.8K
2
2
23
Y1
1
1
10.63MHz
1
2
C42
2
2
C39
1
2
2
1
R212
1
1
R31R30R29 C52
2
2
RX_VCC
CNT1
11
RX VCC
9 AF_OUT
7 GND GND
5 RSSI LDT
CLK
3 TX VCC
DATA
1 AF IN
GND EN
12
10
8
6
4
2
2
2
2
2
1
C53
3
220N
1
1
2
2
Q10
2p
1
2
L15
C4228
TP6
2
1
C67
N.A
100p
1K 1K 1K
1
1
3
1
100p
1
2
2
100
1
1
R32
220N
1
2
2
1
47p
8
TX_VCC
2
2
2
C68
2
9
7
4
6
3
RX_VCC
51
1
1
1
1
1
EN
2
2
TX VCO
18K
C70
BO
GND
1
5
CP1
CLK
VCC
DATA
FIN1
LD
1
1
R33
1
L14 R43
2
OSCO
OSCI
KB8825
C64
5.6K
10
11
12
S/W
100
RX_VCO
1
R421 TX_VCC
15p
100N
GND
2
2
1
C66
R44
13
1
1
2
2
0.5X1.0X1.5t
220
CP2
1 2
R19
C36
220N
L12
2
VCC
2
FIN2
1
1
2
2
1p
2
1
1N
51K
C41
220N
14
8.2N
16
R20
15
C38 C37
8.2N
C34
2
2
2
2.2K
2
47p
1
1 2
2
1p
1
1
C71
10K
1SV239
2p
10K
1
2
1
1
C44
2
D1
C40
R23
R25
1
3p
2
2
3p
2p
1
2
1
R22
1
1
1
C43
C35
1
1
3
1
2
1
2
Q7
C4228
TX_VCC
Q11 2
RFIN+
3
1
470
C69
L13
R16
1
1
15p 3p
220
C4228
1
100N
5.6K
1
TX_VCO1
1
C73
2
C29
4.7N 10K
1
2
1
2
4
2
925~927MHz
220N
RSSI AF_OUT
C25
CP1
L10 R24
2p
C72
1
TP5
C45
220
2
2
2
1
C30 R17
1
6
1
1
Q8
1
R26
2
1N
RFIN-
GND
2
RX VCO
RX_VCC
L11
C74
12
AFO
1
C28
2
220N
C4228
C51C48
R45
13
14
TMC
1
2
1
C46
18K
2
6p
100
1
DEMO
2
1
2
2
2
1
TP4 1
RX_VCO
Q5
KSC1623Y
560p
100N
L9
4p
Q6
KSC1623Y
15N
C47
C49
1
1
6.8K
2
KA8532
2
680
F2
SF X034B
1
2 5
3
100N
1
RSSI
R131 2
2
1
2
1
R28
7p
1
6.8N
U1
R272
1
220
C50
100K
C24
TP3
1
R15
Q4
1
2
1 1
2
2
2
2
2
RX_VCC
3.9nH
C75
AFLT2
AFLT1
2
N.A
560
R11
2
1
C1510.7MHz
10N
6p
902~905MHz
2
2.2K
2.7K
3
10N
2
15
1
C16
1
R7
C12
10K
16
1
2
F1
2
KSC2223Y
2
6p
C14
1N
C1
4.7K
1
22K
1
SGM2016M
C10 R6
10N
R9
150p
3
4
2
2
2
1
2
8.2nH
C13
2
2p
1
2
1
C7
6p
L7
L8
5p
6p
C4228
C5
L6
C76
1
Q2
1
1
R1
5p
C4228
2
1
Q1
1
3
2
2
Q3
2
1
2 1
220N 3.3uH
2
1
L4
1
2
2
2
ANT1
C9
2 3
1
C4
C11 L1
L2
47K
L3
4.7K
2
10N
R4
1
2
2
10N
R2
1
2 1
2 1
1
C8
1
C3
2
1
1
1
220
1
1
2
1
2
1
2
220N
C23
6.8K
C18
220N220
R14
R12
2
2
1
R10
C6 R5
R3
1
1
IF
1
1
1
1
TP2
10N 330
C22
220p
1
TP11 1
AF_OUT
1
2
C17R8
C2
2
2
100p 1.2N
1
C20 C21
2
2
C19
1.5N
CP2
R40
1
5.6K
23
2
2
2 R36 1
1
R35
2
1
30K
1SV239
10N
10N
1
C60
C55
1
1
2
2p
C54
1
C56
2
D2
2
0.5X1.0X1.5t
R34
1
2
2p
1
7.5K
2
L16
1
2p
2
C63
220
10K
1
R39
R41
C59
1
2
2
2 1
3p
3.5p
2
1p
2
1
1
2p
C58
1
10K
C62
1
C65
2
2
1
C61
1
Q9
C4228
220N
2
1
2 R37 1
560
2
1
R38
C57
15K
1N
2
1
15
Final version ( 99.4.30 )
KB8825
1.1GHZ DUAL PLL
CHARACTERISTIC GRAPH
800§Ë
400§Ë
200§Ë
100§Ë
100§Ë
200§Ë
400§Ë
800§Ë
16
Final version ( 99.4.30 )
1.1GHZ DUAL PLL
KB8825
100§Ë
200§Ë
400§Ë
800§Ë
800§Ë
400§Ë
200§Ë
100§Ë
17
Final version ( 99.4.30 )
KB8825
1.1GHZ DUAL PLL
INPUT SENSITIVITY Vin1 (dBm)
INPUT SENSITIVITY -INPUT FREQUENCY (Fin1)
30
20
10
0
.
-10
-20
-30
-40
0
100
200
300
400
500
600
700
800
900
1000
1100
INPUT FREQUENCY Fin1 (MHz)
INPUT SENSITIVITY Vin1 (dBm)
INPUT SENSITIVITY - POWER SUPPLY VOLTAGE (Fin1)
30
20
10
0
500M_min
-10
1100M_mi
500M_Max
1100M_Max
-20
-30
-40
2.2
2.5
3
3.5
4
4.5
5
INPUT FREQUENCY Fin1 (MHz )
18
5.5
6
Final version ( 99.4.30 )
1.1GHZ DUAL PLL
KB8825
INPUT SENSITIVITY Vin2 (dBm)
INPUT SENSITIVITY -INPUT FREQUENCY (Fin2)
30
20
10
0
-10
-20
-30
0
100
200
300
400
500
600
700
800
900
1000
1100
INPUT FREQUENCY Fin2 (MHz)
INPUT SENSITIVITY - POWER SUPPLY VOLTAGE (Fin2)
INPUT SENSITIVITY Vin2 (dBm)
30
20
10
0
500_min
500_Max
-10
1 1 0 0 _ min
1100_Max
-20
-30
-40
2.2
2.5
3
3.5
4
4.5
5
5.5
6
INPUT FREQUENCY Fin2 (MHz)
19
Final version ( 99.4.30 )
KB8825
1.1GHZ DUAL PLL
X I N I N P U T S E N S IT IV IT Y
30
20
Vxin (dBm)
10
0
-1 0
-2 0
-3 0
-4 0
5
10
15
20
25
Fxin (M Hz )
CURRENT CONSUMPTION- POWER SUPPLY VOLTAGE
CURRENT CONSUMPTION Icc (mA)
7
6
5
4
3
2
1
0
0
1
2
3
4
POWER SUPPLY VOLTAGE VCC (V)
20
5
6
Final version ( 99.4.30 )
1.1GHZ DUAL PLL
KB8825
NOTES
21