PCF2123 SPI Real time clock/calendar Rev. 02 — 4 December 2009 Product data sheet 1. General description The PCF2123 is a CMOS1 Real-Time Clock (RTC) and calendar optimized for low power applications. Data is transferred serially via a Serial Peripheral Interface (SPI-bus) with a maximum data rate of 6.25 Mbit/s. An alarm and timer function is also available providing the possibility to generate a wake-up signal on an interrupt pin. An offset register allows fine tuning of the clock. 2. Features n Real time clock provides year, month, day, weekday, hours, minutes, and seconds based on a 32.768 kHz quartz crystal n Low backup current while running: typical 100 nA at VDD = 2.0 V and Tamb = 25 °C n Resolution: seconds to years n Watchdog functionality n Freely programmable timer and alarm with interrupt capability n Clock operating voltage: 1.1 V to 5.5 V n 3 line SPI-bus with separate, but combinable data input and output n Serial interface at VDD = 1.6 V to 5.5 V n 1 second or 1 minute interrupt output n Integrated oscillator load capacitors for CL = 7 pF n Internal Power-On Reset (POR) n Open-drain interrupt and clock output pins n Programmable offset register for frequency adjustment 3. Applications n n n n n n 1. Time keeping application Battery powered devices Metering High duration timers Daily alarms Low standby power applications The definition of the abbreviations and acronyms used in this data sheet can be found in Section 19. PCF2123 NXP Semiconductors SPI Real time clock/calendar 4. Ordering information Table 1. Ordering information Type number Package Name Description Version PCF2123TS TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 PCF2123BS HVQFN16 plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 3 × 3 × 0.85 mm SOT758-1 PCF2123U/10AA PCF2123U/10 wire bond die; 12 bonding pads; 1.492 × 1.449 × 0.20 mm[1] PCF2123U/10 PCF2123U/12AA PCF2123U/12 WLCSP12; wafer level chip size package; 12 bumps; 1.492 × 1.449 × 0.22 mm[2] PCF2123U/12 [1] Sawn wafer on Film Frame Carrier (FFC). [2] Sawn wafer with gold bumps on Film Frame Carrier (FFC). 5. Marking Table 2. Marking codes Type number Marking code PCF2123TS PCF2123 PCF2123BS 123 PCF2123U/10AA PC2123-1 PCF2123U/12AA PC2123-1 PCF2123_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 December 2009 2 of 55 PCF2123 NXP Semiconductors SPI Real time clock/calendar 6. Block diagram OSCI CLKOE COSCI OSCILLATOR 32.768 kHz DIVIDER CLKOUT CLOCK OUT OSCO COSCO MONITOR OFFSET FUNCTION 0Dh Offset_register TIMER FUNCTION TEST VDD 0Eh Timer_clkout 0Fh Countdown_timer VSS CONTROL POWER ON RESET 00h Control_1 01h Control_2 TIME WATCH DOG SDO SPI INTERFACE SDI SCL 02h Seconds 03h Minutes 04h Hours 05h Days 06h Weekdays 07h Months 08h Years ALARM FUNCTION CE Rpd PCF2123 09h Minute_alarm 0Ah Hour_alarm 0Bh Day_alarm 0Ch Weekday_alarm INT INTERRUPT 013aaa223 Fig 1. Block diagram of PCF2123 PCF2123_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 December 2009 3 of 55 PCF2123 NXP Semiconductors SPI Real time clock/calendar 7. Pinning information OSCI 1 14 VDD OSCO 2 13 CLKOUT n.c. 3 12 CLKOE TEST 4 INT 5 10 SCL CE 6 9 SDI VSS 7 8 SDO 13 VDD OSCO 1 12 CLKOUT TEST 2 INT 3 10 SCL CE 4 9 11 CLKOE 6 7 8 n.c. n.c. SDO 001aai551 5 PCF2123 11 n.c. VSS PCF2123 14 n.c. terminal 1 index area 15 n.c. 16 OSCI 7.1 Pinning SDI 001aai550 Transparent top view Top view. For mechanical details, see Figure 30. Fig 2. For mechanical details, see Figure 31. Pin configuration for TSSOP14 (PCF2123TS) Fig 3. OSCI 7 OSCO 8 TEST 9 INT 10 CE 11 VSS 12 Pin configuration for HVQFN16 (PCF2123BS) 6 VDD 5 CLKOUT 4 CLKOE 3 SCL 2 SDI 1 SDO PCF2123U 001aai544 Viewed from active side. For mechanical details, see Figure 32 and Figure 33. Fig 4. Pin configuration for PCF2123U/10 (bare die) and PCF2123U/12 (bare die) PCF2123_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 December 2009 4 of 55 PCF2123 NXP Semiconductors SPI Real time clock/calendar 7.2 Pin description Table 3. Symbol Pin description Pin Description TSSOP14 HVQFN16 PCF2123Ux OSCI 1 16 7 oscillator input; high-impedance node; minimize wire length between quartz and package OSCO 2 1 8 oscillator output; high-impedance node; minimize wire length between quartz and package n.c. 3, 11 6, 7, 14, 15 - do not connect and do not use as feed through; connect to VDD if floating pins are not allowed TEST 4 2 9 test pin; not user accessible; connect to VSS or leave floating (internally pulled down) INT 5 3 10 interrupt output (open-drain; active LOW) CE 6 4 11 chip enable input (active HIGH) with internal pull down VSS 7 5[1] 12[2] ground SDO 8 8 1 serial data output, push-pull; high-impedance when not driving; can be connected to SDI for single wire data line SDI 9 9 2 serial data input; may float when CE is inactive SCL 10 10 3 serial clock input; may float when CE is inactive CLKOE 12 11 4 CLKOUT enable or disable pin; enable is active HIGH CLKOUT 13 12 5 clock output (open-drain) VDD 14 13 6 supply voltage; positive or negative steps in VDD may affect oscillator performance; recommend 100 nF decoupling close to device (see Figure 29) [1] The die paddle (exposed pad) is wired to VSS but should not be electrically contacted. [2] The substrate (rear side of the die) is wired to VSS but should not be electrically contacted. 8. Device protection diagram PCF2123 VDD OSCI CLKOE OSCO CLKOUT TEST SCL INT SDI CE SDO VSS 001aai552 Fig 5. Device diode protection diagram of PCF2123 PCF2123_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 December 2009 5 of 55 PCF2123 NXP Semiconductors SPI Real time clock/calendar 9. Functional description The PCF2123 contains 16 8-bit registers with an auto-incrementing address counter, an on-chip 32.768 kHz oscillator with two integrated load capacitors, a frequency divider which provides the source clock for the Real Time Clock (RTC), a programmable clock output, and a 6.25 Mbit/s SPI-bus. An offset register allows fine tuning of the clock. All 16 registers are designed as addressable 8-bit parallel registers although not all bits are implemented. • The first two registers (memory address 00h and 01h) are used as control registers. • The memory addresses 02h through 08h are used as counters for the clock function (seconds up to years). The registers Seconds, Minutes, Hours, Days, Weekdays, Months, and Years are all coded in Binary Coded Decimal (BCD) format. When one of the RTC registers is read the contents of all counters are frozen. Therefore, faulty reading of the clock and calendar during a carry condition is prevented. • • • • Addresses 09h through 0Ch define the alarm condition. Address 0Dh defines the offset calibration. Address 0Eh defines the clock out and timer mode. Address registers 0Eh and 0Fh are used for the countdown timer function. The countdown timer has four selectable source clocks allowing for countdown periods in the range from 244 µs up to four hours. There are also two pre-defined timers which can be used to generate an interrupt once per second or once per minute. These are defined in register Control_2 (01h). 9.1 Low power operation Minimum power operation will be achieved by reducing the number and frequency of switching signals inside the IC, i.e., low frequency timer clocks and a low frequency CLKOUT will result in lower operating power. A second prime consideration is the series resistance Rs of the quartz used. 9.1.1 Power consumption with respect to quartz series resistance The series resistance acts as a loss element. Low Rs will reduce current consumption further. PCF2123_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 December 2009 6 of 55 PCF2123 NXP Semiconductors SPI Real time clock/calendar 001aai558 250 IDD(1) (nA) 210 170 130 90 50 0 20 40 60 80 Rs(2) (kΩ) 100 Configuration: CLKOUT disabled, VDD = 3 V, timer clock set to 1⁄60 Hz. (1) IDD (nA) minimum power mode. (2) Maximum value for RS is 100 kΩ. Fig 6. IDD with respect to quartz RS 9.1.2 Power consumptions with respect to timer mode Four source clocks are possible for the timer. The 4.096 kHz source clock will add the greatest part to the power consumption. The selection of 64 Hz, 1 Hz or 1⁄60 Hz will be almost indistinguishable and add very little. 001aai559 400 IDD(1) (nA) 300 (2) 200 (3) 100 0 0 2 4 6 VDD (V) Configuration: CLKOUT disabled, quartz RS = 15 kΩ. (1) IDD (nA) minimum power mode. (2) Timer clock = 4 kHz. (3) Timer clock = 64 Hz, 1 Hz, 1⁄60 Hz. Fig 7. IDD with respect to timer clock selection PCF2123_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 December 2009 7 of 55 PCF2123 NXP Semiconductors SPI Real time clock/calendar 9.2 Register overview 16 registers are available. The time registers are encoded in the Binary Coded Decimal (BCD) format to simplify application use. Other registers are either bit-wise or standard binary. Table 4. Registers overview Bit positions labelled as - are not implemented and will return a 0 when read. Bit positions labelled with N should always be written with logic 0[1]. Address Register name Bit 7 6 5 4 3 2 1 0 Control and status registers 00h Control_1 EXT_TEST N STOP SR N 12_24 CIE N 01h Control_2 MI SI MSF TI_TP AF TF AIE TIE Time and date registers 02h Seconds OS SECONDS (0 to 59) 03h Minutes - MINUTES (0 to 59) 04h Hours - - AMPM HOURS (1 to 12) in 12 h mode HOURS (0 to 23) in 24 h mode 05h Days - - DAYS (1 to 31) 06h Weekdays - - - - 07h Months - - - MONTHS (1 to 12) 08h Years YEARS (0 to 99) - WEEKDAYS (0 to 6) Alarm registers 09h Minute_alarm AE_M MINUTE_ALARM (0 to 59) 0Ah Hour_alarm AE_H - AMPM HOUR_ALARM (1 to 12) in 12 h mode HOUR_ALARM (0 to 23) in 24 h mode 0Bh Day_alarm AE_D - DAY_ALARM (1 to 31) 0Ch Weekday_alarm AE_W - - MODE OFFSET[6:0] COF[2:0] - - WEEKDAY_ALARM (0 to 6) TE - Offset register 0Dh Offset_register Timer registers 0Eh Timer_clkout - 0Fh Countdown_timer COUNTDOWN_TIMER[7:0] [1] CTD[1:0] Except in the case of software reset, see Section 9.5. PCF2123_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 December 2009 8 of 55 PCF2123 NXP Semiconductors SPI Real time clock/calendar 9.3 Control registers 9.3.1 Register Control_1 Table 5. Bit 7 Control_1 - control and status register 1 (address 00h) bit description Symbol Value Description Reference EXT_TEST 0[1] normal mode Section 9.12 1 external clock test mode 6 N - unused - 5 STOP 0[1] the RTC source clock runs Section 9.13 1 the RTC clock is stopped; RTC divider chain flip-flops are asynchronously set to logic 0; CLKOUT at 32.768 kHz, 16.384 kHz or 8.192 kHz is still available 4 SR 0[1] 1 no software reset initiate software Section 9.5 reset[2]; this register will always return a 0 when read 3 N - unused - 2 12_24 0[1] 24 hour mode is selected - 1 CIE 0 N 1 12 hour mode is selected 0[1] no correction interrupt generated 1 interrupt pulses will be generated at every correction cycle - unused - [1] Default value. [2] For a software reset, 01011000 (58h) must be sent to register Control_1 (see Section 9.5). PCF2123_2 Product data sheet Section 9.11 © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 December 2009 9 of 55 PCF2123 NXP Semiconductors SPI Real time clock/calendar 9.3.2 Register Control_2 Table 6. Bit Control_2 - control and status register 2 (address 01h) bits description Symbol Value Description Reference 7 MI 0[1] minute interrupt is disabled Section 9.8.3 6 SI 5 MSF 1 minute interrupt is enabled 0[1] second interrupt is disabled 1 second interrupt is enabled 0[1] no minute or second interrupt generated 1 flag set when minute or second interrupt generated; flag must be cleared to clear interrupt when TI_IP = 0 4 3 TI_TP AF 0[1] interrupt pin follows timer flags 1 interrupt pin generates a pulse 0[1] no alarm interrupt generated 1 flag set when alarm triggered; Section 9.9.2 Section 9.7.5 flag must be cleared to clear interrupt 2 TF 0[1] no countdown timer interrupt generated 1 flag set when countdown timer interrupt generated; Section 9.8.4 flag must be cleared to clear interrupt when TI_IP = 0 1 0 [1] AIE TIE 0[1] no interrupt generated from the alarm flag 1 interrupt generated when alarm flag set 0[1] no interrupt generated from the countdown Section 9.9.2 timer 1 interrupt generated by the countdown timer Section 9.9.3 Default value. 9.4 OS flag The PCF2123 includes a flag (OS in register Seconds, see Table 8) which is set whenever the oscillator is stopped (see Figure 8 and Figure 9). The flag will remain set until cleared by software. If the flag cannot be cleared, then the PCF2123 oscillator is not running. This method can be used to monitor the oscillator and to determine if the supply voltage has reduced to the point where oscillation fails. PCF2123_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 December 2009 10 of 55 PCF2123 NXP Semiconductors SPI Real time clock/calendar main supply VDD battery operation VOSC(MIN) t 001aai561 Fig 8. OS set by failing VDD OS = 1 and flag can not be cleared OS = 1 and flag can be cleared VDD oscillation OS flag OS flag cleared by software OS flag set when oscillation stops t oscillation now stable 001aai553 Fig 9. OS flag The oscillator may be stopped, for example, by grounding one of the oscillator pins, OSCI or OSCO. The oscillator is also considered to be stopped during the time between power-on and stable crystal resonance. This time may be in the range of 200 ms to 2 s depending on crystal type, temperature and supply voltage. At power-on the OS flag is always set. 9.5 Reset A reset is automatically generated at power-on. A reset can also be initiated with the software reset command. It is generally recommended to make a software reset after power-on. A software reset can be initiated by setting the bits 6, 4 and 3 in register Control_1 logic 1 and all other bits logic 0 by sending the bit sequence 01011000 (58h), see Figure 10. If this bit sequence is not correct, the software reset instruction will be ignored to protect the device from accidently being reset. When sending the software instruction, the other bits are not written. PCF2123_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 December 2009 11 of 55 PCF2123 NXP Semiconductors SPI Real time clock/calendar R/W b7 0 addr 00HEX b6 0 b5 0 b4 1 b3 0 b2 0 b1 0 software reset 58HEX b0 0 b7 0 b6 1 b5 0 b4 1 b3 1 b2 0 b1 0 b0 0 SCL CE (1) internal reset signal 001aai562 (1) When CE is inactive, the interface is reset. Fig 10. Software reset command After reset, the following mode is entered: • • • • • • 32.768 kHz on pin CLKOUT active 24 hour mode is selected Offset register is set to 0 No alarms set Timer disabled No interrupts enabled Table 7. Register reset values Bits labeled as - are not implemented. Bits labeled as X are undefined at power-on and unchanged by subsequent resets. Address Register name Bit 7 6 5 4 3 2 1 0 00h Control_1 0 0 0 0 0 0 0 0 01h Control_2 0 0 0 0 0 0 0 0 02h Seconds 1 X X X X X X X 03h Minutes - X X X X X X X 04h Hours - - X X X X X X 05h Days - - X X X X X X 06h Weekdays - - - - - X X X 07h Months - - - X X X X X 08h Years X X X X X X X X 09h Minute_alarm 1 X X X X X X X 0Ah Hour_alarm 1 - X X X X X X 0Bh Day_alarm 1 - X X X X X X 0Ch Weekday_alarm 1 - - - - X X X 0Dh Offset_register 0 0 0 0 0 0 0 0 0Eh Timer_clkout - 0 0 0 0 - 1 1 0Fh Countdown_timer X X X X X X X X PCF2123_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 December 2009 12 of 55 PCF2123 NXP Semiconductors SPI Real time clock/calendar 9.6 Time and date function The majority of the registers are coded in the Binary Coded Decimal (BCD) format. BCD is used to simplify application use. An example is shown for the seconds in Table 9. 9.6.1 Register Seconds Table 8. Seconds - seconds register (address 02h) bit description Bit Symbol Value Place value Description 7 OS 0 - clock integrity is guaranteed 1[1] - clock integrity is not guaranteed; oscillator has stopped or been interrupted 6 to 4 SECONDS 0 to 5 ten’s place actual seconds coded in BCD format, see Table 9 3 to 0 unit place [1] 0 to 9 Default value. Table 9. Seconds coded in BCD format Seconds value (decimal) Upper-digit (ten’s place) Digit (unit place) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00 0 0 0 0 0 0 0 0 01 0 0 0 0 0 0 0 1 02 0 0 0 0 0 0 1 0 : : : : : : : : : 09 0 0 0 0 1 0 0 1 10 0 0 0 1 0 0 0 0 : : : : : : : : : 58 0 1 0 1 1 0 0 0 59 0 1 0 1 1 0 0 1 9.6.2 Register Minutes Table 10. Minutes - minutes register (address 03h) bit description Bit Symbol 7 - Value Place value Description - - unused 6 to 4 MINUTES 0 to 5 ten’s place actual minutes coded in BCD format 3 to 0 0 to 9 unit place 9.6.3 Register Hours Table 11. Bit Hours - hours register (address 04h) bit description Symbol 7 to 6 12 hour 5 4 3 to 0 Value Place value Description - unused mode[1] AMPM HOURS 0 - indicates AM 1 - indicates PM 0 to 1 ten’s place actual hours in 12 hour mode coded in BCD format 0 to 9 unit place PCF2123_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 December 2009 13 of 55 PCF2123 NXP Semiconductors SPI Real time clock/calendar Table 11. Bit Hours - hours register (address 04h) bit description …continued Symbol Value Place value Description 5 to 4 HOURS 0 to 2 ten’s place 3 to 0 0 to 9 unit place 24 hour mode[1] [1] actual hours in 24 hour mode coded in BCD format Hour mode is set by the 12_24 bit in register Control_1. 9.6.4 Register Days Table 12. Bit Days - days register (address 05h) bit description Symbol 7 to 6 5 to 4 DAYS[1] 3 to 0 [1] Value Place value Description - - unused 0 to 3 ten’s place actual day coded in BCD format 0 to 9 unit place The PCF2123 compensates for leap years by adding a 29th day to February if the year counter contains a value which is exactly divisible by 4, including the year 00. 9.6.5 Register Weekdays Table 13. Bit Weekdays - weekdays register (address 06h) bit description Value Description 7 to 3 - Symbol - unused 2 to 0 WEEKDAYS 0 to 6 actual weekday values, see Table 14 Table 14. Weekday assignments Day[1] Bit 2 1 0 Sunday 0 0 0 Monday 0 0 1 Tuesday 0 1 0 Wednesday 0 1 1 Thursday 1 0 0 Friday 1 0 1 Saturday 1 1 0 [1] Definition may be re-assigned by the user. 9.6.6 Register Months Table 15. Bit Months - months register (address 07h) bit description Value Place value Description 7 to 5 - - - unused 4 0 to 1 ten’s place actual month coded in BCD format, see Table 16 0 to 9 unit place 3 to 0 Symbol MONTHS PCF2123_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 December 2009 14 of 55 PCF2123 NXP Semiconductors SPI Real time clock/calendar Table 16. Month assignments in BCD format Month Upper-digit (ten’s place) Digit (unit place) Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 January 0 0 0 0 1 February 0 0 0 1 0 March 0 0 0 1 1 April 0 0 1 0 0 May 0 0 1 0 1 June 0 0 1 1 0 July 0 0 1 1 1 August 0 1 0 0 0 September 0 1 0 0 1 October 1 0 0 0 0 November 1 0 0 0 1 December 1 0 0 1 0 9.6.7 Register Years Table 17. Bit Years - years register (08h) bit description Symbol Value Place value Description 7 to 4 YEARS 0 to 9 ten’s place 3 to 0 0 to 9 unit place actual year coded in BCD format 9.6.8 Setting and reading the time Figure 11 shows the data flow and data dependencies starting from the 1 Hz clock tick. 1 Hz tick SECONDS MINUTES 12_24 hour mode HOURS LEAP YEAR CALCULATION DAYS WEEKDAY MONTHS YEARS 001aaf901 Fig 11. Data flow of the time function PCF2123_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 December 2009 15 of 55 PCF2123 NXP Semiconductors SPI Real time clock/calendar During read/write operations, the time counting circuits (memory locations 02h through 08h) are blocked. This prevents • Faulty reading of the clock and calendar during a carry condition • Incrementing the time registers during the read cycle After this read/write access is completed, the time circuit is released again and any pending request to increment the time counters that occurred during the read/write access is serviced. A maximum of 1 request can be stored; therefore, all accesses must be completed within 1 second (see Figure 12). t<1s data bus COMMAND DATA DATA DATA chip enable 013aaa222 Fig 12. Access time for read/write operations As a consequence of this method, it is very important to make a read or write access in one go, that is, setting or reading seconds through to years should be made in one single access. Failing to comply with this method could result in the time becoming corrupted. As an example, if the time (seconds through to hours) is set in one access and then in a second access the date is set, it is possible that the time may increment between the two accesses. A similar problem exists when reading. A roll over may occur between reads thus giving the minutes from one moment and the hours from the next. Therefore it is advised to read all time and date registers in one access. 9.7 Alarm function When one or more of these registers are loaded with a valid minute, hour, day, or weekday and its corresponding alarm enable bit (AE_x) is logic 0, then that information will be compared with the current minute, hour, day, and weekday. 9.7.1 Register Minute_alarm Table 18. Minute_alarm - minute alarm register (address 09h) bit description Bit Symbol Value Place value Description 7 AE_M 0 - minute alarm is enabled 1[1] - minute alarm is disabled 6 to 4 MINUTE_ALARM 0 to 5 ten’s place 3 to 0 0 to 9 unit place minute alarm information coded in BCD format [1] Default value. PCF2123_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 December 2009 16 of 55 PCF2123 NXP Semiconductors SPI Real time clock/calendar 9.7.2 Register Hour_alarm Table 19. Hour_alarm - hour alarm register (address 0Ah) bit description Bit Symbol Value 7 AE_H 0 hour alarm is enabled 1[1] hour alarm is disabled - unused indicates AM 6 - 12 hour Place value Description mode[2] 5 AMPM 0 4 HOUR_ALARM 0 to 1 ten’s place 0 to 9 unit place 5 to 4 HOUR_ALARM 0 to 2 ten’s place 3 to 0 0 to 9 unit place 1 3 to 0 24 hour indicates PM hour alarm information coded in BCD format when in 12 hour mode mode[2] [1] Default value. [2] Hour mode is set by the 12_24 bit in register Control_1. hour alarm information coded in BCD format when in 24 hour mode 9.7.3 Register Day_alarm Table 20. Day_alarm - day alarm register (address 0Bh) bit description Bit Symbol Value Place value Description 7 AE_D 0 - day alarm is enabled 1[1] - day alarm is disabled - - unused 5 to 4 DAY_ALARM 0 to 3 ten’s place 3 to 0 0 to 9 unit place day alarm information coded in BCD format 6 [1] - Default value. 9.7.4 Register Weekday_alarm Table 21. Weekday_alarm - weekday alarm register (address 0Ch) bit description Bit Symbol Value Description 7 AE_W 0 weekday alarm is enabled 1[1] weekday alarm is disabled - unused 6 to 3 - 2 to 0 WEEKDAY_ALARM 0 to 6 [1] weekday alarm information coded in BCD format Default value. 9.7.5 Alarm flag By clearing the MSB, AE_x (Alarm Enable), of one or more of the alarm registers the corresponding alarm condition(s) are active. When an alarm occurs, AF (register Control_2, see Table 6) is set logic 1. The asserted AF can be used to generate an interrupt (INT). The AF is cleared using the interface. PCF2123_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 December 2009 17 of 55 PCF2123 NXP Semiconductors SPI Real time clock/calendar check now signal example AE_M AE_M = 1 MINUTE ALARM = 1 0 MINUTE TIME AE_H HOUR ALARM = HOUR TIME set alarm flag AF (1) AE_D DAY ALARM = DAY TIME AE_W WEEKDAY ALARM = 013aaa088 WEEKDAY TIME (1) Only when all enabled alarm settings are matching. It’s only on increment to a matched case that the alarm flag is set, see Section 9.7.5. Fig 13. Alarm function block diagram The registers at addresses 09h through 0Ch contain alarm information. When one or more of these registers is loaded with minute, hour, day, or weekday, and its corresponding Alarm Enable bit (AE_x) is logic 0, then that information is compared with the current minute, hour, day, and weekday. When all enabled comparisons first match, the Alarm Flag (AF) is set logic 1. The generation of interrupts from the alarm function is controlled via bit AIE (register Control_2, see Table 6). If bit AIE is enabled, the INT pin follows the condition of bit AF. AF will remain set until cleared by the interface. Once AF has been cleared, it will only be set again when the time increments to match the alarm condition once more. Alarm registers which have their AE_x bit logic 1 are ignored. Generation of interrupts from the alarm function is described in Section 9.9.3. minutes counter 44 minute alarm 45 45 46 AF INT when AIE = 1 001aaf903 Example where only the minute alarm is used and no other interrupts are enabled. Fig 14. Alarm flag timing PCF2123_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 December 2009 18 of 55 PCF2123 NXP Semiconductors SPI Real time clock/calendar Figure 14, Table 22 and Table 23 show an example for clearing bit AF, but leaving bit MSF and bit TF unaffected. The flags are cleared by a write command, therefore bits 7, 6, 4, 1 and 0 must be written with their previous values. Repeatedly re-writing these bits has no influence on the functional behavior. To prevent the timer flags being overwritten while clearing bit AF, logic AND is performed during a write access. A flag is cleared by writing logic 0 whilst a flag is not cleared by writing logic 1. Writing logic 1 will result in the flag value remaining unchanged. Table 22. Flag location in register Control_2 Register Bit Control_2 7 6 5 4 3 2 1 0 - - MSF - AF TF - - Table 23 shows what instruction must be sent to clear bit AF. In this example, bit MSF and bit TF are unaffected. Table 23. Example to clear only AF (bit 3) in register Control_2 Register Bit Control_2 7 6 5 4 3 2 1 0 - - 1 - 0 1 - - 9.8 Timer functions The countdown timer has four selectable source clocks allowing for countdown periods in the range from 244 µs to 4 h 15 min. There are also two pre-defined timers which can be used to generate an interrupt once per second or once per minute. For periods greater than 4 hours, the alarm function can be used. Registers 01h, 0Eh and 0Fh are used to control the timer function and output. 9.8.1 Register Timer_clkout Table 24. Timer_clkout - timer control register (address 0Eh) bit description Bit Symbol 7 - 6 to 4 COF[2:0] 3 2 TE - 1 to 0 CTD[1:0] Value Description Reference - unused - [1] CLKOUT control Section 9.10 Section 9.8.4 0 countdown timer is disabled 1 countdown timer is enabled - unused 00 4.096 kHz countdown timer source clock 01 64 Hz countdown timer source clock 10 1 Hz countdown timer source clock 11[2] 1⁄ Hz 60 [1] Values of COF[2:0] see Table 35. [2] Default value. countdown timer source clock PCF2123_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 December 2009 19 of 55 PCF2123 NXP Semiconductors SPI Real time clock/calendar 9.8.2 Register Countdown_timer Table 25. Register Countdown_timer (address 0Ah) bits description Bit Symbol Value Description Reference 7 to 0 COUNTDOWN_TIMER[7:0] 0h to FFh countdown period in seconds: Section 9.8.4 n CountdownPeriod = --------------------------------------------------------------SourceClockFrequency where n is the countdown value 9.8.3 Minute and second interrupt The minute and second interrupts (bits MI and SI) are pre-defined timers for generating periodic interrupts. The timers can be enabled independently from one another. However, a minute interrupt enabled on top of a second interrupt will not be distinguishable since it will occur at the same time; see Figure 15. seconds counter 58 59 minutes counter 59 00 11 12 00 01 INT when SI enabled MSF when SI enabled INT when only MI enabled MSF when only MI enabled 001aaf905 In this example, TI_TP is set to logic 1 resulting in 1⁄64 Hz wide interrupt pulse and the MSF flag is not cleared after an interrupt. Fig 15. INT example for MI and SI Table 26. Effect of bits MI and SI on INT generation Minute interrupt (bit MI) Second interrupt (bit SI) Result 0 0 no interrupt generated 1 0 an interrupt once per minute 0 1 an interrupt once per second 1 1 an interrupt once per second The minute and second flag (bit MSF) is set logic 1 when either the seconds or the minutes counter increments according to the currently enabled interrupt. The flag can be read and cleared by the interface. The status of bit MSF does not affect the INT pulse generation. If the MSF flag is not cleared prior to the next coming interrupt period, an INT pulse will still be generated. The purpose of the flag is to allow the controlling system to interrogate the PCF2123 and identify the source of the interrupt, i.e., minute or second, countdown timer or alarm. PCF2123_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 December 2009 20 of 55 PCF2123 NXP Semiconductors SPI Real time clock/calendar Table 27. Effect of MI and SI on MSF Minute interrupt (bit MI) Second interrupt (bit SI) Result 0 0 MSF never set 1 0 MSF set when minutes counter increments 0 1 MSF set when seconds counter increments 1 1 MSF set when seconds counter increments The duration of both of these timers will be affected by the register Offset_register (see Section 9.11). Only when the Offset_register has the value 00h the periods will be consistent. 9.8.4 Countdown timer function The 8-bit countdown timer at address 0Fh is controlled by the register Timer_clkout at address 0Eh. The register Timer_clkout selects one of 4 source clock frequencies for the timer (4.096 kHz, 64 Hz, 1 Hz, or 1⁄60 Hz) and enables or disables the timer. Table 28. Bits CTD0 and CTD1 for timer frequency selection and countdown timer durations CTD[1:0] Timer source clock frequency[1] Delay Minimum timer duration n=1 Maximum timer duration n = 255 00 4.096 kHz 244 µs 62.256 ms 01 64 Hz 15.625 ms 3.984 s 10 1 Hz[2] 1s 255 s 11 1⁄ 60 60 s 4 h 15 min Hz[2] [1] When not in use, CTD must be set to 1⁄60 Hz for power saving. [2] Time periods can be affected by correction pulses. Remark: Note that all timings which are generated from the 32.768 kHz oscillator are based on the assumption that there is 0 ppm deviation. Deviation in oscillator frequency will result in deviation in timings. This is not applicable to interface timing. The timer counts down from a software-loaded 8-bit binary value, n. Loading the counter with 0 stops the timer. Values from 1 to 255 are valid. When the counter reaches 1, the countdown timer flag (bit TF) will be set and the counter automatically re-loads and starts the next timer period. Reading the timer will return the current value of the countdown counter (see Figure 16). PCF2123_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 December 2009 21 of 55 PCF2123 NXP Semiconductors SPI Real time clock/calendar countdown value, n xx 03 xx 03 timer source clock countdown counter 02 01 03 02 01 03 02 01 03 TE TF INT n n duration of first timer period after enable may range from n − 1 to n + 1 001aaf906 In this example it is assumed that the timer flag is cleared before the next countdown period expires and that the pin INT is set to pulsed mode. Fig 16. General countdown timer behavior If a new value of n is written before the end of the current timer period, then this value will take immediate effect. NXP does not recommend changing n without first disabling the counter (by setting bit TE = 0). The update of n is asynchronous to the timer clock, therefore changing it without setting bit TE = 0 may result in a corrupted value loaded into the countdown counter which results in an undetermined countdown period for the first period. The countdown value n will, however, be correctly stored and correctly loaded on subsequent timer periods. When the countdown timer flag is set, an interrupt signal on INT will be generated provided that this mode is enabled. See Section 9.9.2 for details on how the interrupt can be controlled. When starting the timer for the first time, the first period will have an uncertainty which is a result of the enable instruction being generated from the interface clock which is asynchronous from the timer source clock. Subsequent timer periods will have no such delay. The amount of delay for the first timer period will depend on the chosen source clock, see Table 29. Table 29. First period delay for timer counter value n Timer source clock Minimum timer period Maximum timer period 4.096 kHz n n+1 64 Hz n n+1 1 Hz (n − 1) + 1⁄64 Hz 1⁄ 60 Hz (n − 1) + 1⁄ 64 Hz n + 1⁄64 Hz n + 1⁄64 Hz At the end of every countdown, the timer sets the countdown timer flag (bit TF). Bit TF may only be cleared by software. The asserted bit TF can be used to generate an interrupt (INT). The interrupt may be generated as a pulsed signal every countdown period or as a permanently active signal which follows the condition of bit TF. Bit TI_TP is used to control this mode selection and the interrupt output may be disabled with bit TIE, see Table 6. PCF2123_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 December 2009 22 of 55 PCF2123 NXP Semiconductors SPI Real time clock/calendar When reading the timer, the current countdown value is returned and not the initial value n. Since it is not possible to freeze the countdown timer counter during read back, it is recommended to read the register twice and check for consistent results. Timer source clock frequency selection of 1 Hz and 1⁄60 Hz will be affected by the Offset_register. The duration of a program period will vary according to when the offset is initiated. For example, if a 100 s timer is set using the 1 Hz clock as source, then some 100 s periods will contain correction pulses and therefor be longer or shorter depending on the setting of the Offset_register. See Section 9.11 to understand the operation of the Offset_register. 9.8.5 Timer flags When a minute or second interrupt occurs, bit MSF is set logic 1. Similarly, at the end of a timer countdown or alarm event, bit TF or AF are set logic 1. These bits maintain their value until overwritten by software. If both countdown timer and minute or second interrupts are required in the application, the source of the interrupt can be determined by reading these bits. To prevent one flag being overwritten while clearing another a logical AND is performed during a write access. A flag is cleared by writing logic 0 whilst a flag is not cleared by writing logic 1. Writing logic 1 will result in the flag value remaining unchanged. Three examples are given for clearing the flags. Clearing the flags is made by a write command, therefore bits 7, 6, 4, 1 and 0 must be written with their previous values. Repeatedly re-writing these bits has no influence on the functional behavior. Table 30. Register Control_2 Flag location in register Control_2 Bit 7 6 5 4 3 2 1 0 - - MSF - AF TF - - Table 31, Table 32 and Table 33 show what instruction must be sent to clear the appropriate flag. Table 31. Register Control_2 Table 32. Register Control_2 Table 33. Register Control_2 Example to clear only TF (bit 2) in register Control_2 Bit 7 6 5 4 3 2 1 0 - - 1 - 1 0 - - Example to clear only MSF (bit 5) in register Control_2 Bit 7 6 5 4 3 2 1 0 - - 0 - 1 1 - - Example to clear both TF and MSF (bit 2 and bit 5) in register Control_2 Bit 7 6 5 4 3 2 1 0 - - 0 - 1 0 - - Clearing the alarm flag (bit AF) operates in exactly the same way, see Section 9.7.5. PCF2123_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 December 2009 23 of 55 PCF2123 NXP Semiconductors SPI Real time clock/calendar 9.9 Interrupt output An active LOW interrupt signal is available at pin INT. Operation is controlled via the bits of register Control_2. Interrupts may be sourced from four places: second and minute timer, countdown timer, alarm function or offset function. With bit TI_TP, the timer generated interrupts can be configured to either generate a pulse or to follow the status of the interrupt flags (bits TF and MSF). Correction interrupt pulses are always 1⁄128 second long. Alarm interrupts always follow the condition of AF. SI MSF: MINUTE SECOND FLAG SET SECONDS COUNTER MINUTES COUNTER CLEAR MI to interface: read MSF SI MI 0 PULSE GENERATOR 1 TRIGGER 1 CLEAR from interface: clear MSF TE TF: TIMER COUNTDOWN COUNTER INT TI_TP to interface: read TF TIE 0 SET CLEAR PULSE GENERATOR 2 TRIGGER 1 E.G.AIE CLEAR from interface: clear TF set alarm flag, AF 0 1 AF: ALARM FLAG SET to interface: read AF AIE CLEAR from interface: clear AF PULSE GENERATOR 3 TRIGGER offset circuit: add/substract 1/64 Hz pulse CIE CLEAR from interface: set CIE 001aai555 When bits SI, MI, TIE, AIE and CIE are all disabled, pin INT will remain high-impedance. Fig 17. Interrupt scheme Remark: Note that the interrupts from the four sources are wired-OR, meaning they will mask one another (see Figure 17). 9.9.1 Minute and second interrupts The pulse generator for the minute and second interrupt operates from an internal 64 Hz clock and consequently generates a pulse of 1⁄64 second in duration. PCF2123_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 December 2009 24 of 55 PCF2123 NXP Semiconductors SPI Real time clock/calendar If the MSF flag is cleared before the end of the INT pulse, then the INT pulse is shortened. This allows the source of a system interrupt to be cleared immediately it is serviced, i.e., the system does not have to wait for the completion of the pulse before continuing; see Figure 18. Instructions for clearing MSF are given in Section 9.8.5. seconds counter 58 59 MSF INT (1) SCL 8th clock CLEAR INSTRUCTION instruction 001aaf908 (1) Indicates normal duration of INT pulse (bit TI_TP = 1) Fig 18. Example of shortening the INT pulse by clearing the MSF flag The timing shown for clearing bit MSF in Figure 18 is also valid for the non-pulsed interrupt mode i.e. when bit TI_TP = 0, INT may be shortened by setting both MI and SI or MSF to logic 0. 9.9.2 Countdown timer interrupts The generation of interrupts from the countdown timer is controlled via bit TIE. The pulse generator for the countdown timer interrupt also uses an internal clock, but this time it is dependent on the selected source clock for the countdown timer and on the countdown value n. As a consequence, the width of the interrupt pulse varies (see Table 34). Table 34. INT operation (bit TI_TP = 1) Source clock (Hz) INT period (s) n = 1[1] n>1 4096 1⁄ 8192 1⁄ 4096 64 1⁄ 128 1⁄ 64 1 1⁄ 64 1⁄ 64 1⁄ 60 1⁄ 64 1⁄ 64 [1] n = loaded countdown value. Timer stopped when n = 0. If the TF flag is cleared before the end of the INT pulse, then the INT pulse is shortened. This allows the source of a system interrupt to be cleared immediately it is serviced, i.e., the system does not have to wait for the completion of the pulse before continuing (see Figure 19). Instructions for clearing MSF can be found in Section 9.8.5. PCF2123_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 December 2009 25 of 55 PCF2123 NXP Semiconductors SPI Real time clock/calendar countdown counter 01 n CDTF INT (1) SCL 8th clock instruction CLEAR INSTRUCTION 001aaf909 (1) Indicates normal duration of INT pulse (bit TI_TP = 1). Fig 19. Example of shortening the INT pulse by clearing the TF flag The timing shown for clearing bit TF in Figure 19 is also valid for the non-pulsed interrupt mode, i.e., when bit TI_TP = 0; INT may be shortened by setting bit TIE to logic 0. 9.9.3 Alarm interrupts The generation of interrupts from the alarm function is controlled via bit AIE (see Table 6). If bit AIE is enabled, the INT pin follows the condition of bit AF. Clearing bit AF will immediately clear INT. No pulse generation is possible for alarm interrupts (see Figure 20). minute counter 44 minute alarm 45 45 AF INT SCL 8th clock instruction CLEAR INSTRUCTION 001aaf910 Example where only the minute alarm is used and no other interrupts are enabled. Fig 20. AF timing 9.9.3.1 Correction pulse interrupts Interrupt pulses generated by correction events can be shortened by writing logic 1 to bit CIE in register Control_1. PCF2123_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 December 2009 26 of 55 PCF2123 NXP Semiconductors SPI Real time clock/calendar 9.10 Clock output A programmable square wave is available at pin CLKOUT. Operation is controlled by the COF[2:0] bits in the register Timer_clkout. Frequencies of 32.768 kHz (default) down to 1 Hz can be generated for use as a system clock, microcontroller clock, input to a charge pump, or for calibration of the oscillator. Pin CLKOUT is an open-drain output and enabled at power-on. When disabled the output is high-impedance. The duty cycle of the selected clock is not controlled. However, due to the nature of the clock generation, all will be 50 : 50 except the 32.768 kHz frequencies. The STOP bit function can also affect the CLKOUT signal, depending on the selected frequency. When the STOP bit is set to logic 1, the CLKOUT pin will generate a continuous LOW for those frequencies that can be stopped. For more details of the STOP bit function see Section 9.13. Table 35. CLKOUT frequency selection Bits COF[2:0] CLKOUT frequency (Hz) Typical duty cycle[1] 000 32768 60 : 40 to 40 : 60 no effect 001 16384 50 : 50 no effect 010 8192 50 : 50 no effect 011 4096 50 : 50 CLKOUT = LOW 100 2048 50 : 50 CLKOUT = LOW 101 1024 50 : 50 CLKOUT = LOW 110 1[2] 50 : 50 CLKOUT = LOW 111 CLKOUT = high-Z - - [1] Duty cycle definition: % HIGH-level time : % LOW-level time. [2] 1 Hz clock pulses will be affected by offset correction pulses. Effect of STOP bit 9.10.1 CLKOE pin The CLKOE pin can be used to block the CLKOUT function and force the CLKOUT pin to an high-impedance state. The effect is the same as setting COF[2:0] = 111. 9.11 Offset register The PCF2123 incorporates an offset register (address 0Dh) which can be used to implement several functions, such as: • Ageing adjustment • Temperature compensation • Accuracy tuning The offset is made once every two hours in the normal mode, or once every hour in the course mode. Each LSB will introduce an offset of 2.17 ppm for normal mode and 4.34 ppm for course mode. The values of 2.17 ppm and 4.34 ppm are based on a nominal 32.768 kHz clock. The offset value is coded in two’s complement giving a range of +63 LSB to −64 LSB. PCF2123_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 December 2009 27 of 55 PCF2123 NXP Semiconductors SPI Real time clock/calendar Table 36. Register Offset_register OFFSET[6:0] Offset value in decimal Offset value in ppm Normal mode MODE = 0 Course mode MODE = 1 0 1 1 1 1 1 1 +63 +136.71 +273.42 0 1 1 1 1 1 0 +62 +134.54 +269.08 : : : 0 0 0 0 0 1 0 +2 +4.34 +8.68 0 0 0 0 0 0 1 +1 +2.17 +4.34 0 0 0 0 0 0 0 0[1] 0 0 1 1 1 1 1 1 1 −1 −2.17 −4.34 1 1 1 1 1 1 0 −2 −4.34 −8.68 : : : 1 0 0 0 0 0 1 −63 −136.71 −273.42 1 0 0 0 0 0 0 −64 −138.88 −277.76 : : [1] Default mode. The correction is made by adding or subtracting 64 Hz clock correction pulses, thereby changing the period of a single second. Table 37. Example of converting the offset in ppm to seconds Offset in ppm Seconds per Day Week Month Year 2.17 0.187 1.31 5.69 68.2 4.34 0.375 2.62 11.4 136 In normal mode, the correction is triggered once per two hours and then correction pulses are applied once per minute until the programmed correction values has been implement. In course mode, the correction is triggered once per hour and then correction pulses are applied once per minute up to a maximum of 60 minutes. When correction values greater than 60 are used, additional correction pulses are made in the 59th minute (see Table 38). PCF2123_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 December 2009 28 of 55 PCF2123 NXP Semiconductors SPI Real time clock/calendar Table 38. Correction pulses for course mode Correction value +1 or −1 +2 or −2 +3 or −3 Hour:Minute[1] Correction pulses on INT per minute[2] 02:00 1 02:01 to 02:59 0 02:00 1 02:01 1 02:02 to 02:59 0 02:00 1 02:01 1 02:02 1 02:03 to 02:59 0 : : : +59 or −59 02:00 to 02:58 1 02:59 0 +60 or −60 02:00 to 02:59 1 +61 or −61 02:00 to 02:58 1 +62 or −62 +63 or −63 −64 02:59 2 02:00 to 02:58 1 02:59 3 02:00 to 02:58 1 02:59 4 02:00 to 02:58 1 02:59 5 [1] Example is given in a time range from 2:00 to 2:59. [2] Correction INT pulses are 1⁄128 s wide. For multiple pulses they are repeated at 1⁄64 s interval. It is possible to monitor when correction pulses are applied. The correction interrupt enable mode (bit CIE) will generate a 1⁄128 second pulse on INT for every correction applied. In the case where multiple correction pulses are applied, a 1⁄128 second interrupt pulse will be generated and repeated every 1⁄64 seconds. Correction is applied to the 1 Hz clock. Any timer or clock output using a frequency of 1 Hz or below will also be affected by the correction pulses. PCF2123_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 December 2009 29 of 55 PCF2123 NXP Semiconductors SPI Real time clock/calendar Table 39. Effect of correction pulses Frequency (Hz) Effect of correction CLKOUT 32768 no effect 16384 no effect 8192 no effect 4096 no effect 2048 no effect 1024 no effect 1 effected Time source clock 4096 no effect 64 no effect 1 effected 1⁄ 60 effected 9.12 External clock test mode A test mode is available which allows for on-board testing. In this mode it is possible to set up test conditions and control the operation of the RTC. The test mode is entered by setting bit EXT_TEST in register Control_1. Then pin CLKOUT becomes an input. The test mode replaces the internal clock signal with the signal applied to pin CLKOUT. The signal applied to pin CLKOUT should have a minimum pulse width of 300 ns and a maximum period of 1000 ns. The internal clock, now sourced from CLKOUT, is divided down to 1 Hz by a 26 divide chain called a prescaler. The prescaler can be set into a known state by using bit STOP. When bit STOP is set, the prescaler is reset to 0. (STOP must be cleared before the prescaler can operate again.) From a stop condition, the first 1 second increment will take place after 32 positive edges on pin CLKOUT. Thereafter, every 64 positive edges will cause a 1 second increment. Remark: Entry into test mode is not synchronized to the internal 64 Hz clock. When entering the test mode, no assumption as to the state of the prescaler can be made. Operation example: 1. Set EXT_TEST test mode (register Control_1, bit EXT_TEST = 1). 2. Set STOP (Control_1, bit STOP = 1). 3. Clear STOP (Control_1, bit STOP = 0). 4. Set time registers to desired value. 5. Apply 32 clock pulses to pin CLKOUT. 6. Read time registers to see the first change. PCF2123_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 December 2009 30 of 55 PCF2123 NXP Semiconductors SPI Real time clock/calendar 7. Apply 64 clock pulses to pin CLKOUT. 8. Read time registers to see the second change. Repeat 7 and 8 for additional increments. 9.13 STOP bit function The function of the STOP bit is to allow for accurate starting of the time circuits. The STOP bit function will cause the upper part of the prescaler (F2 to F14) to be held in reset and thus no 1 Hz ticks will be generated. The time circuits can then be set and will not increment until the STOP bit is released (see Figure 22 and Table 40). The STOP bit function will not affect the output of 32.768 kHz, 16.384 kHz or 8.192 kHz (see Section 9.10). F2 RESET F13 RESET 2 Hz F1 oscillator stop flag 4096 Hz F0 8192 Hz 16384 Hz OSCILLATOR 32768 Hz OSCILLATOR STOP DETECTOR F14 1 Hz tick RESET stop 1 Hz 1024 Hz CLKOUT source 8192 Hz 16384 Hz 001aai556 Fig 21. STOP bit functional diagram The lower two stages of the prescaler (F0 and F1) are not reset and because the SPI-bus is asynchronous to the crystal oscillator, the accuracy of re-starting the time circuits will be between 0 and one 8.192 kHz cycle (see Figure 22). 8192 Hz stop released 0 µs to 122 µs 001aaf912 Fig 22. STOP bit release timing The first increment of the time circuits is between 0.499888 s and 0.500000 s after STOP bit is released. The uncertainty is caused by the prescaler bits F0 and F1 not being reset (see Table 40). PCF2123_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 December 2009 31 of 55 PCF2123 NXP Semiconductors SPI Real time clock/calendar Table 40. First increment of time circuits after STOP bit release Bit Prescaler bits STOP F0F1-F2 to F14 [1] 1 Hz tick Time Comment hh:mm:ss Clock is running normally 0 12:45:12 01-0 0001 1101 0100 prescaler counting normally STOP bit is activated by user. F0F1 are not reset and values cannot be predicted externally 1 XX-0 0000 0000 0000 12:45:12 prescaler is reset; time circuits are frozen 08:00:00 prescaler is reset; time circuits are frozen 08:00:00 prescaler is now running 08:00:00 - 08:00:00 - 08:00:00 - : : New time is set by user 1 XX-0 0000 0000 0000 XX-0 0000 0000 0000 XX-1 0000 0000 0000 XX-0 1000 0000 0000 XX-1 1000 0000 0000 : 08:00:00 - 00-0 0000 0000 0001 08:00:01 0 to 1 transition of F14 increments the time circuits 10-0 0000 0000 0001 08:00:01 - : : : 11-1 1111 1111 1111 11-1 1111 1111 1110 08:00:01 - 00-0 0000 0000 0000 08:00:01 - 10-0 0000 0000 0000 08:00:01 - : : : 11-1 1111 1111 1110 08:00:01 - 00-0 0000 0000 0001 08:00:02 0 to 1 transition of F14 increments the time circuits 1s 0 0.499888 - 0.500000 s STOP bit is released by user 001aaf913 [1] F0 is clocked at 32.768 kHz. 9.14 3-line serial interface Data transfer to and from the device is made via a 3-wire SPI-bus (see Table 41). The data lines for input and output are split. The data input and output lines can be connected together to facilitate a bidirectional data bus. The chip enable signal is used to identify the transmitted data. Each data transfer is a byte, with the Most Significant Bit (MSB) sent first (see Figure 24). PCF2123_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 December 2009 32 of 55 PCF2123 NXP Semiconductors SPI Real time clock/calendar Table 41. Serial interface Symbol Function Description CE chip enable input when LOW, the interface is reset; pull-down resistor included; active input may be higher than VDD, but may not be wired permanently HIGH SCL serial clock input when CE is LOW, this input may float; input may be higher than VDD SDI serial data input when CE is LOW, input may float; input may be higher than VDD; input data is sampled on the rising edge of SCL SDO serial data output push-pull output; drives from VSS to VDD; output data is changed on the falling edge of SCL; will be high-Z when not driving; may be connected directly to SDI SDI SDI SDO SDO two wire mode single wire mode 001aai560 Fig 23. SDI, SDO configurations The transmission is controlled by the active HIGH chip enable signal CE. The first byte transmitted is the command byte. Subsequent bytes will be either data to be written or data to be read. Data is sampled on the rising edge of the clock and transferred internally on the falling edge. data bus COMMAND DATA DATA DATA chip enable 001aaf914 Fig 24. Data transfer overview The command byte defines the address of the first register to be accessed and the read/write mode. The address counter will auto increment after every access and will rollover to zero after the last register is accessed. The read/write bit (R/W) defines if the following bytes will be read or write information. Table 42. Command byte definition Bit Symbol 7 R/W Value Description data read or data write selection 0 write data 1 read data 6 to 4 SA 001 subaddress; other codes will cause the device to ignore data transfer 3 to 0 0h to Fh register address range RA In Figure 25, the register Seconds is set to 45 seconds and the register Minutes is set to 10 minutes. PCF2123_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 December 2009 33 of 55 PCF2123 NXP Semiconductors SPI Real time clock/calendar R/W b7 0 addr 02HEX b6 0 b5 0 b4 1 b3 0 b2 0 b1 1 seconds data 45BCD b0 0 b7 0 b6 1 b5 0 b4 0 b3 0 b2 1 minutes data 10BCD b1 0 b0 1 b7 0 b6 0 b5 0 b4 1 b3 0 b2 0 b1 0 b0 0 SCL SDI CE address counter xx 02 03 04 001aaf915 Fig 25. Serial bus write example In Figure 26, the Months and Years registers are read. In this example, pins SDI and SDO are not connected together. For this configuration, it is important that pin SDI is never left floating. It must always be driven either HIGH or LOW. If pin SDI is left open, high IDD currents may result. Short transition periods in the order of 200 ns will not cause any problems. R/W b7 1 addr 07HEX b6 0 b5 0 b4 1 b3 0 b2 1 b1 1 months data 11BCD b0 1 b7 0 b6 0 b5 0 b4 1 b3 0 b2 0 years data 06BCD b1 0 b0 1 b7 0 b6 0 b5 0 b4 0 b3 0 b2 1 b1 1 b0 0 SCL SDI SDO CE address counter xx 07 08 09 001aaf916 Fig 26. Serial bus read example 9.14.1 Interface watchdog timer During read/write operations, the time counting circuits are frozen. To prevent a situation where the accessing device becomes locked and does not clear the interface by setting pin CE LOW, the PCF2123 has a built in watchdog timer. Should the interface be active for more than 1 s from the time a valid subaddress is transmitted, then the PCF2123 will automatically clear the interface and allow the time counting circuits to continue counting. CE must return LOW once more before a new data transfer can be executed. PCF2123_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 December 2009 34 of 55 PCF2123 NXP Semiconductors SPI Real time clock/calendar tw(CE) < 1 s CE data valid sub-address data WD timer time counters data data WD timer running running time counters frozen running 001aai563 a. Correct data transfer: read or write 1 s < tw(CE) < 2 s CE data valid sub-address data data WD timer time counters data data transfer fail WD timer running running time counters frozen WD trips running 001aai564 b. Incorrect data transfer; read or write Fig 27. Interface watchdog timer The watchdog is implemented to prevent the excessive loss of time due to interface access failure e.g. if main power is removed from a battery backed-up system during an interface access. Each time the watchdog period is exceeded, 1 s will be lost from the time counters. The watchdog will trigger between 1 s and 2 s after receiving a valid subaddress. PCF2123_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 December 2009 35 of 55 PCF2123 NXP Semiconductors SPI Real time clock/calendar 10. Limiting values Table 43. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions [1] Max Unit −0.5 +6.5 V VDD supply voltage IDD supply current −50 +50 mA VI input voltage [1] −0.5 +6.5 V VO output voltage [1] −0.5 +6.5 V II input current −10 +10 mA IO output current −10 +10 mA Ptot total power dissipation - 300 mW Tamb ambient temperature VESD Ilu Tstg −40 +85 °C HBM [2] - ±3000 V MM [3] - ±300 V latch-up current [4] - 200 mA storage temperature [5] −65 +150 °C electrostatic discharge voltage [1] With respect to VSS. [2] Pass level; Human Body Model (HBM) according to Ref. 7 “JESD22-A114” [3] Pass level; Machine Model (MM), according to Ref. 8 “JESD22-A115” [4] Pass level; latch-up testing, according to Ref. 9 “JESD78” at maximum ambient temperature (Tamb(max) = +85 °C). [5] According to the NXP store and transport requirements (see Ref. 11 “NX3-00092”) the devices have to be stored at a temperature of +8 °C to +45 °C and a humidity of 25 % to 75 %. For long term storage products deviant conditions are described in that document. PCF2123_2 Product data sheet Min © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 December 2009 36 of 55 PCF2123 NXP Semiconductors SPI Real time clock/calendar 11. Static characteristics Table 44. Static characteristics VDD = 1.1 V to 5.5 V; VSS = 0 V; Tamb = −40 °C to +85 °C; fosc = 32.768 kHz; quartz Rs = 15 kΩ; CL = 7 pF; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit supply voltage for clock data integrity; SPI-bus inactive 1.1 - 5.5 V Tamb = 25 °C - 0.9 - V SPI-bus active 1.6 - 5.5 V fSCL = 4.5 MHz; VDD = 5 V - 250 400 µA fSCL = 1.0 MHz; VDD = 3 V - 30 80 µA Tamb = 25 °C; VDD = 2.0 V - 100 - nA Tamb = 25 °C; VDD = 3.0 V - 110 - nA Tamb = 25 °C; VDD = 5.0 V - 120 - nA VDD = 2.0 V - - 330 nA VDD = 3.0 V - - 350 nA VDD = 5.0 V - - 380 nA VDD = 2.0 V - 260 - nA VDD = 3.0 V - 340 - nA VDD = 5.0 V - 520 - nA VDD = 2.0 V - - 450 nA VDD = 3.0 V - - 550 nA VDD = 5.0 V - - 750 nA Supplies VDD IDD supply current [1] SPI-bus active SPI-bus inactive; CLKOUT disabled SPI-bus inactive; CLKOUT disabled; Tamb = −40 °C to +85 °C [2] [2] SPI-bus inactive; CLKOUT enabled at 32 kHz; Tamb = 25 °C SPI-bus inactive; CLKOUT enabled at 32 kHz; Tamb = −40 °C to +85 °C Inputs VIL LOW-level input voltage - - 0.3VDD V VIH HIGH-level input voltage 0.7VDD - - V VI input voltage −0.5 - +5.5 V on pins CE, SDI, SCL, OSCI, CLKOE, CLKOUT PCF2123_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 December 2009 37 of 55 PCF2123 NXP Semiconductors SPI Real time clock/calendar Table 44. Static characteristics …continued VDD = 1.1 V to 5.5 V; VSS = 0 V; Tamb = −40 °C to +85 °C; fosc = 32.768 kHz; quartz Rs = 15 kΩ; CL = 7 pF; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit IL leakage current VI = VDD or VSS on pins SDI, SCL, OSCI, CLKOE, CLKOUT −1 0 +1 µA VI = VSS on pin CE −1 0 - µA pull-down resistance Rpd Ci on pin CE - 240 550 kΩ - - 7 pF −0.5 - +5.5 V on pin OSCO −0.5 - +5.5 V on pin SDO input capacitance on pins SDI, SCL, CLKOE and CE [3] output voltage on pins CLKOUT and INT [4] Outputs VO −0.5 - VDD + 0.5 V VOH HIGH-level output voltage on pin SDO 0.8VDD - VDD V VOL LOW-level output voltage on pin SDO VSS - 0.2VDD V on pins CLKOUT and INT; VDD = 5 V; IOL = 1.5 mA VSS - 0.4 V IOH HIGH-level output current output source current; VOH = 4.6 V; VDD = 5 V on pin SDO 1.5 - - mA IOL LOW-level output current output sink current; VOL = 0.4 V; VDD = 5 V on pins INT, SDO and CLKOUT 1.5 - - mA ILO output leakage current VO = VDD or VSS −1 0 +1 µA 3.3 7 14 pF - - 100 kΩ CL(itg) integrated load capacitance Rs series resistance on pins OSCO and OSCI [5] [1] For reliable oscillator start at power-on: VDD = VDD(min) + 0.3 V. [2] Timer source clock = 1⁄60 Hz, level of pins CE, SDI and SCL is VDD or VSS. [3] Implicit by design. [4] Refers to external pull-up voltage. [5] Integrated load capacitance, CL(itg), is a calculation of COSCI and COSCO in series. C L ( itg ) = -------------------------------------------- ( C OSCI ⋅ C OSCO ) ( C OSCI + C OSCO ) PCF2123_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 December 2009 38 of 55 PCF2123 NXP Semiconductors SPI Real time clock/calendar 12. Dynamic characteristics Table 45. SPI-bus characteristics VSS = 0 V; Tamb = −40 °C to +85 °C. All timing values are valid within the operating supply voltage and temperature range and referenced to VIL and VIH with an input voltage swing of VSS to VDD. Symbol Parameter Conditions VDD = 1.6 V VDD = 2.4 V VDD = 3.3 V VDD = 5.0 V Min Max Min Max Min Max Min Max Unit Timing characteristics (see Figure 28) fclk(SCL) SCL clock frequency - 2.9 - 4.54 - 5.71 - 8.0 MHz tSCL SCL time 345 - 220 - 175 - 125 - ns tclk(H) clock HIGH time 90 - 50 - 45 - 40 - ns tclk(L) clock LOW time 200 - 120 - 95 - 70 - ns tr rise time for SCL signal - 100 - 100 - 50 - 50 ns tf fall time for SCL signal - 100 - 100 - 50 - 50 ns tsu(CE) CE set-up time 40 - 35 - 30 - 25 - ns th(CE) CE hold time 40 - 30 - 25 - 15 - ns trec(CE) CE recovery time 30 - 25 - 20 - 15 - ns tw(CE) CE pulse width measured after valid subaddress is received - 0.99 - 0.99 - 0.99 - 0.99 s tsu set-up time set-up time for SDI data 10 - 5 - 3 - 2 - ns th hold time hold time for SDI data 25 - 10 - 8 - 5 - ns td(R)SDO SDO read delay time bus load = 50 pF 190 - 108 - 85 - 60 ns tdis(SDO) SDO disable time no load value; bus will be held up by bus capacitance; use RC time constant with application values 70 - 45 - 40 - 27 ns to avoid bus conflict - 0 - 0 - 0 - ns tt(SDI-SDO) transition time from SDI to SDO - 0 PCF2123_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 December 2009 39 of 55 PCF2123 NXP Semiconductors SPI Real time clock/calendar tw(CE) CE tsu(CE) tSCL tclk(H) tclk(L) tr tf trec(CE) th(CE) 80% SCL 20% WRITE tsu th SDI SDO R/W SA2 RA0 b6 b0 b7 b6 b0 Hi Z READ SDI b7 tt(SDI-SDO) tdis(SDO) td(R)SDO SDO Hi Z b7 b6 b0 001aai554 Fig 28. SPI-bus timing PCF2123_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 December 2009 40 of 55 PCF2123 NXP Semiconductors SPI Real time clock/calendar 13. Application information 1F supercapacitor 100 nF VDD OSCI CLKOE CLKOUT INT CE PCF2123 SCL VSS SDO SDI OSCO 001aai557 A 1 farad super capacitor combined with a low VF diode can be used as a standby or back-up supply. With the RTC in its minimum power configuration i.e. timer off and CLKOUT off, the RTC may operate for weeks. Fig 29. Typical application diagram PCF2123_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 December 2009 41 of 55 PCF2123 NXP Semiconductors SPI Real time clock/calendar 14. Package outline TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig 30. Package outline SOT402-1 (TSSOP14) of PCF2123TS PCF2123_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 December 2009 42 of 55 PCF2123 NXP Semiconductors SPI Real time clock/calendar HVQFN16: plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 3 x 3 x 0.85 mm A B D SOT758-1 terminal 1 index area A E A1 c detail X e1 C 1/2 e e 5 y y1 C v M C A B w M C b 8 L 4 9 e e2 Eh 1/2 e 12 1 16 terminal 1 index area 13 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. A1 b 1 0.05 0.00 0.30 0.18 c D (1) Dh E (1) Eh 0.2 3.1 2.9 1.75 1.45 3.1 2.9 1.75 1.45 e e1 1.5 0.5 e2 L v w y y1 1.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT758-1 --- MO-220 --- EUROPEAN PROJECTION ISSUE DATE 02-03-25 02-10-21 Fig 31. Package outline SOT758-1 (HVQFN16) of PCF2123BS PCF2123_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 December 2009 43 of 55 PCF2123 NXP Semiconductors SPI Real time clock/calendar 15. Bare die outline Wire bond die; 12 bonding pads; 1.492 x 1.449 x 0.20 mm PCF2123U/10 D A 6 7 5 8 9 10 11 12 P4 P3 4 x 0 E 3 0 y 2 P2 1 P1 X eD detail X DIMENSIONS (mm are the original dimensions) UNIT mm nom A 0.20 D(1) E(1) eD 1.492 1.449 1.296 P1(2) P2(3) P3(2) P4(3) 0.09 0.081 0.09 0.081 0 Notes 1. Dimension includes saw lane 2. P1 and P3: pad size 3. P2 and P4: passivation opening OUTLINE VERSION 1 mm scale REFERENCES IEC JEDEC EUROPEAN PROJECTION JEITA ISSUE DATE 08-07-16 08-07-24 PCF2123U/10 Fig 32. Bare die outline of PCF2123U/10 Table 46. Bonding pad locations All x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip; see Figure 32. Symbol Pad Coordinates x y SDO 1 648.0 −575.0 SDI 2 648.0 −377.0 SCL 3 648.0 −179.0 CLKOE 4 648.0 171.2 CLKOUT 5 648.0 369.2 VDD 6 648.0 625.7 OSCI 7 −648.0 639.0 OSCO 8 −648.0 421.9 TEST 9 −648.0 −25.9 INT 10 −648.0 −223.9 CE 11 −648.0 −441.0 VSS 12 −648.0 −639.0 PCF2123_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 December 2009 44 of 55 PCF2123 NXP Semiconductors SPI Real time clock/calendar WLCSP12: wafer level chip size package; 12 bumps; 1.492 x 1.449 x 0.22 mm PCF2123U/12 D 6 7 PC2123-1 5 8 4 9 E x0 0 y 10 3 2 11 e 12 1 Y e X P4 P3 A1 P2 A2 P1 A detail Y detail X 0 mm 1 mm scale Dimensions Unit 0.5 A A1 A2 D(1) E(1) P1(2) P2(3) P3(2) P4(3) e max 0.018 1.296 0.084 0.084 nom 0.22 0.015 0.2 1.492 1.449 0.09 0.081 0.09 0.081 min 0.012 0.198 0.078 0.078 Note 1. Dimension includes saw lane. 2. P1 and P3: pad size. 3. P2 and P4: bump size. pcf2123u_12_do References Outline version IEC JEDEC JEITA PCF2123U/12 --- --- --- European projection Issue date 09-10-17 09-10-19 Fig 33. Bare die outline of PCF2123U/12 PCF2123_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 December 2009 45 of 55 PCF2123 NXP Semiconductors SPI Real time clock/calendar Table 47. Bump locations All x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip; see Figure 33. Symbol Bump Coordinates x y SDO 1 648.0 −575.0 SDI 2 648.0 −377.0 SCL 3 648.0 −179.0 CLKOE 4 648.0 171.2 CLKOUT 5 648.0 369.2 VDD 6 648.0 625.7 OSCI 7 −648.0 639.0 OSCO 8 −648.0 421.9 TEST 9 −648.0 −25.9 INT 10 −648.0 −223.9 CE 11 −648.0 −441.0 VSS 12 −648.0 −639.0 Table 48. Alignment mark dimension and location Coordinates x y Location[1] −516.2 693 Dimension 16 µm 13 µm [1] The x/y coordinates of the alignment mark location represent the position of the REF point (see Figure 34) with respect to the center (x/y = 0) of the chip; see Figure 32 and Figure 33. [2] The x/y values of the dimensions represent the extensions of the alignment mark in direction of the coordinate axis (see Figure 34). REF y x 013aaa231 Fig 34. Alignment mark PCF2123_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 December 2009 46 of 55 PCF2123 NXP Semiconductors SPI Real time clock/calendar 16. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent standards. PCF2123_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 December 2009 47 of 55 PCF2123 NXP Semiconductors SPI Real time clock/calendar 17. Packing information 214.50 mm 73.68 mm 71.79 mm 1.2+0 mm −0.1 metal frame 0.25 plastic film ∅ 193.50 mm ∅ 22 5. 50 m m 214.50 mm 1.492 mm ~18 µm (1) 1 45 µm 1 1.449 mm straight edge of the wafer Saw lane ~18 µm X 1 70 µm 1 detail X 013aaa232 (1) Die marking code. Seal ring plus gap to active circuit ~18 µm. Wafer thickness 200 µm. PCF2123U/10: bad die are inked off. PCF2123U/12: bad die are marked in wafer mapping. Fig 35. PCF2123U/10 and PCF2123U/12 sawn wafer on film frame carrier PCF2123_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 December 2009 48 of 55 PCF2123 NXP Semiconductors SPI Real time clock/calendar 18. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 18.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 18.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 18.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities PCF2123_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 December 2009 49 of 55 PCF2123 NXP Semiconductors SPI Real time clock/calendar 18.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 36) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 49 and 50 Table 49. SnPb eutectic process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 ≥ 350 < 2.5 235 220 ≥ 2.5 220 220 Table 50. Lead-free process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 36. PCF2123_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 December 2009 50 of 55 PCF2123 NXP Semiconductors SPI Real time clock/calendar maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 36. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 19. Abbreviations Table 51. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor BCD Binary Coded Decimal FFC Film Frame Carrier HBM Human Body Model LSB Least Significant Bit MM Machine Model MOS Metal Oxide Semiconductor MSB Most Significant Bit MSL Moisture Sensitivity Level PCB Printed-Circuit Board RTC Real Time Clock SMD Surface Mount Device SPI Serial Peripheral Interface PCF2123_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 December 2009 51 of 55 PCF2123 NXP Semiconductors SPI Real time clock/calendar 20. References [1] AN10365 — Surface mount reflow soldering description [2] AN10706 — Handling bare die [3] AN10853 — Handling precautions of ESD sensitive devices [4] IEC 60134 — Rating systems for electronic tubes and valves and analogous semiconductor devices [5] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena [6] IPC/JEDEC J-STD-020D — Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices [7] JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM) [8] JESD22-A115 — Electrostatic Discharge (ESD) Sensitivity Testing Machine Model (MM) [9] JESD78 — IC Latch-Up Test [10] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices [11] NX3-00092 — NXP store and transport requirements [12] SNV-FA-01-02 — Marking Formats Integrated Circuits PCF2123_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 December 2009 52 of 55 PCF2123 NXP Semiconductors SPI Real time clock/calendar 21. Revision history Table 52. Revision history Document ID Release date Data sheet status Change notice Supersedes PCF2123_2 20091204 Product data sheet - PCF2123_1 - - Modifications: PCF2123_1 • Added product type PCF2123U/12 20081119 Product data sheet PCF2123_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 December 2009 53 of 55 PCF2123 NXP Semiconductors SPI Real time clock/calendar 22. Legal information 22.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 22.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 22.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Bare die — All die are tested on compliance with their related technical specifications as stated in this data sheet up to the point of wafer sawing and are handled in accordance with the NXP Semiconductors storage and transportation conditions. If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There are no post-packing tests performed on individual die or wafers. NXP Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. Accordingly, NXP Semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. It is the responsibility of the customer to test and qualify their application in which the die is used. All die sales are conditioned upon and subject to the customer entering into a written die sale agreement with NXP Semiconductors through its legal department. 22.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 23. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] PCF2123_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 4 December 2009 54 of 55 PCF2123 NXP Semiconductors SPI Real time clock/calendar 24. Contents 1 2 3 4 5 6 7 7.1 7.2 8 9 9.1 9.1.1 9.1.2 9.2 9.3 9.3.1 9.3.2 9.4 9.5 9.6 9.6.1 9.6.2 9.6.3 9.6.4 9.6.5 9.6.6 9.6.7 9.6.8 9.7 9.7.1 9.7.2 9.7.3 9.7.4 9.7.5 9.8 9.8.1 9.8.2 9.8.3 9.8.4 9.8.5 9.9 9.9.1 9.9.2 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Device protection diagram . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 6 Low power operation. . . . . . . . . . . . . . . . . . . . . 6 Power consumption with respect to quartz series resistance . . . . . . . . . . . . . . . . . . 6 Power consumptions with respect to timer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Register overview . . . . . . . . . . . . . . . . . . . . . . . 8 Control registers . . . . . . . . . . . . . . . . . . . . . . . . 9 Register Control_1 . . . . . . . . . . . . . . . . . . . . . . 9 Register Control_2 . . . . . . . . . . . . . . . . . . . . . 10 OS flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Time and date function . . . . . . . . . . . . . . . . . . 13 Register Seconds . . . . . . . . . . . . . . . . . . . . . . 13 Register Minutes. . . . . . . . . . . . . . . . . . . . . . . 13 Register Hours . . . . . . . . . . . . . . . . . . . . . . . . 13 Register Days . . . . . . . . . . . . . . . . . . . . . . . . . 14 Register Weekdays. . . . . . . . . . . . . . . . . . . . . 14 Register Months . . . . . . . . . . . . . . . . . . . . . . . 14 Register Years . . . . . . . . . . . . . . . . . . . . . . . . 15 Setting and reading the time. . . . . . . . . . . . . . 15 Alarm function. . . . . . . . . . . . . . . . . . . . . . . . . 16 Register Minute_alarm . . . . . . . . . . . . . . . . . . 16 Register Hour_alarm . . . . . . . . . . . . . . . . . . . 17 Register Day_alarm . . . . . . . . . . . . . . . . . . . . 17 Register Weekday_alarm . . . . . . . . . . . . . . . . 17 Alarm flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Timer functions . . . . . . . . . . . . . . . . . . . . . . . . 19 Register Timer_clkout. . . . . . . . . . . . . . . . . . . 19 Register Countdown_timer . . . . . . . . . . . . . . . 20 Minute and second interrupt . . . . . . . . . . . . . . 20 Countdown timer function . . . . . . . . . . . . . . . . 21 Timer flags . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Interrupt output . . . . . . . . . . . . . . . . . . . . . . . . 24 Minute and second interrupts . . . . . . . . . . . . . 24 Countdown timer interrupts. . . . . . . . . . . . . . . 25 9.9.3 9.9.3.1 9.10 9.10.1 9.11 9.12 9.13 9.14 9.14.1 10 11 12 13 14 15 16 17 18 18.1 18.2 18.3 18.4 19 20 21 22 22.1 22.2 22.3 22.4 23 24 Alarm interrupts . . . . . . . . . . . . . . . . . . . . . . . Correction pulse interrupts . . . . . . . . . . . . . . . Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . CLKOE pin . . . . . . . . . . . . . . . . . . . . . . . . . . . Offset register. . . . . . . . . . . . . . . . . . . . . . . . . External clock test mode . . . . . . . . . . . . . . . . STOP bit function . . . . . . . . . . . . . . . . . . . . . . 3-line serial interface . . . . . . . . . . . . . . . . . . . Interface watchdog timer . . . . . . . . . . . . . . . . Limiting values . . . . . . . . . . . . . . . . . . . . . . . . Static characteristics . . . . . . . . . . . . . . . . . . . Dynamic characteristics . . . . . . . . . . . . . . . . . Application information . . . . . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Bare die outline . . . . . . . . . . . . . . . . . . . . . . . . Handling information . . . . . . . . . . . . . . . . . . . Packing information . . . . . . . . . . . . . . . . . . . . Soldering of SMD packages . . . . . . . . . . . . . . Introduction to soldering. . . . . . . . . . . . . . . . . Wave and reflow soldering . . . . . . . . . . . . . . . Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 26 27 27 27 30 31 32 34 36 37 39 41 42 44 47 48 49 49 49 49 50 51 52 53 54 54 54 54 54 54 55 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 4 December 2009 Document identifier: PCF2123_2