Features • • • • • • • • • • • • • • • • • • Operating Range from 5V to 18V Baud Rate from 2.6 Kbaud up to 20 Kbaud Improved Slew Rate Control According to LIN Specification 2.0 Fully Compatible with 3.3V and 5V Devices Dominant Time-out Function at Transmit Data (TXD) Normal and Sleep Mode Wake-up Capability via LIN Bus (90 µs Dominant) External Wake-up via WAKE Pin (130 µs Low Level) Control of External Voltage Regulator via INH Pin Very Low Standby Current During Sleep Mode (10 µA) 60V Load Dump Protection at LIN Pin (42-V Power Net) Wake-up Source Recognition Bus Pin Short-circuit Protected versus GND and Battery LIN Input Current < 3 µA if VBAT Is Disconnected Overtemperature Protection High EMC Level Interference and Damage Protection According to ISO/CD 7637 ESD HBM 6 kV at LIN Bus Pin and Supply VS Pin LIN Transceiver ATA6661 1. Description The ATA6661 is a fully integrated LIN transceiver according to the LIN specification 2.0. It interfaces the LIN protocol handler and the physical layer. The device is designed to handle the low-speed data communication in vehicles, e.g., in convenience electronics. Improved slope control at the LIN bus ensures secure data communication up to 20 kBaud with an RC-oscillator for protocol handling. In order to comply with the 42-V power net requirements, the bus output is capable of withstanding high voltages. Sleep mode guarantees minimal current consumption. 4729I–AUTO–12/06 DRAFT DRAFT Figure 1-1. Block Diagram ATA6661 RXD 7 VS 6 LIN 5 GND Receiver 1 + Filter Wake up bus timer TXD Short circuit and overtemperature protection 4 TXD Time-out timer Slew rate control VS VS Control unit WAKE 3 Standby mode Wake-up timer 2 8 INH EN 2. Pin Configuration Figure 2-1. Pinning SO8 RXD EN WAKE TXD Figure 2-2. 2 1 2 3 4 8 7 6 5 INH VS LIN GND Pin Description Pin Symbol 1 RXD Function 2 EN 3 WAKE 4 TXD 5 GND 6 LIN LIN bus line input/output 7 VS Battery supply 8 INH Battery related inhibit output for controlling an external voltage regulator; active high after a wake-up request Receive data output (open drain) Enables normal mode, when the input is open or low, the device is in sleep mode High voltage input for local wake-up request Transmit data input; active low output (strong pull-down) after a local wake-up request Ground ATA6661 4729I–AUTO–12/06 DRAFT ATA6661 3. Functional Description 3.1 Supply Pin (VS) Undervoltage detection is implemented to disable transmission if VS is falling to a value below 5V to avoid false bus messages. After switching on VS the IC switches to pre-normal mode and INHIBIT is switched on. The supply current in sleep mode is typically 10 µA. 3.2 Ground Pin (GND) The ATA6661 is neutral on the LIN pin in case of a GND disconnection. It is able to handle a ground shift up to 3V for VS > 9V. 3.3 Bus Pin (LIN) A low-side driver with internal current limitation and thermal shutdown as well as an internal pull-up resistor according to LIN specification 2.0 are implemented. The voltage range is from –27V to +60V. This pin exhibits no reverse current from the LIN bus to VS, even in case of a GND shift or VBatt disconnection. The LIN receiver thresholds are compatible to the LIN protocol specification.The fall time (from recessive to dominant) and the rise time (from dominant to recessive) are slope controlled. The output has a short circuit limitation. This is a self adapting current limitation; i.e., during current limitation as the chip temperature increases so the current reduces. 3.4 Input Pin (TXD) This pin is the microcontroller interface to control the state of the LIN output. TXD is low to bring LIN low. If TXD is high, the LIN output transistor is turned off. In this case, the bus is in recessive mode via the internal pull-up resistor. The TXD pin is compatible to a 3.3V and 5V supply. 3.5 TXD Dominant Time-out Function The TXD input has an internal pull-down resistor. An internal timer prevents the bus line from being driven permanently in dominant state. If TXD is forced low longer than tdom > 6 ms, the pin LIN will be switched off to recessive mode. To reset this mode switch TXD to high (>10 µs) before switching LIN to dominant again. 3.6 Output Pin (RXD) This pin reports to the microcontroller the state of the LIN bus. LIN high (recessive) is reported by a high level at RXD, LIN low (dominant) is reported by a low voltage at RXD. The output is an open drain, therefore, it is compatible to a 3.3V or 5V power supply. The AC characteristics are defined with a pull-up resistor of 5 kΩ to 5V and a load capacitor of 20 pF. The output is short-current protected. In unpowered mode (VS = 0V), RXD is switched off. For ESD protection a Zener diode is implemented with VZ = 6.1V. 3 4729I–AUTO–12/06 DRAFT 3.7 Enable Input Pin (EN) This pin controls the operation mode of the interface. If EN = 1, the interface is in normal mode, with the transmission path from TXD to LIN and from LIN to Rx both active. If EN = 0, the device is switched to sleep mode and no transmission is possible. In sleep mode, the LIN bus pin is connected to VS with a weak pull-up current source. The device can transmit only after being woken up (see next section “Inhibit Output Pin (INH)” ). During sleep mode the device is still supplied from the battery voltage. The supply current is typically 10 µA. The pin EN provides a pull-down resistor in order to force the transceiver into sleep mode in case the pin is disconnected. 3.8 Inhibit Output Pin (INH) This pin is used to control an external switchable voltage regulator having a wake-up input. The inhibit pin provides an internal switch towards pin VS. If the device is in normal mode, the inhibit high-side switch is turned on and the external voltage regulator is activated. When the device is in sleep mode, the inhibit switch is turned off and disables the voltage regulator. A wake-up event on the LIN bus or at pin WAKE will switch the INH pin to the VS level. After a system power-up (VS rises from zero), the pin INH switches automatically to the VS level. The RDSon of the high-side output is < 1 kΩ. 3.9 Wake-up Input Pin (WAKE) This pin is a high-voltage input used to wake-up the device from sleep mode. It is usually connected to an external switch in the application to generate a local wake-up. If you do not need a local wake-up in your application, connect pin WAKE directly to pin VS. A pull-up current source with typically –10 µA is implemented. The voltage threshold for a wake-up signal is 3V below the VS voltage with an output current of typical –3 µA. Wake-up events from sleep mode: • LIN bus • EN pin • WAKE pin Figure 3-1 on page 6, Figure 3-2 and Figure 3-3 on page 7 show details of wake-up operations. 4 ATA6661 4729I–AUTO–12/06 DRAFT 3.10 ATA6661 Mode of Operation 1. Normal mode This is the normal transmitting and receiving mode. All features are available. 2. Sleep mode In this mode the transmission path is disabled and the device is in low power mode. Supply current from VBatt is typically 10 µA. A wake-up signal from the LIN bus or via pin WAKE will be detected and switches the device to pre-normal mode. If EN, then switches to high, normal mode is activated. Input debounce timers at pin WAKE (TWAKE), LIN (TBUS) and EN (Tsleep,Tnom) prevent unwanted wake-up events due to automotive transients or EMI. In sleep mode the INH pin is floating. The internal termination between pin LIN and pin VS is disabled to minimize the power dissipation in case pin LIN is short-circuited to GND. Only a weak pull-up current (typical 10 µA) between pin LIN and pin VS is present. 3. Pre-normal mode At system power-up, the device automatically switches to pre-normal mode. It switches the INH pin to a high state, to the VS level. The microcontroller of the application will then confirm the normal mode by setting the EN pin to high. 4. Unpowered mode In this mode the LIN transceiver is disabled. Data communication is switched off. If VS is higher than VSth undervoltage threshold, the IC mode change from Unpowered to Pre-normal mode. 3.11 Remote Wake-up via Dominant Bus State A falling edge at pin LIN, followed by a dominant bus level maintained for a certain time period (TBUS), results in a remote wake-up request. The device switches to pre-normal mode. Pin INH is activated (switches to V S ) and the internal termination resistor is switched on. The remote wake-up request is indicated by a low level at pin RXD to interrupt the microcontroller (see Figure 3-2 on page 7). The voltage threshold for a wake-up signal is 3V below the VS voltage with an output current of typical –3 µA. 3.12 Local Wake-up via Pin WAKE A falling edge at pin WAKE, followed by a low level maintained for a certain time period (TWAKE), results in a local wake-up request. The extra long wake-up time (TWAKE) ensures that no transient, according to ISO7637, creates a wake-up. The device switches to pre-normal mode. Pin INH is activated (switches to VS) and the internal termination resistor is switched on. The local wake-up request is indicated by a low level at pin RXD to interrupt the microcontroller and a strong pull-down at pin TXD (see Figure 3-3 on page 7). 3.13 Wake-up Source Recognition The device can distinguish between a local wake-up request (pin WAKE) and a remote wake-up request (dominant LIN bus). The wake-up source can be read on pin TXD in pre-normal mode. If an external pull-up resistor (typically 5 kΩ) on pin TXD to the power supply of the microcontroller has been added, a high level indicates a remote wake-up request (weak pull-down at pin TXD) and a low level indicates a local wake-up request (strong pull-down at pin TXD). The wake-up request flag (signalled on pin RXD) as well as the wake-up source flag (signalled on pin TXD) are reset immediately, if the microcontroller sets pin EN to high (see Figure 3-2 on page 7 and Figure 3-3). 5 4729I–AUTO–12/06 DRAFT Figure 3-1. Mode of Operation a: VS > 5V Unpowered Mode VBatt = 0V b b: VS < 4V c: Bus wake-up event d: Wake-up from Wake switch a Pre-normal Mode INH: high (INH internal High Side switch ON) Communication: OFF b d EN = 1 b c Go to sleep command EN = 0 Normal Mode INH: high (INH HS switch ON) Communication: ON 3.14 Sleep Mode Local wake-up event EN = 1 INH: high impedance (INH HS switch OFF) Communication: OFF Fail-safe Features • There are now reverse currents < 3 µA at pin LIN during loss of VBAT or GND. Optimal behavior for bus systems where some slave nodes supplied from battery or ignition. • Pin EN provides pull-down resistor to force the transceiver into sleep mode if EN is disconnected. • Pin RXD is set floating if VBAT is disconnected. • Pin TXD provides a pull-down resistor to provide a static low if TXD is disconnected. • The LIN output driver has a current limitation and if the junction temperature Tj exceeds the thermal shut-down temperature Toff the output driver switches off. • The implemented hysteresis Thys enables the LIN output again after the temperature has been decreased. 3.15 Physical Layer Compatibility Since the LIN physical layer is independent from higher LIN layers (e.g. LIN protocol layer), all nodes with a LIN physical layer according to this revision can be mixed with LIN physical layer nodes, which are according to older versions (i.e. LIN 1.0, LIN 1.1, LIN 1.2, LIN 1.3), without any restrictions. A higher ratio of nodes according to this LIN physical layer specification or the one of revision 2.0 will result in a higher transmission reliability. 6 ATA6661 4729I–AUTO–12/06 DRAFT Figure 3-2. ATA6661 LIN Wake-up Waveform Diagram LIN bus INH Low or floating High RXD High or floating Low Bus wake-up filtering time TBus External voltage regulator On state Off state Node in Operation Regulator wake-up time delay EN EN High Node in sleep state Microcontroller start-up time delay Figure 3-3. LIN Wake-up from Wake-up Switch Wake pin State change INH Low or floating High RXD High or floating Low TXD TXD weak pull-down resistor TXD strong pull-down High weak pull-down Wake filtering time TWAKE Voltage regulator On state Off state Regulator wake-up time delay Node in Operation EN High EN Node in sleep state Microcontroller start-up time delay 7 4729I–AUTO–12/06 DRAFT 4. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Max. Unit –0.3 +40 V Wake DC and transient voltage (with 33 kΩ serial resistor) - Transient voltage due to ISO7637 (coupling 1 nF) –40 –150 +40 +100 V V Logic pins (RXD, TXD, EN) –0.3 +6 V LIN - DC voltage - Transient voltage due to ISO7637 (coupling 1 nF) –40 –150 +60 +100 V V INH - DC voltage –0.3 +40 V ESD (DIN EN 61000-4-2) According LIN EMC Test Specification V1.3 - Pin VS, LIN - Pin Wake (with 33 kΩ serial resistor) –6000 –5000 +6000 +5000 V V ESD S5.1 - All pins –3000 +3000 V CDM ESD STM 5.3.1-1999 - All pins FCDM ESD STM 5.3.1- All pins MM JEDEC A115A - All pins –500 –1000 –200 +500 +1000 +200 V V V VS - Continuous supply voltage Symbol Min. Typ. Junction temperature Tj –40 +150 °C Storage temperature Tstg –55 +150 °C Operating ambient temperature Tamb –40 +125 °C Thermal shutdown Toff 150 165 180 °C Thermal shutdown hysteresis Thys 5 10 20 °C 5. Thermal Resistance Parameters Thermal resistance junction ambient 8 Symbol Value Unit RthJA 160 K/W ATA6661 4729I–AUTO–12/06 DRAFT ATA6661 6. Electrical Characteristics 5V < VS < 18V, Tamb = –40°C to +125°C No. 1 1.1 1.2 Parameters Nominal DC voltage range Supply current in sleep mode Supply current in normal mode 1.5 VS undervoltage threshold 1.6 VS undervoltage threshold hysteresis 2 Pin Symbol Min. Typ. Max. Unit Type* 5 13.5 18 V A VS Pin 1.3 1.4 Test Conditions 7 VS Sleep mode Vlin > VBatt – 0.5V VBatt < 14V 7 IVSstby 10 20 µA A Bus recessive 7 IVSrec 1.6 3 mA A Bus dominant Total bus load > 500Ω 7 IVSdom 1.6 3 mA A 4.6 5 V A V A 8 mA A 0.4 V A VSth 7 VSth_hys 4 0.2 RXD Output Pin (Open Drain) 2.1 Low level input current Normal mode VLIN = 0V, VRXD = 0.4V 1 IRXDL 2.2 RXD saturation voltage 5 kΩ pull-up resistor to 5V 1 VsatRXD 2.3 High level leakage current Normal mode VLIN = VBAT, VRXD = 5V 1 IRXDH –3 +3 µA A 2.4 ESD zener diode IRXD = 100 µA 1 VZRXD 6.1 8.6 V A 3 2 5 TXD Input Pin 3.1 Low level voltage input 4 VTXDL –0.3 +0.8 V A 3.2 High level voltage input 4 VTXDH 2 7 V A 3.3 Pull-down resistor VTXD = 5V 4 RTXD 125 600 kΩ A 3.4 Low level leakage current VTXD = 0V 4 ITXD –3 +3 µA A 3.5 Low-level input current at local wake-up request Pre-normal mode VLIN = VBAT; VWAKE = 0V 4 ITXDwake 2 8 mA A 4 250 5 EN Input Pin 4.1 Low level voltage input 2 VENL –0.3 +0.8 V A 4.2 High level voltage input 2 VENH 2 7 V A 4.3 Pull-down resistor VEN = 5V 2 REN 125 600 kΩ A 4.4 Low level input current VEN = 0V 2 IEN –3 +3 µA A 4.5 Enable negative slope for go to sleep Negative slope VEN = 2V to 0.8V 2 SlopeEN 60 µs A 5 250 INH Output Pin 5.1 High level voltage Normal mode IINH = –200 µA 8 VINHH VS – 0.8 VS V A 5.2 High level leakage current Sleep mode VINH = 27V, VBatt = 27V 8 IINHL –3 +3 µA A 3 VWAKEH VS – 1V VS + 0.3V V A 3 VWAKEL –27V VS – 3V V A 6 WAKE Pin 6.1 High level input voltage 6.2 Low level input voltage IWAKE = Typically –3 µA *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 9 4729I–AUTO–12/06 DRAFT 6. Electrical Characteristics (Continued) 5V < VS < 18V, Tamb = –40°C to +125°C No. Parameters Test Conditions 6.3 Wake pull-up current 6.4 High level leakage current 7 Pin Symbol Min. Typ. VS < 27V 3 IWAKE –30 –10 VS = 27V, VWAKE = 27V 3 IWAKE –5 0.9 × VS Max. Unit Type* µA A +5 µA A VS V A LIN Bus Driver 7.1 Driver recessive output voltage RLOAD = 500Ω/1 kΩ 6 VBUSrec 7.2 Driver dominant voltage VBUSdom_DRV_LoSUP VVS = 7V, Rload = 500Ω 6 V_LoSUP 1.2 V A 7.3 Driver dominant voltage VBUSdom_DRV_HiSUP VVS = 18V, Rload = 500Ω 6 V_HiSUP 2 V A 7.4 Driver dominant voltage VBUSdom_DRV_LoSUP VVS = 7V, Rload = 1000Ω 6 V_LoSUP_1k 0.6 V A 7.5 Driver dominant voltage VBUSdom_DRV_HiSUP VVS = 18V, Rload = 1000Ω 6 V_HiSUP_1k_ 0.8 V A 7.6 Pull-up resistor to VS The serial diode is mandatory 6 RLIN 20 60 kΩ A 7.7 Self-adapting current limitation VBUS = VBAT_max Tj = 125°C Tj = 27°C Tj = –40°C 6 IBUS_LIM 52 100 150 110 170 230 mA mA mA A 7.8 Input leakage current at the receiver, inclusive pull-up resistor as specified Input leakage current Driver off VBUS = 0V, VBatt = 12V 6 IBUS_PAS_dom –1 mA A 7.9 Leakage current LIN recessive Driver off 8V < VBAT < 18V 8V < VBUS < 18V VBUS ≥ VBAT 6 IBUS_PAS_rec 7.10 Leakage current at ground loss, Control unit disconnected from GNDDevice = VS ground, VBAT =12V Loss of local ground must not 0V < VBUS < 18V affect communication in the residual network 6 IBUS_NO_gnd 7.11 Node has to sustain the current that can flow under this condition, bus must remain operational under this condition VBAT disconnected VSUP_Device = GND 0V < VBUS < 18V 6 IBUS 8 –10 30 15 20 µA A +0.5 +10 µA A 0.5 3 µA A 0.5 × VS 0.525 × VS V A LIN Bus Receiver 8.1 Center of receiver threshold VBUS_CNT = (Vth_dom + Vth_rec)/2 6 VBUS_CNT 0.475 × VS 8.2 Receiver dominant state VEN = 5V 6 VBUSdom –27 0.4 × VS V A 8.3 Receiver recessive state VEN = 5V 6 VBUSrec 0.6 × VS 40 V A 8.4 Receiver input hysteresis VHYS = Vth_rec – Vth_dom 6 VBUShys 0.028 × VS 0.175 × VS V A 8.5 Wake detection LIN High level input voltage 6 VLINH VS – 1V VS + 0.3V V A 0.1 × VS *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 10 ATA6661 4729I–AUTO–12/06 DRAFT ATA6661 6. Electrical Characteristics (Continued) 5V < VS < 18V, Tamb = –40°C to +125°C No. Parameters Test Conditions 8.6 Wake detection LIN Low level input voltage 8.7 LIN pull-up current 9 Pin Symbol Min. Typ. ILIN = Typically –3 µA 6 VLINL –27V VS < 27V 6 ILIN –30 –10 Max. Unit Type* VS – 3V V A µA A Internal Timers 9.1 Dominant time for wake-up via LIN bus VLIN = 0V 6 TBUS 30 90 150 µs A 9.2 Time of low pulse for wake-up via pin WAKE VWAKE = 0V 3 TWAKE 60 130 200 µs A 9.3 Time delay for mode change from pre-normal mode to normal VEN = 5V mode via pin EN 2 Tnorm 2 10 15 µs A 9.4 Time delay for mode change from normal mode into sleep mode via pin EN VEN = 0V 2 Tsleep 2 10 12 µs A 9.5 TXD dominant time out timer VTXD = 0V 4 Tdom 6 9 20 ms A 9.6 Power-up delay between VS = 5V until INH switches to high VVS = 5V 200 µs A 10 LIN Bus Driver (see Figure 6-1 on page 12) Bus load conditions: Load1 small 1 nF 1 kΩ, Load2 big 10 nF 500Ω, RRXD = 5 kΩ, CRXD = 20 pF; The following two rows specifies the timing parameters for proper operation at 20.0 Kbit/s. TVS Duty cycle 1 THRec(max) = 0.744 × VS THDom(max) = 0.581 × VS VS = 7.0V to 18V tBit = 50 µs D1 = tbus_rec(min)/(2 × tBit) 6 D1 10.2 Duty cycle 1 THRec(min) = 0.422 × VS THDom(min) = 0.284 × VS VS = 7.0V to 18V tBit = 50 µs D2 = tbus_rec(max)/(2 × tBit) 6 D2 10.3 Slope time falling and rising edge at LIN Load1/Load2 VS = 7.3V to 18V 6 tSlope_fall tSlope_rise 3.5 22.5 µs A 10.4 Symmetry of rising and falling edge VS = 7.3V tsym = tSlope_fall – tSlope_rise tsym –4 +4 µs A 6 µs A +2 µs A 10.1 11 0.396 A 0.581 A Receiver Electrical AC Parameters of the LIN Physical Layer LIN receiver, RXD load conditions (CRXD): 20 pF, Rpull-up = 5 kΩ 11.1 Propagation delay of receiver (see Figure 6-1 on page 12) trec_pd = max(trx_pdr, trx_pdf) trx_pd 11.2 Symmetry of receiver propagation delay rising edge minus falling edge trx_sym = trx_pdr – trx_pdf trx_sym –2 *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 11 4729I–AUTO–12/06 DRAFT Figure 6-1. Definition of Bus Timing Parameter tBit tBit tBit TXD (Input to transmitting node) tBus_dom(max) tBus_rec(min) Thresholds of receiving node1 THRec(max) VS (Transceiver supply of transmitting node) THDom(max) LIN Bus Signal Thresholds of THRec(min) receiving node2 THDom(min) tBus_dom(min) tBus_rec(max) RXD (Output of receiving node1) trx_pdf(1) trx_pdr(1) RXD (Output of receiving node2) trx_pdr(2) 12 trx_pdf(2) ATA6661 4729I–AUTO–12/06 DRAFT Figure 6-2. ATA6661 Application Circuit Master node pull-up VBATTERY + 22 µF 100 nF 12V 5V 1k + 7 ATA6661 5 kΩ VS Receiver 1 LIN sub bus VDD Microcontroller RXD Filter SCI LIN Wake-up bus timer 4 TXD Time-out timer TXD IO VS 33 kΩ 3 WAKE Slew rate control Short circuit and overtemperature protection 220 pF VS Control unit 10 kΩ External switch 6 Wake-up timer 5 Standby mode GND 2 8 EN INH 13 4729I–AUTO–12/06 DRAFT 7. Ordering Information Extended Type Number Package Remarks ATA6661-TAQJ SO8 LIN transceiver, Pb-free, taped and reeled ATA6661-TAPJ SO8 LIN transceiver, Pb-free, taped and reeled 8. Package Information Package SO8 Dimensions in mm 5.2 4.8 5.00 4.85 3.7 1.4 0.25 0.10 0.4 1.27 6.15 5.85 3.81 8 0.2 3.8 5 technical drawings according to DIN specifications 1 14 4 ATA6661 4729I–AUTO–12/06 DRAFT ATA6661 9. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. 4729I-AUTO-12/06 4729H-AUTO-10/06 History • Put datasheet in a new template • Section 3.5 “TXD Dominant Time-out Function” changed • Section 7 “Ordering Information” on page 14 changed • Put datasheet in a new template • Pb-free logo on page 1 deleted • Features on page 1 changed • Section 3-10 “Mode of Operation” on page 5 changed • Figure 3-1 “Mode of Operation” on page 6 changed • Section 3.15 “Physical Layer Compatibility” on page 6 added • Section 6 “Electrical Characteristics” number 4.5 on page 9 added • Section 6 “Electrical Characteristics” number 9.5 on page 11 changed • Section 6 “Electrical Characteristics” number 10.3 and 10.4 on page 11 added • Figure 6-2 “Application Circuit” on page 12 changed 4729G-AUTO-10/05 4729F-AUTO-05/05 4729E-AUTO-01/05 4729D-AUTO-10/04 4729C-AUTO-06/04 • Pb-free Logo on page 1 added • Table “Ordering Information” on page 13 changed • • • • • • • • • • • • • • • • • • • • • Section 2.14 “Fail-safe Features” on page 5 changed Figure 2.2 “LIN Wake-up Waveform Diagram” on page 6 changed Table “Absolute Maximum Ratings” on page 7 changed Table “Electrical Characteristics”: Rows: 7.1, 7.2, 7.4, 8.5, 9.3 and 9.5 changed Put datasheet in a new template Table “Ordering Information” on page 13 changed Put datasheet into new template Section “Features” on page 1 changed Figure 1 “Block Diagram” on page 1 changed Section “Bus Pin (LIN)” on page 2 changed Section “TX Dominant Time-out Function” on page 3 changed Section “Output Pin (RXD)” on page 3 changed Section “Inhibit Output Pin (INH)” on page 3 changed Section “Wake-up Input Pin (WAKE)” on page 3 changed Section “Remote Wake-up via Dominant Bus State” on page 4 changed Section “Fail-safe Features” added Table “Absolute Maximum Ratings” on page 7 changed Table “Electrical Characteristics”: Rows: 1.3, 1.4, 1.5, 6.2, 7.9, 7.10, 7.11 and 9.3 changed Table “Electrical Characteristics”: Rows: 2.4, 8.5, 8.6 and 8.7 Figure 7 “Application Circuit” on page 12 changed Table “Ordering Information” on page 13 changed 15 4729I–AUTO–12/06 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 1150 East Cheyenne Mtn. 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Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2006 Atmel Corporation. All rights reserved. Atmel ®, logo and combinations thereof, Everywhere You Are® and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. DRAFT 4729I–AUTO–12/06